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[S390] convert sclp printks to pr_xxx macros.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / s390 / net / qeth_core_main.c
CommitLineData
4a71df50
FB		 1/*
2 * drivers/s390/net/qeth_core_main.c
3 *
4 * Copyright IBM Corp. 2007
5 * Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
6 * Frank Pavlic <fpavlic@de.ibm.com>,
7 * Thomas Spatzier <tspat@de.ibm.com>,
8 * Frank Blaschka <frank.blaschka@de.ibm.com>
9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/string.h>
14#include <linux/errno.h>
15#include <linux/kernel.h>
16#include <linux/ip.h>
17#include <linux/ipv6.h>
18#include <linux/tcp.h>
19#include <linux/mii.h>
20#include <linux/kthread.h>
21
ab4227cb
MS		 22#include <asm/ebcdic.h>
23#include <asm/io.h>
4a71df50
FB		 24#include <asm/s390_rdev.h>
25
26#include "qeth_core.h"
27#include "qeth_core_offl.h"
28
d11ba0c4
PT		 29struct qeth_dbf_info qeth_dbf[QETH_DBF_INFOS] = {
30 /* define dbf - Name, Pages, Areas, Maxlen, Level, View, Handle */
31 /* N P A M L V H */
32 [QETH_DBF_SETUP] = {"qeth_setup",
33 8, 1, 8, 5, &debug_hex_ascii_view, NULL},
34 [QETH_DBF_QERR] = {"qeth_qerr",
35 2, 1, 8, 2, &debug_hex_ascii_view, NULL},
36 [QETH_DBF_TRACE] = {"qeth_trace",
37 4, 1, 8, 3, &debug_hex_ascii_view, NULL},
38 [QETH_DBF_MSG] = {"qeth_msg",
39 8, 1, 128, 3, &debug_sprintf_view, NULL},
40 [QETH_DBF_SENSE] = {"qeth_sense",
41 2, 1, 64, 2, &debug_hex_ascii_view, NULL},
42 [QETH_DBF_MISC] = {"qeth_misc",
43 2, 1, 256, 2, &debug_hex_ascii_view, NULL},
44 [QETH_DBF_CTRL] = {"qeth_control",
45 8, 1, QETH_DBF_CTRL_LEN, 5, &debug_hex_ascii_view, NULL},
46};
47EXPORT_SYMBOL_GPL(qeth_dbf);
4a71df50
FB		 48
49struct qeth_card_list_struct qeth_core_card_list;
50EXPORT_SYMBOL_GPL(qeth_core_card_list);
683d718a
FB		 51struct kmem_cache *qeth_core_header_cache;
52EXPORT_SYMBOL_GPL(qeth_core_header_cache);
4a71df50
FB		 53
54static struct device *qeth_core_root_dev;
55static unsigned int known_devices[][10] = QETH_MODELLIST_ARRAY;
56static struct lock_class_key qdio_out_skb_queue_key;
4a71df50
FB		 57
58static void qeth_send_control_data_cb(struct qeth_channel *,
59 struct qeth_cmd_buffer *);
60static int qeth_issue_next_read(struct qeth_card *);
61static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *);
62static void qeth_setup_ccw(struct qeth_channel *, unsigned char *, __u32);
63static void qeth_free_buffer_pool(struct qeth_card *);
64static int qeth_qdio_establish(struct qeth_card *);
65
66
67static inline void __qeth_fill_buffer_frag(struct sk_buff *skb,
68 struct qdio_buffer *buffer, int is_tso,
69 int *next_element_to_fill)
70{
71 struct skb_frag_struct *frag;
72 int fragno;
73 unsigned long addr;
74 int element, cnt, dlen;
75
76 fragno = skb_shinfo(skb)->nr_frags;
77 element = *next_element_to_fill;
78 dlen = 0;
79
80 if (is_tso)
81 buffer->element[element].flags =
82 SBAL_FLAGS_MIDDLE_FRAG;
83 else
84 buffer->element[element].flags =
85 SBAL_FLAGS_FIRST_FRAG;
86 dlen = skb->len - skb->data_len;
87 if (dlen) {
88 buffer->element[element].addr = skb->data;
89 buffer->element[element].length = dlen;
90 element++;
91 }
92 for (cnt = 0; cnt < fragno; cnt++) {
93 frag = &skb_shinfo(skb)->frags[cnt];
94 addr = (page_to_pfn(frag->page) << PAGE_SHIFT) +
95 frag->page_offset;
96 buffer->element[element].addr = (char *)addr;
97 buffer->element[element].length = frag->size;
98 if (cnt < (fragno - 1))
99 buffer->element[element].flags =
100 SBAL_FLAGS_MIDDLE_FRAG;
101 else
102 buffer->element[element].flags =
103 SBAL_FLAGS_LAST_FRAG;
104 element++;
105 }
106 *next_element_to_fill = element;
107}
108
109static inline const char *qeth_get_cardname(struct qeth_card *card)
110{
111 if (card->info.guestlan) {
112 switch (card->info.type) {
113 case QETH_CARD_TYPE_OSAE:
114 return " Guest LAN QDIO";
115 case QETH_CARD_TYPE_IQD:
116 return " Guest LAN Hiper";
117 default:
118 return " unknown";
119 }
120 } else {
121 switch (card->info.type) {
122 case QETH_CARD_TYPE_OSAE:
123 return " OSD Express";
124 case QETH_CARD_TYPE_IQD:
125 return " HiperSockets";
126 case QETH_CARD_TYPE_OSN:
127 return " OSN QDIO";
128 default:
129 return " unknown";
130 }
131 }
132 return " n/a";
133}
134
135/* max length to be returned: 14 */
136const char *qeth_get_cardname_short(struct qeth_card *card)
137{
138 if (card->info.guestlan) {
139 switch (card->info.type) {
140 case QETH_CARD_TYPE_OSAE:
141 return "GuestLAN QDIO";
142 case QETH_CARD_TYPE_IQD:
143 return "GuestLAN Hiper";
144 default:
145 return "unknown";
146 }
147 } else {
148 switch (card->info.type) {
149 case QETH_CARD_TYPE_OSAE:
150 switch (card->info.link_type) {
151 case QETH_LINK_TYPE_FAST_ETH:
152 return "OSD_100";
153 case QETH_LINK_TYPE_HSTR:
154 return "HSTR";
155 case QETH_LINK_TYPE_GBIT_ETH:
156 return "OSD_1000";
157 case QETH_LINK_TYPE_10GBIT_ETH:
158 return "OSD_10GIG";
159 case QETH_LINK_TYPE_LANE_ETH100:
160 return "OSD_FE_LANE";
161 case QETH_LINK_TYPE_LANE_TR:
162 return "OSD_TR_LANE";
163 case QETH_LINK_TYPE_LANE_ETH1000:
164 return "OSD_GbE_LANE";
165 case QETH_LINK_TYPE_LANE:
166 return "OSD_ATM_LANE";
167 default:
168 return "OSD_Express";
169 }
170 case QETH_CARD_TYPE_IQD:
171 return "HiperSockets";
172 case QETH_CARD_TYPE_OSN:
173 return "OSN";
174 default:
175 return "unknown";
176 }
177 }
178 return "n/a";
179}
180
181void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,
182 int clear_start_mask)
183{
184 unsigned long flags;
185
186 spin_lock_irqsave(&card->thread_mask_lock, flags);
187 card->thread_allowed_mask = threads;
188 if (clear_start_mask)
189 card->thread_start_mask &= threads;
190 spin_unlock_irqrestore(&card->thread_mask_lock, flags);
191 wake_up(&card->wait_q);
192}
193EXPORT_SYMBOL_GPL(qeth_set_allowed_threads);
194
195int qeth_threads_running(struct qeth_card *card, unsigned long threads)
196{
197 unsigned long flags;
198 int rc = 0;
199
200 spin_lock_irqsave(&card->thread_mask_lock, flags);
201 rc = (card->thread_running_mask & threads);
202 spin_unlock_irqrestore(&card->thread_mask_lock, flags);
203 return rc;
204}
205EXPORT_SYMBOL_GPL(qeth_threads_running);
206
207int qeth_wait_for_threads(struct qeth_card *card, unsigned long threads)
208{
209 return wait_event_interruptible(card->wait_q,
210 qeth_threads_running(card, threads) == 0);
211}
212EXPORT_SYMBOL_GPL(qeth_wait_for_threads);
213
214void qeth_clear_working_pool_list(struct qeth_card *card)
215{
216 struct qeth_buffer_pool_entry *pool_entry, *tmp;
217
d11ba0c4 218 QETH_DBF_TEXT(TRACE, 5, "clwrklst");
4a71df50
FB		 219 list_for_each_entry_safe(pool_entry, tmp,
220 &card->qdio.in_buf_pool.entry_list, list){
221 list_del(&pool_entry->list);
222 }
223}
224EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);
225
226static int qeth_alloc_buffer_pool(struct qeth_card *card)
227{
228 struct qeth_buffer_pool_entry *pool_entry;
229 void *ptr;
230 int i, j;
231
d11ba0c4 232 QETH_DBF_TEXT(TRACE, 5, "alocpool");
4a71df50
FB		 233 for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {
234 pool_entry = kmalloc(sizeof(*pool_entry), GFP_KERNEL);
235 if (!pool_entry) {
236 qeth_free_buffer_pool(card);
237 return -ENOMEM;
238 }
239 for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) {
508b3c4f 240 ptr = (void *) __get_free_page(GFP_KERNEL);
4a71df50
FB		 241 if (!ptr) {
242 while (j > 0)
243 free_page((unsigned long)
244 pool_entry->elements[--j]);
245 kfree(pool_entry);
246 qeth_free_buffer_pool(card);
247 return -ENOMEM;
248 }
249 pool_entry->elements[j] = ptr;
250 }
251 list_add(&pool_entry->init_list,
252 &card->qdio.init_pool.entry_list);
253 }
254 return 0;
255}
256
257int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt)
258{
d11ba0c4 259 QETH_DBF_TEXT(TRACE, 2, "realcbp");
4a71df50
FB		 260
261 if ((card->state != CARD_STATE_DOWN) &&
262 (card->state != CARD_STATE_RECOVER))
263 return -EPERM;
264
265 /* TODO: steel/add buffers from/to a running card's buffer pool (?) */
266 qeth_clear_working_pool_list(card);
267 qeth_free_buffer_pool(card);
268 card->qdio.in_buf_pool.buf_count = bufcnt;
269 card->qdio.init_pool.buf_count = bufcnt;
270 return qeth_alloc_buffer_pool(card);
271}
272
273int qeth_set_large_send(struct qeth_card *card,
274 enum qeth_large_send_types type)
275{
276 int rc = 0;
277
278 if (card->dev == NULL) {
279 card->options.large_send = type;
280 return 0;
281 }
282 if (card->state == CARD_STATE_UP)
283 netif_tx_disable(card->dev);
284 card->options.large_send = type;
285 switch (card->options.large_send) {
286 case QETH_LARGE_SEND_EDDP:
287 card->dev->features |= NETIF_F_TSO | NETIF_F_SG |
288 NETIF_F_HW_CSUM;
289 break;
290 case QETH_LARGE_SEND_TSO:
291 if (qeth_is_supported(card, IPA_OUTBOUND_TSO)) {
292 card->dev->features |= NETIF_F_TSO | NETIF_F_SG |
293 NETIF_F_HW_CSUM;
294 } else {
4a71df50
FB		 295 card->dev->features &= ~(NETIF_F_TSO | NETIF_F_SG |
296 NETIF_F_HW_CSUM);
297 card->options.large_send = QETH_LARGE_SEND_NO;
298 rc = -EOPNOTSUPP;
299 }
300 break;
301 default: /* includes QETH_LARGE_SEND_NO */
302 card->dev->features &= ~(NETIF_F_TSO | NETIF_F_SG |
303 NETIF_F_HW_CSUM);
304 break;
305 }
306 if (card->state == CARD_STATE_UP)
307 netif_wake_queue(card->dev);
308 return rc;
309}
310EXPORT_SYMBOL_GPL(qeth_set_large_send);
311
312static int qeth_issue_next_read(struct qeth_card *card)
313{
314 int rc;
315 struct qeth_cmd_buffer *iob;
316
d11ba0c4 317 QETH_DBF_TEXT(TRACE, 5, "issnxrd");
4a71df50
FB		 318 if (card->read.state != CH_STATE_UP)
319 return -EIO;
320 iob = qeth_get_buffer(&card->read);
321 if (!iob) {
322 PRINT_WARN("issue_next_read failed: no iob available!\n");
323 return -ENOMEM;
324 }
325 qeth_setup_ccw(&card->read, iob->data, QETH_BUFSIZE);
d11ba0c4 326 QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
4a71df50
FB		 327 rc = ccw_device_start(card->read.ccwdev, &card->read.ccw,
328 (addr_t) iob, 0, 0);
329 if (rc) {
330 PRINT_ERR("Error in starting next read ccw! rc=%i\n", rc);
331 atomic_set(&card->read.irq_pending, 0);
332 qeth_schedule_recovery(card);
333 wake_up(&card->wait_q);
334 }
335 return rc;
336}
337
338static struct qeth_reply *qeth_alloc_reply(struct qeth_card *card)
339{
340 struct qeth_reply *reply;
341
342 reply = kzalloc(sizeof(struct qeth_reply), GFP_ATOMIC);
343 if (reply) {
344 atomic_set(&reply->refcnt, 1);
345 atomic_set(&reply->received, 0);
346 reply->card = card;
347 };
348 return reply;
349}
350
351static void qeth_get_reply(struct qeth_reply *reply)
352{
353 WARN_ON(atomic_read(&reply->refcnt) <= 0);
354 atomic_inc(&reply->refcnt);
355}
356
357static void qeth_put_reply(struct qeth_reply *reply)
358{
359 WARN_ON(atomic_read(&reply->refcnt) <= 0);
360 if (atomic_dec_and_test(&reply->refcnt))
361 kfree(reply);
362}
363
d11ba0c4 364static void qeth_issue_ipa_msg(struct qeth_ipa_cmd *cmd, int rc,
4a71df50
FB		 365 struct qeth_card *card)
366{
4a71df50 367 char *ipa_name;
d11ba0c4 368 int com = cmd->hdr.command;
4a71df50 369 ipa_name = qeth_get_ipa_cmd_name(com);
d11ba0c4
PT		 370 if (rc)
371 QETH_DBF_MESSAGE(2, "IPA: %s(x%X) for %s returned x%X \"%s\"\n",
372 ipa_name, com, QETH_CARD_IFNAME(card),
373 rc, qeth_get_ipa_msg(rc));
374 else
375 QETH_DBF_MESSAGE(5, "IPA: %s(x%X) for %s succeeded\n",
376 ipa_name, com, QETH_CARD_IFNAME(card));
4a71df50
FB		 377}
378
379static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card,
380 struct qeth_cmd_buffer *iob)
381{
382 struct qeth_ipa_cmd *cmd = NULL;
383
d11ba0c4 384 QETH_DBF_TEXT(TRACE, 5, "chkipad");
4a71df50
FB		 385 if (IS_IPA(iob->data)) {
386 cmd = (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data);
387 if (IS_IPA_REPLY(cmd)) {
d11ba0c4
PT		 388 if (cmd->hdr.command < IPA_CMD_SETCCID ||
389 cmd->hdr.command > IPA_CMD_MODCCID)
390 qeth_issue_ipa_msg(cmd,
391 cmd->hdr.return_code, card);
4a71df50
FB		 392 return cmd;
393 } else {
394 switch (cmd->hdr.command) {
395 case IPA_CMD_STOPLAN:
396 PRINT_WARN("Link failure on %s (CHPID 0x%X) - "
397 "there is a network problem or "
398 "someone pulled the cable or "
399 "disabled the port.\n",
400 QETH_CARD_IFNAME(card),
401 card->info.chpid);
402 card->lan_online = 0;
403 if (card->dev && netif_carrier_ok(card->dev))
404 netif_carrier_off(card->dev);
405 return NULL;
406 case IPA_CMD_STARTLAN:
407 PRINT_INFO("Link reestablished on %s "
408 "(CHPID 0x%X). Scheduling "
409 "IP address reset.\n",
410 QETH_CARD_IFNAME(card),
411 card->info.chpid);
412 netif_carrier_on(card->dev);
922dc062 413 card->lan_online = 1;
4a71df50
FB		 414 qeth_schedule_recovery(card);
415 return NULL;
416 case IPA_CMD_MODCCID:
417 return cmd;
418 case IPA_CMD_REGISTER_LOCAL_ADDR:
d11ba0c4 419 QETH_DBF_TEXT(TRACE, 3, "irla");
4a71df50
FB		 420 break;
421 case IPA_CMD_UNREGISTER_LOCAL_ADDR:
d11ba0c4 422 QETH_DBF_TEXT(TRACE, 3, "urla");
4a71df50
FB		 423 break;
424 default:
c4cef07c 425 QETH_DBF_MESSAGE(2, "Received data is IPA "
4a71df50
FB		 426 "but not a reply!\n");
427 break;
428 }
429 }
430 }
431 return cmd;
432}
433
434void qeth_clear_ipacmd_list(struct qeth_card *card)
435{
436 struct qeth_reply *reply, *r;
437 unsigned long flags;
438
d11ba0c4 439 QETH_DBF_TEXT(TRACE, 4, "clipalst");
4a71df50
FB		 440
441 spin_lock_irqsave(&card->lock, flags);
442 list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
443 qeth_get_reply(reply);
444 reply->rc = -EIO;
445 atomic_inc(&reply->received);
446 list_del_init(&reply->list);
447 wake_up(&reply->wait_q);
448 qeth_put_reply(reply);
449 }
450 spin_unlock_irqrestore(&card->lock, flags);
451}
452EXPORT_SYMBOL_GPL(qeth_clear_ipacmd_list);
453
454static int qeth_check_idx_response(unsigned char *buffer)
455{
456 if (!buffer)
457 return 0;
458
d11ba0c4 459 QETH_DBF_HEX(CTRL, 2, buffer, QETH_DBF_CTRL_LEN);
4a71df50
FB		 460 if ((buffer[2] & 0xc0) == 0xc0) {
461 PRINT_WARN("received an IDX TERMINATE "
462 "with cause code 0x%02x%s\n",
463 buffer[4],
464 ((buffer[4] == 0x22) ?
465 " -- try another portname" : ""));
d11ba0c4
PT		 466 QETH_DBF_TEXT(TRACE, 2, "ckidxres");
467 QETH_DBF_TEXT(TRACE, 2, " idxterm");
468 QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
4a71df50
FB		 469 return -EIO;
470 }
471 return 0;
472}
473
474static void qeth_setup_ccw(struct qeth_channel *channel, unsigned char *iob,
475 __u32 len)
476{
477 struct qeth_card *card;
478
d11ba0c4 479 QETH_DBF_TEXT(TRACE, 4, "setupccw");
4a71df50
FB		 480 card = CARD_FROM_CDEV(channel->ccwdev);
481 if (channel == &card->read)
482 memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
483 else
484 memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
485 channel->ccw.count = len;
486 channel->ccw.cda = (__u32) __pa(iob);
487}
488
489static struct qeth_cmd_buffer *__qeth_get_buffer(struct qeth_channel *channel)
490{
491 __u8 index;
492
d11ba0c4 493 QETH_DBF_TEXT(TRACE, 6, "getbuff");
4a71df50
FB		 494 index = channel->io_buf_no;
495 do {
496 if (channel->iob[index].state == BUF_STATE_FREE) {
497 channel->iob[index].state = BUF_STATE_LOCKED;
498 channel->io_buf_no = (channel->io_buf_no + 1) %
499 QETH_CMD_BUFFER_NO;
500 memset(channel->iob[index].data, 0, QETH_BUFSIZE);
501 return channel->iob + index;
502 }
503 index = (index + 1) % QETH_CMD_BUFFER_NO;
504 } while (index != channel->io_buf_no);
505
506 return NULL;
507}
508
509void qeth_release_buffer(struct qeth_channel *channel,
510 struct qeth_cmd_buffer *iob)
511{
512 unsigned long flags;
513
d11ba0c4 514 QETH_DBF_TEXT(TRACE, 6, "relbuff");
4a71df50
FB		 515 spin_lock_irqsave(&channel->iob_lock, flags);
516 memset(iob->data, 0, QETH_BUFSIZE);
517 iob->state = BUF_STATE_FREE;
518 iob->callback = qeth_send_control_data_cb;
519 iob->rc = 0;
520 spin_unlock_irqrestore(&channel->iob_lock, flags);
521}
522EXPORT_SYMBOL_GPL(qeth_release_buffer);
523
524static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *channel)
525{
526 struct qeth_cmd_buffer *buffer = NULL;
527 unsigned long flags;
528
529 spin_lock_irqsave(&channel->iob_lock, flags);
530 buffer = __qeth_get_buffer(channel);
531 spin_unlock_irqrestore(&channel->iob_lock, flags);
532 return buffer;
533}
534
535struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *channel)
536{
537 struct qeth_cmd_buffer *buffer;
538 wait_event(channel->wait_q,
539 ((buffer = qeth_get_buffer(channel)) != NULL));
540 return buffer;
541}
542EXPORT_SYMBOL_GPL(qeth_wait_for_buffer);
543
544void qeth_clear_cmd_buffers(struct qeth_channel *channel)
545{
546 int cnt;
547
548 for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
549 qeth_release_buffer(channel, &channel->iob[cnt]);
550 channel->buf_no = 0;
551 channel->io_buf_no = 0;
552}
553EXPORT_SYMBOL_GPL(qeth_clear_cmd_buffers);
554
555static void qeth_send_control_data_cb(struct qeth_channel *channel,
556 struct qeth_cmd_buffer *iob)
557{
558 struct qeth_card *card;
559 struct qeth_reply *reply, *r;
560 struct qeth_ipa_cmd *cmd;
561 unsigned long flags;
562 int keep_reply;
563
d11ba0c4 564 QETH_DBF_TEXT(TRACE, 4, "sndctlcb");
4a71df50
FB		 565
566 card = CARD_FROM_CDEV(channel->ccwdev);
567 if (qeth_check_idx_response(iob->data)) {
568 qeth_clear_ipacmd_list(card);
569 qeth_schedule_recovery(card);
570 goto out;
571 }
572
573 cmd = qeth_check_ipa_data(card, iob);
574 if ((cmd == NULL) && (card->state != CARD_STATE_DOWN))
575 goto out;
576 /*in case of OSN : check if cmd is set */
577 if (card->info.type == QETH_CARD_TYPE_OSN &&
578 cmd &&
579 cmd->hdr.command != IPA_CMD_STARTLAN &&
580 card->osn_info.assist_cb != NULL) {
581 card->osn_info.assist_cb(card->dev, cmd);
582 goto out;
583 }
584
585 spin_lock_irqsave(&card->lock, flags);
586 list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
587 if ((reply->seqno == QETH_IDX_COMMAND_SEQNO) ||
588 ((cmd) && (reply->seqno == cmd->hdr.seqno))) {
589 qeth_get_reply(reply);
590 list_del_init(&reply->list);
591 spin_unlock_irqrestore(&card->lock, flags);
592 keep_reply = 0;
593 if (reply->callback != NULL) {
594 if (cmd) {
595 reply->offset = (__u16)((char *)cmd -
596 (char *)iob->data);
597 keep_reply = reply->callback(card,
598 reply,
599 (unsigned long)cmd);
600 } else
601 keep_reply = reply->callback(card,
602 reply,
603 (unsigned long)iob);
604 }
605 if (cmd)
606 reply->rc = (u16) cmd->hdr.return_code;
607 else if (iob->rc)
608 reply->rc = iob->rc;
609 if (keep_reply) {
610 spin_lock_irqsave(&card->lock, flags);
611 list_add_tail(&reply->list,
612 &card->cmd_waiter_list);
613 spin_unlock_irqrestore(&card->lock, flags);
614 } else {
615 atomic_inc(&reply->received);
616 wake_up(&reply->wait_q);
617 }
618 qeth_put_reply(reply);
619 goto out;
620 }
621 }
622 spin_unlock_irqrestore(&card->lock, flags);
623out:
624 memcpy(&card->seqno.pdu_hdr_ack,
625 QETH_PDU_HEADER_SEQ_NO(iob->data),
626 QETH_SEQ_NO_LENGTH);
627 qeth_release_buffer(channel, iob);
628}
629
630static int qeth_setup_channel(struct qeth_channel *channel)
631{
632 int cnt;
633
d11ba0c4 634 QETH_DBF_TEXT(SETUP, 2, "setupch");
4a71df50
FB		 635 for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) {
636 channel->iob[cnt].data = (char *)
637 kmalloc(QETH_BUFSIZE, GFP_DMA|GFP_KERNEL);
638 if (channel->iob[cnt].data == NULL)
639 break;
640 channel->iob[cnt].state = BUF_STATE_FREE;
641 channel->iob[cnt].channel = channel;
642 channel->iob[cnt].callback = qeth_send_control_data_cb;
643 channel->iob[cnt].rc = 0;
644 }
645 if (cnt < QETH_CMD_BUFFER_NO) {
646 while (cnt-- > 0)
647 kfree(channel->iob[cnt].data);
648 return -ENOMEM;
649 }
650 channel->buf_no = 0;
651 channel->io_buf_no = 0;
652 atomic_set(&channel->irq_pending, 0);
653 spin_lock_init(&channel->iob_lock);
654
655 init_waitqueue_head(&channel->wait_q);
656 return 0;
657}
658
659static int qeth_set_thread_start_bit(struct qeth_card *card,
660 unsigned long thread)
661{
662 unsigned long flags;
663
664 spin_lock_irqsave(&card->thread_mask_lock, flags);
665 if (!(card->thread_allowed_mask & thread) ||
666 (card->thread_start_mask & thread)) {
667 spin_unlock_irqrestore(&card->thread_mask_lock, flags);
668 return -EPERM;
669 }
670 card->thread_start_mask |= thread;
671 spin_unlock_irqrestore(&card->thread_mask_lock, flags);
672 return 0;
673}
674
675void qeth_clear_thread_start_bit(struct qeth_card *card, unsigned long thread)
676{
677 unsigned long flags;
678
679 spin_lock_irqsave(&card->thread_mask_lock, flags);
680 card->thread_start_mask &= ~thread;
681 spin_unlock_irqrestore(&card->thread_mask_lock, flags);
682 wake_up(&card->wait_q);
683}
684EXPORT_SYMBOL_GPL(qeth_clear_thread_start_bit);
685
686void qeth_clear_thread_running_bit(struct qeth_card *card, unsigned long thread)
687{
688 unsigned long flags;
689
690 spin_lock_irqsave(&card->thread_mask_lock, flags);
691 card->thread_running_mask &= ~thread;
692 spin_unlock_irqrestore(&card->thread_mask_lock, flags);
693 wake_up(&card->wait_q);
694}
695EXPORT_SYMBOL_GPL(qeth_clear_thread_running_bit);
696
697static int __qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
698{
699 unsigned long flags;
700 int rc = 0;
701
702 spin_lock_irqsave(&card->thread_mask_lock, flags);
703 if (card->thread_start_mask & thread) {
704 if ((card->thread_allowed_mask & thread) &&
705 !(card->thread_running_mask & thread)) {
706 rc = 1;
707 card->thread_start_mask &= ~thread;
708 card->thread_running_mask |= thread;
709 } else
710 rc = -EPERM;
711 }
712 spin_unlock_irqrestore(&card->thread_mask_lock, flags);
713 return rc;
714}
715
716int qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
717{
718 int rc = 0;
719
720 wait_event(card->wait_q,
721 (rc = __qeth_do_run_thread(card, thread)) >= 0);
722 return rc;
723}
724EXPORT_SYMBOL_GPL(qeth_do_run_thread);
725
726void qeth_schedule_recovery(struct qeth_card *card)
727{
d11ba0c4 728 QETH_DBF_TEXT(TRACE, 2, "startrec");
4a71df50
FB		 729 if (qeth_set_thread_start_bit(card, QETH_RECOVER_THREAD) == 0)
730 schedule_work(&card->kernel_thread_starter);
731}
732EXPORT_SYMBOL_GPL(qeth_schedule_recovery);
733
734static int qeth_get_problem(struct ccw_device *cdev, struct irb *irb)
735{
736 int dstat, cstat;
737 char *sense;
738
739 sense = (char *) irb->ecw;
23d805b6
PO		 740 cstat = irb->scsw.cmd.cstat;
741 dstat = irb->scsw.cmd.dstat;
4a71df50
FB		 742
743 if (cstat & (SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK |
744 SCHN_STAT_CHN_DATA_CHK | SCHN_STAT_CHAIN_CHECK |
745 SCHN_STAT_PROT_CHECK | SCHN_STAT_PROG_CHECK)) {
d11ba0c4 746 QETH_DBF_TEXT(TRACE, 2, "CGENCHK");
4a71df50 747 PRINT_WARN("check on device %s, dstat=x%x, cstat=x%x ",
2a0217d5 748 dev_name(&cdev->dev), dstat, cstat);
4a71df50
FB		 749 print_hex_dump(KERN_WARNING, "qeth: irb ", DUMP_PREFIX_OFFSET,
750 16, 1, irb, 64, 1);
751 return 1;
752 }
753
754 if (dstat & DEV_STAT_UNIT_CHECK) {
755 if (sense[SENSE_RESETTING_EVENT_BYTE] &
756 SENSE_RESETTING_EVENT_FLAG) {
d11ba0c4 757 QETH_DBF_TEXT(TRACE, 2, "REVIND");
4a71df50
FB		 758 return 1;
759 }
760 if (sense[SENSE_COMMAND_REJECT_BYTE] &
761 SENSE_COMMAND_REJECT_FLAG) {
d11ba0c4 762 QETH_DBF_TEXT(TRACE, 2, "CMDREJi");
28a7e4c9 763 return 1;
4a71df50
FB		 764 }
765 if ((sense[2] == 0xaf) && (sense[3] == 0xfe)) {
d11ba0c4 766 QETH_DBF_TEXT(TRACE, 2, "AFFE");
4a71df50
FB		 767 return 1;
768 }
769 if ((!sense[0]) && (!sense[1]) && (!sense[2]) && (!sense[3])) {
d11ba0c4 770 QETH_DBF_TEXT(TRACE, 2, "ZEROSEN");
4a71df50
FB		 771 return 0;
772 }
d11ba0c4 773 QETH_DBF_TEXT(TRACE, 2, "DGENCHK");
4a71df50
FB		 774 return 1;
775 }
776 return 0;
777}
778
779static long __qeth_check_irb_error(struct ccw_device *cdev,
780 unsigned long intparm, struct irb *irb)
781{
782 if (!IS_ERR(irb))
783 return 0;
784
785 switch (PTR_ERR(irb)) {
786 case -EIO:
2a0217d5 787 PRINT_WARN("i/o-error on device %s\n", dev_name(&cdev->dev));
d11ba0c4
PT		 788 QETH_DBF_TEXT(TRACE, 2, "ckirberr");
789 QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
4a71df50
FB		 790 break;
791 case -ETIMEDOUT:
2a0217d5 792 PRINT_WARN("timeout on device %s\n", dev_name(&cdev->dev));
d11ba0c4
PT		 793 QETH_DBF_TEXT(TRACE, 2, "ckirberr");
794 QETH_DBF_TEXT_(TRACE, 2, " rc%d", -ETIMEDOUT);
4a71df50
FB		 795 if (intparm == QETH_RCD_PARM) {
796 struct qeth_card *card = CARD_FROM_CDEV(cdev);
797
798 if (card && (card->data.ccwdev == cdev)) {
799 card->data.state = CH_STATE_DOWN;
800 wake_up(&card->wait_q);
801 }
802 }
803 break;
804 default:
805 PRINT_WARN("unknown error %ld on device %s\n", PTR_ERR(irb),
2a0217d5 806 dev_name(&cdev->dev));
d11ba0c4
PT		 807 QETH_DBF_TEXT(TRACE, 2, "ckirberr");
808 QETH_DBF_TEXT(TRACE, 2, " rc???");
4a71df50
FB		 809 }
810 return PTR_ERR(irb);
811}
812
813static void qeth_irq(struct ccw_device *cdev, unsigned long intparm,
814 struct irb *irb)
815{
816 int rc;
817 int cstat, dstat;
818 struct qeth_cmd_buffer *buffer;
819 struct qeth_channel *channel;
820 struct qeth_card *card;
821 struct qeth_cmd_buffer *iob;
822 __u8 index;
823
d11ba0c4 824 QETH_DBF_TEXT(TRACE, 5, "irq");
4a71df50
FB		 825
826 if (__qeth_check_irb_error(cdev, intparm, irb))
827 return;
23d805b6
PO		 828 cstat = irb->scsw.cmd.cstat;
829 dstat = irb->scsw.cmd.dstat;
4a71df50
FB		 830
831 card = CARD_FROM_CDEV(cdev);
832 if (!card)
833 return;
834
835 if (card->read.ccwdev == cdev) {
836 channel = &card->read;
d11ba0c4 837 QETH_DBF_TEXT(TRACE, 5, "read");
4a71df50
FB		 838 } else if (card->write.ccwdev == cdev) {
839 channel = &card->write;
d11ba0c4 840 QETH_DBF_TEXT(TRACE, 5, "write");
4a71df50
FB		 841 } else {
842 channel = &card->data;
d11ba0c4 843 QETH_DBF_TEXT(TRACE, 5, "data");
4a71df50
FB		 844 }
845 atomic_set(&channel->irq_pending, 0);
846
23d805b6 847 if (irb->scsw.cmd.fctl & (SCSW_FCTL_CLEAR_FUNC))
4a71df50
FB		 848 channel->state = CH_STATE_STOPPED;
849
23d805b6 850 if (irb->scsw.cmd.fctl & (SCSW_FCTL_HALT_FUNC))
4a71df50
FB		 851 channel->state = CH_STATE_HALTED;
852
853 /*let's wake up immediately on data channel*/
854 if ((channel == &card->data) && (intparm != 0) &&
855 (intparm != QETH_RCD_PARM))
856 goto out;
857
858 if (intparm == QETH_CLEAR_CHANNEL_PARM) {
d11ba0c4 859 QETH_DBF_TEXT(TRACE, 6, "clrchpar");
4a71df50
FB		 860 /* we don't have to handle this further */
861 intparm = 0;
862 }
863 if (intparm == QETH_HALT_CHANNEL_PARM) {
d11ba0c4 864 QETH_DBF_TEXT(TRACE, 6, "hltchpar");
4a71df50
FB		 865 /* we don't have to handle this further */
866 intparm = 0;
867 }
868 if ((dstat & DEV_STAT_UNIT_EXCEP) ||
869 (dstat & DEV_STAT_UNIT_CHECK) ||
870 (cstat)) {
871 if (irb->esw.esw0.erw.cons) {
872 /* TODO: we should make this s390dbf */
873 PRINT_WARN("sense data available on channel %s.\n",
874 CHANNEL_ID(channel));
875 PRINT_WARN(" cstat 0x%X\n dstat 0x%X\n", cstat, dstat);
876 print_hex_dump(KERN_WARNING, "qeth: irb ",
877 DUMP_PREFIX_OFFSET, 16, 1, irb, 32, 1);
878 print_hex_dump(KERN_WARNING, "qeth: sense data ",
879 DUMP_PREFIX_OFFSET, 16, 1, irb->ecw, 32, 1);
880 }
881 if (intparm == QETH_RCD_PARM) {
882 channel->state = CH_STATE_DOWN;
883 goto out;
884 }
885 rc = qeth_get_problem(cdev, irb);
886 if (rc) {
28a7e4c9 887 qeth_clear_ipacmd_list(card);
4a71df50
FB		 888 qeth_schedule_recovery(card);
889 goto out;
890 }
891 }
892
893 if (intparm == QETH_RCD_PARM) {
894 channel->state = CH_STATE_RCD_DONE;
895 goto out;
896 }
897 if (intparm) {
898 buffer = (struct qeth_cmd_buffer *) __va((addr_t)intparm);
899 buffer->state = BUF_STATE_PROCESSED;
900 }
901 if (channel == &card->data)
902 return;
903 if (channel == &card->read &&
904 channel->state == CH_STATE_UP)
905 qeth_issue_next_read(card);
906
907 iob = channel->iob;
908 index = channel->buf_no;
909 while (iob[index].state == BUF_STATE_PROCESSED) {
910 if (iob[index].callback != NULL)
911 iob[index].callback(channel, iob + index);
912
913 index = (index + 1) % QETH_CMD_BUFFER_NO;
914 }
915 channel->buf_no = index;
916out:
917 wake_up(&card->wait_q);
918 return;
919}
920
921static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
922 struct qeth_qdio_out_buffer *buf)
923{
924 int i;
925 struct sk_buff *skb;
926
927 /* is PCI flag set on buffer? */
928 if (buf->buffer->element[0].flags & 0x40)
929 atomic_dec(&queue->set_pci_flags_count);
930
931 skb = skb_dequeue(&buf->skb_list);
932 while (skb) {
933 atomic_dec(&skb->users);
934 dev_kfree_skb_any(skb);
935 skb = skb_dequeue(&buf->skb_list);
936 }
937 qeth_eddp_buf_release_contexts(buf);
938 for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(queue->card); ++i) {
683d718a
FB		 939 if (buf->buffer->element[i].addr && buf->is_header[i])
940 kmem_cache_free(qeth_core_header_cache,
941 buf->buffer->element[i].addr);
942 buf->is_header[i] = 0;
4a71df50
FB		 943 buf->buffer->element[i].length = 0;
944 buf->buffer->element[i].addr = NULL;
945 buf->buffer->element[i].flags = 0;
946 }
947 buf->next_element_to_fill = 0;
948 atomic_set(&buf->state, QETH_QDIO_BUF_EMPTY);
949}
950
951void qeth_clear_qdio_buffers(struct qeth_card *card)
952{
953 int i, j;
954
d11ba0c4 955 QETH_DBF_TEXT(TRACE, 2, "clearqdbf");
4a71df50
FB		 956 /* clear outbound buffers to free skbs */
957 for (i = 0; i < card->qdio.no_out_queues; ++i)
958 if (card->qdio.out_qs[i]) {
959 for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
960 qeth_clear_output_buffer(card->qdio.out_qs[i],
961 &card->qdio.out_qs[i]->bufs[j]);
962 }
963}
964EXPORT_SYMBOL_GPL(qeth_clear_qdio_buffers);
965
966static void qeth_free_buffer_pool(struct qeth_card *card)
967{
968 struct qeth_buffer_pool_entry *pool_entry, *tmp;
969 int i = 0;
d11ba0c4 970 QETH_DBF_TEXT(TRACE, 5, "freepool");
4a71df50
FB		 971 list_for_each_entry_safe(pool_entry, tmp,
972 &card->qdio.init_pool.entry_list, init_list){
973 for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i)
974 free_page((unsigned long)pool_entry->elements[i]);
975 list_del(&pool_entry->init_list);
976 kfree(pool_entry);
977 }
978}
979
980static void qeth_free_qdio_buffers(struct qeth_card *card)
981{
982 int i, j;
983
d11ba0c4 984 QETH_DBF_TEXT(TRACE, 2, "freeqdbf");
4a71df50
FB		 985 if (atomic_xchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED) ==
986 QETH_QDIO_UNINITIALIZED)
987 return;
988 kfree(card->qdio.in_q);
989 card->qdio.in_q = NULL;
990 /* inbound buffer pool */
991 qeth_free_buffer_pool(card);
992 /* free outbound qdio_qs */
993 if (card->qdio.out_qs) {
994 for (i = 0; i < card->qdio.no_out_queues; ++i) {
995 for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
996 qeth_clear_output_buffer(card->qdio.out_qs[i],
997 &card->qdio.out_qs[i]->bufs[j]);
998 kfree(card->qdio.out_qs[i]);
999 }
1000 kfree(card->qdio.out_qs);
1001 card->qdio.out_qs = NULL;
1002 }
1003}
1004
1005static void qeth_clean_channel(struct qeth_channel *channel)
1006{
1007 int cnt;
1008
d11ba0c4 1009 QETH_DBF_TEXT(SETUP, 2, "freech");
4a71df50
FB		 1010 for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
1011 kfree(channel->iob[cnt].data);
1012}
1013
1014static int qeth_is_1920_device(struct qeth_card *card)
1015{
1016 int single_queue = 0;
1017 struct ccw_device *ccwdev;
1018 struct channelPath_dsc {
1019 u8 flags;
1020 u8 lsn;
1021 u8 desc;
1022 u8 chpid;
1023 u8 swla;
1024 u8 zeroes;
1025 u8 chla;
1026 u8 chpp;
1027 } *chp_dsc;
1028
d11ba0c4 1029 QETH_DBF_TEXT(SETUP, 2, "chk_1920");
4a71df50
FB		 1030
1031 ccwdev = card->data.ccwdev;
1032 chp_dsc = (struct channelPath_dsc *)ccw_device_get_chp_desc(ccwdev, 0);
1033 if (chp_dsc != NULL) {
1034 /* CHPP field bit 6 == 1 -> single queue */
1035 single_queue = ((chp_dsc->chpp & 0x02) == 0x02);
1036 kfree(chp_dsc);
1037 }
d11ba0c4 1038 QETH_DBF_TEXT_(SETUP, 2, "rc:%x", single_queue);
4a71df50
FB		 1039 return single_queue;
1040}
1041
1042static void qeth_init_qdio_info(struct qeth_card *card)
1043{
d11ba0c4 1044 QETH_DBF_TEXT(SETUP, 4, "intqdinf");
4a71df50
FB		 1045 atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
1046 /* inbound */
1047 card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
1048 card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_DEFAULT;
1049 card->qdio.in_buf_pool.buf_count = card->qdio.init_pool.buf_count;
1050 INIT_LIST_HEAD(&card->qdio.in_buf_pool.entry_list);
1051 INIT_LIST_HEAD(&card->qdio.init_pool.entry_list);
1052}
1053
1054static void qeth_set_intial_options(struct qeth_card *card)
1055{
1056 card->options.route4.type = NO_ROUTER;
1057 card->options.route6.type = NO_ROUTER;
1058 card->options.checksum_type = QETH_CHECKSUM_DEFAULT;
1059 card->options.broadcast_mode = QETH_TR_BROADCAST_ALLRINGS;
1060 card->options.macaddr_mode = QETH_TR_MACADDR_NONCANONICAL;
1061 card->options.fake_broadcast = 0;
1062 card->options.add_hhlen = DEFAULT_ADD_HHLEN;
1063 card->options.fake_ll = 0;
1064 card->options.performance_stats = 0;
1065 card->options.rx_sg_cb = QETH_RX_SG_CB;
1066}
1067
1068static int qeth_do_start_thread(struct qeth_card *card, unsigned long thread)
1069{
1070 unsigned long flags;
1071 int rc = 0;
1072
1073 spin_lock_irqsave(&card->thread_mask_lock, flags);
d11ba0c4 1074 QETH_DBF_TEXT_(TRACE, 4, " %02x%02x%02x",
4a71df50
FB		 1075 (u8) card->thread_start_mask,
1076 (u8) card->thread_allowed_mask,
1077 (u8) card->thread_running_mask);
1078 rc = (card->thread_start_mask & thread);
1079 spin_unlock_irqrestore(&card->thread_mask_lock, flags);
1080 return rc;
1081}
1082
1083static void qeth_start_kernel_thread(struct work_struct *work)
1084{
1085 struct qeth_card *card = container_of(work, struct qeth_card,
1086 kernel_thread_starter);
d11ba0c4 1087 QETH_DBF_TEXT(TRACE , 2, "strthrd");
4a71df50
FB		 1088
1089 if (card->read.state != CH_STATE_UP &&
1090 card->write.state != CH_STATE_UP)
1091 return;
1092 if (qeth_do_start_thread(card, QETH_RECOVER_THREAD))
1093 kthread_run(card->discipline.recover, (void *) card,
1094 "qeth_recover");
1095}
1096
1097static int qeth_setup_card(struct qeth_card *card)
1098{
1099
d11ba0c4
PT		 1100 QETH_DBF_TEXT(SETUP, 2, "setupcrd");
1101 QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
4a71df50
FB		 1102
1103 card->read.state = CH_STATE_DOWN;
1104 card->write.state = CH_STATE_DOWN;
1105 card->data.state = CH_STATE_DOWN;
1106 card->state = CARD_STATE_DOWN;
1107 card->lan_online = 0;
1108 card->use_hard_stop = 0;
1109 card->dev = NULL;
1110 spin_lock_init(&card->vlanlock);
1111 spin_lock_init(&card->mclock);
1112 card->vlangrp = NULL;
1113 spin_lock_init(&card->lock);
1114 spin_lock_init(&card->ip_lock);
1115 spin_lock_init(&card->thread_mask_lock);
1116 card->thread_start_mask = 0;
1117 card->thread_allowed_mask = 0;
1118 card->thread_running_mask = 0;
1119 INIT_WORK(&card->kernel_thread_starter, qeth_start_kernel_thread);
1120 INIT_LIST_HEAD(&card->ip_list);
1121 card->ip_tbd_list = kmalloc(sizeof(struct list_head), GFP_KERNEL);
1122 if (!card->ip_tbd_list) {
d11ba0c4 1123 QETH_DBF_TEXT(SETUP, 0, "iptbdnom");
4a71df50
FB		 1124 return -ENOMEM;
1125 }
1126 INIT_LIST_HEAD(card->ip_tbd_list);
1127 INIT_LIST_HEAD(&card->cmd_waiter_list);
1128 init_waitqueue_head(&card->wait_q);
1129 /* intial options */
1130 qeth_set_intial_options(card);
1131 /* IP address takeover */
1132 INIT_LIST_HEAD(&card->ipato.entries);
1133 card->ipato.enabled = 0;
1134 card->ipato.invert4 = 0;
1135 card->ipato.invert6 = 0;
1136 /* init QDIO stuff */
1137 qeth_init_qdio_info(card);
1138 return 0;
1139}
1140
6bcac508
MS		 1141static void qeth_core_sl_print(struct seq_file *m, struct service_level *slr)
1142{
1143 struct qeth_card *card = container_of(slr, struct qeth_card,
1144 qeth_service_level);
1145 seq_printf(m, "qeth: %s firmware level %s\n", CARD_BUS_ID(card),
1146 card->info.mcl_level);
1147}
1148
4a71df50
FB		 1149static struct qeth_card *qeth_alloc_card(void)
1150{
1151 struct qeth_card *card;
1152
d11ba0c4 1153 QETH_DBF_TEXT(SETUP, 2, "alloccrd");
4a71df50
FB		 1154 card = kzalloc(sizeof(struct qeth_card), GFP_DMA|GFP_KERNEL);
1155 if (!card)
1156 return NULL;
d11ba0c4 1157 QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
4a71df50
FB		 1158 if (qeth_setup_channel(&card->read)) {
1159 kfree(card);
1160 return NULL;
1161 }
1162 if (qeth_setup_channel(&card->write)) {
1163 qeth_clean_channel(&card->read);
1164 kfree(card);
1165 return NULL;
1166 }
1167 card->options.layer2 = -1;
6bcac508
MS		 1168 card->qeth_service_level.seq_print = qeth_core_sl_print;
1169 register_service_level(&card->qeth_service_level);
4a71df50
FB		 1170 return card;
1171}
1172
1173static int qeth_determine_card_type(struct qeth_card *card)
1174{
1175 int i = 0;
1176
d11ba0c4 1177 QETH_DBF_TEXT(SETUP, 2, "detcdtyp");
4a71df50
FB		 1178
1179 card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT;
1180 card->qdio.default_out_queue = QETH_DEFAULT_QUEUE;
1181 while (known_devices[i][4]) {
1182 if ((CARD_RDEV(card)->id.dev_type == known_devices[i][2]) &&
1183 (CARD_RDEV(card)->id.dev_model == known_devices[i][3])) {
1184 card->info.type = known_devices[i][4];
1185 card->qdio.no_out_queues = known_devices[i][8];
1186 card->info.is_multicast_different = known_devices[i][9];
1187 if (qeth_is_1920_device(card)) {
1188 PRINT_INFO("Priority Queueing not able "
1189 "due to hardware limitations!\n");
1190 card->qdio.no_out_queues = 1;
1191 card->qdio.default_out_queue = 0;
1192 }
1193 return 0;
1194 }
1195 i++;
1196 }
1197 card->info.type = QETH_CARD_TYPE_UNKNOWN;
1198 PRINT_ERR("unknown card type on device %s\n", CARD_BUS_ID(card));
1199 return -ENOENT;
1200}
1201
1202static int qeth_clear_channel(struct qeth_channel *channel)
1203{
1204 unsigned long flags;
1205 struct qeth_card *card;
1206 int rc;
1207
d11ba0c4 1208 QETH_DBF_TEXT(TRACE, 3, "clearch");
4a71df50
FB		 1209 card = CARD_FROM_CDEV(channel->ccwdev);
1210 spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
1211 rc = ccw_device_clear(channel->ccwdev, QETH_CLEAR_CHANNEL_PARM);
1212 spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
1213
1214 if (rc)
1215 return rc;
1216 rc = wait_event_interruptible_timeout(card->wait_q,
1217 channel->state == CH_STATE_STOPPED, QETH_TIMEOUT);
1218 if (rc == -ERESTARTSYS)
1219 return rc;
1220 if (channel->state != CH_STATE_STOPPED)
1221 return -ETIME;
1222 channel->state = CH_STATE_DOWN;
1223 return 0;
1224}
1225
1226static int qeth_halt_channel(struct qeth_channel *channel)
1227{
1228 unsigned long flags;
1229 struct qeth_card *card;
1230 int rc;
1231
d11ba0c4 1232 QETH_DBF_TEXT(TRACE, 3, "haltch");
4a71df50
FB		 1233 card = CARD_FROM_CDEV(channel->ccwdev);
1234 spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
1235 rc = ccw_device_halt(channel->ccwdev, QETH_HALT_CHANNEL_PARM);
1236 spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
1237
1238 if (rc)
1239 return rc;
1240 rc = wait_event_interruptible_timeout(card->wait_q,
1241 channel->state == CH_STATE_HALTED, QETH_TIMEOUT);
1242 if (rc == -ERESTARTSYS)
1243 return rc;
1244 if (channel->state != CH_STATE_HALTED)
1245 return -ETIME;
1246 return 0;
1247}
1248
1249static int qeth_halt_channels(struct qeth_card *card)
1250{
1251 int rc1 = 0, rc2 = 0, rc3 = 0;
1252
d11ba0c4 1253 QETH_DBF_TEXT(TRACE, 3, "haltchs");
4a71df50
FB		 1254 rc1 = qeth_halt_channel(&card->read);
1255 rc2 = qeth_halt_channel(&card->write);
1256 rc3 = qeth_halt_channel(&card->data);
1257 if (rc1)
1258 return rc1;
1259 if (rc2)
1260 return rc2;
1261 return rc3;
1262}
1263
1264static int qeth_clear_channels(struct qeth_card *card)
1265{
1266 int rc1 = 0, rc2 = 0, rc3 = 0;
1267
d11ba0c4 1268 QETH_DBF_TEXT(TRACE, 3, "clearchs");
4a71df50
FB		 1269 rc1 = qeth_clear_channel(&card->read);
1270 rc2 = qeth_clear_channel(&card->write);
1271 rc3 = qeth_clear_channel(&card->data);
1272 if (rc1)
1273 return rc1;
1274 if (rc2)
1275 return rc2;
1276 return rc3;
1277}
1278
1279static int qeth_clear_halt_card(struct qeth_card *card, int halt)
1280{
1281 int rc = 0;
1282
d11ba0c4
PT		 1283 QETH_DBF_TEXT(TRACE, 3, "clhacrd");
1284 QETH_DBF_HEX(TRACE, 3, &card, sizeof(void *));
4a71df50
FB		 1285
1286 if (halt)
1287 rc = qeth_halt_channels(card);
1288 if (rc)
1289 return rc;
1290 return qeth_clear_channels(card);
1291}
1292
1293int qeth_qdio_clear_card(struct qeth_card *card, int use_halt)
1294{
1295 int rc = 0;
1296
d11ba0c4 1297 QETH_DBF_TEXT(TRACE, 3, "qdioclr");
4a71df50
FB		 1298 switch (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ESTABLISHED,
1299 QETH_QDIO_CLEANING)) {
1300 case QETH_QDIO_ESTABLISHED:
1301 if (card->info.type == QETH_CARD_TYPE_IQD)
1302 rc = qdio_cleanup(CARD_DDEV(card),
1303 QDIO_FLAG_CLEANUP_USING_HALT);
1304 else
1305 rc = qdio_cleanup(CARD_DDEV(card),
1306 QDIO_FLAG_CLEANUP_USING_CLEAR);
1307 if (rc)
d11ba0c4 1308 QETH_DBF_TEXT_(TRACE, 3, "1err%d", rc);
4a71df50
FB		 1309 atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
1310 break;
1311 case QETH_QDIO_CLEANING:
1312 return rc;
1313 default:
1314 break;
1315 }
1316 rc = qeth_clear_halt_card(card, use_halt);
1317 if (rc)
d11ba0c4 1318 QETH_DBF_TEXT_(TRACE, 3, "2err%d", rc);
4a71df50
FB		 1319 card->state = CARD_STATE_DOWN;
1320 return rc;
1321}
1322EXPORT_SYMBOL_GPL(qeth_qdio_clear_card);
1323
1324static int qeth_read_conf_data(struct qeth_card *card, void **buffer,
1325 int *length)
1326{
1327 struct ciw *ciw;
1328 char *rcd_buf;
1329 int ret;
1330 struct qeth_channel *channel = &card->data;
1331 unsigned long flags;
1332
1333 /*
1334 * scan for RCD command in extended SenseID data
1335 */
1336 ciw = ccw_device_get_ciw(channel->ccwdev, CIW_TYPE_RCD);
1337 if (!ciw || ciw->cmd == 0)
1338 return -EOPNOTSUPP;
1339 rcd_buf = kzalloc(ciw->count, GFP_KERNEL | GFP_DMA);
1340 if (!rcd_buf)
1341 return -ENOMEM;
1342
1343 channel->ccw.cmd_code = ciw->cmd;
1344 channel->ccw.cda = (__u32) __pa(rcd_buf);
1345 channel->ccw.count = ciw->count;
1346 channel->ccw.flags = CCW_FLAG_SLI;
1347 channel->state = CH_STATE_RCD;
1348 spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
1349 ret = ccw_device_start_timeout(channel->ccwdev, &channel->ccw,
1350 QETH_RCD_PARM, LPM_ANYPATH, 0,
1351 QETH_RCD_TIMEOUT);
1352 spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
1353 if (!ret)
1354 wait_event(card->wait_q,
1355 (channel->state == CH_STATE_RCD_DONE ||
1356 channel->state == CH_STATE_DOWN));
1357 if (channel->state == CH_STATE_DOWN)
1358 ret = -EIO;
1359 else
1360 channel->state = CH_STATE_DOWN;
1361 if (ret) {
1362 kfree(rcd_buf);
1363 *buffer = NULL;
1364 *length = 0;
1365 } else {
1366 *length = ciw->count;
1367 *buffer = rcd_buf;
1368 }
1369 return ret;
1370}
1371
1372static int qeth_get_unitaddr(struct qeth_card *card)
1373{
1374 int length;
1375 char *prcd;
1376 int rc;
1377
d11ba0c4 1378 QETH_DBF_TEXT(SETUP, 2, "getunit");
4a71df50
FB		 1379 rc = qeth_read_conf_data(card, (void **) &prcd, &length);
1380 if (rc) {
1381 PRINT_ERR("qeth_read_conf_data for device %s returned %i\n",
1382 CARD_DDEV_ID(card), rc);
1383 return rc;
1384 }
1385 card->info.chpid = prcd[30];
1386 card->info.unit_addr2 = prcd[31];
1387 card->info.cula = prcd[63];
1388 card->info.guestlan = ((prcd[0x10] == _ascebc['V']) &&
1389 (prcd[0x11] == _ascebc['M']));
1390 kfree(prcd);
1391 return 0;
1392}
1393
1394static void qeth_init_tokens(struct qeth_card *card)
1395{
1396 card->token.issuer_rm_w = 0x00010103UL;
1397 card->token.cm_filter_w = 0x00010108UL;
1398 card->token.cm_connection_w = 0x0001010aUL;
1399 card->token.ulp_filter_w = 0x0001010bUL;
1400 card->token.ulp_connection_w = 0x0001010dUL;
1401}
1402
1403static void qeth_init_func_level(struct qeth_card *card)
1404{
1405 if (card->ipato.enabled) {
1406 if (card->info.type == QETH_CARD_TYPE_IQD)
1407 card->info.func_level =
1408 QETH_IDX_FUNC_LEVEL_IQD_ENA_IPAT;
1409 else
1410 card->info.func_level =
1411 QETH_IDX_FUNC_LEVEL_OSAE_ENA_IPAT;
1412 } else {
1413 if (card->info.type == QETH_CARD_TYPE_IQD)
1414 /*FIXME:why do we have same values for dis and ena for
1415 osae??? */
1416 card->info.func_level =
1417 QETH_IDX_FUNC_LEVEL_IQD_DIS_IPAT;
1418 else
1419 card->info.func_level =
1420 QETH_IDX_FUNC_LEVEL_OSAE_DIS_IPAT;
1421 }
1422}
1423
4a71df50
FB		 1424static int qeth_idx_activate_get_answer(struct qeth_channel *channel,
1425 void (*idx_reply_cb)(struct qeth_channel *,
1426 struct qeth_cmd_buffer *))
1427{
1428 struct qeth_cmd_buffer *iob;
1429 unsigned long flags;
1430 int rc;
1431 struct qeth_card *card;
1432
d11ba0c4 1433 QETH_DBF_TEXT(SETUP, 2, "idxanswr");
4a71df50
FB		 1434 card = CARD_FROM_CDEV(channel->ccwdev);
1435 iob = qeth_get_buffer(channel);
1436 iob->callback = idx_reply_cb;
1437 memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
1438 channel->ccw.count = QETH_BUFSIZE;
1439 channel->ccw.cda = (__u32) __pa(iob->data);
1440
1441 wait_event(card->wait_q,
1442 atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
d11ba0c4 1443 QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
4a71df50
FB		 1444 spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
1445 rc = ccw_device_start(channel->ccwdev,
1446 &channel->ccw, (addr_t) iob, 0, 0);
1447 spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
1448
1449 if (rc) {
14cc21b6 1450 QETH_DBF_MESSAGE(2, "Error2 in activating channel rc=%d\n", rc);
d11ba0c4 1451 QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
4a71df50
FB		 1452 atomic_set(&channel->irq_pending, 0);
1453 wake_up(&card->wait_q);
1454 return rc;
1455 }
1456 rc = wait_event_interruptible_timeout(card->wait_q,
1457 channel->state == CH_STATE_UP, QETH_TIMEOUT);
1458 if (rc == -ERESTARTSYS)
1459 return rc;
1460 if (channel->state != CH_STATE_UP) {
1461 rc = -ETIME;
d11ba0c4 1462 QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
4a71df50
FB		 1463 qeth_clear_cmd_buffers(channel);
1464 } else
1465 rc = 0;
1466 return rc;
1467}
1468
1469static int qeth_idx_activate_channel(struct qeth_channel *channel,
1470 void (*idx_reply_cb)(struct qeth_channel *,
1471 struct qeth_cmd_buffer *))
1472{
1473 struct qeth_card *card;
1474 struct qeth_cmd_buffer *iob;
1475 unsigned long flags;
1476 __u16 temp;
1477 __u8 tmp;
1478 int rc;
f06f6f32 1479 struct ccw_dev_id temp_devid;
4a71df50
FB		 1480
1481 card = CARD_FROM_CDEV(channel->ccwdev);
1482
d11ba0c4 1483 QETH_DBF_TEXT(SETUP, 2, "idxactch");
4a71df50
FB		 1484
1485 iob = qeth_get_buffer(channel);
1486 iob->callback = idx_reply_cb;
1487 memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
1488 channel->ccw.count = IDX_ACTIVATE_SIZE;
1489 channel->ccw.cda = (__u32) __pa(iob->data);
1490 if (channel == &card->write) {
1491 memcpy(iob->data, IDX_ACTIVATE_WRITE, IDX_ACTIVATE_SIZE);
1492 memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
1493 &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
1494 card->seqno.trans_hdr++;
1495 } else {
1496 memcpy(iob->data, IDX_ACTIVATE_READ, IDX_ACTIVATE_SIZE);
1497 memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
1498 &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
1499 }
1500 tmp = ((__u8)card->info.portno) | 0x80;
1501 memcpy(QETH_IDX_ACT_PNO(iob->data), &tmp, 1);
1502 memcpy(QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
1503 &card->token.issuer_rm_w, QETH_MPC_TOKEN_LENGTH);
1504 memcpy(QETH_IDX_ACT_FUNC_LEVEL(iob->data),
1505 &card->info.func_level, sizeof(__u16));
f06f6f32
CH		 1506 ccw_device_get_id(CARD_DDEV(card), &temp_devid);
1507 memcpy(QETH_IDX_ACT_QDIO_DEV_CUA(iob->data), &temp_devid.devno, 2);
4a71df50
FB		 1508 temp = (card->info.cula << 8) + card->info.unit_addr2;
1509 memcpy(QETH_IDX_ACT_QDIO_DEV_REALADDR(iob->data), &temp, 2);
1510
1511 wait_event(card->wait_q,
1512 atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
d11ba0c4 1513 QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
4a71df50
FB		 1514 spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
1515 rc = ccw_device_start(channel->ccwdev,
1516 &channel->ccw, (addr_t) iob, 0, 0);
1517 spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
1518
1519 if (rc) {
14cc21b6
FB		 1520 QETH_DBF_MESSAGE(2, "Error1 in activating channel. rc=%d\n",
1521 rc);
d11ba0c4 1522 QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
4a71df50
FB		 1523 atomic_set(&channel->irq_pending, 0);
1524 wake_up(&card->wait_q);
1525 return rc;
1526 }
1527 rc = wait_event_interruptible_timeout(card->wait_q,
1528 channel->state == CH_STATE_ACTIVATING, QETH_TIMEOUT);
1529 if (rc == -ERESTARTSYS)
1530 return rc;
1531 if (channel->state != CH_STATE_ACTIVATING) {
1532 PRINT_WARN("IDX activate timed out!\n");
d11ba0c4 1533 QETH_DBF_TEXT_(SETUP, 2, "2err%d", -ETIME);
4a71df50
FB		 1534 qeth_clear_cmd_buffers(channel);
1535 return -ETIME;
1536 }
1537 return qeth_idx_activate_get_answer(channel, idx_reply_cb);
1538}
1539
1540static int qeth_peer_func_level(int level)
1541{
1542 if ((level & 0xff) == 8)
1543 return (level & 0xff) + 0x400;
1544 if (((level >> 8) & 3) == 1)
1545 return (level & 0xff) + 0x200;
1546 return level;
1547}
1548
1549static void qeth_idx_write_cb(struct qeth_channel *channel,
1550 struct qeth_cmd_buffer *iob)
1551{
1552 struct qeth_card *card;
1553 __u16 temp;
1554
d11ba0c4 1555 QETH_DBF_TEXT(SETUP , 2, "idxwrcb");
4a71df50
FB		 1556
1557 if (channel->state == CH_STATE_DOWN) {
1558 channel->state = CH_STATE_ACTIVATING;
1559 goto out;
1560 }
1561 card = CARD_FROM_CDEV(channel->ccwdev);
1562
1563 if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
1564 if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
1565 PRINT_ERR("IDX_ACTIVATE on write channel device %s: "
1566 "adapter exclusively used by another host\n",
1567 CARD_WDEV_ID(card));
1568 else
1569 PRINT_ERR("IDX_ACTIVATE on write channel device %s: "
1570 "negative reply\n", CARD_WDEV_ID(card));
1571 goto out;
1572 }
1573 memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
1574 if ((temp & ~0x0100) != qeth_peer_func_level(card->info.func_level)) {
1575 PRINT_WARN("IDX_ACTIVATE on write channel device %s: "
1576 "function level mismatch "
1577 "(sent: 0x%x, received: 0x%x)\n",
1578 CARD_WDEV_ID(card), card->info.func_level, temp);
1579 goto out;
1580 }
1581 channel->state = CH_STATE_UP;
1582out:
1583 qeth_release_buffer(channel, iob);
1584}
1585
1586static void qeth_idx_read_cb(struct qeth_channel *channel,
1587 struct qeth_cmd_buffer *iob)
1588{
1589 struct qeth_card *card;
1590 __u16 temp;
1591
d11ba0c4 1592 QETH_DBF_TEXT(SETUP , 2, "idxrdcb");
4a71df50
FB		 1593 if (channel->state == CH_STATE_DOWN) {
1594 channel->state = CH_STATE_ACTIVATING;
1595 goto out;
1596 }
1597
1598 card = CARD_FROM_CDEV(channel->ccwdev);
1599 if (qeth_check_idx_response(iob->data))
1600 goto out;
1601
1602 if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
1603 if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
1604 PRINT_ERR("IDX_ACTIVATE on read channel device %s: "
1605 "adapter exclusively used by another host\n",
1606 CARD_RDEV_ID(card));
1607 else
1608 PRINT_ERR("IDX_ACTIVATE on read channel device %s: "
1609 "negative reply\n", CARD_RDEV_ID(card));
1610 goto out;
1611 }
1612
1613/**
1614 * temporary fix for microcode bug
1615 * to revert it,replace OR by AND
1616 */
1617 if ((!QETH_IDX_NO_PORTNAME_REQUIRED(iob->data)) ||
1618 (card->info.type == QETH_CARD_TYPE_OSAE))
1619 card->info.portname_required = 1;
1620
1621 memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
1622 if (temp != qeth_peer_func_level(card->info.func_level)) {
1623 PRINT_WARN("IDX_ACTIVATE on read channel device %s: function "
1624 "level mismatch (sent: 0x%x, received: 0x%x)\n",
1625 CARD_RDEV_ID(card), card->info.func_level, temp);
1626 goto out;
1627 }
1628 memcpy(&card->token.issuer_rm_r,
1629 QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
1630 QETH_MPC_TOKEN_LENGTH);
1631 memcpy(&card->info.mcl_level[0],
1632 QETH_IDX_REPLY_LEVEL(iob->data), QETH_MCL_LENGTH);
1633 channel->state = CH_STATE_UP;
1634out:
1635 qeth_release_buffer(channel, iob);
1636}
1637
1638void qeth_prepare_control_data(struct qeth_card *card, int len,
1639 struct qeth_cmd_buffer *iob)
1640{
1641 qeth_setup_ccw(&card->write, iob->data, len);
1642 iob->callback = qeth_release_buffer;
1643
1644 memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
1645 &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
1646 card->seqno.trans_hdr++;
1647 memcpy(QETH_PDU_HEADER_SEQ_NO(iob->data),
1648 &card->seqno.pdu_hdr, QETH_SEQ_NO_LENGTH);
1649 card->seqno.pdu_hdr++;
1650 memcpy(QETH_PDU_HEADER_ACK_SEQ_NO(iob->data),
1651 &card->seqno.pdu_hdr_ack, QETH_SEQ_NO_LENGTH);
d11ba0c4 1652 QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
4a71df50
FB		 1653}
1654EXPORT_SYMBOL_GPL(qeth_prepare_control_data);
1655
1656int qeth_send_control_data(struct qeth_card *card, int len,
1657 struct qeth_cmd_buffer *iob,
1658 int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
1659 unsigned long),
1660 void *reply_param)
1661{
1662 int rc;
1663 unsigned long flags;
1664 struct qeth_reply *reply = NULL;
1665 unsigned long timeout;
1666
d11ba0c4 1667 QETH_DBF_TEXT(TRACE, 2, "sendctl");
4a71df50
FB		 1668
1669 reply = qeth_alloc_reply(card);
1670 if (!reply) {
4a71df50
FB		 1671 return -ENOMEM;
1672 }
1673 reply->callback = reply_cb;
1674 reply->param = reply_param;
1675 if (card->state == CARD_STATE_DOWN)
1676 reply->seqno = QETH_IDX_COMMAND_SEQNO;
1677 else
1678 reply->seqno = card->seqno.ipa++;
1679 init_waitqueue_head(&reply->wait_q);
1680 spin_lock_irqsave(&card->lock, flags);
1681 list_add_tail(&reply->list, &card->cmd_waiter_list);
1682 spin_unlock_irqrestore(&card->lock, flags);
d11ba0c4 1683 QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
4a71df50
FB		 1684
1685 while (atomic_cmpxchg(&card->write.irq_pending, 0, 1)) ;
1686 qeth_prepare_control_data(card, len, iob);
1687
1688 if (IS_IPA(iob->data))
1689 timeout = jiffies + QETH_IPA_TIMEOUT;
1690 else
1691 timeout = jiffies + QETH_TIMEOUT;
1692
d11ba0c4 1693 QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
4a71df50
FB		 1694 spin_lock_irqsave(get_ccwdev_lock(card->write.ccwdev), flags);
1695 rc = ccw_device_start(card->write.ccwdev, &card->write.ccw,
1696 (addr_t) iob, 0, 0);
1697 spin_unlock_irqrestore(get_ccwdev_lock(card->write.ccwdev), flags);
1698 if (rc) {
1699 PRINT_WARN("qeth_send_control_data: "
1700 "ccw_device_start rc = %i\n", rc);
d11ba0c4 1701 QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
4a71df50
FB		 1702 spin_lock_irqsave(&card->lock, flags);
1703 list_del_init(&reply->list);
1704 qeth_put_reply(reply);
1705 spin_unlock_irqrestore(&card->lock, flags);
1706 qeth_release_buffer(iob->channel, iob);
1707 atomic_set(&card->write.irq_pending, 0);
1708 wake_up(&card->wait_q);
1709 return rc;
1710 }
1711 while (!atomic_read(&reply->received)) {
1712 if (time_after(jiffies, timeout)) {
1713 spin_lock_irqsave(&reply->card->lock, flags);
1714 list_del_init(&reply->list);
1715 spin_unlock_irqrestore(&reply->card->lock, flags);
1716 reply->rc = -ETIME;
1717 atomic_inc(&reply->received);
1718 wake_up(&reply->wait_q);
1719 }
1720 cpu_relax();
1721 };
1722 rc = reply->rc;
1723 qeth_put_reply(reply);
1724 return rc;
1725}
1726EXPORT_SYMBOL_GPL(qeth_send_control_data);
1727
1728static int qeth_cm_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
1729 unsigned long data)
1730{
1731 struct qeth_cmd_buffer *iob;
1732
d11ba0c4 1733 QETH_DBF_TEXT(SETUP, 2, "cmenblcb");
4a71df50
FB		 1734
1735 iob = (struct qeth_cmd_buffer *) data;
1736 memcpy(&card->token.cm_filter_r,
1737 QETH_CM_ENABLE_RESP_FILTER_TOKEN(iob->data),
1738 QETH_MPC_TOKEN_LENGTH);
d11ba0c4 1739 QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
4a71df50
FB		 1740 return 0;
1741}
1742
1743static int qeth_cm_enable(struct qeth_card *card)
1744{
1745 int rc;
1746 struct qeth_cmd_buffer *iob;
1747
d11ba0c4 1748 QETH_DBF_TEXT(SETUP, 2, "cmenable");
4a71df50
FB		 1749
1750 iob = qeth_wait_for_buffer(&card->write);
1751 memcpy(iob->data, CM_ENABLE, CM_ENABLE_SIZE);
1752 memcpy(QETH_CM_ENABLE_ISSUER_RM_TOKEN(iob->data),
1753 &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
1754 memcpy(QETH_CM_ENABLE_FILTER_TOKEN(iob->data),
1755 &card->token.cm_filter_w, QETH_MPC_TOKEN_LENGTH);
1756
1757 rc = qeth_send_control_data(card, CM_ENABLE_SIZE, iob,
1758 qeth_cm_enable_cb, NULL);
1759 return rc;
1760}
1761
1762static int qeth_cm_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
1763 unsigned long data)
1764{
1765
1766 struct qeth_cmd_buffer *iob;
1767
d11ba0c4 1768 QETH_DBF_TEXT(SETUP, 2, "cmsetpcb");
4a71df50
FB		 1769
1770 iob = (struct qeth_cmd_buffer *) data;
1771 memcpy(&card->token.cm_connection_r,
1772 QETH_CM_SETUP_RESP_DEST_ADDR(iob->data),
1773 QETH_MPC_TOKEN_LENGTH);
d11ba0c4 1774 QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
4a71df50
FB		 1775 return 0;
1776}
1777
1778static int qeth_cm_setup(struct qeth_card *card)
1779{
1780 int rc;
1781 struct qeth_cmd_buffer *iob;
1782
d11ba0c4 1783 QETH_DBF_TEXT(SETUP, 2, "cmsetup");
4a71df50
FB		 1784
1785 iob = qeth_wait_for_buffer(&card->write);
1786 memcpy(iob->data, CM_SETUP, CM_SETUP_SIZE);
1787 memcpy(QETH_CM_SETUP_DEST_ADDR(iob->data),
1788 &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
1789 memcpy(QETH_CM_SETUP_CONNECTION_TOKEN(iob->data),
1790 &card->token.cm_connection_w, QETH_MPC_TOKEN_LENGTH);
1791 memcpy(QETH_CM_SETUP_FILTER_TOKEN(iob->data),
1792 &card->token.cm_filter_r, QETH_MPC_TOKEN_LENGTH);
1793 rc = qeth_send_control_data(card, CM_SETUP_SIZE, iob,
1794 qeth_cm_setup_cb, NULL);
1795 return rc;
1796
1797}
1798
1799static inline int qeth_get_initial_mtu_for_card(struct qeth_card *card)
1800{
1801 switch (card->info.type) {
1802 case QETH_CARD_TYPE_UNKNOWN:
1803 return 1500;
1804 case QETH_CARD_TYPE_IQD:
1805 return card->info.max_mtu;
1806 case QETH_CARD_TYPE_OSAE:
1807 switch (card->info.link_type) {
1808 case QETH_LINK_TYPE_HSTR:
1809 case QETH_LINK_TYPE_LANE_TR:
1810 return 2000;
1811 default:
1812 return 1492;
1813 }
1814 default:
1815 return 1500;
1816 }
1817}
1818
1819static inline int qeth_get_max_mtu_for_card(int cardtype)
1820{
1821 switch (cardtype) {
1822
1823 case QETH_CARD_TYPE_UNKNOWN:
1824 case QETH_CARD_TYPE_OSAE:
1825 case QETH_CARD_TYPE_OSN:
1826 return 61440;
1827 case QETH_CARD_TYPE_IQD:
1828 return 57344;
1829 default:
1830 return 1500;
1831 }
1832}
1833
1834static inline int qeth_get_mtu_out_of_mpc(int cardtype)
1835{
1836 switch (cardtype) {
1837 case QETH_CARD_TYPE_IQD:
1838 return 1;
1839 default:
1840 return 0;
1841 }
1842}
1843
1844static inline int qeth_get_mtu_outof_framesize(int framesize)
1845{
1846 switch (framesize) {
1847 case 0x4000:
1848 return 8192;
1849 case 0x6000:
1850 return 16384;
1851 case 0xa000:
1852 return 32768;
1853 case 0xffff:
1854 return 57344;
1855 default:
1856 return 0;
1857 }
1858}
1859
1860static inline int qeth_mtu_is_valid(struct qeth_card *card, int mtu)
1861{
1862 switch (card->info.type) {
1863 case QETH_CARD_TYPE_OSAE:
1864 return ((mtu >= 576) && (mtu <= 61440));
1865 case QETH_CARD_TYPE_IQD:
1866 return ((mtu >= 576) &&
1867 (mtu <= card->info.max_mtu + 4096 - 32));
1868 case QETH_CARD_TYPE_OSN:
1869 case QETH_CARD_TYPE_UNKNOWN:
1870 default:
1871 return 1;
1872 }
1873}
1874
1875static int qeth_ulp_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
1876 unsigned long data)
1877{
1878
1879 __u16 mtu, framesize;
1880 __u16 len;
1881 __u8 link_type;
1882 struct qeth_cmd_buffer *iob;
1883
d11ba0c4 1884 QETH_DBF_TEXT(SETUP, 2, "ulpenacb");
4a71df50
FB		 1885
1886 iob = (struct qeth_cmd_buffer *) data;
1887 memcpy(&card->token.ulp_filter_r,
1888 QETH_ULP_ENABLE_RESP_FILTER_TOKEN(iob->data),
1889 QETH_MPC_TOKEN_LENGTH);
1890 if (qeth_get_mtu_out_of_mpc(card->info.type)) {
1891 memcpy(&framesize, QETH_ULP_ENABLE_RESP_MAX_MTU(iob->data), 2);
1892 mtu = qeth_get_mtu_outof_framesize(framesize);
1893 if (!mtu) {
1894 iob->rc = -EINVAL;
d11ba0c4 1895 QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
4a71df50
FB		 1896 return 0;
1897 }
1898 card->info.max_mtu = mtu;
1899 card->info.initial_mtu = mtu;
1900 card->qdio.in_buf_size = mtu + 2 * PAGE_SIZE;
1901 } else {
1902 card->info.initial_mtu = qeth_get_initial_mtu_for_card(card);
1903 card->info.max_mtu = qeth_get_max_mtu_for_card(card->info.type);
1904 card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
1905 }
1906
1907 memcpy(&len, QETH_ULP_ENABLE_RESP_DIFINFO_LEN(iob->data), 2);
1908 if (len >= QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE) {
1909 memcpy(&link_type,
1910 QETH_ULP_ENABLE_RESP_LINK_TYPE(iob->data), 1);
1911 card->info.link_type = link_type;
1912 } else
1913 card->info.link_type = 0;
d11ba0c4 1914 QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
4a71df50
FB		 1915 return 0;
1916}
1917
1918static int qeth_ulp_enable(struct qeth_card *card)
1919{
1920 int rc;
1921 char prot_type;
1922 struct qeth_cmd_buffer *iob;
1923
1924 /*FIXME: trace view callbacks*/
d11ba0c4 1925 QETH_DBF_TEXT(SETUP, 2, "ulpenabl");
4a71df50
FB		 1926
1927 iob = qeth_wait_for_buffer(&card->write);
1928 memcpy(iob->data, ULP_ENABLE, ULP_ENABLE_SIZE);
1929
1930 *(QETH_ULP_ENABLE_LINKNUM(iob->data)) =
1931 (__u8) card->info.portno;
1932 if (card->options.layer2)
1933 if (card->info.type == QETH_CARD_TYPE_OSN)
1934 prot_type = QETH_PROT_OSN2;
1935 else
1936 prot_type = QETH_PROT_LAYER2;
1937 else
1938 prot_type = QETH_PROT_TCPIP;
1939
1940 memcpy(QETH_ULP_ENABLE_PROT_TYPE(iob->data), &prot_type, 1);
1941 memcpy(QETH_ULP_ENABLE_DEST_ADDR(iob->data),
1942 &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
1943 memcpy(QETH_ULP_ENABLE_FILTER_TOKEN(iob->data),
1944 &card->token.ulp_filter_w, QETH_MPC_TOKEN_LENGTH);
1945 memcpy(QETH_ULP_ENABLE_PORTNAME_AND_LL(iob->data),
1946 card->info.portname, 9);
1947 rc = qeth_send_control_data(card, ULP_ENABLE_SIZE, iob,
1948 qeth_ulp_enable_cb, NULL);
1949 return rc;
1950
1951}
1952
1953static int qeth_ulp_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
1954 unsigned long data)
1955{
1956 struct qeth_cmd_buffer *iob;
1957
d11ba0c4 1958 QETH_DBF_TEXT(SETUP, 2, "ulpstpcb");
4a71df50
FB		 1959
1960 iob = (struct qeth_cmd_buffer *) data;
1961 memcpy(&card->token.ulp_connection_r,
1962 QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
1963 QETH_MPC_TOKEN_LENGTH);
d11ba0c4 1964 QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
4a71df50
FB		 1965 return 0;
1966}
1967
1968static int qeth_ulp_setup(struct qeth_card *card)
1969{
1970 int rc;
1971 __u16 temp;
1972 struct qeth_cmd_buffer *iob;
1973 struct ccw_dev_id dev_id;
1974
d11ba0c4 1975 QETH_DBF_TEXT(SETUP, 2, "ulpsetup");
4a71df50
FB		 1976
1977 iob = qeth_wait_for_buffer(&card->write);
1978 memcpy(iob->data, ULP_SETUP, ULP_SETUP_SIZE);
1979
1980 memcpy(QETH_ULP_SETUP_DEST_ADDR(iob->data),
1981 &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
1982 memcpy(QETH_ULP_SETUP_CONNECTION_TOKEN(iob->data),
1983 &card->token.ulp_connection_w, QETH_MPC_TOKEN_LENGTH);
1984 memcpy(QETH_ULP_SETUP_FILTER_TOKEN(iob->data),
1985 &card->token.ulp_filter_r, QETH_MPC_TOKEN_LENGTH);
1986
1987 ccw_device_get_id(CARD_DDEV(card), &dev_id);
1988 memcpy(QETH_ULP_SETUP_CUA(iob->data), &dev_id.devno, 2);
1989 temp = (card->info.cula << 8) + card->info.unit_addr2;
1990 memcpy(QETH_ULP_SETUP_REAL_DEVADDR(iob->data), &temp, 2);
1991 rc = qeth_send_control_data(card, ULP_SETUP_SIZE, iob,
1992 qeth_ulp_setup_cb, NULL);
1993 return rc;
1994}
1995
1996static int qeth_alloc_qdio_buffers(struct qeth_card *card)
1997{
1998 int i, j;
1999
d11ba0c4 2000 QETH_DBF_TEXT(SETUP, 2, "allcqdbf");
4a71df50
FB		 2001
2002 if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED,
2003 QETH_QDIO_ALLOCATED) != QETH_QDIO_UNINITIALIZED)
2004 return 0;
2005
2006 card->qdio.in_q = kmalloc(sizeof(struct qeth_qdio_q),
508b3c4f 2007 GFP_KERNEL);
4a71df50
FB		 2008 if (!card->qdio.in_q)
2009 goto out_nomem;
d11ba0c4
PT		 2010 QETH_DBF_TEXT(SETUP, 2, "inq");
2011 QETH_DBF_HEX(SETUP, 2, &card->qdio.in_q, sizeof(void *));
4a71df50
FB		 2012 memset(card->qdio.in_q, 0, sizeof(struct qeth_qdio_q));
2013 /* give inbound qeth_qdio_buffers their qdio_buffers */
2014 for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
2015 card->qdio.in_q->bufs[i].buffer =
2016 &card->qdio.in_q->qdio_bufs[i];
2017 /* inbound buffer pool */
2018 if (qeth_alloc_buffer_pool(card))
2019 goto out_freeinq;
2020 /* outbound */
2021 card->qdio.out_qs =
2022 kmalloc(card->qdio.no_out_queues *
2023 sizeof(struct qeth_qdio_out_q *), GFP_KERNEL);
2024 if (!card->qdio.out_qs)
2025 goto out_freepool;
2026 for (i = 0; i < card->qdio.no_out_queues; ++i) {
2027 card->qdio.out_qs[i] = kmalloc(sizeof(struct qeth_qdio_out_q),
508b3c4f 2028 GFP_KERNEL);
4a71df50
FB		 2029 if (!card->qdio.out_qs[i])
2030 goto out_freeoutq;
d11ba0c4
PT		 2031 QETH_DBF_TEXT_(SETUP, 2, "outq %i", i);
2032 QETH_DBF_HEX(SETUP, 2, &card->qdio.out_qs[i], sizeof(void *));
4a71df50
FB		 2033 memset(card->qdio.out_qs[i], 0, sizeof(struct qeth_qdio_out_q));
2034 card->qdio.out_qs[i]->queue_no = i;
2035 /* give outbound qeth_qdio_buffers their qdio_buffers */
2036 for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
2037 card->qdio.out_qs[i]->bufs[j].buffer =
2038 &card->qdio.out_qs[i]->qdio_bufs[j];
2039 skb_queue_head_init(&card->qdio.out_qs[i]->bufs[j].
2040 skb_list);
2041 lockdep_set_class(
2042 &card->qdio.out_qs[i]->bufs[j].skb_list.lock,
2043 &qdio_out_skb_queue_key);
2044 INIT_LIST_HEAD(&card->qdio.out_qs[i]->bufs[j].ctx_list);
2045 }
2046 }
2047 return 0;
2048
2049out_freeoutq:
2050 while (i > 0)
2051 kfree(card->qdio.out_qs[--i]);
2052 kfree(card->qdio.out_qs);
2053 card->qdio.out_qs = NULL;
2054out_freepool:
2055 qeth_free_buffer_pool(card);
2056out_freeinq:
2057 kfree(card->qdio.in_q);
2058 card->qdio.in_q = NULL;
2059out_nomem:
2060 atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
2061 return -ENOMEM;
2062}
2063
2064static void qeth_create_qib_param_field(struct qeth_card *card,
2065 char *param_field)
2066{
2067
2068 param_field[0] = _ascebc['P'];
2069 param_field[1] = _ascebc['C'];
2070 param_field[2] = _ascebc['I'];
2071 param_field[3] = _ascebc['T'];
2072 *((unsigned int *) (&param_field[4])) = QETH_PCI_THRESHOLD_A(card);
2073 *((unsigned int *) (&param_field[8])) = QETH_PCI_THRESHOLD_B(card);
2074 *((unsigned int *) (&param_field[12])) = QETH_PCI_TIMER_VALUE(card);
2075}
2076
2077static void qeth_create_qib_param_field_blkt(struct qeth_card *card,
2078 char *param_field)
2079{
2080 param_field[16] = _ascebc['B'];
2081 param_field[17] = _ascebc['L'];
2082 param_field[18] = _ascebc['K'];
2083 param_field[19] = _ascebc['T'];
2084 *((unsigned int *) (&param_field[20])) = card->info.blkt.time_total;
2085 *((unsigned int *) (&param_field[24])) = card->info.blkt.inter_packet;
2086 *((unsigned int *) (&param_field[28])) =
2087 card->info.blkt.inter_packet_jumbo;
2088}
2089
2090static int qeth_qdio_activate(struct qeth_card *card)
2091{
d11ba0c4 2092 QETH_DBF_TEXT(SETUP, 3, "qdioact");
779e6e1c 2093 return qdio_activate(CARD_DDEV(card));
4a71df50
FB		 2094}
2095
2096static int qeth_dm_act(struct qeth_card *card)
2097{
2098 int rc;
2099 struct qeth_cmd_buffer *iob;
2100
d11ba0c4 2101 QETH_DBF_TEXT(SETUP, 2, "dmact");
4a71df50
FB		 2102
2103 iob = qeth_wait_for_buffer(&card->write);
2104 memcpy(iob->data, DM_ACT, DM_ACT_SIZE);
2105
2106 memcpy(QETH_DM_ACT_DEST_ADDR(iob->data),
2107 &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
2108 memcpy(QETH_DM_ACT_CONNECTION_TOKEN(iob->data),
2109 &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
2110 rc = qeth_send_control_data(card, DM_ACT_SIZE, iob, NULL, NULL);
2111 return rc;
2112}
2113
2114static int qeth_mpc_initialize(struct qeth_card *card)
2115{
2116 int rc;
2117
d11ba0c4 2118 QETH_DBF_TEXT(SETUP, 2, "mpcinit");
4a71df50
FB		 2119
2120 rc = qeth_issue_next_read(card);
2121 if (rc) {
d11ba0c4 2122 QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
4a71df50
FB		 2123 return rc;
2124 }
2125 rc = qeth_cm_enable(card);
2126 if (rc) {
d11ba0c4 2127 QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
4a71df50
FB		 2128 goto out_qdio;
2129 }
2130 rc = qeth_cm_setup(card);
2131 if (rc) {
d11ba0c4 2132 QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
4a71df50
FB		 2133 goto out_qdio;
2134 }
2135 rc = qeth_ulp_enable(card);
2136 if (rc) {
d11ba0c4 2137 QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
4a71df50
FB		 2138 goto out_qdio;
2139 }
2140 rc = qeth_ulp_setup(card);
2141 if (rc) {
d11ba0c4 2142 QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
4a71df50
FB		 2143 goto out_qdio;
2144 }
2145 rc = qeth_alloc_qdio_buffers(card);
2146 if (rc) {
d11ba0c4 2147 QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
4a71df50
FB		 2148 goto out_qdio;
2149 }
2150 rc = qeth_qdio_establish(card);
2151 if (rc) {
d11ba0c4 2152 QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
4a71df50
FB		 2153 qeth_free_qdio_buffers(card);
2154 goto out_qdio;
2155 }
2156 rc = qeth_qdio_activate(card);
2157 if (rc) {
d11ba0c4 2158 QETH_DBF_TEXT_(SETUP, 2, "7err%d", rc);
4a71df50
FB		 2159 goto out_qdio;
2160 }
2161 rc = qeth_dm_act(card);
2162 if (rc) {
d11ba0c4 2163 QETH_DBF_TEXT_(SETUP, 2, "8err%d", rc);
4a71df50
FB		 2164 goto out_qdio;
2165 }
2166
2167 return 0;
2168out_qdio:
2169 qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
2170 return rc;
2171}
2172
2173static void qeth_print_status_with_portname(struct qeth_card *card)
2174{
2175 char dbf_text[15];
2176 int i;
2177
2178 sprintf(dbf_text, "%s", card->info.portname + 1);
2179 for (i = 0; i < 8; i++)
2180 dbf_text[i] =
2181 (char) _ebcasc[(__u8) dbf_text[i]];
2182 dbf_text[8] = 0;
2183 PRINT_INFO("Device %s/%s/%s is a%s card%s%s%s\n"
2184 "with link type %s (portname: %s)\n",
2185 CARD_RDEV_ID(card),
2186 CARD_WDEV_ID(card),
2187 CARD_DDEV_ID(card),
2188 qeth_get_cardname(card),
2189 (card->info.mcl_level[0]) ? " (level: " : "",
2190 (card->info.mcl_level[0]) ? card->info.mcl_level : "",
2191 (card->info.mcl_level[0]) ? ")" : "",
2192 qeth_get_cardname_short(card),
2193 dbf_text);
2194
2195}
2196
2197static void qeth_print_status_no_portname(struct qeth_card *card)
2198{
2199 if (card->info.portname[0])
2200 PRINT_INFO("Device %s/%s/%s is a%s "
2201 "card%s%s%s\nwith link type %s "
2202 "(no portname needed by interface).\n",
2203 CARD_RDEV_ID(card),
2204 CARD_WDEV_ID(card),
2205 CARD_DDEV_ID(card),
2206 qeth_get_cardname(card),
2207 (card->info.mcl_level[0]) ? " (level: " : "",
2208 (card->info.mcl_level[0]) ? card->info.mcl_level : "",
2209 (card->info.mcl_level[0]) ? ")" : "",
2210 qeth_get_cardname_short(card));
2211 else
2212 PRINT_INFO("Device %s/%s/%s is a%s "
2213 "card%s%s%s\nwith link type %s.\n",
2214 CARD_RDEV_ID(card),
2215 CARD_WDEV_ID(card),
2216 CARD_DDEV_ID(card),
2217 qeth_get_cardname(card),
2218 (card->info.mcl_level[0]) ? " (level: " : "",
2219 (card->info.mcl_level[0]) ? card->info.mcl_level : "",
2220 (card->info.mcl_level[0]) ? ")" : "",
2221 qeth_get_cardname_short(card));
2222}
2223
2224void qeth_print_status_message(struct qeth_card *card)
2225{
2226 switch (card->info.type) {
2227 case QETH_CARD_TYPE_OSAE:
2228 /* VM will use a non-zero first character
2229 * to indicate a HiperSockets like reporting
2230 * of the level OSA sets the first character to zero
2231 * */
2232 if (!card->info.mcl_level[0]) {
2233 sprintf(card->info.mcl_level, "%02x%02x",
2234 card->info.mcl_level[2],
2235 card->info.mcl_level[3]);
2236
2237 card->info.mcl_level[QETH_MCL_LENGTH] = 0;
2238 break;
2239 }
2240 /* fallthrough */
2241 case QETH_CARD_TYPE_IQD:
2242 if (card->info.guestlan) {
2243 card->info.mcl_level[0] = (char) _ebcasc[(__u8)
2244 card->info.mcl_level[0]];
2245 card->info.mcl_level[1] = (char) _ebcasc[(__u8)
2246 card->info.mcl_level[1]];
2247 card->info.mcl_level[2] = (char) _ebcasc[(__u8)
2248 card->info.mcl_level[2]];
2249 card->info.mcl_level[3] = (char) _ebcasc[(__u8)
2250 card->info.mcl_level[3]];
2251 card->info.mcl_level[QETH_MCL_LENGTH] = 0;
2252 }
2253 break;
2254 default:
2255 memset(&card->info.mcl_level[0], 0, QETH_MCL_LENGTH + 1);
2256 }
2257 if (card->info.portname_required)
2258 qeth_print_status_with_portname(card);
2259 else
2260 qeth_print_status_no_portname(card);
2261}
2262EXPORT_SYMBOL_GPL(qeth_print_status_message);
2263
4a71df50
FB		 2264static void qeth_initialize_working_pool_list(struct qeth_card *card)
2265{
2266 struct qeth_buffer_pool_entry *entry;
2267
d11ba0c4 2268 QETH_DBF_TEXT(TRACE, 5, "inwrklst");
4a71df50
FB		 2269
2270 list_for_each_entry(entry,
2271 &card->qdio.init_pool.entry_list, init_list) {
2272 qeth_put_buffer_pool_entry(card, entry);
2273 }
2274}
2275
2276static inline struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry(
2277 struct qeth_card *card)
2278{
2279 struct list_head *plh;
2280 struct qeth_buffer_pool_entry *entry;
2281 int i, free;
2282 struct page *page;
2283
2284 if (list_empty(&card->qdio.in_buf_pool.entry_list))
2285 return NULL;
2286
2287 list_for_each(plh, &card->qdio.in_buf_pool.entry_list) {
2288 entry = list_entry(plh, struct qeth_buffer_pool_entry, list);
2289 free = 1;
2290 for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
2291 if (page_count(virt_to_page(entry->elements[i])) > 1) {
2292 free = 0;
2293 break;
2294 }
2295 }
2296 if (free) {
2297 list_del_init(&entry->list);
2298 return entry;
2299 }
2300 }
2301
2302 /* no free buffer in pool so take first one and swap pages */
2303 entry = list_entry(card->qdio.in_buf_pool.entry_list.next,
2304 struct qeth_buffer_pool_entry, list);
2305 for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
2306 if (page_count(virt_to_page(entry->elements[i])) > 1) {
508b3c4f 2307 page = alloc_page(GFP_ATOMIC);
4a71df50
FB		 2308 if (!page) {
2309 return NULL;
2310 } else {
2311 free_page((unsigned long)entry->elements[i]);
2312 entry->elements[i] = page_address(page);
2313 if (card->options.performance_stats)
2314 card->perf_stats.sg_alloc_page_rx++;
2315 }
2316 }
2317 }
2318 list_del_init(&entry->list);
2319 return entry;
2320}
2321
2322static int qeth_init_input_buffer(struct qeth_card *card,
2323 struct qeth_qdio_buffer *buf)
2324{
2325 struct qeth_buffer_pool_entry *pool_entry;
2326 int i;
2327
2328 pool_entry = qeth_find_free_buffer_pool_entry(card);
2329 if (!pool_entry)
2330 return 1;
2331
2332 /*
2333 * since the buffer is accessed only from the input_tasklet
2334 * there shouldn't be a need to synchronize; also, since we use
2335 * the QETH_IN_BUF_REQUEUE_THRESHOLD we should never run out off
2336 * buffers
2337 */
4a71df50
FB		 2338
2339 buf->pool_entry = pool_entry;
2340 for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
2341 buf->buffer->element[i].length = PAGE_SIZE;
2342 buf->buffer->element[i].addr = pool_entry->elements[i];
2343 if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)
2344 buf->buffer->element[i].flags = SBAL_FLAGS_LAST_ENTRY;
2345 else
2346 buf->buffer->element[i].flags = 0;
2347 }
2348 return 0;
2349}
2350
2351int qeth_init_qdio_queues(struct qeth_card *card)
2352{
2353 int i, j;
2354 int rc;
2355
d11ba0c4 2356 QETH_DBF_TEXT(SETUP, 2, "initqdqs");
4a71df50
FB		 2357
2358 /* inbound queue */
2359 memset(card->qdio.in_q->qdio_bufs, 0,
2360 QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
2361 qeth_initialize_working_pool_list(card);
2362 /*give only as many buffers to hardware as we have buffer pool entries*/
2363 for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i)
2364 qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);
2365 card->qdio.in_q->next_buf_to_init =
2366 card->qdio.in_buf_pool.buf_count - 1;
2367 rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,
779e6e1c 2368 card->qdio.in_buf_pool.buf_count - 1);
4a71df50 2369 if (rc) {
d11ba0c4 2370 QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
4a71df50
FB		 2371 return rc;
2372 }
4a71df50
FB		 2373 /* outbound queue */
2374 for (i = 0; i < card->qdio.no_out_queues; ++i) {
2375 memset(card->qdio.out_qs[i]->qdio_bufs, 0,
2376 QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
2377 for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
2378 qeth_clear_output_buffer(card->qdio.out_qs[i],
2379 &card->qdio.out_qs[i]->bufs[j]);
2380 }
2381 card->qdio.out_qs[i]->card = card;
2382 card->qdio.out_qs[i]->next_buf_to_fill = 0;
2383 card->qdio.out_qs[i]->do_pack = 0;
2384 atomic_set(&card->qdio.out_qs[i]->used_buffers, 0);
2385 atomic_set(&card->qdio.out_qs[i]->set_pci_flags_count, 0);
2386 atomic_set(&card->qdio.out_qs[i]->state,
2387 QETH_OUT_Q_UNLOCKED);
2388 }
2389 return 0;
2390}
2391EXPORT_SYMBOL_GPL(qeth_init_qdio_queues);
2392
2393static inline __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type)
2394{
2395 switch (link_type) {
2396 case QETH_LINK_TYPE_HSTR:
2397 return 2;
2398 default:
2399 return 1;
2400 }
2401}
2402
2403static void qeth_fill_ipacmd_header(struct qeth_card *card,
2404 struct qeth_ipa_cmd *cmd, __u8 command,
2405 enum qeth_prot_versions prot)
2406{
2407 memset(cmd, 0, sizeof(struct qeth_ipa_cmd));
2408 cmd->hdr.command = command;
2409 cmd->hdr.initiator = IPA_CMD_INITIATOR_HOST;
2410 cmd->hdr.seqno = card->seqno.ipa;
2411 cmd->hdr.adapter_type = qeth_get_ipa_adp_type(card->info.link_type);
2412 cmd->hdr.rel_adapter_no = (__u8) card->info.portno;
2413 if (card->options.layer2)
2414 cmd->hdr.prim_version_no = 2;
2415 else
2416 cmd->hdr.prim_version_no = 1;
2417 cmd->hdr.param_count = 1;
2418 cmd->hdr.prot_version = prot;
2419 cmd->hdr.ipa_supported = 0;
2420 cmd->hdr.ipa_enabled = 0;
2421}
2422
2423struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *card,
2424 enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
2425{
2426 struct qeth_cmd_buffer *iob;
2427 struct qeth_ipa_cmd *cmd;
2428
2429 iob = qeth_wait_for_buffer(&card->write);
2430 cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
2431 qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);
2432
2433 return iob;
2434}
2435EXPORT_SYMBOL_GPL(qeth_get_ipacmd_buffer);
2436
2437void qeth_prepare_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
2438 char prot_type)
2439{
2440 memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
2441 memcpy(QETH_IPA_CMD_PROT_TYPE(iob->data), &prot_type, 1);
2442 memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
2443 &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
2444}
2445EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);
2446
2447int qeth_send_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
2448 int (*reply_cb)(struct qeth_card *, struct qeth_reply*,
2449 unsigned long),
2450 void *reply_param)
2451{
2452 int rc;
2453 char prot_type;
4a71df50 2454
d11ba0c4 2455 QETH_DBF_TEXT(TRACE, 4, "sendipa");
4a71df50
FB		 2456
2457 if (card->options.layer2)
2458 if (card->info.type == QETH_CARD_TYPE_OSN)
2459 prot_type = QETH_PROT_OSN2;
2460 else
2461 prot_type = QETH_PROT_LAYER2;
2462 else
2463 prot_type = QETH_PROT_TCPIP;
2464 qeth_prepare_ipa_cmd(card, iob, prot_type);
d11ba0c4
PT		 2465 rc = qeth_send_control_data(card, IPA_CMD_LENGTH,
2466 iob, reply_cb, reply_param);
4a71df50
FB		 2467 return rc;
2468}
2469EXPORT_SYMBOL_GPL(qeth_send_ipa_cmd);
2470
2471static int qeth_send_startstoplan(struct qeth_card *card,
2472 enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
2473{
2474 int rc;
2475 struct qeth_cmd_buffer *iob;
2476
2477 iob = qeth_get_ipacmd_buffer(card, ipacmd, prot);
2478 rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
2479
2480 return rc;
2481}
2482
2483int qeth_send_startlan(struct qeth_card *card)
2484{
2485 int rc;
2486
d11ba0c4 2487 QETH_DBF_TEXT(SETUP, 2, "strtlan");
4a71df50
FB		 2488
2489 rc = qeth_send_startstoplan(card, IPA_CMD_STARTLAN, 0);
2490 return rc;
2491}
2492EXPORT_SYMBOL_GPL(qeth_send_startlan);
2493
2494int qeth_send_stoplan(struct qeth_card *card)
2495{
2496 int rc = 0;
2497
2498 /*
2499 * TODO: according to the IPA format document page 14,
2500 * TCP/IP (we!) never issue a STOPLAN
2501 * is this right ?!?
2502 */
d11ba0c4 2503 QETH_DBF_TEXT(SETUP, 2, "stoplan");
4a71df50
FB		 2504
2505 rc = qeth_send_startstoplan(card, IPA_CMD_STOPLAN, 0);
2506 return rc;
2507}
2508EXPORT_SYMBOL_GPL(qeth_send_stoplan);
2509
2510int qeth_default_setadapterparms_cb(struct qeth_card *card,
2511 struct qeth_reply *reply, unsigned long data)
2512{
2513 struct qeth_ipa_cmd *cmd;
2514
d11ba0c4 2515 QETH_DBF_TEXT(TRACE, 4, "defadpcb");
4a71df50
FB		 2516
2517 cmd = (struct qeth_ipa_cmd *) data;
2518 if (cmd->hdr.return_code == 0)
2519 cmd->hdr.return_code =
2520 cmd->data.setadapterparms.hdr.return_code;
2521 return 0;
2522}
2523EXPORT_SYMBOL_GPL(qeth_default_setadapterparms_cb);
2524
2525static int qeth_query_setadapterparms_cb(struct qeth_card *card,
2526 struct qeth_reply *reply, unsigned long data)
2527{
2528 struct qeth_ipa_cmd *cmd;
2529
d11ba0c4 2530 QETH_DBF_TEXT(TRACE, 3, "quyadpcb");
4a71df50
FB		 2531
2532 cmd = (struct qeth_ipa_cmd *) data;
2533 if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f)
2534 card->info.link_type =
2535 cmd->data.setadapterparms.data.query_cmds_supp.lan_type;
2536 card->options.adp.supported_funcs =
2537 cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds;
2538 return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
2539}
2540
2541struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card,
2542 __u32 command, __u32 cmdlen)
2543{
2544 struct qeth_cmd_buffer *iob;
2545 struct qeth_ipa_cmd *cmd;
2546
2547 iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,
2548 QETH_PROT_IPV4);
2549 cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
2550 cmd->data.setadapterparms.hdr.cmdlength = cmdlen;
2551 cmd->data.setadapterparms.hdr.command_code = command;
2552 cmd->data.setadapterparms.hdr.used_total = 1;
2553 cmd->data.setadapterparms.hdr.seq_no = 1;
2554
2555 return iob;
2556}
2557EXPORT_SYMBOL_GPL(qeth_get_adapter_cmd);
2558
2559int qeth_query_setadapterparms(struct qeth_card *card)
2560{
2561 int rc;
2562 struct qeth_cmd_buffer *iob;
2563
d11ba0c4 2564 QETH_DBF_TEXT(TRACE, 3, "queryadp");
4a71df50
FB		 2565 iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,
2566 sizeof(struct qeth_ipacmd_setadpparms));
2567 rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);
2568 return rc;
2569}
2570EXPORT_SYMBOL_GPL(qeth_query_setadapterparms);
2571
2572int qeth_check_qdio_errors(struct qdio_buffer *buf, unsigned int qdio_error,
779e6e1c 2573 const char *dbftext)
4a71df50 2574{
779e6e1c 2575 if (qdio_error) {
d11ba0c4
PT		 2576 QETH_DBF_TEXT(TRACE, 2, dbftext);
2577 QETH_DBF_TEXT(QERR, 2, dbftext);
2578 QETH_DBF_TEXT_(QERR, 2, " F15=%02X",
4a71df50 2579 buf->element[15].flags & 0xff);
d11ba0c4 2580 QETH_DBF_TEXT_(QERR, 2, " F14=%02X",
4a71df50 2581 buf->element[14].flags & 0xff);
d11ba0c4 2582 QETH_DBF_TEXT_(QERR, 2, " qerr=%X", qdio_error);
4a71df50
FB		 2583 return 1;
2584 }
2585 return 0;
2586}
2587EXPORT_SYMBOL_GPL(qeth_check_qdio_errors);
2588
2589void qeth_queue_input_buffer(struct qeth_card *card, int index)
2590{
2591 struct qeth_qdio_q *queue = card->qdio.in_q;
2592 int count;
2593 int i;
2594 int rc;
2595 int newcount = 0;
2596
4a71df50
FB		 2597 count = (index < queue->next_buf_to_init)?
2598 card->qdio.in_buf_pool.buf_count -
2599 (queue->next_buf_to_init - index) :
2600 card->qdio.in_buf_pool.buf_count -
2601 (queue->next_buf_to_init + QDIO_MAX_BUFFERS_PER_Q - index);
2602 /* only requeue at a certain threshold to avoid SIGAs */
2603 if (count >= QETH_IN_BUF_REQUEUE_THRESHOLD(card)) {
2604 for (i = queue->next_buf_to_init;
2605 i < queue->next_buf_to_init + count; ++i) {
2606 if (qeth_init_input_buffer(card,
2607 &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q])) {
2608 break;
2609 } else {
2610 newcount++;
2611 }
2612 }
2613
2614 if (newcount < count) {
2615 /* we are in memory shortage so we switch back to
2616 traditional skb allocation and drop packages */
4a71df50
FB		 2617 atomic_set(&card->force_alloc_skb, 3);
2618 count = newcount;
2619 } else {
4a71df50
FB		 2620 atomic_add_unless(&card->force_alloc_skb, -1, 0);
2621 }
2622
2623 /*
2624 * according to old code it should be avoided to requeue all
2625 * 128 buffers in order to benefit from PCI avoidance.
2626 * this function keeps at least one buffer (the buffer at
2627 * 'index') un-requeued -> this buffer is the first buffer that
2628 * will be requeued the next time
2629 */
2630 if (card->options.performance_stats) {
2631 card->perf_stats.inbound_do_qdio_cnt++;
2632 card->perf_stats.inbound_do_qdio_start_time =
2633 qeth_get_micros();
2634 }
779e6e1c
JG		 2635 rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0,
2636 queue->next_buf_to_init, count);
4a71df50
FB		 2637 if (card->options.performance_stats)
2638 card->perf_stats.inbound_do_qdio_time +=
2639 qeth_get_micros() -
2640 card->perf_stats.inbound_do_qdio_start_time;
2641 if (rc) {
2642 PRINT_WARN("qeth_queue_input_buffer's do_QDIO "
2643 "return %i (device %s).\n",
2644 rc, CARD_DDEV_ID(card));
d11ba0c4
PT		 2645 QETH_DBF_TEXT(TRACE, 2, "qinberr");
2646 QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
4a71df50
FB		 2647 }
2648 queue->next_buf_to_init = (queue->next_buf_to_init + count) %
2649 QDIO_MAX_BUFFERS_PER_Q;
2650 }
2651}
2652EXPORT_SYMBOL_GPL(qeth_queue_input_buffer);
2653
2654static int qeth_handle_send_error(struct qeth_card *card,
779e6e1c 2655 struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err)
4a71df50
FB		 2656{
2657 int sbalf15 = buffer->buffer->element[15].flags & 0xff;
779e6e1c 2658 int cc = qdio_err & 3;
4a71df50 2659
d11ba0c4 2660 QETH_DBF_TEXT(TRACE, 6, "hdsnderr");
779e6e1c 2661 qeth_check_qdio_errors(buffer->buffer, qdio_err, "qouterr");
4a71df50
FB		 2662 switch (cc) {
2663 case 0:
2664 if (qdio_err) {
d11ba0c4
PT		 2665 QETH_DBF_TEXT(TRACE, 1, "lnkfail");
2666 QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
2667 QETH_DBF_TEXT_(TRACE, 1, "%04x %02x",
4a71df50
FB		 2668 (u16)qdio_err, (u8)sbalf15);
2669 return QETH_SEND_ERROR_LINK_FAILURE;
2670 }
2671 return QETH_SEND_ERROR_NONE;
2672 case 2:
779e6e1c 2673 if (qdio_err & QDIO_ERROR_SIGA_BUSY) {
d11ba0c4
PT		 2674 QETH_DBF_TEXT(TRACE, 1, "SIGAcc2B");
2675 QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
4a71df50
FB		 2676 return QETH_SEND_ERROR_KICK_IT;
2677 }
2678 if ((sbalf15 >= 15) && (sbalf15 <= 31))
2679 return QETH_SEND_ERROR_RETRY;
2680 return QETH_SEND_ERROR_LINK_FAILURE;
2681 /* look at qdio_error and sbalf 15 */
2682 case 1:
d11ba0c4
PT		 2683 QETH_DBF_TEXT(TRACE, 1, "SIGAcc1");
2684 QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
4a71df50
FB		 2685 return QETH_SEND_ERROR_LINK_FAILURE;
2686 case 3:
2687 default:
d11ba0c4
PT		 2688 QETH_DBF_TEXT(TRACE, 1, "SIGAcc3");
2689 QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
4a71df50
FB		 2690 return QETH_SEND_ERROR_KICK_IT;
2691 }
2692}
2693
2694/*
2695 * Switched to packing state if the number of used buffers on a queue
2696 * reaches a certain limit.
2697 */
2698static void qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q *queue)
2699{
2700 if (!queue->do_pack) {
2701 if (atomic_read(&queue->used_buffers)
2702 >= QETH_HIGH_WATERMARK_PACK){
2703 /* switch non-PACKING -> PACKING */
d11ba0c4 2704 QETH_DBF_TEXT(TRACE, 6, "np->pack");
4a71df50
FB		 2705 if (queue->card->options.performance_stats)
2706 queue->card->perf_stats.sc_dp_p++;
2707 queue->do_pack = 1;
2708 }
2709 }
2710}
2711
2712/*
2713 * Switches from packing to non-packing mode. If there is a packing
2714 * buffer on the queue this buffer will be prepared to be flushed.
2715 * In that case 1 is returned to inform the caller. If no buffer
2716 * has to be flushed, zero is returned.
2717 */
2718static int qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q *queue)
2719{
2720 struct qeth_qdio_out_buffer *buffer;
2721 int flush_count = 0;
2722
2723 if (queue->do_pack) {
2724 if (atomic_read(&queue->used_buffers)
2725 <= QETH_LOW_WATERMARK_PACK) {
2726 /* switch PACKING -> non-PACKING */
d11ba0c4 2727 QETH_DBF_TEXT(TRACE, 6, "pack->np");
4a71df50
FB		 2728 if (queue->card->options.performance_stats)
2729 queue->card->perf_stats.sc_p_dp++;
2730 queue->do_pack = 0;
2731 /* flush packing buffers */
2732 buffer = &queue->bufs[queue->next_buf_to_fill];
2733 if ((atomic_read(&buffer->state) ==
2734 QETH_QDIO_BUF_EMPTY) &&
2735 (buffer->next_element_to_fill > 0)) {
2736 atomic_set(&buffer->state,
2737 QETH_QDIO_BUF_PRIMED);
2738 flush_count++;
2739 queue->next_buf_to_fill =
2740 (queue->next_buf_to_fill + 1) %
2741 QDIO_MAX_BUFFERS_PER_Q;
2742 }
2743 }
2744 }
2745 return flush_count;
2746}
2747
2748/*
2749 * Called to flush a packing buffer if no more pci flags are on the queue.
2750 * Checks if there is a packing buffer and prepares it to be flushed.
2751 * In that case returns 1, otherwise zero.
2752 */
2753static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue)
2754{
2755 struct qeth_qdio_out_buffer *buffer;
2756
2757 buffer = &queue->bufs[queue->next_buf_to_fill];
2758 if ((atomic_read(&buffer->state) == QETH_QDIO_BUF_EMPTY) &&
2759 (buffer->next_element_to_fill > 0)) {
2760 /* it's a packing buffer */
2761 atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
2762 queue->next_buf_to_fill =
2763 (queue->next_buf_to_fill + 1) % QDIO_MAX_BUFFERS_PER_Q;
2764 return 1;
2765 }
2766 return 0;
2767}
2768
779e6e1c
JG		 2769static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int index,
2770 int count)
4a71df50
FB		 2771{
2772 struct qeth_qdio_out_buffer *buf;
2773 int rc;
2774 int i;
2775 unsigned int qdio_flags;
2776
4a71df50
FB		 2777 for (i = index; i < index + count; ++i) {
2778 buf = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
2779 buf->buffer->element[buf->next_element_to_fill - 1].flags |=
2780 SBAL_FLAGS_LAST_ENTRY;
2781
2782 if (queue->card->info.type == QETH_CARD_TYPE_IQD)
2783 continue;
2784
2785 if (!queue->do_pack) {
2786 if ((atomic_read(&queue->used_buffers) >=
2787 (QETH_HIGH_WATERMARK_PACK -
2788 QETH_WATERMARK_PACK_FUZZ)) &&
2789 !atomic_read(&queue->set_pci_flags_count)) {
2790 /* it's likely that we'll go to packing
2791 * mode soon */
2792 atomic_inc(&queue->set_pci_flags_count);
2793 buf->buffer->element[0].flags |= 0x40;
2794 }
2795 } else {
2796 if (!atomic_read(&queue->set_pci_flags_count)) {
2797 /*
2798 * there's no outstanding PCI any more, so we
2799 * have to request a PCI to be sure the the PCI
2800 * will wake at some time in the future then we
2801 * can flush packed buffers that might still be
2802 * hanging around, which can happen if no
2803 * further send was requested by the stack
2804 */
2805 atomic_inc(&queue->set_pci_flags_count);
2806 buf->buffer->element[0].flags |= 0x40;
2807 }
2808 }
2809 }
2810
2811 queue->card->dev->trans_start = jiffies;
2812 if (queue->card->options.performance_stats) {
2813 queue->card->perf_stats.outbound_do_qdio_cnt++;
2814 queue->card->perf_stats.outbound_do_qdio_start_time =
2815 qeth_get_micros();
2816 }
2817 qdio_flags = QDIO_FLAG_SYNC_OUTPUT;
4a71df50
FB		 2818 if (atomic_read(&queue->set_pci_flags_count))
2819 qdio_flags |= QDIO_FLAG_PCI_OUT;
2820 rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags,
779e6e1c 2821 queue->queue_no, index, count);
4a71df50
FB		 2822 if (queue->card->options.performance_stats)
2823 queue->card->perf_stats.outbound_do_qdio_time +=
2824 qeth_get_micros() -
2825 queue->card->perf_stats.outbound_do_qdio_start_time;
2826 if (rc) {
d11ba0c4
PT		 2827 QETH_DBF_TEXT(TRACE, 2, "flushbuf");
2828 QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
2829 QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_DDEV_ID(queue->card));
4a71df50
FB		 2830 queue->card->stats.tx_errors += count;
2831 /* this must not happen under normal circumstances. if it
2832 * happens something is really wrong -> recover */
2833 qeth_schedule_recovery(queue->card);
2834 return;
2835 }
2836 atomic_add(count, &queue->used_buffers);
2837 if (queue->card->options.performance_stats)
2838 queue->card->perf_stats.bufs_sent += count;
2839}
2840
2841static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue)
2842{
2843 int index;
2844 int flush_cnt = 0;
2845 int q_was_packing = 0;
2846
2847 /*
2848 * check if weed have to switch to non-packing mode or if
2849 * we have to get a pci flag out on the queue
2850 */
2851 if ((atomic_read(&queue->used_buffers) <= QETH_LOW_WATERMARK_PACK) ||
2852 !atomic_read(&queue->set_pci_flags_count)) {
2853 if (atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH) ==
2854 QETH_OUT_Q_UNLOCKED) {
2855 /*
2856 * If we get in here, there was no action in
2857 * do_send_packet. So, we check if there is a
2858 * packing buffer to be flushed here.
2859 */
2860 netif_stop_queue(queue->card->dev);
2861 index = queue->next_buf_to_fill;
2862 q_was_packing = queue->do_pack;
2863 /* queue->do_pack may change */
2864 barrier();
2865 flush_cnt += qeth_switch_to_nonpacking_if_needed(queue);
2866 if (!flush_cnt &&
2867 !atomic_read(&queue->set_pci_flags_count))
2868 flush_cnt +=
2869 qeth_flush_buffers_on_no_pci(queue);
2870 if (queue->card->options.performance_stats &&
2871 q_was_packing)
2872 queue->card->perf_stats.bufs_sent_pack +=
2873 flush_cnt;
2874 if (flush_cnt)
779e6e1c 2875 qeth_flush_buffers(queue, index, flush_cnt);
4a71df50
FB		 2876 atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
2877 }
2878 }
2879}
2880
779e6e1c
JG		 2881void qeth_qdio_output_handler(struct ccw_device *ccwdev,
2882 unsigned int qdio_error, int __queue, int first_element,
2883 int count, unsigned long card_ptr)
4a71df50
FB		 2884{
2885 struct qeth_card *card = (struct qeth_card *) card_ptr;
2886 struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue];
2887 struct qeth_qdio_out_buffer *buffer;
2888 int i;
2889
d11ba0c4 2890 QETH_DBF_TEXT(TRACE, 6, "qdouhdl");
779e6e1c
JG		 2891 if (qdio_error & QDIO_ERROR_ACTIVATE_CHECK_CONDITION) {
2892 QETH_DBF_TEXT(TRACE, 2, "achkcond");
2893 QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
2894 netif_stop_queue(card->dev);
2895 qeth_schedule_recovery(card);
2896 return;
4a71df50
FB		 2897 }
2898 if (card->options.performance_stats) {
2899 card->perf_stats.outbound_handler_cnt++;
2900 card->perf_stats.outbound_handler_start_time =
2901 qeth_get_micros();
2902 }
2903 for (i = first_element; i < (first_element + count); ++i) {
2904 buffer = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
2905 /*we only handle the KICK_IT error by doing a recovery */
779e6e1c 2906 if (qeth_handle_send_error(card, buffer, qdio_error)
4a71df50
FB		 2907 == QETH_SEND_ERROR_KICK_IT){
2908 netif_stop_queue(card->dev);
2909 qeth_schedule_recovery(card);
2910 return;
2911 }
2912 qeth_clear_output_buffer(queue, buffer);
2913 }
2914 atomic_sub(count, &queue->used_buffers);
2915 /* check if we need to do something on this outbound queue */
2916 if (card->info.type != QETH_CARD_TYPE_IQD)
2917 qeth_check_outbound_queue(queue);
2918
2919 netif_wake_queue(queue->card->dev);
2920 if (card->options.performance_stats)
2921 card->perf_stats.outbound_handler_time += qeth_get_micros() -
2922 card->perf_stats.outbound_handler_start_time;
2923}
2924EXPORT_SYMBOL_GPL(qeth_qdio_output_handler);
2925
2926int qeth_get_cast_type(struct qeth_card *card, struct sk_buff *skb)
2927{
2928 int cast_type = RTN_UNSPEC;
2929
2930 if (card->info.type == QETH_CARD_TYPE_OSN)
2931 return cast_type;
2932
2933 if (skb->dst && skb->dst->neighbour) {
2934 cast_type = skb->dst->neighbour->type;
2935 if ((cast_type == RTN_BROADCAST) ||
2936 (cast_type == RTN_MULTICAST) ||
2937 (cast_type == RTN_ANYCAST))
2938 return cast_type;
2939 else
2940 return RTN_UNSPEC;
2941 }
2942 /* try something else */
2943 if (skb->protocol == ETH_P_IPV6)
2944 return (skb_network_header(skb)[24] == 0xff) ?
2945 RTN_MULTICAST : 0;
2946 else if (skb->protocol == ETH_P_IP)
2947 return ((skb_network_header(skb)[16] & 0xf0) == 0xe0) ?
2948 RTN_MULTICAST : 0;
2949 /* ... */
2950 if (!memcmp(skb->data, skb->dev->broadcast, 6))
2951 return RTN_BROADCAST;
2952 else {
2953 u16 hdr_mac;
2954
2955 hdr_mac = *((u16 *)skb->data);
2956 /* tr multicast? */
2957 switch (card->info.link_type) {
2958 case QETH_LINK_TYPE_HSTR:
2959 case QETH_LINK_TYPE_LANE_TR:
2960 if ((hdr_mac == QETH_TR_MAC_NC) ||
2961 (hdr_mac == QETH_TR_MAC_C))
2962 return RTN_MULTICAST;
2963 break;
2964 /* eth or so multicast? */
2965 default:
2966 if ((hdr_mac == QETH_ETH_MAC_V4) ||
2967 (hdr_mac == QETH_ETH_MAC_V6))
2968 return RTN_MULTICAST;
2969 }
2970 }
2971 return cast_type;
2972}
2973EXPORT_SYMBOL_GPL(qeth_get_cast_type);
2974
2975int qeth_get_priority_queue(struct qeth_card *card, struct sk_buff *skb,
2976 int ipv, int cast_type)
2977{
2978 if (!ipv && (card->info.type == QETH_CARD_TYPE_OSAE))
2979 return card->qdio.default_out_queue;
2980 switch (card->qdio.no_out_queues) {
2981 case 4:
2982 if (cast_type && card->info.is_multicast_different)
2983 return card->info.is_multicast_different &
2984 (card->qdio.no_out_queues - 1);
2985 if (card->qdio.do_prio_queueing && (ipv == 4)) {
2986 const u8 tos = ip_hdr(skb)->tos;
2987
2988 if (card->qdio.do_prio_queueing ==
2989 QETH_PRIO_Q_ING_TOS) {
2990 if (tos & IP_TOS_NOTIMPORTANT)
2991 return 3;
2992 if (tos & IP_TOS_HIGHRELIABILITY)
2993 return 2;
2994 if (tos & IP_TOS_HIGHTHROUGHPUT)
2995 return 1;
2996 if (tos & IP_TOS_LOWDELAY)
2997 return 0;
2998 }
2999 if (card->qdio.do_prio_queueing ==
3000 QETH_PRIO_Q_ING_PREC)
3001 return 3 - (tos >> 6);
3002 } else if (card->qdio.do_prio_queueing && (ipv == 6)) {
3003 /* TODO: IPv6!!! */
3004 }
3005 return card->qdio.default_out_queue;
3006 case 1: /* fallthrough for single-out-queue 1920-device */
3007 default:
3008 return card->qdio.default_out_queue;
3009 }
3010}
3011EXPORT_SYMBOL_GPL(qeth_get_priority_queue);
3012
4a71df50
FB		 3013int qeth_get_elements_no(struct qeth_card *card, void *hdr,
3014 struct sk_buff *skb, int elems)
3015{
3016 int elements_needed = 0;
3017
3018 if (skb_shinfo(skb)->nr_frags > 0)
3019 elements_needed = (skb_shinfo(skb)->nr_frags + 1);
3020 if (elements_needed == 0)
683d718a
FB		 3021 elements_needed = 1 + (((((unsigned long) skb->data) %
3022 PAGE_SIZE) + skb->len) >> PAGE_SHIFT);
4a71df50 3023 if ((elements_needed + elems) > QETH_MAX_BUFFER_ELEMENTS(card)) {
14cc21b6 3024 QETH_DBF_MESSAGE(2, "Invalid size of IP packet "
4a71df50
FB		 3025 "(Number=%d / Length=%d). Discarded.\n",
3026 (elements_needed+elems), skb->len);
3027 return 0;
3028 }
3029 return elements_needed;
3030}
3031EXPORT_SYMBOL_GPL(qeth_get_elements_no);
3032
f90b744e 3033static inline void __qeth_fill_buffer(struct sk_buff *skb,
683d718a
FB		 3034 struct qdio_buffer *buffer, int is_tso, int *next_element_to_fill,
3035 int offset)
4a71df50 3036{
e1f03ae8 3037 int length = skb->len;
4a71df50
FB		 3038 int length_here;
3039 int element;
3040 char *data;
3041 int first_lap ;
3042
3043 element = *next_element_to_fill;
3044 data = skb->data;
3045 first_lap = (is_tso == 0 ? 1 : 0);
3046
683d718a
FB		 3047 if (offset >= 0) {
3048 data = skb->data + offset;
e1f03ae8 3049 length -= offset;
683d718a
FB		 3050 first_lap = 0;
3051 }
3052
4a71df50
FB		 3053 while (length > 0) {
3054 /* length_here is the remaining amount of data in this page */
3055 length_here = PAGE_SIZE - ((unsigned long) data % PAGE_SIZE);
3056 if (length < length_here)
3057 length_here = length;
3058
3059 buffer->element[element].addr = data;
3060 buffer->element[element].length = length_here;
3061 length -= length_here;
3062 if (!length) {
3063 if (first_lap)
3064 buffer->element[element].flags = 0;
3065 else
3066 buffer->element[element].flags =
3067 SBAL_FLAGS_LAST_FRAG;
3068 } else {
3069 if (first_lap)
3070 buffer->element[element].flags =
3071 SBAL_FLAGS_FIRST_FRAG;
3072 else
3073 buffer->element[element].flags =
3074 SBAL_FLAGS_MIDDLE_FRAG;
3075 }
3076 data += length_here;
3077 element++;
3078 first_lap = 0;
3079 }
3080 *next_element_to_fill = element;
3081}
3082
f90b744e 3083static inline int qeth_fill_buffer(struct qeth_qdio_out_q *queue,
683d718a
FB		 3084 struct qeth_qdio_out_buffer *buf, struct sk_buff *skb,
3085 struct qeth_hdr *hdr, int offset, int hd_len)
4a71df50
FB		 3086{
3087 struct qdio_buffer *buffer;
4a71df50
FB		 3088 int flush_cnt = 0, hdr_len, large_send = 0;
3089
4a71df50
FB		 3090 buffer = buf->buffer;
3091 atomic_inc(&skb->users);
3092 skb_queue_tail(&buf->skb_list, skb);
3093
4a71df50 3094 /*check first on TSO ....*/
683d718a 3095 if (hdr->hdr.l3.id == QETH_HEADER_TYPE_TSO) {
4a71df50
FB		 3096 int element = buf->next_element_to_fill;
3097
683d718a
FB		 3098 hdr_len = sizeof(struct qeth_hdr_tso) +
3099 ((struct qeth_hdr_tso *)hdr)->ext.dg_hdr_len;
4a71df50
FB		 3100 /*fill first buffer entry only with header information */
3101 buffer->element[element].addr = skb->data;
3102 buffer->element[element].length = hdr_len;
3103 buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
3104 buf->next_element_to_fill++;
3105 skb->data += hdr_len;
3106 skb->len -= hdr_len;
3107 large_send = 1;
3108 }
683d718a
FB		 3109
3110 if (offset >= 0) {
3111 int element = buf->next_element_to_fill;
3112 buffer->element[element].addr = hdr;
3113 buffer->element[element].length = sizeof(struct qeth_hdr) +
3114 hd_len;
3115 buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
3116 buf->is_header[element] = 1;
3117 buf->next_element_to_fill++;
3118 }
3119
4a71df50
FB		 3120 if (skb_shinfo(skb)->nr_frags == 0)
3121 __qeth_fill_buffer(skb, buffer, large_send,
683d718a 3122 (int *)&buf->next_element_to_fill, offset);
4a71df50
FB		 3123 else
3124 __qeth_fill_buffer_frag(skb, buffer, large_send,
3125 (int *)&buf->next_element_to_fill);
3126
3127 if (!queue->do_pack) {
d11ba0c4 3128 QETH_DBF_TEXT(TRACE, 6, "fillbfnp");
4a71df50
FB		 3129 /* set state to PRIMED -> will be flushed */
3130 atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
3131 flush_cnt = 1;
3132 } else {
d11ba0c4 3133 QETH_DBF_TEXT(TRACE, 6, "fillbfpa");
4a71df50
FB		 3134 if (queue->card->options.performance_stats)
3135 queue->card->perf_stats.skbs_sent_pack++;
3136 if (buf->next_element_to_fill >=
3137 QETH_MAX_BUFFER_ELEMENTS(queue->card)) {
3138 /*
3139 * packed buffer if full -> set state PRIMED
3140 * -> will be flushed
3141 */
3142 atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
3143 flush_cnt = 1;
3144 }
3145 }
3146 return flush_cnt;
3147}
3148
3149int qeth_do_send_packet_fast(struct qeth_card *card,
3150 struct qeth_qdio_out_q *queue, struct sk_buff *skb,
3151 struct qeth_hdr *hdr, int elements_needed,
683d718a 3152 struct qeth_eddp_context *ctx, int offset, int hd_len)
4a71df50
FB		 3153{
3154 struct qeth_qdio_out_buffer *buffer;
3155 int buffers_needed = 0;
3156 int flush_cnt = 0;
3157 int index;
3158
4a71df50
FB		 3159 /* spin until we get the queue ... */
3160 while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
3161 QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
3162 /* ... now we've got the queue */
3163 index = queue->next_buf_to_fill;
3164 buffer = &queue->bufs[queue->next_buf_to_fill];
3165 /*
3166 * check if buffer is empty to make sure that we do not 'overtake'
3167 * ourselves and try to fill a buffer that is already primed
3168 */
3169 if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY)
3170 goto out;
3171 if (ctx == NULL)
3172 queue->next_buf_to_fill = (queue->next_buf_to_fill + 1) %
3173 QDIO_MAX_BUFFERS_PER_Q;
3174 else {
3175 buffers_needed = qeth_eddp_check_buffers_for_context(queue,
3176 ctx);
3177 if (buffers_needed < 0)
3178 goto out;
3179 queue->next_buf_to_fill =
3180 (queue->next_buf_to_fill + buffers_needed) %
3181 QDIO_MAX_BUFFERS_PER_Q;
3182 }
3183 atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
3184 if (ctx == NULL) {
683d718a 3185 qeth_fill_buffer(queue, buffer, skb, hdr, offset, hd_len);
779e6e1c 3186 qeth_flush_buffers(queue, index, 1);
4a71df50
FB		 3187 } else {
3188 flush_cnt = qeth_eddp_fill_buffer(queue, ctx, index);
3189 WARN_ON(buffers_needed != flush_cnt);
779e6e1c 3190 qeth_flush_buffers(queue, index, flush_cnt);
4a71df50
FB		 3191 }
3192 return 0;
3193out:
3194 atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
3195 return -EBUSY;
3196}
3197EXPORT_SYMBOL_GPL(qeth_do_send_packet_fast);
3198
3199int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue,
3200 struct sk_buff *skb, struct qeth_hdr *hdr,
3201 int elements_needed, struct qeth_eddp_context *ctx)
3202{
3203 struct qeth_qdio_out_buffer *buffer;
3204 int start_index;
3205 int flush_count = 0;
3206 int do_pack = 0;
3207 int tmp;
3208 int rc = 0;
3209
4a71df50
FB		 3210 /* spin until we get the queue ... */
3211 while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
3212 QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
3213 start_index = queue->next_buf_to_fill;
3214 buffer = &queue->bufs[queue->next_buf_to_fill];
3215 /*
3216 * check if buffer is empty to make sure that we do not 'overtake'
3217 * ourselves and try to fill a buffer that is already primed
3218 */
3219 if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) {
3220 atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
3221 return -EBUSY;
3222 }
3223 /* check if we need to switch packing state of this queue */
3224 qeth_switch_to_packing_if_needed(queue);
3225 if (queue->do_pack) {
3226 do_pack = 1;
3227 if (ctx == NULL) {
3228 /* does packet fit in current buffer? */
3229 if ((QETH_MAX_BUFFER_ELEMENTS(card) -
3230 buffer->next_element_to_fill) < elements_needed) {
3231 /* ... no -> set state PRIMED */
3232 atomic_set(&buffer->state,
3233 QETH_QDIO_BUF_PRIMED);
3234 flush_count++;
3235 queue->next_buf_to_fill =
3236 (queue->next_buf_to_fill + 1) %
3237 QDIO_MAX_BUFFERS_PER_Q;
3238 buffer = &queue->bufs[queue->next_buf_to_fill];
3239 /* we did a step forward, so check buffer state
3240 * again */
3241 if (atomic_read(&buffer->state) !=
3242 QETH_QDIO_BUF_EMPTY){
779e6e1c
JG		 3243 qeth_flush_buffers(queue, start_index,
3244 flush_count);
4a71df50
FB		 3245 atomic_set(&queue->state,
3246 QETH_OUT_Q_UNLOCKED);
3247 return -EBUSY;
3248 }
3249 }
3250 } else {
3251 /* check if we have enough elements (including following
3252 * free buffers) to handle eddp context */
3253 if (qeth_eddp_check_buffers_for_context(queue, ctx)
3254 < 0) {
4a71df50
FB		 3255 rc = -EBUSY;
3256 goto out;
3257 }
3258 }
3259 }
3260 if (ctx == NULL)
683d718a 3261 tmp = qeth_fill_buffer(queue, buffer, skb, hdr, -1, 0);
4a71df50
FB		 3262 else {
3263 tmp = qeth_eddp_fill_buffer(queue, ctx,
3264 queue->next_buf_to_fill);
3265 if (tmp < 0) {
4a71df50
FB		 3266 rc = -EBUSY;
3267 goto out;
3268 }
3269 }
3270 queue->next_buf_to_fill = (queue->next_buf_to_fill + tmp) %
3271 QDIO_MAX_BUFFERS_PER_Q;
3272 flush_count += tmp;
3273out:
3274 if (flush_count)
779e6e1c 3275 qeth_flush_buffers(queue, start_index, flush_count);
4a71df50
FB		 3276 else if (!atomic_read(&queue->set_pci_flags_count))
3277 atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH);
3278 /*
3279 * queue->state will go from LOCKED -> UNLOCKED or from
3280 * LOCKED_FLUSH -> LOCKED if output_handler wanted to 'notify' us
3281 * (switch packing state or flush buffer to get another pci flag out).
3282 * In that case we will enter this loop
3283 */
3284 while (atomic_dec_return(&queue->state)) {
3285 flush_count = 0;
3286 start_index = queue->next_buf_to_fill;
3287 /* check if we can go back to non-packing state */
3288 flush_count += qeth_switch_to_nonpacking_if_needed(queue);
3289 /*
3290 * check if we need to flush a packing buffer to get a pci
3291 * flag out on the queue
3292 */
3293 if (!flush_count && !atomic_read(&queue->set_pci_flags_count))
3294 flush_count += qeth_flush_buffers_on_no_pci(queue);
3295 if (flush_count)
779e6e1c 3296 qeth_flush_buffers(queue, start_index, flush_count);
4a71df50
FB		 3297 }
3298 /* at this point the queue is UNLOCKED again */
3299 if (queue->card->options.performance_stats && do_pack)
3300 queue->card->perf_stats.bufs_sent_pack += flush_count;
3301
3302 return rc;
3303}
3304EXPORT_SYMBOL_GPL(qeth_do_send_packet);
3305
3306static int qeth_setadp_promisc_mode_cb(struct qeth_card *card,
3307 struct qeth_reply *reply, unsigned long data)
3308{
3309 struct qeth_ipa_cmd *cmd;
3310 struct qeth_ipacmd_setadpparms *setparms;
3311
d11ba0c4 3312 QETH_DBF_TEXT(TRACE, 4, "prmadpcb");
4a71df50
FB		 3313
3314 cmd = (struct qeth_ipa_cmd *) data;
3315 setparms = &(cmd->data.setadapterparms);
3316
3317 qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
3318 if (cmd->hdr.return_code) {
d11ba0c4 3319 QETH_DBF_TEXT_(TRACE, 4, "prmrc%2.2x", cmd->hdr.return_code);
4a71df50
FB		 3320 setparms->data.mode = SET_PROMISC_MODE_OFF;
3321 }
3322 card->info.promisc_mode = setparms->data.mode;
3323 return 0;
3324}
3325
3326void qeth_setadp_promisc_mode(struct qeth_card *card)
3327{
3328 enum qeth_ipa_promisc_modes mode;
3329 struct net_device *dev = card->dev;
3330 struct qeth_cmd_buffer *iob;
3331 struct qeth_ipa_cmd *cmd;
3332
d11ba0c4 3333 QETH_DBF_TEXT(TRACE, 4, "setprom");
4a71df50
FB		 3334
3335 if (((dev->flags & IFF_PROMISC) &&
3336 (card->info.promisc_mode == SET_PROMISC_MODE_ON)) ||
3337 (!(dev->flags & IFF_PROMISC) &&
3338 (card->info.promisc_mode == SET_PROMISC_MODE_OFF)))
3339 return;
3340 mode = SET_PROMISC_MODE_OFF;
3341 if (dev->flags & IFF_PROMISC)
3342 mode = SET_PROMISC_MODE_ON;
d11ba0c4 3343 QETH_DBF_TEXT_(TRACE, 4, "mode:%x", mode);
4a71df50
FB		 3344
3345 iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,
3346 sizeof(struct qeth_ipacmd_setadpparms));
3347 cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);
3348 cmd->data.setadapterparms.data.mode = mode;
3349 qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);
3350}
3351EXPORT_SYMBOL_GPL(qeth_setadp_promisc_mode);
3352
3353int qeth_change_mtu(struct net_device *dev, int new_mtu)
3354{
3355 struct qeth_card *card;
3356 char dbf_text[15];
3357
509e2562 3358 card = dev->ml_priv;
4a71df50 3359
d11ba0c4 3360 QETH_DBF_TEXT(TRACE, 4, "chgmtu");
4a71df50 3361 sprintf(dbf_text, "%8x", new_mtu);
d11ba0c4 3362 QETH_DBF_TEXT(TRACE, 4, dbf_text);
4a71df50
FB		 3363
3364 if (new_mtu < 64)
3365 return -EINVAL;
3366 if (new_mtu > 65535)
3367 return -EINVAL;
3368 if ((!qeth_is_supported(card, IPA_IP_FRAGMENTATION)) &&
3369 (!qeth_mtu_is_valid(card, new_mtu)))
3370 return -EINVAL;
3371 dev->mtu = new_mtu;
3372 return 0;
3373}
3374EXPORT_SYMBOL_GPL(qeth_change_mtu);
3375
3376struct net_device_stats *qeth_get_stats(struct net_device *dev)
3377{
3378 struct qeth_card *card;
3379
509e2562 3380 card = dev->ml_priv;
4a71df50 3381
d11ba0c4 3382 QETH_DBF_TEXT(TRACE, 5, "getstat");
4a71df50
FB		 3383
3384 return &card->stats;
3385}
3386EXPORT_SYMBOL_GPL(qeth_get_stats);
3387
3388static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card,
3389 struct qeth_reply *reply, unsigned long data)
3390{
3391 struct qeth_ipa_cmd *cmd;
3392
d11ba0c4 3393 QETH_DBF_TEXT(TRACE, 4, "chgmaccb");
4a71df50
FB		 3394
3395 cmd = (struct qeth_ipa_cmd *) data;
3396 if (!card->options.layer2 ||
3397 !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) {
3398 memcpy(card->dev->dev_addr,
3399 &cmd->data.setadapterparms.data.change_addr.addr,
3400 OSA_ADDR_LEN);
3401 card->info.mac_bits |= QETH_LAYER2_MAC_READ;
3402 }
3403 qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
3404 return 0;
3405}
3406
3407int qeth_setadpparms_change_macaddr(struct qeth_card *card)
3408{
3409 int rc;
3410 struct qeth_cmd_buffer *iob;
3411 struct qeth_ipa_cmd *cmd;
3412
d11ba0c4 3413 QETH_DBF_TEXT(TRACE, 4, "chgmac");
4a71df50
FB		 3414
3415 iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,
3416 sizeof(struct qeth_ipacmd_setadpparms));
3417 cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
3418 cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;
3419 cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;
3420 memcpy(&cmd->data.setadapterparms.data.change_addr.addr,
3421 card->dev->dev_addr, OSA_ADDR_LEN);
3422 rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_change_macaddr_cb,
3423 NULL);
3424 return rc;
3425}
3426EXPORT_SYMBOL_GPL(qeth_setadpparms_change_macaddr);
3427
3428void qeth_tx_timeout(struct net_device *dev)
3429{
3430 struct qeth_card *card;
3431
509e2562 3432 card = dev->ml_priv;
4a71df50
FB		 3433 card->stats.tx_errors++;
3434 qeth_schedule_recovery(card);
3435}
3436EXPORT_SYMBOL_GPL(qeth_tx_timeout);
3437
3438int qeth_mdio_read(struct net_device *dev, int phy_id, int regnum)
3439{
509e2562 3440 struct qeth_card *card = dev->ml_priv;
4a71df50
FB		 3441 int rc = 0;
3442
3443 switch (regnum) {
3444 case MII_BMCR: /* Basic mode control register */
3445 rc = BMCR_FULLDPLX;
3446 if ((card->info.link_type != QETH_LINK_TYPE_GBIT_ETH) &&
3447 (card->info.link_type != QETH_LINK_TYPE_OSN) &&
3448 (card->info.link_type != QETH_LINK_TYPE_10GBIT_ETH))
3449 rc |= BMCR_SPEED100;
3450 break;
3451 case MII_BMSR: /* Basic mode status register */
3452 rc = BMSR_ERCAP | BMSR_ANEGCOMPLETE | BMSR_LSTATUS |
3453 BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL |
3454 BMSR_100BASE4;
3455 break;
3456 case MII_PHYSID1: /* PHYS ID 1 */
3457 rc = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 8) |
3458 dev->dev_addr[2];
3459 rc = (rc >> 5) & 0xFFFF;
3460 break;
3461 case MII_PHYSID2: /* PHYS ID 2 */
3462 rc = (dev->dev_addr[2] << 10) & 0xFFFF;
3463 break;
3464 case MII_ADVERTISE: /* Advertisement control reg */
3465 rc = ADVERTISE_ALL;
3466 break;
3467 case MII_LPA: /* Link partner ability reg */
3468 rc = LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL |
3469 LPA_100BASE4 | LPA_LPACK;
3470 break;
3471 case MII_EXPANSION: /* Expansion register */
3472 break;
3473 case MII_DCOUNTER: /* disconnect counter */
3474 break;
3475 case MII_FCSCOUNTER: /* false carrier counter */
3476 break;
3477 case MII_NWAYTEST: /* N-way auto-neg test register */
3478 break;
3479 case MII_RERRCOUNTER: /* rx error counter */
3480 rc = card->stats.rx_errors;
3481 break;
3482 case MII_SREVISION: /* silicon revision */
3483 break;
3484 case MII_RESV1: /* reserved 1 */
3485 break;
3486 case MII_LBRERROR: /* loopback, rx, bypass error */
3487 break;
3488 case MII_PHYADDR: /* physical address */
3489 break;
3490 case MII_RESV2: /* reserved 2 */
3491 break;
3492 case MII_TPISTATUS: /* TPI status for 10mbps */
3493 break;
3494 case MII_NCONFIG: /* network interface config */
3495 break;
3496 default:
3497 break;
3498 }
3499 return rc;
3500}
3501EXPORT_SYMBOL_GPL(qeth_mdio_read);
3502
3503static int qeth_send_ipa_snmp_cmd(struct qeth_card *card,
3504 struct qeth_cmd_buffer *iob, int len,
3505 int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
3506 unsigned long),
3507 void *reply_param)
3508{
3509 u16 s1, s2;
3510
d11ba0c4 3511 QETH_DBF_TEXT(TRACE, 4, "sendsnmp");
4a71df50
FB		 3512
3513 memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
3514 memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
3515 &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
3516 /* adjust PDU length fields in IPA_PDU_HEADER */
3517 s1 = (u32) IPA_PDU_HEADER_SIZE + len;
3518 s2 = (u32) len;
3519 memcpy(QETH_IPA_PDU_LEN_TOTAL(iob->data), &s1, 2);
3520 memcpy(QETH_IPA_PDU_LEN_PDU1(iob->data), &s2, 2);
3521 memcpy(QETH_IPA_PDU_LEN_PDU2(iob->data), &s2, 2);
3522 memcpy(QETH_IPA_PDU_LEN_PDU3(iob->data), &s2, 2);
3523 return qeth_send_control_data(card, IPA_PDU_HEADER_SIZE + len, iob,
3524 reply_cb, reply_param);
3525}
3526
3527static int qeth_snmp_command_cb(struct qeth_card *card,
3528 struct qeth_reply *reply, unsigned long sdata)
3529{
3530 struct qeth_ipa_cmd *cmd;
3531 struct qeth_arp_query_info *qinfo;
3532 struct qeth_snmp_cmd *snmp;
3533 unsigned char *data;
3534 __u16 data_len;
3535
d11ba0c4 3536 QETH_DBF_TEXT(TRACE, 3, "snpcmdcb");
4a71df50
FB		 3537
3538 cmd = (struct qeth_ipa_cmd *) sdata;
3539 data = (unsigned char *)((char *)cmd - reply->offset);
3540 qinfo = (struct qeth_arp_query_info *) reply->param;
3541 snmp = &cmd->data.setadapterparms.data.snmp;
3542
3543 if (cmd->hdr.return_code) {
d11ba0c4 3544 QETH_DBF_TEXT_(TRACE, 4, "scer1%i", cmd->hdr.return_code);
4a71df50
FB		 3545 return 0;
3546 }
3547 if (cmd->data.setadapterparms.hdr.return_code) {
3548 cmd->hdr.return_code =
3549 cmd->data.setadapterparms.hdr.return_code;
d11ba0c4 3550 QETH_DBF_TEXT_(TRACE, 4, "scer2%i", cmd->hdr.return_code);
4a71df50
FB		 3551 return 0;
3552 }
3553 data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data));
3554 if (cmd->data.setadapterparms.hdr.seq_no == 1)
3555 data_len -= (__u16)((char *)&snmp->data - (char *)cmd);
3556 else
3557 data_len -= (__u16)((char *)&snmp->request - (char *)cmd);
3558
3559 /* check if there is enough room in userspace */
3560 if ((qinfo->udata_len - qinfo->udata_offset) < data_len) {
d11ba0c4 3561 QETH_DBF_TEXT_(TRACE, 4, "scer3%i", -ENOMEM);
4a71df50
FB		 3562 cmd->hdr.return_code = -ENOMEM;
3563 return 0;
3564 }
d11ba0c4 3565 QETH_DBF_TEXT_(TRACE, 4, "snore%i",
4a71df50 3566 cmd->data.setadapterparms.hdr.used_total);
d11ba0c4 3567 QETH_DBF_TEXT_(TRACE, 4, "sseqn%i",
4a71df50
FB		 3568 cmd->data.setadapterparms.hdr.seq_no);
3569 /*copy entries to user buffer*/
3570 if (cmd->data.setadapterparms.hdr.seq_no == 1) {
3571 memcpy(qinfo->udata + qinfo->udata_offset,
3572 (char *)snmp,
3573 data_len + offsetof(struct qeth_snmp_cmd, data));
3574 qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data);
3575 } else {
3576 memcpy(qinfo->udata + qinfo->udata_offset,
3577 (char *)&snmp->request, data_len);
3578 }
3579 qinfo->udata_offset += data_len;
3580 /* check if all replies received ... */
d11ba0c4 3581 QETH_DBF_TEXT_(TRACE, 4, "srtot%i",
4a71df50 3582 cmd->data.setadapterparms.hdr.used_total);
d11ba0c4 3583 QETH_DBF_TEXT_(TRACE, 4, "srseq%i",
4a71df50
FB		 3584 cmd->data.setadapterparms.hdr.seq_no);
3585 if (cmd->data.setadapterparms.hdr.seq_no <
3586 cmd->data.setadapterparms.hdr.used_total)
3587 return 1;
3588 return 0;
3589}
3590
3591int qeth_snmp_command(struct qeth_card *card, char __user *udata)
3592{
3593 struct qeth_cmd_buffer *iob;
3594 struct qeth_ipa_cmd *cmd;
3595 struct qeth_snmp_ureq *ureq;
3596 int req_len;
3597 struct qeth_arp_query_info qinfo = {0, };
3598 int rc = 0;
3599
d11ba0c4 3600 QETH_DBF_TEXT(TRACE, 3, "snmpcmd");
4a71df50
FB		 3601
3602 if (card->info.guestlan)
3603 return -EOPNOTSUPP;
3604
3605 if ((!qeth_adp_supported(card, IPA_SETADP_SET_SNMP_CONTROL)) &&
3606 (!card->options.layer2)) {
4a71df50
FB		 3607 return -EOPNOTSUPP;
3608 }
3609 /* skip 4 bytes (data_len struct member) to get req_len */
3610 if (copy_from_user(&req_len, udata + sizeof(int), sizeof(int)))
3611 return -EFAULT;
3612 ureq = kmalloc(req_len+sizeof(struct qeth_snmp_ureq_hdr), GFP_KERNEL);
3613 if (!ureq) {
d11ba0c4 3614 QETH_DBF_TEXT(TRACE, 2, "snmpnome");
4a71df50
FB		 3615 return -ENOMEM;
3616 }
3617 if (copy_from_user(ureq, udata,
3618 req_len + sizeof(struct qeth_snmp_ureq_hdr))) {
3619 kfree(ureq);
3620 return -EFAULT;
3621 }
3622 qinfo.udata_len = ureq->hdr.data_len;
3623 qinfo.udata = kzalloc(qinfo.udata_len, GFP_KERNEL);
3624 if (!qinfo.udata) {
3625 kfree(ureq);
3626 return -ENOMEM;
3627 }
3628 qinfo.udata_offset = sizeof(struct qeth_snmp_ureq_hdr);
3629
3630 iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,
3631 QETH_SNMP_SETADP_CMDLENGTH + req_len);
3632 cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
3633 memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);
3634 rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,
3635 qeth_snmp_command_cb, (void *)&qinfo);
3636 if (rc)
14cc21b6 3637 QETH_DBF_MESSAGE(2, "SNMP command failed on %s: (0x%x)\n",
4a71df50
FB		 3638 QETH_CARD_IFNAME(card), rc);
3639 else {
3640 if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))
3641 rc = -EFAULT;
3642 }
3643
3644 kfree(ureq);
3645 kfree(qinfo.udata);
3646 return rc;
3647}
3648EXPORT_SYMBOL_GPL(qeth_snmp_command);
3649
3650static inline int qeth_get_qdio_q_format(struct qeth_card *card)
3651{
3652 switch (card->info.type) {
3653 case QETH_CARD_TYPE_IQD:
3654 return 2;
3655 default:
3656 return 0;
3657 }
3658}
3659
3660static int qeth_qdio_establish(struct qeth_card *card)
3661{
3662 struct qdio_initialize init_data;
3663 char *qib_param_field;
3664 struct qdio_buffer **in_sbal_ptrs;
3665 struct qdio_buffer **out_sbal_ptrs;
3666 int i, j, k;
3667 int rc = 0;
3668
d11ba0c4 3669 QETH_DBF_TEXT(SETUP, 2, "qdioest");
4a71df50
FB		 3670
3671 qib_param_field = kzalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(char),
3672 GFP_KERNEL);
3673 if (!qib_param_field)
3674 return -ENOMEM;
3675
3676 qeth_create_qib_param_field(card, qib_param_field);
3677 qeth_create_qib_param_field_blkt(card, qib_param_field);
3678
3679 in_sbal_ptrs = kmalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(void *),
3680 GFP_KERNEL);
3681 if (!in_sbal_ptrs) {
3682 kfree(qib_param_field);
3683 return -ENOMEM;
3684 }
3685 for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
3686 in_sbal_ptrs[i] = (struct qdio_buffer *)
3687 virt_to_phys(card->qdio.in_q->bufs[i].buffer);
3688
3689 out_sbal_ptrs =
3690 kmalloc(card->qdio.no_out_queues * QDIO_MAX_BUFFERS_PER_Q *
3691 sizeof(void *), GFP_KERNEL);
3692 if (!out_sbal_ptrs) {
3693 kfree(in_sbal_ptrs);
3694 kfree(qib_param_field);
3695 return -ENOMEM;
3696 }
3697 for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i)
3698 for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j, ++k) {
3699 out_sbal_ptrs[k] = (struct qdio_buffer *)virt_to_phys(
3700 card->qdio.out_qs[i]->bufs[j].buffer);
3701 }
3702
3703 memset(&init_data, 0, sizeof(struct qdio_initialize));
3704 init_data.cdev = CARD_DDEV(card);
3705 init_data.q_format = qeth_get_qdio_q_format(card);
3706 init_data.qib_param_field_format = 0;
3707 init_data.qib_param_field = qib_param_field;
4a71df50
FB		 3708 init_data.no_input_qs = 1;
3709 init_data.no_output_qs = card->qdio.no_out_queues;
3710 init_data.input_handler = card->discipline.input_handler;
3711 init_data.output_handler = card->discipline.output_handler;
3712 init_data.int_parm = (unsigned long) card;
3713 init_data.flags = QDIO_INBOUND_0COPY_SBALS |
3714 QDIO_OUTBOUND_0COPY_SBALS |
3715 QDIO_USE_OUTBOUND_PCIS;
3716 init_data.input_sbal_addr_array = (void **) in_sbal_ptrs;
3717 init_data.output_sbal_addr_array = (void **) out_sbal_ptrs;
3718
3719 if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ALLOCATED,
3720 QETH_QDIO_ESTABLISHED) == QETH_QDIO_ALLOCATED) {
3721 rc = qdio_initialize(&init_data);
3722 if (rc)
3723 atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
3724 }
3725 kfree(out_sbal_ptrs);
3726 kfree(in_sbal_ptrs);
3727 kfree(qib_param_field);
3728 return rc;
3729}
3730
3731static void qeth_core_free_card(struct qeth_card *card)
3732{
3733
d11ba0c4
PT		 3734 QETH_DBF_TEXT(SETUP, 2, "freecrd");
3735 QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
4a71df50
FB		 3736 qeth_clean_channel(&card->read);
3737 qeth_clean_channel(&card->write);
3738 if (card->dev)
3739 free_netdev(card->dev);
3740 kfree(card->ip_tbd_list);
3741 qeth_free_qdio_buffers(card);
6bcac508 3742 unregister_service_level(&card->qeth_service_level);
4a71df50
FB		 3743 kfree(card);
3744}
3745
3746static struct ccw_device_id qeth_ids[] = {
3747 {CCW_DEVICE(0x1731, 0x01), .driver_info = QETH_CARD_TYPE_OSAE},
3748 {CCW_DEVICE(0x1731, 0x05), .driver_info = QETH_CARD_TYPE_IQD},
3749 {CCW_DEVICE(0x1731, 0x06), .driver_info = QETH_CARD_TYPE_OSN},
3750 {},
3751};
3752MODULE_DEVICE_TABLE(ccw, qeth_ids);
3753
3754static struct ccw_driver qeth_ccw_driver = {
3755 .name = "qeth",
3756 .ids = qeth_ids,
3757 .probe = ccwgroup_probe_ccwdev,
3758 .remove = ccwgroup_remove_ccwdev,
3759};
3760
3761static int qeth_core_driver_group(const char *buf, struct device *root_dev,
3762 unsigned long driver_id)
3763{
022b660a
UB		 3764 return ccwgroup_create_from_string(root_dev, driver_id,
3765 &qeth_ccw_driver, 3, buf);
4a71df50
FB		 3766}
3767
3768int qeth_core_hardsetup_card(struct qeth_card *card)
3769{
bbd50e17 3770 struct qdio_ssqd_desc *ssqd;
4a71df50 3771 int retries = 3;
779e6e1c 3772 int mpno = 0;
4a71df50
FB		 3773 int rc;
3774
d11ba0c4 3775 QETH_DBF_TEXT(SETUP, 2, "hrdsetup");
4a71df50
FB		 3776 atomic_set(&card->force_alloc_skb, 0);
3777retry:
3778 if (retries < 3) {
3779 PRINT_WARN("Retrying to do IDX activates.\n");
3780 ccw_device_set_offline(CARD_DDEV(card));
3781 ccw_device_set_offline(CARD_WDEV(card));
3782 ccw_device_set_offline(CARD_RDEV(card));
3783 ccw_device_set_online(CARD_RDEV(card));
3784 ccw_device_set_online(CARD_WDEV(card));
3785 ccw_device_set_online(CARD_DDEV(card));
3786 }
3787 rc = qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
3788 if (rc == -ERESTARTSYS) {
d11ba0c4 3789 QETH_DBF_TEXT(SETUP, 2, "break1");
4a71df50
FB		 3790 return rc;
3791 } else if (rc) {
d11ba0c4 3792 QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
4a71df50
FB		 3793 if (--retries < 0)
3794 goto out;
3795 else
3796 goto retry;
3797 }
3798
3799 rc = qeth_get_unitaddr(card);
3800 if (rc) {
d11ba0c4 3801 QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
4a71df50
FB		 3802 return rc;
3803 }
779e6e1c 3804
bbd50e17
JG		 3805 ssqd = kmalloc(sizeof(struct qdio_ssqd_desc), GFP_KERNEL);
3806 if (!ssqd) {
3807 rc = -ENOMEM;
3808 goto out;
3809 }
3810 rc = qdio_get_ssqd_desc(CARD_DDEV(card), ssqd);
3811 if (rc == 0)
3812 mpno = ssqd->pcnt;
3813 kfree(ssqd);
3814
a74b08c7
UB		 3815 if (mpno)
3816 mpno = min(mpno - 1, QETH_MAX_PORTNO);
4a71df50 3817 if (card->info.portno > mpno) {
14cc21b6
FB		 3818 QETH_DBF_MESSAGE(2, "Device %s does not offer port number %d"
3819 "\n.", CARD_BUS_ID(card), card->info.portno);
4a71df50
FB		 3820 rc = -ENODEV;
3821 goto out;
3822 }
3823 qeth_init_tokens(card);
3824 qeth_init_func_level(card);
3825 rc = qeth_idx_activate_channel(&card->read, qeth_idx_read_cb);
3826 if (rc == -ERESTARTSYS) {
d11ba0c4 3827 QETH_DBF_TEXT(SETUP, 2, "break2");
4a71df50
FB		 3828 return rc;
3829 } else if (rc) {
d11ba0c4 3830 QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
4a71df50
FB		 3831 if (--retries < 0)
3832 goto out;
3833 else
3834 goto retry;
3835 }
3836 rc = qeth_idx_activate_channel(&card->write, qeth_idx_write_cb);
3837 if (rc == -ERESTARTSYS) {
d11ba0c4 3838 QETH_DBF_TEXT(SETUP, 2, "break3");
4a71df50
FB		 3839 return rc;
3840 } else if (rc) {
d11ba0c4 3841 QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
4a71df50
FB		 3842 if (--retries < 0)
3843 goto out;
3844 else
3845 goto retry;
3846 }
3847 rc = qeth_mpc_initialize(card);
3848 if (rc) {
d11ba0c4 3849 QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
4a71df50
FB		 3850 goto out;
3851 }
3852 return 0;
3853out:
3854 PRINT_ERR("Initialization in hardsetup failed! rc=%d\n", rc);
3855 return rc;
3856}
3857EXPORT_SYMBOL_GPL(qeth_core_hardsetup_card);
3858
3859static inline int qeth_create_skb_frag(struct qdio_buffer_element *element,
3860 struct sk_buff **pskb, int offset, int *pfrag, int data_len)
3861{
3862 struct page *page = virt_to_page(element->addr);
3863 if (*pskb == NULL) {
3864 /* the upper protocol layers assume that there is data in the
3865 * skb itself. Copy a small amount (64 bytes) to make them
3866 * happy. */
3867 *pskb = dev_alloc_skb(64 + ETH_HLEN);
3868 if (!(*pskb))
3869 return -ENOMEM;
3870 skb_reserve(*pskb, ETH_HLEN);
3871 if (data_len <= 64) {
3872 memcpy(skb_put(*pskb, data_len), element->addr + offset,
3873 data_len);
3874 } else {
3875 get_page(page);
3876 memcpy(skb_put(*pskb, 64), element->addr + offset, 64);
3877 skb_fill_page_desc(*pskb, *pfrag, page, offset + 64,
3878 data_len - 64);
3879 (*pskb)->data_len += data_len - 64;
3880 (*pskb)->len += data_len - 64;
3881 (*pskb)->truesize += data_len - 64;
3882 (*pfrag)++;
3883 }
3884 } else {
3885 get_page(page);
3886 skb_fill_page_desc(*pskb, *pfrag, page, offset, data_len);
3887 (*pskb)->data_len += data_len;
3888 (*pskb)->len += data_len;
3889 (*pskb)->truesize += data_len;
3890 (*pfrag)++;
3891 }
3892 return 0;
3893}
3894
3895struct sk_buff *qeth_core_get_next_skb(struct qeth_card *card,
3896 struct qdio_buffer *buffer,
3897 struct qdio_buffer_element **__element, int *__offset,
3898 struct qeth_hdr **hdr)
3899{
3900 struct qdio_buffer_element *element = *__element;
3901 int offset = *__offset;
3902 struct sk_buff *skb = NULL;
3903 int skb_len;
3904 void *data_ptr;
3905 int data_len;
3906 int headroom = 0;
3907 int use_rx_sg = 0;
3908 int frag = 0;
3909
4a71df50
FB		 3910 /* qeth_hdr must not cross element boundaries */
3911 if (element->length < offset + sizeof(struct qeth_hdr)) {
3912 if (qeth_is_last_sbale(element))
3913 return NULL;
3914 element++;
3915 offset = 0;
3916 if (element->length < sizeof(struct qeth_hdr))
3917 return NULL;
3918 }
3919 *hdr = element->addr + offset;
3920
3921 offset += sizeof(struct qeth_hdr);
3922 if (card->options.layer2) {
3923 if (card->info.type == QETH_CARD_TYPE_OSN) {
3924 skb_len = (*hdr)->hdr.osn.pdu_length;
3925 headroom = sizeof(struct qeth_hdr);
3926 } else {
3927 skb_len = (*hdr)->hdr.l2.pkt_length;
3928 }
3929 } else {
3930 skb_len = (*hdr)->hdr.l3.length;
b403e685
FB		 3931 if ((card->info.link_type == QETH_LINK_TYPE_LANE_TR) ||
3932 (card->info.link_type == QETH_LINK_TYPE_HSTR))
3933 headroom = TR_HLEN;
3934 else
3935 headroom = ETH_HLEN;
4a71df50
FB		 3936 }
3937
3938 if (!skb_len)
3939 return NULL;
3940
3941 if ((skb_len >= card->options.rx_sg_cb) &&
3942 (!(card->info.type == QETH_CARD_TYPE_OSN)) &&
3943 (!atomic_read(&card->force_alloc_skb))) {
3944 use_rx_sg = 1;
3945 } else {
3946 skb = dev_alloc_skb(skb_len + headroom);
3947 if (!skb)
3948 goto no_mem;
3949 if (headroom)
3950 skb_reserve(skb, headroom);
3951 }
3952
3953 data_ptr = element->addr + offset;
3954 while (skb_len) {
3955 data_len = min(skb_len, (int)(element->length - offset));
3956 if (data_len) {
3957 if (use_rx_sg) {
3958 if (qeth_create_skb_frag(element, &skb, offset,
3959 &frag, data_len))
3960 goto no_mem;
3961 } else {
3962 memcpy(skb_put(skb, data_len), data_ptr,
3963 data_len);
3964 }
3965 }
3966 skb_len -= data_len;
3967 if (skb_len) {
3968 if (qeth_is_last_sbale(element)) {
d11ba0c4
PT		 3969 QETH_DBF_TEXT(TRACE, 4, "unexeob");
3970 QETH_DBF_TEXT_(TRACE, 4, "%s",
4a71df50 3971 CARD_BUS_ID(card));
d11ba0c4
PT		 3972 QETH_DBF_TEXT(QERR, 2, "unexeob");
3973 QETH_DBF_TEXT_(QERR, 2, "%s",
4a71df50 3974 CARD_BUS_ID(card));
d11ba0c4 3975 QETH_DBF_HEX(MISC, 4, buffer, sizeof(*buffer));
4a71df50
FB		 3976 dev_kfree_skb_any(skb);
3977 card->stats.rx_errors++;
3978 return NULL;
3979 }
3980 element++;
3981 offset = 0;
3982 data_ptr = element->addr;
3983 } else {
3984 offset += data_len;
3985 }
3986 }
3987 *__element = element;
3988 *__offset = offset;
3989 if (use_rx_sg && card->options.performance_stats) {
3990 card->perf_stats.sg_skbs_rx++;
3991 card->perf_stats.sg_frags_rx += skb_shinfo(skb)->nr_frags;
3992 }
3993 return skb;
3994no_mem:
3995 if (net_ratelimit()) {
d11ba0c4
PT		 3996 QETH_DBF_TEXT(TRACE, 2, "noskbmem");
3997 QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
4a71df50
FB		 3998 }
3999 card->stats.rx_dropped++;
4000 return NULL;
4001}
4002EXPORT_SYMBOL_GPL(qeth_core_get_next_skb);
4003
4004static void qeth_unregister_dbf_views(void)
4005{
d11ba0c4
PT		 4006 int x;
4007 for (x = 0; x < QETH_DBF_INFOS; x++) {
4008 debug_unregister(qeth_dbf[x].id);
4009 qeth_dbf[x].id = NULL;
4010 }
4a71df50
FB		 4011}
4012
345aa66e 4013void qeth_dbf_longtext(enum qeth_dbf_names dbf_nix, int level, char *fmt, ...)
cd023216
PT		 4014{
4015 char dbf_txt_buf[32];
345aa66e 4016 va_list args;
cd023216
PT		 4017
4018 if (level > (qeth_dbf[dbf_nix].id)->level)
4019 return;
345aa66e
PT		 4020 va_start(args, fmt);
4021 vsnprintf(dbf_txt_buf, sizeof(dbf_txt_buf), fmt, args);
4022 va_end(args);
cd023216 4023 debug_text_event(qeth_dbf[dbf_nix].id, level, dbf_txt_buf);
cd023216
PT		 4024}
4025EXPORT_SYMBOL_GPL(qeth_dbf_longtext);
4026
4a71df50
FB		 4027static int qeth_register_dbf_views(void)
4028{
d11ba0c4
PT		 4029 int ret;
4030 int x;
4031
4032 for (x = 0; x < QETH_DBF_INFOS; x++) {
4033 /* register the areas */
4034 qeth_dbf[x].id = debug_register(qeth_dbf[x].name,
4035 qeth_dbf[x].pages,
4036 qeth_dbf[x].areas,
4037 qeth_dbf[x].len);
4038 if (qeth_dbf[x].id == NULL) {
4039 qeth_unregister_dbf_views();
4040 return -ENOMEM;
4041 }
4a71df50 4042
d11ba0c4
PT		 4043 /* register a view */
4044 ret = debug_register_view(qeth_dbf[x].id, qeth_dbf[x].view);
4045 if (ret) {
4046 qeth_unregister_dbf_views();
4047 return ret;
4048 }
4a71df50 4049
d11ba0c4
PT		 4050 /* set a passing level */
4051 debug_set_level(qeth_dbf[x].id, qeth_dbf[x].level);
4052 }
4a71df50
FB		 4053
4054 return 0;
4055}
4056
4057int qeth_core_load_discipline(struct qeth_card *card,
4058 enum qeth_discipline_id discipline)
4059{
4060 int rc = 0;
4061 switch (discipline) {
4062 case QETH_DISCIPLINE_LAYER3:
4063 card->discipline.ccwgdriver = try_then_request_module(
4064 symbol_get(qeth_l3_ccwgroup_driver),
4065 "qeth_l3");
4066 break;
4067 case QETH_DISCIPLINE_LAYER2:
4068 card->discipline.ccwgdriver = try_then_request_module(
4069 symbol_get(qeth_l2_ccwgroup_driver),
4070 "qeth_l2");
4071 break;
4072 }
4073 if (!card->discipline.ccwgdriver) {
4074 PRINT_ERR("Support for discipline %d not present\n",
4075 discipline);
4076 rc = -EINVAL;
4077 }
4078 return rc;
4079}
4080
4081void qeth_core_free_discipline(struct qeth_card *card)
4082{
4083 if (card->options.layer2)
4084 symbol_put(qeth_l2_ccwgroup_driver);
4085 else
4086 symbol_put(qeth_l3_ccwgroup_driver);
4087 card->discipline.ccwgdriver = NULL;
4088}
4089
4090static int qeth_core_probe_device(struct ccwgroup_device *gdev)
4091{
4092 struct qeth_card *card;
4093 struct device *dev;
4094 int rc;
4095 unsigned long flags;
4096
d11ba0c4 4097 QETH_DBF_TEXT(SETUP, 2, "probedev");
4a71df50
FB		 4098
4099 dev = &gdev->dev;
4100 if (!get_device(dev))
4101 return -ENODEV;
4102
2a0217d5 4103 QETH_DBF_TEXT_(SETUP, 2, "%s", dev_name(&gdev->dev));
4a71df50
FB		 4104
4105 card = qeth_alloc_card();
4106 if (!card) {
d11ba0c4 4107 QETH_DBF_TEXT_(SETUP, 2, "1err%d", -ENOMEM);
4a71df50
FB		 4108 rc = -ENOMEM;
4109 goto err_dev;
4110 }
4111 card->read.ccwdev = gdev->cdev[0];
4112 card->write.ccwdev = gdev->cdev[1];
4113 card->data.ccwdev = gdev->cdev[2];
4114 dev_set_drvdata(&gdev->dev, card);
4115 card->gdev = gdev;
4116 gdev->cdev[0]->handler = qeth_irq;
4117 gdev->cdev[1]->handler = qeth_irq;
4118 gdev->cdev[2]->handler = qeth_irq;
4119
4120 rc = qeth_determine_card_type(card);
4121 if (rc) {
d11ba0c4 4122 QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
4a71df50
FB		 4123 goto err_card;
4124 }
4125 rc = qeth_setup_card(card);
4126 if (rc) {
d11ba0c4 4127 QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
4a71df50
FB		 4128 goto err_card;
4129 }
4130
4131 if (card->info.type == QETH_CARD_TYPE_OSN) {
4132 rc = qeth_core_create_osn_attributes(dev);
4133 if (rc)
4134 goto err_card;
4135 rc = qeth_core_load_discipline(card, QETH_DISCIPLINE_LAYER2);
4136 if (rc) {
4137 qeth_core_remove_osn_attributes(dev);
4138 goto err_card;
4139 }
4140 rc = card->discipline.ccwgdriver->probe(card->gdev);
4141 if (rc) {
4142 qeth_core_free_discipline(card);
4143 qeth_core_remove_osn_attributes(dev);
4144 goto err_card;
4145 }
4146 } else {
4147 rc = qeth_core_create_device_attributes(dev);
4148 if (rc)
4149 goto err_card;
4150 }
4151
4152 write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
4153 list_add_tail(&card->list, &qeth_core_card_list.list);
4154 write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
4155 return 0;
4156
4157err_card:
4158 qeth_core_free_card(card);
4159err_dev:
4160 put_device(dev);
4161 return rc;
4162}
4163
4164static void qeth_core_remove_device(struct ccwgroup_device *gdev)
4165{
4166 unsigned long flags;
4167 struct qeth_card *card = dev_get_drvdata(&gdev->dev);
4168
28a7e4c9 4169 QETH_DBF_TEXT(SETUP, 2, "removedv");
4a71df50
FB		 4170 if (card->discipline.ccwgdriver) {
4171 card->discipline.ccwgdriver->remove(gdev);
4172 qeth_core_free_discipline(card);
4173 }
4174
4175 if (card->info.type == QETH_CARD_TYPE_OSN) {
4176 qeth_core_remove_osn_attributes(&gdev->dev);
4177 } else {
4178 qeth_core_remove_device_attributes(&gdev->dev);
4179 }
4180 write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
4181 list_del(&card->list);
4182 write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
4183 qeth_core_free_card(card);
4184 dev_set_drvdata(&gdev->dev, NULL);
4185 put_device(&gdev->dev);
4186 return;
4187}
4188
4189static int qeth_core_set_online(struct ccwgroup_device *gdev)
4190{
4191 struct qeth_card *card = dev_get_drvdata(&gdev->dev);
4192 int rc = 0;
4193 int def_discipline;
4194
4195 if (!card->discipline.ccwgdriver) {
4196 if (card->info.type == QETH_CARD_TYPE_IQD)
4197 def_discipline = QETH_DISCIPLINE_LAYER3;
4198 else
4199 def_discipline = QETH_DISCIPLINE_LAYER2;
4200 rc = qeth_core_load_discipline(card, def_discipline);
4201 if (rc)
4202 goto err;
4203 rc = card->discipline.ccwgdriver->probe(card->gdev);
4204 if (rc)
4205 goto err;
4206 }
4207 rc = card->discipline.ccwgdriver->set_online(gdev);
4208err:
4209 return rc;
4210}
4211
4212static int qeth_core_set_offline(struct ccwgroup_device *gdev)
4213{
4214 struct qeth_card *card = dev_get_drvdata(&gdev->dev);
4215 return card->discipline.ccwgdriver->set_offline(gdev);
4216}
4217
4218static void qeth_core_shutdown(struct ccwgroup_device *gdev)
4219{
4220 struct qeth_card *card = dev_get_drvdata(&gdev->dev);
4221 if (card->discipline.ccwgdriver &&
4222 card->discipline.ccwgdriver->shutdown)
4223 card->discipline.ccwgdriver->shutdown(gdev);
4224}
4225
4226static struct ccwgroup_driver qeth_core_ccwgroup_driver = {
4227 .owner = THIS_MODULE,
4228 .name = "qeth",
4229 .driver_id = 0xD8C5E3C8,
4230 .probe = qeth_core_probe_device,
4231 .remove = qeth_core_remove_device,
4232 .set_online = qeth_core_set_online,
4233 .set_offline = qeth_core_set_offline,
4234 .shutdown = qeth_core_shutdown,
4235};
4236
4237static ssize_t
4238qeth_core_driver_group_store(struct device_driver *ddrv, const char *buf,
4239 size_t count)
4240{
4241 int err;
4242 err = qeth_core_driver_group(buf, qeth_core_root_dev,
4243 qeth_core_ccwgroup_driver.driver_id);
4244 if (err)
4245 return err;
4246 else
4247 return count;
4248}
4249
4250static DRIVER_ATTR(group, 0200, NULL, qeth_core_driver_group_store);
4251
4252static struct {
4253 const char str[ETH_GSTRING_LEN];
4254} qeth_ethtool_stats_keys[] = {
4255/* 0 */{"rx skbs"},
4256 {"rx buffers"},
4257 {"tx skbs"},
4258 {"tx buffers"},
4259 {"tx skbs no packing"},
4260 {"tx buffers no packing"},
4261 {"tx skbs packing"},
4262 {"tx buffers packing"},
4263 {"tx sg skbs"},
4264 {"tx sg frags"},
4265/* 10 */{"rx sg skbs"},
4266 {"rx sg frags"},
4267 {"rx sg page allocs"},
4268 {"tx large kbytes"},
4269 {"tx large count"},
4270 {"tx pk state ch n->p"},
4271 {"tx pk state ch p->n"},
4272 {"tx pk watermark low"},
4273 {"tx pk watermark high"},
4274 {"queue 0 buffer usage"},
4275/* 20 */{"queue 1 buffer usage"},
4276 {"queue 2 buffer usage"},
4277 {"queue 3 buffer usage"},
4278 {"rx handler time"},
4279 {"rx handler count"},
4280 {"rx do_QDIO time"},
4281 {"rx do_QDIO count"},
4282 {"tx handler time"},
4283 {"tx handler count"},
4284 {"tx time"},
4285/* 30 */{"tx count"},
4286 {"tx do_QDIO time"},
4287 {"tx do_QDIO count"},
4288};
4289
4290int qeth_core_get_stats_count(struct net_device *dev)
4291{
4292 return (sizeof(qeth_ethtool_stats_keys) / ETH_GSTRING_LEN);
4293}
4294EXPORT_SYMBOL_GPL(qeth_core_get_stats_count);
4295
4296void qeth_core_get_ethtool_stats(struct net_device *dev,
4297 struct ethtool_stats *stats, u64 *data)
4298{
509e2562 4299 struct qeth_card *card = dev->ml_priv;
4a71df50
FB		 4300 data[0] = card->stats.rx_packets -
4301 card->perf_stats.initial_rx_packets;
4302 data[1] = card->perf_stats.bufs_rec;
4303 data[2] = card->stats.tx_packets -
4304 card->perf_stats.initial_tx_packets;
4305 data[3] = card->perf_stats.bufs_sent;
4306 data[4] = card->stats.tx_packets - card->perf_stats.initial_tx_packets
4307 - card->perf_stats.skbs_sent_pack;
4308 data[5] = card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack;
4309 data[6] = card->perf_stats.skbs_sent_pack;
4310 data[7] = card->perf_stats.bufs_sent_pack;
4311 data[8] = card->perf_stats.sg_skbs_sent;
4312 data[9] = card->perf_stats.sg_frags_sent;
4313 data[10] = card->perf_stats.sg_skbs_rx;
4314 data[11] = card->perf_stats.sg_frags_rx;
4315 data[12] = card->perf_stats.sg_alloc_page_rx;
4316 data[13] = (card->perf_stats.large_send_bytes >> 10);
4317 data[14] = card->perf_stats.large_send_cnt;
4318 data[15] = card->perf_stats.sc_dp_p;
4319 data[16] = card->perf_stats.sc_p_dp;
4320 data[17] = QETH_LOW_WATERMARK_PACK;
4321 data[18] = QETH_HIGH_WATERMARK_PACK;
4322 data[19] = atomic_read(&card->qdio.out_qs[0]->used_buffers);
4323 data[20] = (card->qdio.no_out_queues > 1) ?
4324 atomic_read(&card->qdio.out_qs[1]->used_buffers) : 0;
4325 data[21] = (card->qdio.no_out_queues > 2) ?
4326 atomic_read(&card->qdio.out_qs[2]->used_buffers) : 0;
4327 data[22] = (card->qdio.no_out_queues > 3) ?
4328 atomic_read(&card->qdio.out_qs[3]->used_buffers) : 0;
4329 data[23] = card->perf_stats.inbound_time;
4330 data[24] = card->perf_stats.inbound_cnt;
4331 data[25] = card->perf_stats.inbound_do_qdio_time;
4332 data[26] = card->perf_stats.inbound_do_qdio_cnt;
4333 data[27] = card->perf_stats.outbound_handler_time;
4334 data[28] = card->perf_stats.outbound_handler_cnt;
4335 data[29] = card->perf_stats.outbound_time;
4336 data[30] = card->perf_stats.outbound_cnt;
4337 data[31] = card->perf_stats.outbound_do_qdio_time;
4338 data[32] = card->perf_stats.outbound_do_qdio_cnt;
4339}
4340EXPORT_SYMBOL_GPL(qeth_core_get_ethtool_stats);
4341
4342void qeth_core_get_strings(struct net_device *dev, u32 stringset, u8 *data)
4343{
4344 switch (stringset) {
4345 case ETH_SS_STATS:
4346 memcpy(data, &qeth_ethtool_stats_keys,
4347 sizeof(qeth_ethtool_stats_keys));
4348 break;
4349 default:
4350 WARN_ON(1);
4351 break;
4352 }
4353}
4354EXPORT_SYMBOL_GPL(qeth_core_get_strings);
4355
4356void qeth_core_get_drvinfo(struct net_device *dev,
4357 struct ethtool_drvinfo *info)
4358{
509e2562 4359 struct qeth_card *card = dev->ml_priv;
4a71df50
FB		 4360 if (card->options.layer2)
4361 strcpy(info->driver, "qeth_l2");
4362 else
4363 strcpy(info->driver, "qeth_l3");
4364
4365 strcpy(info->version, "1.0");
4366 strcpy(info->fw_version, card->info.mcl_level);
4367 sprintf(info->bus_info, "%s/%s/%s",
4368 CARD_RDEV_ID(card),
4369 CARD_WDEV_ID(card),
4370 CARD_DDEV_ID(card));
4371}
4372EXPORT_SYMBOL_GPL(qeth_core_get_drvinfo);
4373
3f9975aa
FB		 4374int qeth_core_ethtool_get_settings(struct net_device *netdev,
4375 struct ethtool_cmd *ecmd)
4376{
509e2562 4377 struct qeth_card *card = netdev->ml_priv;
3f9975aa
FB		 4378 enum qeth_link_types link_type;
4379
4380 if ((card->info.type == QETH_CARD_TYPE_IQD) || (card->info.guestlan))
4381 link_type = QETH_LINK_TYPE_10GBIT_ETH;
4382 else
4383 link_type = card->info.link_type;
4384
4385 ecmd->transceiver = XCVR_INTERNAL;
4386 ecmd->supported = SUPPORTED_Autoneg;
4387 ecmd->advertising = ADVERTISED_Autoneg;
4388 ecmd->duplex = DUPLEX_FULL;
4389 ecmd->autoneg = AUTONEG_ENABLE;
4390
4391 switch (link_type) {
4392 case QETH_LINK_TYPE_FAST_ETH:
4393 case QETH_LINK_TYPE_LANE_ETH100:
4394 ecmd->supported |= SUPPORTED_10baseT_Half |
4395 SUPPORTED_10baseT_Full |
4396 SUPPORTED_100baseT_Half |
4397 SUPPORTED_100baseT_Full |
4398 SUPPORTED_TP;
4399 ecmd->advertising |= ADVERTISED_10baseT_Half |
4400 ADVERTISED_10baseT_Full |
4401 ADVERTISED_100baseT_Half |
4402 ADVERTISED_100baseT_Full |
4403 ADVERTISED_TP;
4404 ecmd->speed = SPEED_100;
4405 ecmd->port = PORT_TP;
4406 break;
4407
4408 case QETH_LINK_TYPE_GBIT_ETH:
4409 case QETH_LINK_TYPE_LANE_ETH1000:
4410 ecmd->supported |= SUPPORTED_10baseT_Half |
4411 SUPPORTED_10baseT_Full |
4412 SUPPORTED_100baseT_Half |
4413 SUPPORTED_100baseT_Full |
4414 SUPPORTED_1000baseT_Half |
4415 SUPPORTED_1000baseT_Full |
4416 SUPPORTED_FIBRE;
4417 ecmd->advertising |= ADVERTISED_10baseT_Half |
4418 ADVERTISED_10baseT_Full |
4419 ADVERTISED_100baseT_Half |
4420 ADVERTISED_100baseT_Full |
4421 ADVERTISED_1000baseT_Half |
4422 ADVERTISED_1000baseT_Full |
4423 ADVERTISED_FIBRE;
4424 ecmd->speed = SPEED_1000;
4425 ecmd->port = PORT_FIBRE;
4426 break;
4427
4428 case QETH_LINK_TYPE_10GBIT_ETH:
4429 ecmd->supported |= SUPPORTED_10baseT_Half |
4430 SUPPORTED_10baseT_Full |
4431 SUPPORTED_100baseT_Half |
4432 SUPPORTED_100baseT_Full |
4433 SUPPORTED_1000baseT_Half |
4434 SUPPORTED_1000baseT_Full |
4435 SUPPORTED_10000baseT_Full |
4436 SUPPORTED_FIBRE;
4437 ecmd->advertising |= ADVERTISED_10baseT_Half |
4438 ADVERTISED_10baseT_Full |
4439 ADVERTISED_100baseT_Half |
4440 ADVERTISED_100baseT_Full |
4441 ADVERTISED_1000baseT_Half |
4442 ADVERTISED_1000baseT_Full |
4443 ADVERTISED_10000baseT_Full |
4444 ADVERTISED_FIBRE;
4445 ecmd->speed = SPEED_10000;
4446 ecmd->port = PORT_FIBRE;
4447 break;
4448
4449 default:
4450 ecmd->supported |= SUPPORTED_10baseT_Half |
4451 SUPPORTED_10baseT_Full |
4452 SUPPORTED_TP;
4453 ecmd->advertising |= ADVERTISED_10baseT_Half |
4454 ADVERTISED_10baseT_Full |
4455 ADVERTISED_TP;
4456 ecmd->speed = SPEED_10;
4457 ecmd->port = PORT_TP;
4458 }
4459
4460 return 0;
4461}
4462EXPORT_SYMBOL_GPL(qeth_core_ethtool_get_settings);
4463
4a71df50
FB		 4464static int __init qeth_core_init(void)
4465{
4466 int rc;
4467
4468 PRINT_INFO("loading core functions\n");
4469 INIT_LIST_HEAD(&qeth_core_card_list.list);
4470 rwlock_init(&qeth_core_card_list.rwlock);
4471
4472 rc = qeth_register_dbf_views();
4473 if (rc)
4474 goto out_err;
4475 rc = ccw_driver_register(&qeth_ccw_driver);
4476 if (rc)
4477 goto ccw_err;
4478 rc = ccwgroup_driver_register(&qeth_core_ccwgroup_driver);
4479 if (rc)
4480 goto ccwgroup_err;
4481 rc = driver_create_file(&qeth_core_ccwgroup_driver.driver,
4482 &driver_attr_group);
4483 if (rc)
4484 goto driver_err;
4485 qeth_core_root_dev = s390_root_dev_register("qeth");
4486 rc = IS_ERR(qeth_core_root_dev) ? PTR_ERR(qeth_core_root_dev) : 0;
4487 if (rc)
4488 goto register_err;
4a71df50 4489
683d718a
FB		 4490 qeth_core_header_cache = kmem_cache_create("qeth_hdr",
4491 sizeof(struct qeth_hdr) + ETH_HLEN, 64, 0, NULL);
4492 if (!qeth_core_header_cache) {
4493 rc = -ENOMEM;
4494 goto slab_err;
4495 }
4496
4497 return 0;
4498slab_err:
4499 s390_root_dev_unregister(qeth_core_root_dev);
4a71df50
FB		 4500register_err:
4501 driver_remove_file(&qeth_core_ccwgroup_driver.driver,
4502 &driver_attr_group);
4503driver_err:
4504 ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
4505ccwgroup_err:
4506 ccw_driver_unregister(&qeth_ccw_driver);
4507ccw_err:
4508 qeth_unregister_dbf_views();
4509out_err:
4510 PRINT_ERR("Initialization failed with code %d\n", rc);
4511 return rc;
4512}
4513
4514static void __exit qeth_core_exit(void)
4515{
4516 s390_root_dev_unregister(qeth_core_root_dev);
4517 driver_remove_file(&qeth_core_ccwgroup_driver.driver,
4518 &driver_attr_group);
4519 ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
4520 ccw_driver_unregister(&qeth_ccw_driver);
683d718a 4521 kmem_cache_destroy(qeth_core_header_cache);
4a71df50
FB		 4522 qeth_unregister_dbf_views();
4523 PRINT_INFO("core functions removed\n");
4524}
4525
4526module_init(qeth_core_init);
4527module_exit(qeth_core_exit);
4528MODULE_AUTHOR("Frank Blaschka <frank.blaschka@de.ibm.com>");
4529MODULE_DESCRIPTION("qeth core functions");
4530MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)