[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / s390 / cio / ioasm.h

#ifndef S390_CIO_IOASM_H
#define S390_CIO_IOASM_H

#include <asm/chpid.h>
#include <asm/schid.h>
#include "orb.h"
#include "cio.h"

/*
 * TPI info structure
 */
struct tpi_info {
	struct subchannel_id schid;
	__u32 intparm;		 /* interruption parameter */
	__u32 adapter_IO : 1;
	__u32 reserved2	 : 1;
	__u32 isc	 : 3;
	__u32 reserved3	 : 12;
	__u32 int_type	 : 3;
	__u32 reserved4	 : 12;
} __attribute__ ((packed));


/*
 * Some S390 specific IO instructions as inline
 */

static inline int stsch_err(struct subchannel_id schid, struct schib *addr)
{
	register struct subchannel_id reg1 asm ("1") = schid;
	int ccode = -EIO;

	asm volatile(
		"	stsch	0(%3)\n"
		"0:	ipm	%0\n"
		"	srl	%0,28\n"
		"1:\n"
		EX_TABLE(0b,1b)
		: "+d" (ccode), "=m" (*addr)
		: "d" (reg1), "a" (addr)
		: "cc");
	return ccode;
}

static inline int msch(struct subchannel_id schid, struct schib *addr)
{
	register struct subchannel_id reg1 asm ("1") = schid;
	int ccode;

	asm volatile(
		"	msch	0(%2)\n"
		"	ipm	%0\n"
		"	srl	%0,28"
		: "=d" (ccode)
		: "d" (reg1), "a" (addr), "m" (*addr)
		: "cc");
	return ccode;
}

static inline int msch_err(struct subchannel_id schid, struct schib *addr)
{
	register struct subchannel_id reg1 asm ("1") = schid;
	int ccode = -EIO;

	asm volatile(
		"	msch	0(%2)\n"
		"0:	ipm	%0\n"
		"	srl	%0,28\n"
		"1:\n"
		EX_TABLE(0b,1b)
		: "+d" (ccode)
		: "d" (reg1), "a" (addr), "m" (*addr)
		: "cc");
	return ccode;
}

static inline int tsch(struct subchannel_id schid, struct irb *addr)
{
	register struct subchannel_id reg1 asm ("1") = schid;
	int ccode;

	asm volatile(
		"	tsch	0(%3)\n"
		"	ipm	%0\n"
		"	srl	%0,28"
		: "=d" (ccode), "=m" (*addr)
		: "d" (reg1), "a" (addr)
		: "cc");
	return ccode;
}

static inline int ssch(struct subchannel_id schid, union orb *addr)
{
	register struct subchannel_id reg1 asm("1") = schid;
	int ccode = -EIO;

	asm volatile(
		"	ssch	0(%2)\n"
		"0:	ipm	%0\n"
		"	srl	%0,28\n"
		"1:\n"
		EX_TABLE(0b, 1b)
		: "+d" (ccode)
		: "d" (reg1), "a" (addr), "m" (*addr)
		: "cc", "memory");
	return ccode;
}

static inline int csch(struct subchannel_id schid)
{
	register struct subchannel_id reg1 asm("1") = schid;
	int ccode;

	asm volatile(
		"	csch\n"
		"	ipm	%0\n"
		"	srl	%0,28"
		: "=d" (ccode)
		: "d" (reg1)
		: "cc");
	return ccode;
}

static inline int tpi(struct tpi_info *addr)
{
	int ccode;

	asm volatile(
		"	tpi	0(%2)\n"
		"	ipm	%0\n"
		"	srl	%0,28"
		: "=d" (ccode), "=m" (*addr)
		: "a" (addr)
		: "cc");
	return ccode;
}

static inline int chsc(void *chsc_area)
{
	typedef struct { char _[4096]; } addr_type;
	int cc;

	asm volatile(
		"	.insn	rre,0xb25f0000,%2,0\n"
		"	ipm	%0\n"
		"	srl	%0,28\n"
		: "=d" (cc), "=m" (*(addr_type *) chsc_area)
		: "d" (chsc_area), "m" (*(addr_type *) chsc_area)
		: "cc");
	return cc;
}

static inline int rchp(struct chp_id chpid)
{
	register struct chp_id reg1 asm ("1") = chpid;
	int ccode;

	asm volatile(
		"	lr	1,%1\n"
		"	rchp\n"
		"	ipm	%0\n"
		"	srl	%0,28"
		: "=d" (ccode) : "d" (reg1) : "cc");
	return ccode;
}

#endif
Commit	Line	Data
1da177e4 LT	1	#ifndef S390_CIO_IOASM_H
	2	#define S390_CIO_IOASM_H
	3
e5854a58	4	#include <asm/chpid.h>
9d92a7e1	5	#include <asm/schid.h>
dbda8ce5 SO	6	#include "orb.h"
dbda8ce5 SO	7	#include "cio.h"
a8237fc4	8
1da177e4 LT	9	/*
	10	* TPI info structure
	11	*/
	12	struct tpi_info {
a8237fc4	13	struct subchannel_id schid;
1da177e4 LT	14	__u32 intparm; /* interruption parameter */
	15	__u32 adapter_IO : 1;
	16	__u32 reserved2 : 1;
	17	__u32 isc : 3;
	18	__u32 reserved3 : 12;
	19	__u32 int_type : 3;
	20	__u32 reserved4 : 12;
	21	} __attribute__ ((packed));
	22
	23
	24	/*
	25	* Some S390 specific IO instructions as inline
	26	*/
	27
f9c9fe3e	28	static inline int stsch_err(struct subchannel_id schid, struct schib *addr)
fb6958a5	29	{
94c12cc7 MS	30	register struct subchannel_id reg1 asm ("1") = schid;
94c12cc7 MS	31	int ccode = -EIO;
fb6958a5	32
94c12cc7	33	asm volatile(
f9c9fe3e	34	" stsch 0(%3)\n"
94c12cc7 MS	35	"0: ipm %0\n"
94c12cc7 MS	36	" srl %0,28\n"
fb6958a5	37	"1:\n"
94c12cc7	38	EX_TABLE(0b,1b)
f9c9fe3e PO	39	: "+d" (ccode), "=m" (*addr)
	40	: "d" (reg1), "a" (addr)
	41	: "cc");
fb6958a5 CH	42	return ccode;
	43	}
	44
f9c9fe3e	45	static inline int msch(struct subchannel_id schid, struct schib *addr)
1da177e4	46	{
94c12cc7	47	register struct subchannel_id reg1 asm ("1") = schid;
1da177e4 LT	48	int ccode;
1da177e4 LT	49
94c12cc7 MS	50	asm volatile(
	51	" msch 0(%2)\n"
	52	" ipm %0\n"
	53	" srl %0,28"
f9c9fe3e PO	54	: "=d" (ccode)
	55	: "d" (reg1), "a" (addr), "m" (*addr)
	56	: "cc");
1da177e4 LT	57	return ccode;
	58	}
	59
f9c9fe3e	60	static inline int msch_err(struct subchannel_id schid, struct schib *addr)
1da177e4	61	{
94c12cc7 MS	62	register struct subchannel_id reg1 asm ("1") = schid;
94c12cc7 MS	63	int ccode = -EIO;
1da177e4	64
94c12cc7 MS	65	asm volatile(
	66	" msch 0(%2)\n"
	67	"0: ipm %0\n"
	68	" srl %0,28\n"
1da177e4	69	"1:\n"
94c12cc7	70	EX_TABLE(0b,1b)
f9c9fe3e PO	71	: "+d" (ccode)
	72	: "d" (reg1), "a" (addr), "m" (*addr)
	73	: "cc");
1da177e4 LT	74	return ccode;
	75	}
	76
f9c9fe3e	77	static inline int tsch(struct subchannel_id schid, struct irb *addr)
1da177e4	78	{
94c12cc7	79	register struct subchannel_id reg1 asm ("1") = schid;
1da177e4 LT	80	int ccode;
1da177e4 LT	81
94c12cc7	82	asm volatile(
f9c9fe3e	83	" tsch 0(%3)\n"
94c12cc7 MS	84	" ipm %0\n"
94c12cc7 MS	85	" srl %0,28"
f9c9fe3e PO	86	: "=d" (ccode), "=m" (*addr)
	87	: "d" (reg1), "a" (addr)
	88	: "cc");
1da177e4 LT	89	return ccode;
	90	}
	91
dbda8ce5 SO	92	static inline int ssch(struct subchannel_id schid, union orb *addr)
	93	{
	94	register struct subchannel_id reg1 asm("1") = schid;
	95	int ccode = -EIO;
	96
	97	asm volatile(
	98	" ssch 0(%2)\n"
	99	"0: ipm %0\n"
	100	" srl %0,28\n"
	101	"1:\n"
	102	EX_TABLE(0b, 1b)
	103	: "+d" (ccode)
	104	: "d" (reg1), "a" (addr), "m" (*addr)
	105	: "cc", "memory");
	106	return ccode;
	107	}
	108
	109	static inline int csch(struct subchannel_id schid)
	110	{
	111	register struct subchannel_id reg1 asm("1") = schid;
	112	int ccode;
	113
	114	asm volatile(
	115	" csch\n"
	116	" ipm %0\n"
	117	" srl %0,28"
	118	: "=d" (ccode)
	119	: "d" (reg1)
	120	: "cc");
	121	return ccode;
	122	}
	123
f9c9fe3e	124	static inline int tpi(struct tpi_info *addr)
1da177e4 LT	125	{
	126	int ccode;
	127
94c12cc7	128	asm volatile(
f9c9fe3e	129	" tpi 0(%2)\n"
94c12cc7 MS	130	" ipm %0\n"
94c12cc7 MS	131	" srl %0,28"
f9c9fe3e PO	132	: "=d" (ccode), "=m" (*addr)
	133	: "a" (addr)
	134	: "cc");
1da177e4 LT	135	return ccode;
	136	}
	137
4c24da79	138	static inline int chsc(void *chsc_area)
1da177e4	139	{
a8237fc4	140	typedef struct { char _[4096]; } addr_type;
1da177e4 LT	141	int cc;
1da177e4 LT	142
94c12cc7 MS	143	asm volatile(
	144	" .insn rre,0xb25f0000,%2,0\n"
	145	" ipm %0\n"
	146	" srl %0,28\n"
a8237fc4 CH	147	: "=d" (cc), "=m" ((addr_type ) chsc_area)
a8237fc4 CH	148	: "d" (chsc_area), "m" ((addr_type ) chsc_area)
94c12cc7	149	: "cc");
1da177e4 LT	150	return cc;
	151	}
	152
f86635fa	153	static inline int rchp(struct chp_id chpid)
1da177e4	154	{
f86635fa	155	register struct chp_id reg1 asm ("1") = chpid;
1da177e4 LT	156	int ccode;
1da177e4 LT	157
94c12cc7 MS	158	asm volatile(
	159	" lr 1,%1\n"
	160	" rchp\n"
	161	" ipm %0\n"
	162	" srl %0,28"
	163	: "=d" (ccode) : "d" (reg1) : "cc");
1da177e4 LT	164	return ccode;
	165	}
	166
	167	#endif