[GitHub/LineageOS/android_kernel_samsung_universal7580.git] / drivers / rtc / rtc-twl.c

/*
 * rtc-twl.c -- TWL Real Time Clock interface
 *
 * Copyright (C) 2007 MontaVista Software, Inc
 * Author: Alexandre Rusev <source@mvista.com>
 *
 * Based on original TI driver twl4030-rtc.c
 *   Copyright (C) 2006 Texas Instruments, Inc.
 *
 * Based on rtc-omap.c
 *   Copyright (C) 2003 MontaVista Software, Inc.
 *   Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com>
 *   Copyright (C) 2006 David Brownell
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/rtc.h>
#include <linux/bcd.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>

#include <linux/i2c/twl.h>


/*
 * RTC block register offsets (use TWL_MODULE_RTC)
 */
enum {
	REG_SECONDS_REG = 0,
	REG_MINUTES_REG,
	REG_HOURS_REG,
	REG_DAYS_REG,
	REG_MONTHS_REG,
	REG_YEARS_REG,
	REG_WEEKS_REG,

	REG_ALARM_SECONDS_REG,
	REG_ALARM_MINUTES_REG,
	REG_ALARM_HOURS_REG,
	REG_ALARM_DAYS_REG,
	REG_ALARM_MONTHS_REG,
	REG_ALARM_YEARS_REG,

	REG_RTC_CTRL_REG,
	REG_RTC_STATUS_REG,
	REG_RTC_INTERRUPTS_REG,

	REG_RTC_COMP_LSB_REG,
	REG_RTC_COMP_MSB_REG,
};
static const u8 twl4030_rtc_reg_map[] = {
	[REG_SECONDS_REG] = 0x00,
	[REG_MINUTES_REG] = 0x01,
	[REG_HOURS_REG] = 0x02,
	[REG_DAYS_REG] = 0x03,
	[REG_MONTHS_REG] = 0x04,
	[REG_YEARS_REG] = 0x05,
	[REG_WEEKS_REG] = 0x06,

	[REG_ALARM_SECONDS_REG] = 0x07,
	[REG_ALARM_MINUTES_REG] = 0x08,
	[REG_ALARM_HOURS_REG] = 0x09,
	[REG_ALARM_DAYS_REG] = 0x0A,
	[REG_ALARM_MONTHS_REG] = 0x0B,
	[REG_ALARM_YEARS_REG] = 0x0C,

	[REG_RTC_CTRL_REG] = 0x0D,
	[REG_RTC_STATUS_REG] = 0x0E,
	[REG_RTC_INTERRUPTS_REG] = 0x0F,

	[REG_RTC_COMP_LSB_REG] = 0x10,
	[REG_RTC_COMP_MSB_REG] = 0x11,
};
static const u8 twl6030_rtc_reg_map[] = {
	[REG_SECONDS_REG] = 0x00,
	[REG_MINUTES_REG] = 0x01,
	[REG_HOURS_REG] = 0x02,
	[REG_DAYS_REG] = 0x03,
	[REG_MONTHS_REG] = 0x04,
	[REG_YEARS_REG] = 0x05,
	[REG_WEEKS_REG] = 0x06,

	[REG_ALARM_SECONDS_REG] = 0x08,
	[REG_ALARM_MINUTES_REG] = 0x09,
	[REG_ALARM_HOURS_REG] = 0x0A,
	[REG_ALARM_DAYS_REG] = 0x0B,
	[REG_ALARM_MONTHS_REG] = 0x0C,
	[REG_ALARM_YEARS_REG] = 0x0D,

	[REG_RTC_CTRL_REG] = 0x10,
	[REG_RTC_STATUS_REG] = 0x11,
	[REG_RTC_INTERRUPTS_REG] = 0x12,

	[REG_RTC_COMP_LSB_REG] = 0x13,
	[REG_RTC_COMP_MSB_REG] = 0x14,
};

/* RTC_CTRL_REG bitfields */
#define BIT_RTC_CTRL_REG_STOP_RTC_M              0x01
#define BIT_RTC_CTRL_REG_ROUND_30S_M             0x02
#define BIT_RTC_CTRL_REG_AUTO_COMP_M             0x04
#define BIT_RTC_CTRL_REG_MODE_12_24_M            0x08
#define BIT_RTC_CTRL_REG_TEST_MODE_M             0x10
#define BIT_RTC_CTRL_REG_SET_32_COUNTER_M        0x20
#define BIT_RTC_CTRL_REG_GET_TIME_M              0x40

/* RTC_STATUS_REG bitfields */
#define BIT_RTC_STATUS_REG_RUN_M                 0x02
#define BIT_RTC_STATUS_REG_1S_EVENT_M            0x04
#define BIT_RTC_STATUS_REG_1M_EVENT_M            0x08
#define BIT_RTC_STATUS_REG_1H_EVENT_M            0x10
#define BIT_RTC_STATUS_REG_1D_EVENT_M            0x20
#define BIT_RTC_STATUS_REG_ALARM_M               0x40
#define BIT_RTC_STATUS_REG_POWER_UP_M            0x80

/* RTC_INTERRUPTS_REG bitfields */
#define BIT_RTC_INTERRUPTS_REG_EVERY_M           0x03
#define BIT_RTC_INTERRUPTS_REG_IT_TIMER_M        0x04
#define BIT_RTC_INTERRUPTS_REG_IT_ALARM_M        0x08


/* REG_SECONDS_REG through REG_YEARS_REG is how many registers? */
#define ALL_TIME_REGS		6

/*----------------------------------------------------------------------*/
static u8  *rtc_reg_map;

/*
 * Supports 1 byte read from TWL RTC register.
 */
static int twl_rtc_read_u8(u8 *data, u8 reg)
{
	int ret;

	ret = twl_i2c_read_u8(TWL_MODULE_RTC, data, (rtc_reg_map[reg]));
	if (ret < 0)
		pr_err("twl_rtc: Could not read TWL"
		       "register %X - error %d\n", reg, ret);
	return ret;
}

/*
 * Supports 1 byte write to TWL RTC registers.
 */
static int twl_rtc_write_u8(u8 data, u8 reg)
{
	int ret;

	ret = twl_i2c_write_u8(TWL_MODULE_RTC, data, (rtc_reg_map[reg]));
	if (ret < 0)
		pr_err("twl_rtc: Could not write TWL"
		       "register %X - error %d\n", reg, ret);
	return ret;
}

/*
 * Cache the value for timer/alarm interrupts register; this is
 * only changed by callers holding rtc ops lock (or resume).
 */
static unsigned char rtc_irq_bits;

/*
 * Enable 1/second update and/or alarm interrupts.
 */
static int set_rtc_irq_bit(unsigned char bit)
{
	unsigned char val;
	int ret;

	val = rtc_irq_bits | bit;
	val &= ~BIT_RTC_INTERRUPTS_REG_EVERY_M;
	ret = twl_rtc_write_u8(val, REG_RTC_INTERRUPTS_REG);
	if (ret == 0)
		rtc_irq_bits = val;

	return ret;
}

/*
 * Disable update and/or alarm interrupts.
 */
static int mask_rtc_irq_bit(unsigned char bit)
{
	unsigned char val;
	int ret;

	val = rtc_irq_bits & ~bit;
	ret = twl_rtc_write_u8(val, REG_RTC_INTERRUPTS_REG);
	if (ret == 0)
		rtc_irq_bits = val;

	return ret;
}

static int twl_rtc_alarm_irq_enable(struct device *dev, unsigned enabled)
{
	int ret;

	if (enabled)
		ret = set_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
	else
		ret = mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);

	return ret;
}

/*
 * Gets current TWL RTC time and date parameters.
 *
 * The RTC's time/alarm representation is not what gmtime(3) requires
 * Linux to use:
 *
 *  - Months are 1..12 vs Linux 0-11
 *  - Years are 0..99 vs Linux 1900..N (we assume 21st century)
 */
static int twl_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	unsigned char rtc_data[ALL_TIME_REGS + 1];
	int ret;
	u8 save_control;

	ret = twl_rtc_read_u8(&save_control, REG_RTC_CTRL_REG);
	if (ret < 0)
		return ret;

	save_control |= BIT_RTC_CTRL_REG_GET_TIME_M;

	ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
	if (ret < 0)
		return ret;

	ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data,
			(rtc_reg_map[REG_SECONDS_REG]), ALL_TIME_REGS);

	if (ret < 0) {
		dev_err(dev, "rtc_read_time error %d\n", ret);
		return ret;
	}

	tm->tm_sec = bcd2bin(rtc_data[0]);
	tm->tm_min = bcd2bin(rtc_data[1]);
	tm->tm_hour = bcd2bin(rtc_data[2]);
	tm->tm_mday = bcd2bin(rtc_data[3]);
	tm->tm_mon = bcd2bin(rtc_data[4]) - 1;
	tm->tm_year = bcd2bin(rtc_data[5]) + 100;

	return ret;
}

static int twl_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	unsigned char save_control;
	unsigned char rtc_data[ALL_TIME_REGS + 1];
	int ret;

	rtc_data[1] = bin2bcd(tm->tm_sec);
	rtc_data[2] = bin2bcd(tm->tm_min);
	rtc_data[3] = bin2bcd(tm->tm_hour);
	rtc_data[4] = bin2bcd(tm->tm_mday);
	rtc_data[5] = bin2bcd(tm->tm_mon + 1);
	rtc_data[6] = bin2bcd(tm->tm_year - 100);

	/* Stop RTC while updating the TC registers */
	ret = twl_rtc_read_u8(&save_control, REG_RTC_CTRL_REG);
	if (ret < 0)
		goto out;

	save_control &= ~BIT_RTC_CTRL_REG_STOP_RTC_M;
	ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
	if (ret < 0)
		goto out;

	/* update all the time registers in one shot */
	ret = twl_i2c_write(TWL_MODULE_RTC, rtc_data,
		(rtc_reg_map[REG_SECONDS_REG]), ALL_TIME_REGS);
	if (ret < 0) {
		dev_err(dev, "rtc_set_time error %d\n", ret);
		goto out;
	}

	/* Start back RTC */
	save_control |= BIT_RTC_CTRL_REG_STOP_RTC_M;
	ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);

out:
	return ret;
}

/*
 * Gets current TWL RTC alarm time.
 */
static int twl_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
	unsigned char rtc_data[ALL_TIME_REGS + 1];
	int ret;

	ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data,
			(rtc_reg_map[REG_ALARM_SECONDS_REG]), ALL_TIME_REGS);
	if (ret < 0) {
		dev_err(dev, "rtc_read_alarm error %d\n", ret);
		return ret;
	}

	/* some of these fields may be wildcard/"match all" */
	alm->time.tm_sec = bcd2bin(rtc_data[0]);
	alm->time.tm_min = bcd2bin(rtc_data[1]);
	alm->time.tm_hour = bcd2bin(rtc_data[2]);
	alm->time.tm_mday = bcd2bin(rtc_data[3]);
	alm->time.tm_mon = bcd2bin(rtc_data[4]) - 1;
	alm->time.tm_year = bcd2bin(rtc_data[5]) + 100;

	/* report cached alarm enable state */
	if (rtc_irq_bits & BIT_RTC_INTERRUPTS_REG_IT_ALARM_M)
		alm->enabled = 1;

	return ret;
}

static int twl_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
	unsigned char alarm_data[ALL_TIME_REGS + 1];
	int ret;

	ret = twl_rtc_alarm_irq_enable(dev, 0);
	if (ret)
		goto out;

	alarm_data[1] = bin2bcd(alm->time.tm_sec);
	alarm_data[2] = bin2bcd(alm->time.tm_min);
	alarm_data[3] = bin2bcd(alm->time.tm_hour);
	alarm_data[4] = bin2bcd(alm->time.tm_mday);
	alarm_data[5] = bin2bcd(alm->time.tm_mon + 1);
	alarm_data[6] = bin2bcd(alm->time.tm_year - 100);

	/* update all the alarm registers in one shot */
	ret = twl_i2c_write(TWL_MODULE_RTC, alarm_data,
		(rtc_reg_map[REG_ALARM_SECONDS_REG]), ALL_TIME_REGS);
	if (ret) {
		dev_err(dev, "rtc_set_alarm error %d\n", ret);
		goto out;
	}

	if (alm->enabled)
		ret = twl_rtc_alarm_irq_enable(dev, 1);
out:
	return ret;
}

static irqreturn_t twl_rtc_interrupt(int irq, void *rtc)
{
	unsigned long events = 0;
	int ret = IRQ_NONE;
	int res;
	u8 rd_reg;

	res = twl_rtc_read_u8(&rd_reg, REG_RTC_STATUS_REG);
	if (res)
		goto out;
	/*
	 * Figure out source of interrupt: ALARM or TIMER in RTC_STATUS_REG.
	 * only one (ALARM or RTC) interrupt source may be enabled
	 * at time, we also could check our results
	 * by reading RTS_INTERRUPTS_REGISTER[IT_TIMER,IT_ALARM]
	 */
	if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M)
		events |= RTC_IRQF | RTC_AF;
	else
		events |= RTC_IRQF | RTC_UF;

	res = twl_rtc_write_u8(rd_reg | BIT_RTC_STATUS_REG_ALARM_M,
				   REG_RTC_STATUS_REG);
	if (res)
		goto out;

	if (twl_class_is_4030()) {
		/* Clear on Read enabled. RTC_IT bit of TWL4030_INT_PWR_ISR1
		 * needs 2 reads to clear the interrupt. One read is done in
		 * do_twl_pwrirq(). Doing the second read, to clear
		 * the bit.
		 *
		 * FIXME the reason PWR_ISR1 needs an extra read is that
		 * RTC_IF retriggered until we cleared REG_ALARM_M above.
		 * But re-reading like this is a bad hack; by doing so we
		 * risk wrongly clearing status for some other IRQ (losing
		 * the interrupt).  Be smarter about handling RTC_UF ...
		 */
		res = twl_i2c_read_u8(TWL4030_MODULE_INT,
			&rd_reg, TWL4030_INT_PWR_ISR1);
		if (res)
			goto out;
	}

	/* Notify RTC core on event */
	rtc_update_irq(rtc, 1, events);

	ret = IRQ_HANDLED;
out:
	return ret;
}

static struct rtc_class_ops twl_rtc_ops = {
	.read_time	= twl_rtc_read_time,
	.set_time	= twl_rtc_set_time,
	.read_alarm	= twl_rtc_read_alarm,
	.set_alarm	= twl_rtc_set_alarm,
	.alarm_irq_enable = twl_rtc_alarm_irq_enable,
};

/*----------------------------------------------------------------------*/

static int __devinit twl_rtc_probe(struct platform_device *pdev)
{
	struct rtc_device *rtc;
	int ret = -EINVAL;
	int irq = platform_get_irq(pdev, 0);
	u8 rd_reg;

	if (irq <= 0)
		goto out1;

	ret = twl_rtc_read_u8(&rd_reg, REG_RTC_STATUS_REG);
	if (ret < 0)
		goto out1;

	if (rd_reg & BIT_RTC_STATUS_REG_POWER_UP_M)
		dev_warn(&pdev->dev, "Power up reset detected.\n");

	if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M)
		dev_warn(&pdev->dev, "Pending Alarm interrupt detected.\n");

	/* Clear RTC Power up reset and pending alarm interrupts */
	ret = twl_rtc_write_u8(rd_reg, REG_RTC_STATUS_REG);
	if (ret < 0)
		goto out1;

	if (twl_class_is_6030()) {
		twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK,
			REG_INT_MSK_LINE_A);
		twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK,
			REG_INT_MSK_STS_A);
	}

	/* Check RTC module status, Enable if it is off */
	ret = twl_rtc_read_u8(&rd_reg, REG_RTC_CTRL_REG);
	if (ret < 0)
		goto out1;

	if (!(rd_reg & BIT_RTC_CTRL_REG_STOP_RTC_M)) {
		dev_info(&pdev->dev, "Enabling TWL-RTC.\n");
		rd_reg = BIT_RTC_CTRL_REG_STOP_RTC_M;
		ret = twl_rtc_write_u8(rd_reg, REG_RTC_CTRL_REG);
		if (ret < 0)
			goto out1;
	}

	/* init cached IRQ enable bits */
	ret = twl_rtc_read_u8(&rtc_irq_bits, REG_RTC_INTERRUPTS_REG);
	if (ret < 0)
		goto out1;

	rtc = rtc_device_register(pdev->name,
				  &pdev->dev, &twl_rtc_ops, THIS_MODULE);
	if (IS_ERR(rtc)) {
		ret = PTR_ERR(rtc);
		dev_err(&pdev->dev, "can't register RTC device, err %ld\n",
			PTR_ERR(rtc));
		goto out1;
	}

	ret = request_threaded_irq(irq, NULL, twl_rtc_interrupt,
				   IRQF_TRIGGER_RISING,
				   dev_name(&rtc->dev), rtc);
	if (ret < 0) {
		dev_err(&pdev->dev, "IRQ is not free.\n");
		goto out2;
	}

	platform_set_drvdata(pdev, rtc);
	return 0;

out2:
	rtc_device_unregister(rtc);
out1:
	return ret;
}

/*
 * Disable all TWL RTC module interrupts.
 * Sets status flag to free.
 */
static int __devexit twl_rtc_remove(struct platform_device *pdev)
{
	/* leave rtc running, but disable irqs */
	struct rtc_device *rtc = platform_get_drvdata(pdev);
	int irq = platform_get_irq(pdev, 0);

	mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
	mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
	if (twl_class_is_6030()) {
		twl6030_interrupt_mask(TWL6030_RTC_INT_MASK,
			REG_INT_MSK_LINE_A);
		twl6030_interrupt_mask(TWL6030_RTC_INT_MASK,
			REG_INT_MSK_STS_A);
	}


	free_irq(irq, rtc);

	rtc_device_unregister(rtc);
	platform_set_drvdata(pdev, NULL);
	return 0;
}

static void twl_rtc_shutdown(struct platform_device *pdev)
{
	/* mask timer interrupts, but leave alarm interrupts on to enable
	   power-on when alarm is triggered */
	mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
}

#ifdef CONFIG_PM

static unsigned char irqstat;

static int twl_rtc_suspend(struct platform_device *pdev, pm_message_t state)
{
	irqstat = rtc_irq_bits;

	mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
	return 0;
}

static int twl_rtc_resume(struct platform_device *pdev)
{
	set_rtc_irq_bit(irqstat);
	return 0;
}

#else
#define twl_rtc_suspend NULL
#define twl_rtc_resume  NULL
#endif

MODULE_ALIAS("platform:twl_rtc");

static struct platform_driver twl4030rtc_driver = {
	.probe		= twl_rtc_probe,
	.remove		= __devexit_p(twl_rtc_remove),
	.shutdown	= twl_rtc_shutdown,
	.suspend	= twl_rtc_suspend,
	.resume		= twl_rtc_resume,
	.driver		= {
		.owner	= THIS_MODULE,
		.name	= "twl_rtc",
	},
};

static int __init twl_rtc_init(void)
{
	if (twl_class_is_4030())
		rtc_reg_map = (u8 *) twl4030_rtc_reg_map;
	else
		rtc_reg_map = (u8 *) twl6030_rtc_reg_map;

	return platform_driver_register(&twl4030rtc_driver);
}
module_init(twl_rtc_init);

static void __exit twl_rtc_exit(void)
{
	platform_driver_unregister(&twl4030rtc_driver);
}
module_exit(twl_rtc_exit);

MODULE_AUTHOR("Texas Instruments, MontaVista Software");
MODULE_LICENSE("GPL");
Commit	Line	Data
f96411ab	1	/*
ef3b7d0d	2	* rtc-twl.c -- TWL Real Time Clock interface
f96411ab DB	3	*
	4	* Copyright (C) 2007 MontaVista Software, Inc
	5	* Author: Alexandre Rusev <source@mvista.com>
	6	*
	7	* Based on original TI driver twl4030-rtc.c
	8	* Copyright (C) 2006 Texas Instruments, Inc.
	9	*
	10	* Based on rtc-omap.c
	11	* Copyright (C) 2003 MontaVista Software, Inc.
	12	* Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com>
	13	* Copyright (C) 2006 David Brownell
	14	*
	15	* This program is free software; you can redistribute it and/or
	16	* modify it under the terms of the GNU General Public License
	17	* as published by the Free Software Foundation; either version
	18	* 2 of the License, or (at your option) any later version.
	19	*/
	20
	21	#include <linux/kernel.h>
2fac6674	22	#include <linux/errno.h>
f96411ab DB	23	#include <linux/init.h>
	24	#include <linux/module.h>
	25	#include <linux/types.h>
	26	#include <linux/rtc.h>
	27	#include <linux/bcd.h>
	28	#include <linux/platform_device.h>
	29	#include <linux/interrupt.h>
	30
b07682b6	31	#include <linux/i2c/twl.h>
f96411ab DB	32
	33
	34	/*
	35	* RTC block register offsets (use TWL_MODULE_RTC)
	36	*/
a6b49ffd B	37	enum {
	38	REG_SECONDS_REG = 0,
	39	REG_MINUTES_REG,
	40	REG_HOURS_REG,
	41	REG_DAYS_REG,
	42	REG_MONTHS_REG,
	43	REG_YEARS_REG,
	44	REG_WEEKS_REG,
	45
	46	REG_ALARM_SECONDS_REG,
	47	REG_ALARM_MINUTES_REG,
	48	REG_ALARM_HOURS_REG,
	49	REG_ALARM_DAYS_REG,
	50	REG_ALARM_MONTHS_REG,
	51	REG_ALARM_YEARS_REG,
	52
	53	REG_RTC_CTRL_REG,
	54	REG_RTC_STATUS_REG,
	55	REG_RTC_INTERRUPTS_REG,
	56
	57	REG_RTC_COMP_LSB_REG,
	58	REG_RTC_COMP_MSB_REG,
	59	};
2e84067b	60	static const u8 twl4030_rtc_reg_map[] = {
a6b49ffd B	61	[REG_SECONDS_REG] = 0x00,
	62	[REG_MINUTES_REG] = 0x01,
	63	[REG_HOURS_REG] = 0x02,
	64	[REG_DAYS_REG] = 0x03,
	65	[REG_MONTHS_REG] = 0x04,
	66	[REG_YEARS_REG] = 0x05,
	67	[REG_WEEKS_REG] = 0x06,
	68
	69	[REG_ALARM_SECONDS_REG] = 0x07,
	70	[REG_ALARM_MINUTES_REG] = 0x08,
	71	[REG_ALARM_HOURS_REG] = 0x09,
	72	[REG_ALARM_DAYS_REG] = 0x0A,
	73	[REG_ALARM_MONTHS_REG] = 0x0B,
	74	[REG_ALARM_YEARS_REG] = 0x0C,
	75
	76	[REG_RTC_CTRL_REG] = 0x0D,
	77	[REG_RTC_STATUS_REG] = 0x0E,
	78	[REG_RTC_INTERRUPTS_REG] = 0x0F,
	79
	80	[REG_RTC_COMP_LSB_REG] = 0x10,
	81	[REG_RTC_COMP_MSB_REG] = 0x11,
	82	};
2e84067b	83	static const u8 twl6030_rtc_reg_map[] = {
a6b49ffd B	84	[REG_SECONDS_REG] = 0x00,
	85	[REG_MINUTES_REG] = 0x01,
	86	[REG_HOURS_REG] = 0x02,
	87	[REG_DAYS_REG] = 0x03,
	88	[REG_MONTHS_REG] = 0x04,
	89	[REG_YEARS_REG] = 0x05,
	90	[REG_WEEKS_REG] = 0x06,
	91
	92	[REG_ALARM_SECONDS_REG] = 0x08,
	93	[REG_ALARM_MINUTES_REG] = 0x09,
	94	[REG_ALARM_HOURS_REG] = 0x0A,
	95	[REG_ALARM_DAYS_REG] = 0x0B,
	96	[REG_ALARM_MONTHS_REG] = 0x0C,
	97	[REG_ALARM_YEARS_REG] = 0x0D,
	98
	99	[REG_RTC_CTRL_REG] = 0x10,
	100	[REG_RTC_STATUS_REG] = 0x11,
	101	[REG_RTC_INTERRUPTS_REG] = 0x12,
	102
	103	[REG_RTC_COMP_LSB_REG] = 0x13,
	104	[REG_RTC_COMP_MSB_REG] = 0x14,
	105	};
f96411ab DB	106
	107	/* RTC_CTRL_REG bitfields */
	108	#define BIT_RTC_CTRL_REG_STOP_RTC_M 0x01
	109	#define BIT_RTC_CTRL_REG_ROUND_30S_M 0x02
	110	#define BIT_RTC_CTRL_REG_AUTO_COMP_M 0x04
	111	#define BIT_RTC_CTRL_REG_MODE_12_24_M 0x08
	112	#define BIT_RTC_CTRL_REG_TEST_MODE_M 0x10
	113	#define BIT_RTC_CTRL_REG_SET_32_COUNTER_M 0x20
	114	#define BIT_RTC_CTRL_REG_GET_TIME_M 0x40
	115
	116	/* RTC_STATUS_REG bitfields */
	117	#define BIT_RTC_STATUS_REG_RUN_M 0x02
	118	#define BIT_RTC_STATUS_REG_1S_EVENT_M 0x04
	119	#define BIT_RTC_STATUS_REG_1M_EVENT_M 0x08
	120	#define BIT_RTC_STATUS_REG_1H_EVENT_M 0x10
	121	#define BIT_RTC_STATUS_REG_1D_EVENT_M 0x20
	122	#define BIT_RTC_STATUS_REG_ALARM_M 0x40
	123	#define BIT_RTC_STATUS_REG_POWER_UP_M 0x80
	124
	125	/* RTC_INTERRUPTS_REG bitfields */
	126	#define BIT_RTC_INTERRUPTS_REG_EVERY_M 0x03
	127	#define BIT_RTC_INTERRUPTS_REG_IT_TIMER_M 0x04
	128	#define BIT_RTC_INTERRUPTS_REG_IT_ALARM_M 0x08
	129
	130
	131	/* REG_SECONDS_REG through REG_YEARS_REG is how many registers? */
	132	#define ALL_TIME_REGS 6
	133
	134	/----------------------------------------------------------------------/
a6b49ffd	135	static u8 *rtc_reg_map;
f96411ab DB	136
f96411ab DB	137	/*
ef3b7d0d	138	* Supports 1 byte read from TWL RTC register.
f96411ab	139	*/
ef3b7d0d	140	static int twl_rtc_read_u8(u8 *data, u8 reg)
f96411ab DB	141	{
	142	int ret;
	143
a6b49ffd	144	ret = twl_i2c_read_u8(TWL_MODULE_RTC, data, (rtc_reg_map[reg]));
f96411ab	145	if (ret < 0)
ef3b7d0d	146	pr_err("twl_rtc: Could not read TWL"
f96411ab DB	147	"register %X - error %d\n", reg, ret);
	148	return ret;
	149	}
	150
	151	/*
ef3b7d0d	152	* Supports 1 byte write to TWL RTC registers.
f96411ab	153	*/
ef3b7d0d	154	static int twl_rtc_write_u8(u8 data, u8 reg)
f96411ab DB	155	{
	156	int ret;
	157
a6b49ffd	158	ret = twl_i2c_write_u8(TWL_MODULE_RTC, data, (rtc_reg_map[reg]));
f96411ab	159	if (ret < 0)
ef3b7d0d	160	pr_err("twl_rtc: Could not write TWL"
f96411ab DB	161	"register %X - error %d\n", reg, ret);
	162	return ret;
	163	}
	164
	165	/*
	166	* Cache the value for timer/alarm interrupts register; this is
	167	* only changed by callers holding rtc ops lock (or resume).
	168	*/
	169	static unsigned char rtc_irq_bits;
	170
	171	/*
a748384b	172	* Enable 1/second update and/or alarm interrupts.
f96411ab DB	173	*/
	174	static int set_rtc_irq_bit(unsigned char bit)
	175	{
	176	unsigned char val;
	177	int ret;
	178
	179	val = rtc_irq_bits \| bit;
a748384b	180	val &= ~BIT_RTC_INTERRUPTS_REG_EVERY_M;
ef3b7d0d	181	ret = twl_rtc_write_u8(val, REG_RTC_INTERRUPTS_REG);
f96411ab DB	182	if (ret == 0)
	183	rtc_irq_bits = val;
	184
	185	return ret;
	186	}
	187
	188	/*
a748384b	189	* Disable update and/or alarm interrupts.
f96411ab DB	190	*/
	191	static int mask_rtc_irq_bit(unsigned char bit)
	192	{
	193	unsigned char val;
	194	int ret;
	195
	196	val = rtc_irq_bits & ~bit;
ef3b7d0d	197	ret = twl_rtc_write_u8(val, REG_RTC_INTERRUPTS_REG);
f96411ab DB	198	if (ret == 0)
	199	rtc_irq_bits = val;
	200
	201	return ret;
	202	}
	203
ef3b7d0d	204	static int twl_rtc_alarm_irq_enable(struct device *dev, unsigned enabled)
f96411ab DB	205	{
	206	int ret;
	207
	208	if (enabled)
	209	ret = set_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
	210	else
	211	ret = mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
	212
	213	return ret;
	214	}
	215
f96411ab	216	/*
ef3b7d0d	217	* Gets current TWL RTC time and date parameters.
f96411ab DB	218	*
	219	* The RTC's time/alarm representation is not what gmtime(3) requires
	220	* Linux to use:
	221	*
	222	* - Months are 1..12 vs Linux 0-11
	223	* - Years are 0..99 vs Linux 1900..N (we assume 21st century)
	224	*/
ef3b7d0d	225	static int twl_rtc_read_time(struct device dev, struct rtc_time tm)
f96411ab DB	226	{
	227	unsigned char rtc_data[ALL_TIME_REGS + 1];
	228	int ret;
	229	u8 save_control;
	230
ef3b7d0d	231	ret = twl_rtc_read_u8(&save_control, REG_RTC_CTRL_REG);
f96411ab DB	232	if (ret < 0)
	233	return ret;
	234
	235	save_control \|= BIT_RTC_CTRL_REG_GET_TIME_M;
	236
ef3b7d0d	237	ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
f96411ab DB	238	if (ret < 0)
	239	return ret;
	240
ef3b7d0d	241	ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data,
a6b49ffd	242	(rtc_reg_map[REG_SECONDS_REG]), ALL_TIME_REGS);
f96411ab DB	243
	244	if (ret < 0) {
	245	dev_err(dev, "rtc_read_time error %d\n", ret);
	246	return ret;
	247	}
	248
	249	tm->tm_sec = bcd2bin(rtc_data[0]);
	250	tm->tm_min = bcd2bin(rtc_data[1]);
	251	tm->tm_hour = bcd2bin(rtc_data[2]);
	252	tm->tm_mday = bcd2bin(rtc_data[3]);
	253	tm->tm_mon = bcd2bin(rtc_data[4]) - 1;
	254	tm->tm_year = bcd2bin(rtc_data[5]) + 100;
	255
	256	return ret;
	257	}
	258
ef3b7d0d	259	static int twl_rtc_set_time(struct device dev, struct rtc_time tm)
f96411ab DB	260	{
	261	unsigned char save_control;
	262	unsigned char rtc_data[ALL_TIME_REGS + 1];
	263	int ret;
	264
	265	rtc_data[1] = bin2bcd(tm->tm_sec);
	266	rtc_data[2] = bin2bcd(tm->tm_min);
	267	rtc_data[3] = bin2bcd(tm->tm_hour);
	268	rtc_data[4] = bin2bcd(tm->tm_mday);
	269	rtc_data[5] = bin2bcd(tm->tm_mon + 1);
	270	rtc_data[6] = bin2bcd(tm->tm_year - 100);
	271
	272	/* Stop RTC while updating the TC registers */
ef3b7d0d	273	ret = twl_rtc_read_u8(&save_control, REG_RTC_CTRL_REG);
f96411ab DB	274	if (ret < 0)
	275	goto out;
	276
	277	save_control &= ~BIT_RTC_CTRL_REG_STOP_RTC_M;
8f6b0dd3	278	ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
f96411ab DB	279	if (ret < 0)
	280	goto out;
	281
	282	/* update all the time registers in one shot */
ef3b7d0d	283	ret = twl_i2c_write(TWL_MODULE_RTC, rtc_data,
a6b49ffd	284	(rtc_reg_map[REG_SECONDS_REG]), ALL_TIME_REGS);
f96411ab DB	285	if (ret < 0) {
	286	dev_err(dev, "rtc_set_time error %d\n", ret);
	287	goto out;
	288	}
	289
	290	/* Start back RTC */
	291	save_control \|= BIT_RTC_CTRL_REG_STOP_RTC_M;
ef3b7d0d	292	ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
f96411ab DB	293
	294	out:
	295	return ret;
	296	}
	297
	298	/*
ef3b7d0d	299	* Gets current TWL RTC alarm time.
f96411ab	300	*/
ef3b7d0d	301	static int twl_rtc_read_alarm(struct device dev, struct rtc_wkalrm alm)
f96411ab DB	302	{
	303	unsigned char rtc_data[ALL_TIME_REGS + 1];
	304	int ret;
	305
ef3b7d0d	306	ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data,
a6b49ffd	307	(rtc_reg_map[REG_ALARM_SECONDS_REG]), ALL_TIME_REGS);
f96411ab DB	308	if (ret < 0) {
	309	dev_err(dev, "rtc_read_alarm error %d\n", ret);
	310	return ret;
	311	}
	312
	313	/* some of these fields may be wildcard/"match all" */
	314	alm->time.tm_sec = bcd2bin(rtc_data[0]);
	315	alm->time.tm_min = bcd2bin(rtc_data[1]);
	316	alm->time.tm_hour = bcd2bin(rtc_data[2]);
	317	alm->time.tm_mday = bcd2bin(rtc_data[3]);
	318	alm->time.tm_mon = bcd2bin(rtc_data[4]) - 1;
	319	alm->time.tm_year = bcd2bin(rtc_data[5]) + 100;
	320
	321	/* report cached alarm enable state */
	322	if (rtc_irq_bits & BIT_RTC_INTERRUPTS_REG_IT_ALARM_M)
	323	alm->enabled = 1;
	324
	325	return ret;
	326	}
	327
ef3b7d0d	328	static int twl_rtc_set_alarm(struct device dev, struct rtc_wkalrm alm)
f96411ab DB	329	{
	330	unsigned char alarm_data[ALL_TIME_REGS + 1];
	331	int ret;
	332
ef3b7d0d	333	ret = twl_rtc_alarm_irq_enable(dev, 0);
f96411ab DB	334	if (ret)
	335	goto out;
	336
	337	alarm_data[1] = bin2bcd(alm->time.tm_sec);
	338	alarm_data[2] = bin2bcd(alm->time.tm_min);
	339	alarm_data[3] = bin2bcd(alm->time.tm_hour);
	340	alarm_data[4] = bin2bcd(alm->time.tm_mday);
	341	alarm_data[5] = bin2bcd(alm->time.tm_mon + 1);
	342	alarm_data[6] = bin2bcd(alm->time.tm_year - 100);
	343
	344	/* update all the alarm registers in one shot */
ef3b7d0d	345	ret = twl_i2c_write(TWL_MODULE_RTC, alarm_data,
a6b49ffd	346	(rtc_reg_map[REG_ALARM_SECONDS_REG]), ALL_TIME_REGS);
f96411ab DB	347	if (ret) {
	348	dev_err(dev, "rtc_set_alarm error %d\n", ret);
	349	goto out;
	350	}
	351
	352	if (alm->enabled)
ef3b7d0d	353	ret = twl_rtc_alarm_irq_enable(dev, 1);
f96411ab DB	354	out:
	355	return ret;
	356	}
	357
ef3b7d0d	358	static irqreturn_t twl_rtc_interrupt(int irq, void *rtc)
f96411ab DB	359	{
	360	unsigned long events = 0;
	361	int ret = IRQ_NONE;
	362	int res;
	363	u8 rd_reg;
	364
ef3b7d0d	365	res = twl_rtc_read_u8(&rd_reg, REG_RTC_STATUS_REG);
f96411ab DB	366	if (res)
	367	goto out;
	368	/*
	369	* Figure out source of interrupt: ALARM or TIMER in RTC_STATUS_REG.
	370	* only one (ALARM or RTC) interrupt source may be enabled
	371	* at time, we also could check our results
	372	* by reading RTS_INTERRUPTS_REGISTER[IT_TIMER,IT_ALARM]
	373	*/
	374	if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M)
	375	events \|= RTC_IRQF \| RTC_AF;
	376	else
	377	events \|= RTC_IRQF \| RTC_UF;
	378
ef3b7d0d	379	res = twl_rtc_write_u8(rd_reg \| BIT_RTC_STATUS_REG_ALARM_M,
f96411ab DB	380	REG_RTC_STATUS_REG);
	381	if (res)
	382	goto out;
	383
a6b49ffd B	384	if (twl_class_is_4030()) {
	385	/* Clear on Read enabled. RTC_IT bit of TWL4030_INT_PWR_ISR1
	386	* needs 2 reads to clear the interrupt. One read is done in
	387	* do_twl_pwrirq(). Doing the second read, to clear
	388	* the bit.
	389	*
	390	* FIXME the reason PWR_ISR1 needs an extra read is that
	391	* RTC_IF retriggered until we cleared REG_ALARM_M above.
	392	* But re-reading like this is a bad hack; by doing so we
	393	* risk wrongly clearing status for some other IRQ (losing
	394	* the interrupt). Be smarter about handling RTC_UF ...
	395	*/
	396	res = twl_i2c_read_u8(TWL4030_MODULE_INT,
f96411ab	397	&rd_reg, TWL4030_INT_PWR_ISR1);
a6b49ffd B	398	if (res)
	399	goto out;
	400	}
f96411ab DB	401
	402	/* Notify RTC core on event */
	403	rtc_update_irq(rtc, 1, events);
	404
	405	ret = IRQ_HANDLED;
	406	out:
	407	return ret;
	408	}
	409
ef3b7d0d B	410	static struct rtc_class_ops twl_rtc_ops = {
	411	.read_time = twl_rtc_read_time,
	412	.set_time = twl_rtc_set_time,
	413	.read_alarm = twl_rtc_read_alarm,
	414	.set_alarm = twl_rtc_set_alarm,
	415	.alarm_irq_enable = twl_rtc_alarm_irq_enable,
f96411ab DB	416	};
	417
	418	/----------------------------------------------------------------------/
	419
ef3b7d0d	420	static int __devinit twl_rtc_probe(struct platform_device *pdev)
f96411ab DB	421	{
f96411ab DB	422	struct rtc_device *rtc;
7e72c686	423	int ret = -EINVAL;
f96411ab DB	424	int irq = platform_get_irq(pdev, 0);
	425	u8 rd_reg;
	426
2fac6674	427	if (irq <= 0)
7e72c686	428	goto out1;
f96411ab	429
ef3b7d0d	430	ret = twl_rtc_read_u8(&rd_reg, REG_RTC_STATUS_REG);
f96411ab DB	431	if (ret < 0)
	432	goto out1;
	433
	434	if (rd_reg & BIT_RTC_STATUS_REG_POWER_UP_M)
	435	dev_warn(&pdev->dev, "Power up reset detected.\n");
	436
	437	if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M)
	438	dev_warn(&pdev->dev, "Pending Alarm interrupt detected.\n");
	439
	440	/* Clear RTC Power up reset and pending alarm interrupts */
ef3b7d0d	441	ret = twl_rtc_write_u8(rd_reg, REG_RTC_STATUS_REG);
f96411ab DB	442	if (ret < 0)
	443	goto out1;
	444
a6b49ffd B	445	if (twl_class_is_6030()) {
	446	twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK,
	447	REG_INT_MSK_LINE_A);
	448	twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK,
	449	REG_INT_MSK_STS_A);
	450	}
	451
f96411ab	452	/* Check RTC module status, Enable if it is off */
ef3b7d0d	453	ret = twl_rtc_read_u8(&rd_reg, REG_RTC_CTRL_REG);
f96411ab	454	if (ret < 0)
7e72c686	455	goto out1;
f96411ab DB	456
f96411ab DB	457	if (!(rd_reg & BIT_RTC_CTRL_REG_STOP_RTC_M)) {
ef3b7d0d	458	dev_info(&pdev->dev, "Enabling TWL-RTC.\n");
f96411ab	459	rd_reg = BIT_RTC_CTRL_REG_STOP_RTC_M;
ef3b7d0d	460	ret = twl_rtc_write_u8(rd_reg, REG_RTC_CTRL_REG);
f96411ab	461	if (ret < 0)
7e72c686	462	goto out1;
f96411ab DB	463	}
	464
	465	/* init cached IRQ enable bits */
ef3b7d0d	466	ret = twl_rtc_read_u8(&rtc_irq_bits, REG_RTC_INTERRUPTS_REG);
f96411ab	467	if (ret < 0)
7e72c686 TP	468	goto out1;
	469
	470	rtc = rtc_device_register(pdev->name,
	471	&pdev->dev, &twl_rtc_ops, THIS_MODULE);
	472	if (IS_ERR(rtc)) {
	473	ret = PTR_ERR(rtc);
	474	dev_err(&pdev->dev, "can't register RTC device, err %ld\n",
	475	PTR_ERR(rtc));
	476	goto out1;
	477	}
	478
	479	ret = request_threaded_irq(irq, NULL, twl_rtc_interrupt,
	480	IRQF_TRIGGER_RISING,
	481	dev_name(&rtc->dev), rtc);
	482	if (ret < 0) {
	483	dev_err(&pdev->dev, "IRQ is not free.\n");
f96411ab	484	goto out2;
7e72c686	485	}
f96411ab	486
7e72c686 TP	487	platform_set_drvdata(pdev, rtc);
7e72c686 TP	488	return 0;
f96411ab	489
f96411ab	490	out2:
f96411ab	491	rtc_device_unregister(rtc);
7e72c686	492	out1:
f96411ab DB	493	return ret;
	494	}
	495
	496	/*
ef3b7d0d	497	* Disable all TWL RTC module interrupts.
f96411ab DB	498	* Sets status flag to free.
f96411ab DB	499	*/
ef3b7d0d	500	static int __devexit twl_rtc_remove(struct platform_device *pdev)
f96411ab DB	501	{
	502	/* leave rtc running, but disable irqs */
	503	struct rtc_device *rtc = platform_get_drvdata(pdev);
	504	int irq = platform_get_irq(pdev, 0);
	505
	506	mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
	507	mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
a6b49ffd B	508	if (twl_class_is_6030()) {
	509	twl6030_interrupt_mask(TWL6030_RTC_INT_MASK,
	510	REG_INT_MSK_LINE_A);
	511	twl6030_interrupt_mask(TWL6030_RTC_INT_MASK,
	512	REG_INT_MSK_STS_A);
	513	}
	514
f96411ab DB	515
	516	free_irq(irq, rtc);
	517
	518	rtc_device_unregister(rtc);
	519	platform_set_drvdata(pdev, NULL);
	520	return 0;
	521	}
	522
ef3b7d0d	523	static void twl_rtc_shutdown(struct platform_device *pdev)
f96411ab	524	{
cafa1d8b MH	525	/* mask timer interrupts, but leave alarm interrupts on to enable
	526	power-on when alarm is triggered */
	527	mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
f96411ab DB	528	}
	529
	530	#ifdef CONFIG_PM
	531
	532	static unsigned char irqstat;
	533
ef3b7d0d	534	static int twl_rtc_suspend(struct platform_device *pdev, pm_message_t state)
f96411ab DB	535	{
	536	irqstat = rtc_irq_bits;
	537
f993004d	538	mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
f96411ab DB	539	return 0;
	540	}
	541
ef3b7d0d	542	static int twl_rtc_resume(struct platform_device *pdev)
f96411ab DB	543	{
	544	set_rtc_irq_bit(irqstat);
	545	return 0;
	546	}
	547
	548	#else
ef3b7d0d B	549	#define twl_rtc_suspend NULL
ef3b7d0d B	550	#define twl_rtc_resume NULL
f96411ab DB	551	#endif
f96411ab DB	552
ef3b7d0d	553	MODULE_ALIAS("platform:twl_rtc");
f96411ab DB	554
f96411ab DB	555	static struct platform_driver twl4030rtc_driver = {
ef3b7d0d B	556	.probe = twl_rtc_probe,
	557	.remove = __devexit_p(twl_rtc_remove),
	558	.shutdown = twl_rtc_shutdown,
	559	.suspend = twl_rtc_suspend,
	560	.resume = twl_rtc_resume,
f96411ab DB	561	.driver = {
f96411ab DB	562	.owner = THIS_MODULE,
ef3b7d0d	563	.name = "twl_rtc",
f96411ab DB	564	},
	565	};
	566
ef3b7d0d	567	static int __init twl_rtc_init(void)
f96411ab	568	{
a6b49ffd B	569	if (twl_class_is_4030())
	570	rtc_reg_map = (u8 *) twl4030_rtc_reg_map;
	571	else
	572	rtc_reg_map = (u8 *) twl6030_rtc_reg_map;
	573
f96411ab DB	574	return platform_driver_register(&twl4030rtc_driver);
f96411ab DB	575	}
ef3b7d0d	576	module_init(twl_rtc_init);
f96411ab	577
ef3b7d0d	578	static void __exit twl_rtc_exit(void)
f96411ab DB	579	{
	580	platform_driver_unregister(&twl4030rtc_driver);
	581	}
ef3b7d0d	582	module_exit(twl_rtc_exit);
f96411ab DB	583
	584	MODULE_AUTHOR("Texas Instruments, MontaVista Software");
	585	MODULE_LICENSE("GPL");