[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / rtc / rtc-twl.c

/*
 * rtc-twl.c -- TWL Real Time Clock interface
 *
 * Copyright (C) 2007 MontaVista Software, Inc
 * Author: Alexandre Rusev <source@mvista.com>
 *
 * Based on original TI driver twl4030-rtc.c
 *   Copyright (C) 2006 Texas Instruments, Inc.
 *
 * Based on rtc-omap.c
 *   Copyright (C) 2003 MontaVista Software, Inc.
 *   Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com>
 *   Copyright (C) 2006 David Brownell
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/rtc.h>
#include <linux/bcd.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>

#include <linux/i2c/twl.h>


/*
 * RTC block register offsets (use TWL_MODULE_RTC)
 */
enum {
	REG_SECONDS_REG = 0,
	REG_MINUTES_REG,
	REG_HOURS_REG,
	REG_DAYS_REG,
	REG_MONTHS_REG,
	REG_YEARS_REG,
	REG_WEEKS_REG,

	REG_ALARM_SECONDS_REG,
	REG_ALARM_MINUTES_REG,
	REG_ALARM_HOURS_REG,
	REG_ALARM_DAYS_REG,
	REG_ALARM_MONTHS_REG,
	REG_ALARM_YEARS_REG,

	REG_RTC_CTRL_REG,
	REG_RTC_STATUS_REG,
	REG_RTC_INTERRUPTS_REG,

	REG_RTC_COMP_LSB_REG,
	REG_RTC_COMP_MSB_REG,
};
static const u8 twl4030_rtc_reg_map[] = {
	[REG_SECONDS_REG] = 0x00,
	[REG_MINUTES_REG] = 0x01,
	[REG_HOURS_REG] = 0x02,
	[REG_DAYS_REG] = 0x03,
	[REG_MONTHS_REG] = 0x04,
	[REG_YEARS_REG] = 0x05,
	[REG_WEEKS_REG] = 0x06,

	[REG_ALARM_SECONDS_REG] = 0x07,
	[REG_ALARM_MINUTES_REG] = 0x08,
	[REG_ALARM_HOURS_REG] = 0x09,
	[REG_ALARM_DAYS_REG] = 0x0A,
	[REG_ALARM_MONTHS_REG] = 0x0B,
	[REG_ALARM_YEARS_REG] = 0x0C,

	[REG_RTC_CTRL_REG] = 0x0D,
	[REG_RTC_STATUS_REG] = 0x0E,
	[REG_RTC_INTERRUPTS_REG] = 0x0F,

	[REG_RTC_COMP_LSB_REG] = 0x10,
	[REG_RTC_COMP_MSB_REG] = 0x11,
};
static const u8 twl6030_rtc_reg_map[] = {
	[REG_SECONDS_REG] = 0x00,
	[REG_MINUTES_REG] = 0x01,
	[REG_HOURS_REG] = 0x02,
	[REG_DAYS_REG] = 0x03,
	[REG_MONTHS_REG] = 0x04,
	[REG_YEARS_REG] = 0x05,
	[REG_WEEKS_REG] = 0x06,

	[REG_ALARM_SECONDS_REG] = 0x08,
	[REG_ALARM_MINUTES_REG] = 0x09,
	[REG_ALARM_HOURS_REG] = 0x0A,
	[REG_ALARM_DAYS_REG] = 0x0B,
	[REG_ALARM_MONTHS_REG] = 0x0C,
	[REG_ALARM_YEARS_REG] = 0x0D,

	[REG_RTC_CTRL_REG] = 0x10,
	[REG_RTC_STATUS_REG] = 0x11,
	[REG_RTC_INTERRUPTS_REG] = 0x12,

	[REG_RTC_COMP_LSB_REG] = 0x13,
	[REG_RTC_COMP_MSB_REG] = 0x14,
};

/* RTC_CTRL_REG bitfields */
#define BIT_RTC_CTRL_REG_STOP_RTC_M              0x01
#define BIT_RTC_CTRL_REG_ROUND_30S_M             0x02
#define BIT_RTC_CTRL_REG_AUTO_COMP_M             0x04
#define BIT_RTC_CTRL_REG_MODE_12_24_M            0x08
#define BIT_RTC_CTRL_REG_TEST_MODE_M             0x10
#define BIT_RTC_CTRL_REG_SET_32_COUNTER_M        0x20
#define BIT_RTC_CTRL_REG_GET_TIME_M              0x40
#define BIT_RTC_CTRL_REG_RTC_V_OPT               0x80

/* RTC_STATUS_REG bitfields */
#define BIT_RTC_STATUS_REG_RUN_M                 0x02
#define BIT_RTC_STATUS_REG_1S_EVENT_M            0x04
#define BIT_RTC_STATUS_REG_1M_EVENT_M            0x08
#define BIT_RTC_STATUS_REG_1H_EVENT_M            0x10
#define BIT_RTC_STATUS_REG_1D_EVENT_M            0x20
#define BIT_RTC_STATUS_REG_ALARM_M               0x40
#define BIT_RTC_STATUS_REG_POWER_UP_M            0x80

/* RTC_INTERRUPTS_REG bitfields */
#define BIT_RTC_INTERRUPTS_REG_EVERY_M           0x03
#define BIT_RTC_INTERRUPTS_REG_IT_TIMER_M        0x04
#define BIT_RTC_INTERRUPTS_REG_IT_ALARM_M        0x08


/* REG_SECONDS_REG through REG_YEARS_REG is how many registers? */
#define ALL_TIME_REGS		6

/*----------------------------------------------------------------------*/
static u8  *rtc_reg_map;

/*
 * Supports 1 byte read from TWL RTC register.
 */
static int twl_rtc_read_u8(u8 *data, u8 reg)
{
	int ret;

	ret = twl_i2c_read_u8(TWL_MODULE_RTC, data, (rtc_reg_map[reg]));
	if (ret < 0)
		pr_err("twl_rtc: Could not read TWL"
		       "register %X - error %d\n", reg, ret);
	return ret;
}

/*
 * Supports 1 byte write to TWL RTC registers.
 */
static int twl_rtc_write_u8(u8 data, u8 reg)
{
	int ret;

	ret = twl_i2c_write_u8(TWL_MODULE_RTC, data, (rtc_reg_map[reg]));
	if (ret < 0)
		pr_err("twl_rtc: Could not write TWL"
		       "register %X - error %d\n", reg, ret);
	return ret;
}

/*
 * Cache the value for timer/alarm interrupts register; this is
 * only changed by callers holding rtc ops lock (or resume).
 */
static unsigned char rtc_irq_bits;

/*
 * Enable 1/second update and/or alarm interrupts.
 */
static int set_rtc_irq_bit(unsigned char bit)
{
	unsigned char val;
	int ret;

	/* if the bit is set, return from here */
	if (rtc_irq_bits & bit)
		return 0;

	val = rtc_irq_bits | bit;
	val &= ~BIT_RTC_INTERRUPTS_REG_EVERY_M;
	ret = twl_rtc_write_u8(val, REG_RTC_INTERRUPTS_REG);
	if (ret == 0)
		rtc_irq_bits = val;

	return ret;
}

/*
 * Disable update and/or alarm interrupts.
 */
static int mask_rtc_irq_bit(unsigned char bit)
{
	unsigned char val;
	int ret;

	/* if the bit is clear, return from here */
	if (!(rtc_irq_bits & bit))
		return 0;

	val = rtc_irq_bits & ~bit;
	ret = twl_rtc_write_u8(val, REG_RTC_INTERRUPTS_REG);
	if (ret == 0)
		rtc_irq_bits = val;

	return ret;
}

static int twl_rtc_alarm_irq_enable(struct device *dev, unsigned enabled)
{
	int ret;

	if (enabled)
		ret = set_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
	else
		ret = mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);

	return ret;
}

/*
 * Gets current TWL RTC time and date parameters.
 *
 * The RTC's time/alarm representation is not what gmtime(3) requires
 * Linux to use:
 *
 *  - Months are 1..12 vs Linux 0-11
 *  - Years are 0..99 vs Linux 1900..N (we assume 21st century)
 */
static int twl_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	unsigned char rtc_data[ALL_TIME_REGS + 1];
	int ret;
	u8 save_control;
	u8 rtc_control;

	ret = twl_rtc_read_u8(&save_control, REG_RTC_CTRL_REG);
	if (ret < 0) {
		dev_err(dev, "%s: reading CTRL_REG, error %d\n", __func__, ret);
		return ret;
	}
	/* for twl6030/32 make sure BIT_RTC_CTRL_REG_GET_TIME_M is clear */
	if (twl_class_is_6030()) {
		if (save_control & BIT_RTC_CTRL_REG_GET_TIME_M) {
			save_control &= ~BIT_RTC_CTRL_REG_GET_TIME_M;
			ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
			if (ret < 0) {
				dev_err(dev, "%s clr GET_TIME, error %d\n",
					__func__, ret);
				return ret;
			}
		}
	}

	/* Copy RTC counting registers to static registers or latches */
	rtc_control = save_control | BIT_RTC_CTRL_REG_GET_TIME_M;

	/* for twl6030/32 enable read access to static shadowed registers */
	if (twl_class_is_6030())
		rtc_control |= BIT_RTC_CTRL_REG_RTC_V_OPT;

	ret = twl_rtc_write_u8(rtc_control, REG_RTC_CTRL_REG);
	if (ret < 0) {
		dev_err(dev, "%s: writing CTRL_REG, error %d\n", __func__, ret);
		return ret;
	}

	ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data,
			(rtc_reg_map[REG_SECONDS_REG]), ALL_TIME_REGS);

	if (ret < 0) {
		dev_err(dev, "%s: reading data, error %d\n", __func__, ret);
		return ret;
	}

	/* for twl6030 restore original state of rtc control register */
	if (twl_class_is_6030()) {
		ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
		if (ret < 0) {
			dev_err(dev, "%s: restore CTRL_REG, error %d\n",
				__func__, ret);
			return ret;
		}
	}

	tm->tm_sec = bcd2bin(rtc_data[0]);
	tm->tm_min = bcd2bin(rtc_data[1]);
	tm->tm_hour = bcd2bin(rtc_data[2]);
	tm->tm_mday = bcd2bin(rtc_data[3]);
	tm->tm_mon = bcd2bin(rtc_data[4]) - 1;
	tm->tm_year = bcd2bin(rtc_data[5]) + 100;

	return ret;
}

static int twl_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	unsigned char save_control;
	unsigned char rtc_data[ALL_TIME_REGS + 1];
	int ret;

	rtc_data[1] = bin2bcd(tm->tm_sec);
	rtc_data[2] = bin2bcd(tm->tm_min);
	rtc_data[3] = bin2bcd(tm->tm_hour);
	rtc_data[4] = bin2bcd(tm->tm_mday);
	rtc_data[5] = bin2bcd(tm->tm_mon + 1);
	rtc_data[6] = bin2bcd(tm->tm_year - 100);

	/* Stop RTC while updating the TC registers */
	ret = twl_rtc_read_u8(&save_control, REG_RTC_CTRL_REG);
	if (ret < 0)
		goto out;

	save_control &= ~BIT_RTC_CTRL_REG_STOP_RTC_M;
	ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
	if (ret < 0)
		goto out;

	/* update all the time registers in one shot */
	ret = twl_i2c_write(TWL_MODULE_RTC, rtc_data,
		(rtc_reg_map[REG_SECONDS_REG]), ALL_TIME_REGS);
	if (ret < 0) {
		dev_err(dev, "rtc_set_time error %d\n", ret);
		goto out;
	}

	/* Start back RTC */
	save_control |= BIT_RTC_CTRL_REG_STOP_RTC_M;
	ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);

out:
	return ret;
}

/*
 * Gets current TWL RTC alarm time.
 */
static int twl_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
	unsigned char rtc_data[ALL_TIME_REGS + 1];
	int ret;

	ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data,
			(rtc_reg_map[REG_ALARM_SECONDS_REG]), ALL_TIME_REGS);
	if (ret < 0) {
		dev_err(dev, "rtc_read_alarm error %d\n", ret);
		return ret;
	}

	/* some of these fields may be wildcard/"match all" */
	alm->time.tm_sec = bcd2bin(rtc_data[0]);
	alm->time.tm_min = bcd2bin(rtc_data[1]);
	alm->time.tm_hour = bcd2bin(rtc_data[2]);
	alm->time.tm_mday = bcd2bin(rtc_data[3]);
	alm->time.tm_mon = bcd2bin(rtc_data[4]) - 1;
	alm->time.tm_year = bcd2bin(rtc_data[5]) + 100;

	/* report cached alarm enable state */
	if (rtc_irq_bits & BIT_RTC_INTERRUPTS_REG_IT_ALARM_M)
		alm->enabled = 1;

	return ret;
}

static int twl_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
	unsigned char alarm_data[ALL_TIME_REGS + 1];
	int ret;

	ret = twl_rtc_alarm_irq_enable(dev, 0);
	if (ret)
		goto out;

	alarm_data[1] = bin2bcd(alm->time.tm_sec);
	alarm_data[2] = bin2bcd(alm->time.tm_min);
	alarm_data[3] = bin2bcd(alm->time.tm_hour);
	alarm_data[4] = bin2bcd(alm->time.tm_mday);
	alarm_data[5] = bin2bcd(alm->time.tm_mon + 1);
	alarm_data[6] = bin2bcd(alm->time.tm_year - 100);

	/* update all the alarm registers in one shot */
	ret = twl_i2c_write(TWL_MODULE_RTC, alarm_data,
		(rtc_reg_map[REG_ALARM_SECONDS_REG]), ALL_TIME_REGS);
	if (ret) {
		dev_err(dev, "rtc_set_alarm error %d\n", ret);
		goto out;
	}

	if (alm->enabled)
		ret = twl_rtc_alarm_irq_enable(dev, 1);
out:
	return ret;
}

static irqreturn_t twl_rtc_interrupt(int irq, void *rtc)
{
	unsigned long events;
	int ret = IRQ_NONE;
	int res;
	u8 rd_reg;

	res = twl_rtc_read_u8(&rd_reg, REG_RTC_STATUS_REG);
	if (res)
		goto out;
	/*
	 * Figure out source of interrupt: ALARM or TIMER in RTC_STATUS_REG.
	 * only one (ALARM or RTC) interrupt source may be enabled
	 * at time, we also could check our results
	 * by reading RTS_INTERRUPTS_REGISTER[IT_TIMER,IT_ALARM]
	 */
	if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M)
		events = RTC_IRQF | RTC_AF;
	else
		events = RTC_IRQF | RTC_PF;

	res = twl_rtc_write_u8(BIT_RTC_STATUS_REG_ALARM_M,
				   REG_RTC_STATUS_REG);
	if (res)
		goto out;

	if (twl_class_is_4030()) {
		/* Clear on Read enabled. RTC_IT bit of TWL4030_INT_PWR_ISR1
		 * needs 2 reads to clear the interrupt. One read is done in
		 * do_twl_pwrirq(). Doing the second read, to clear
		 * the bit.
		 *
		 * FIXME the reason PWR_ISR1 needs an extra read is that
		 * RTC_IF retriggered until we cleared REG_ALARM_M above.
		 * But re-reading like this is a bad hack; by doing so we
		 * risk wrongly clearing status for some other IRQ (losing
		 * the interrupt).  Be smarter about handling RTC_UF ...
		 */
		res = twl_i2c_read_u8(TWL4030_MODULE_INT,
			&rd_reg, TWL4030_INT_PWR_ISR1);
		if (res)
			goto out;
	}

	/* Notify RTC core on event */
	rtc_update_irq(rtc, 1, events);

	ret = IRQ_HANDLED;
out:
	return ret;
}

static struct rtc_class_ops twl_rtc_ops = {
	.read_time	= twl_rtc_read_time,
	.set_time	= twl_rtc_set_time,
	.read_alarm	= twl_rtc_read_alarm,
	.set_alarm	= twl_rtc_set_alarm,
	.alarm_irq_enable = twl_rtc_alarm_irq_enable,
};

/*----------------------------------------------------------------------*/

static int __devinit twl_rtc_probe(struct platform_device *pdev)
{
	struct rtc_device *rtc;
	int ret = -EINVAL;
	int irq = platform_get_irq(pdev, 0);
	u8 rd_reg;

	if (irq <= 0)
		goto out1;

	ret = twl_rtc_read_u8(&rd_reg, REG_RTC_STATUS_REG);
	if (ret < 0)
		goto out1;

	if (rd_reg & BIT_RTC_STATUS_REG_POWER_UP_M)
		dev_warn(&pdev->dev, "Power up reset detected.\n");

	if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M)
		dev_warn(&pdev->dev, "Pending Alarm interrupt detected.\n");

	/* Clear RTC Power up reset and pending alarm interrupts */
	ret = twl_rtc_write_u8(rd_reg, REG_RTC_STATUS_REG);
	if (ret < 0)
		goto out1;

	if (twl_class_is_6030()) {
		twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK,
			REG_INT_MSK_LINE_A);
		twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK,
			REG_INT_MSK_STS_A);
	}

	dev_info(&pdev->dev, "Enabling TWL-RTC\n");
	ret = twl_rtc_write_u8(BIT_RTC_CTRL_REG_STOP_RTC_M, REG_RTC_CTRL_REG);
	if (ret < 0)
		goto out1;

	/* ensure interrupts are disabled, bootloaders can be strange */
	ret = twl_rtc_write_u8(0, REG_RTC_INTERRUPTS_REG);
	if (ret < 0)
		dev_warn(&pdev->dev, "unable to disable interrupt\n");

	/* init cached IRQ enable bits */
	ret = twl_rtc_read_u8(&rtc_irq_bits, REG_RTC_INTERRUPTS_REG);
	if (ret < 0)
		goto out1;

	rtc = rtc_device_register(pdev->name,
				  &pdev->dev, &twl_rtc_ops, THIS_MODULE);
	if (IS_ERR(rtc)) {
		ret = PTR_ERR(rtc);
		dev_err(&pdev->dev, "can't register RTC device, err %ld\n",
			PTR_ERR(rtc));
		goto out1;
	}

	ret = request_threaded_irq(irq, NULL, twl_rtc_interrupt,
				   IRQF_TRIGGER_RISING | IRQF_ONESHOT,
				   dev_name(&rtc->dev), rtc);
	if (ret < 0) {
		dev_err(&pdev->dev, "IRQ is not free.\n");
		goto out2;
	}

	platform_set_drvdata(pdev, rtc);
	return 0;

out2:
	rtc_device_unregister(rtc);
out1:
	return ret;
}

/*
 * Disable all TWL RTC module interrupts.
 * Sets status flag to free.
 */
static int __devexit twl_rtc_remove(struct platform_device *pdev)
{
	/* leave rtc running, but disable irqs */
	struct rtc_device *rtc = platform_get_drvdata(pdev);
	int irq = platform_get_irq(pdev, 0);

	mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
	mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
	if (twl_class_is_6030()) {
		twl6030_interrupt_mask(TWL6030_RTC_INT_MASK,
			REG_INT_MSK_LINE_A);
		twl6030_interrupt_mask(TWL6030_RTC_INT_MASK,
			REG_INT_MSK_STS_A);
	}


	free_irq(irq, rtc);

	rtc_device_unregister(rtc);
	platform_set_drvdata(pdev, NULL);
	return 0;
}

static void twl_rtc_shutdown(struct platform_device *pdev)
{
	/* mask timer interrupts, but leave alarm interrupts on to enable
	   power-on when alarm is triggered */
	mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
}

#ifdef CONFIG_PM

static unsigned char irqstat;

static int twl_rtc_suspend(struct platform_device *pdev, pm_message_t state)
{
	irqstat = rtc_irq_bits;

	mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
	return 0;
}

static int twl_rtc_resume(struct platform_device *pdev)
{
	set_rtc_irq_bit(irqstat);
	return 0;
}

#else
#define twl_rtc_suspend NULL
#define twl_rtc_resume  NULL
#endif

static const struct of_device_id twl_rtc_of_match[] = {
	{.compatible = "ti,twl4030-rtc", },
	{ },
};
MODULE_DEVICE_TABLE(of, twl_rtc_of_match);
MODULE_ALIAS("platform:twl_rtc");

static struct platform_driver twl4030rtc_driver = {
	.probe		= twl_rtc_probe,
	.remove		= __devexit_p(twl_rtc_remove),
	.shutdown	= twl_rtc_shutdown,
	.suspend	= twl_rtc_suspend,
	.resume		= twl_rtc_resume,
	.driver		= {
		.owner		= THIS_MODULE,
		.name		= "twl_rtc",
		.of_match_table = twl_rtc_of_match,
	},
};

static int __init twl_rtc_init(void)
{
	if (twl_class_is_4030())
		rtc_reg_map = (u8 *) twl4030_rtc_reg_map;
	else
		rtc_reg_map = (u8 *) twl6030_rtc_reg_map;

	return platform_driver_register(&twl4030rtc_driver);
}
module_init(twl_rtc_init);

static void __exit twl_rtc_exit(void)
{
	platform_driver_unregister(&twl4030rtc_driver);
}
module_exit(twl_rtc_exit);

MODULE_AUTHOR("Texas Instruments, MontaVista Software");
MODULE_LICENSE("GPL");
Commit	Line	Data
f96411ab	1	/*
ef3b7d0d	2	* rtc-twl.c -- TWL Real Time Clock interface
f96411ab DB	3	*
	4	* Copyright (C) 2007 MontaVista Software, Inc
	5	* Author: Alexandre Rusev <source@mvista.com>
	6	*
	7	* Based on original TI driver twl4030-rtc.c
	8	* Copyright (C) 2006 Texas Instruments, Inc.
	9	*
	10	* Based on rtc-omap.c
	11	* Copyright (C) 2003 MontaVista Software, Inc.
	12	* Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com>
	13	* Copyright (C) 2006 David Brownell
	14	*
	15	* This program is free software; you can redistribute it and/or
	16	* modify it under the terms of the GNU General Public License
	17	* as published by the Free Software Foundation; either version
	18	* 2 of the License, or (at your option) any later version.
	19	*/
	20
	21	#include <linux/kernel.h>
2fac6674	22	#include <linux/errno.h>
f96411ab DB	23	#include <linux/init.h>
	24	#include <linux/module.h>
	25	#include <linux/types.h>
	26	#include <linux/rtc.h>
	27	#include <linux/bcd.h>
	28	#include <linux/platform_device.h>
	29	#include <linux/interrupt.h>
	30
b07682b6	31	#include <linux/i2c/twl.h>
f96411ab DB	32
	33
	34	/*
	35	* RTC block register offsets (use TWL_MODULE_RTC)
	36	*/
a6b49ffd B	37	enum {
	38	REG_SECONDS_REG = 0,
	39	REG_MINUTES_REG,
	40	REG_HOURS_REG,
	41	REG_DAYS_REG,
	42	REG_MONTHS_REG,
	43	REG_YEARS_REG,
	44	REG_WEEKS_REG,
	45
	46	REG_ALARM_SECONDS_REG,
	47	REG_ALARM_MINUTES_REG,
	48	REG_ALARM_HOURS_REG,
	49	REG_ALARM_DAYS_REG,
	50	REG_ALARM_MONTHS_REG,
	51	REG_ALARM_YEARS_REG,
	52
	53	REG_RTC_CTRL_REG,
	54	REG_RTC_STATUS_REG,
	55	REG_RTC_INTERRUPTS_REG,
	56
	57	REG_RTC_COMP_LSB_REG,
	58	REG_RTC_COMP_MSB_REG,
	59	};
2e84067b	60	static const u8 twl4030_rtc_reg_map[] = {
a6b49ffd B	61	[REG_SECONDS_REG] = 0x00,
	62	[REG_MINUTES_REG] = 0x01,
	63	[REG_HOURS_REG] = 0x02,
	64	[REG_DAYS_REG] = 0x03,
	65	[REG_MONTHS_REG] = 0x04,
	66	[REG_YEARS_REG] = 0x05,
	67	[REG_WEEKS_REG] = 0x06,
	68
	69	[REG_ALARM_SECONDS_REG] = 0x07,
	70	[REG_ALARM_MINUTES_REG] = 0x08,
	71	[REG_ALARM_HOURS_REG] = 0x09,
	72	[REG_ALARM_DAYS_REG] = 0x0A,
	73	[REG_ALARM_MONTHS_REG] = 0x0B,
	74	[REG_ALARM_YEARS_REG] = 0x0C,
	75
	76	[REG_RTC_CTRL_REG] = 0x0D,
	77	[REG_RTC_STATUS_REG] = 0x0E,
	78	[REG_RTC_INTERRUPTS_REG] = 0x0F,
	79
	80	[REG_RTC_COMP_LSB_REG] = 0x10,
	81	[REG_RTC_COMP_MSB_REG] = 0x11,
	82	};
2e84067b	83	static const u8 twl6030_rtc_reg_map[] = {
a6b49ffd B	84	[REG_SECONDS_REG] = 0x00,
	85	[REG_MINUTES_REG] = 0x01,
	86	[REG_HOURS_REG] = 0x02,
	87	[REG_DAYS_REG] = 0x03,
	88	[REG_MONTHS_REG] = 0x04,
	89	[REG_YEARS_REG] = 0x05,
	90	[REG_WEEKS_REG] = 0x06,
	91
	92	[REG_ALARM_SECONDS_REG] = 0x08,
	93	[REG_ALARM_MINUTES_REG] = 0x09,
	94	[REG_ALARM_HOURS_REG] = 0x0A,
	95	[REG_ALARM_DAYS_REG] = 0x0B,
	96	[REG_ALARM_MONTHS_REG] = 0x0C,
	97	[REG_ALARM_YEARS_REG] = 0x0D,
	98
	99	[REG_RTC_CTRL_REG] = 0x10,
	100	[REG_RTC_STATUS_REG] = 0x11,
	101	[REG_RTC_INTERRUPTS_REG] = 0x12,
	102
	103	[REG_RTC_COMP_LSB_REG] = 0x13,
	104	[REG_RTC_COMP_MSB_REG] = 0x14,
	105	};
f96411ab DB	106
	107	/* RTC_CTRL_REG bitfields */
	108	#define BIT_RTC_CTRL_REG_STOP_RTC_M 0x01
	109	#define BIT_RTC_CTRL_REG_ROUND_30S_M 0x02
	110	#define BIT_RTC_CTRL_REG_AUTO_COMP_M 0x04
	111	#define BIT_RTC_CTRL_REG_MODE_12_24_M 0x08
	112	#define BIT_RTC_CTRL_REG_TEST_MODE_M 0x10
	113	#define BIT_RTC_CTRL_REG_SET_32_COUNTER_M 0x20
	114	#define BIT_RTC_CTRL_REG_GET_TIME_M 0x40
f3ec434c	115	#define BIT_RTC_CTRL_REG_RTC_V_OPT 0x80
f96411ab DB	116
	117	/* RTC_STATUS_REG bitfields */
	118	#define BIT_RTC_STATUS_REG_RUN_M 0x02
	119	#define BIT_RTC_STATUS_REG_1S_EVENT_M 0x04
	120	#define BIT_RTC_STATUS_REG_1M_EVENT_M 0x08
	121	#define BIT_RTC_STATUS_REG_1H_EVENT_M 0x10
	122	#define BIT_RTC_STATUS_REG_1D_EVENT_M 0x20
	123	#define BIT_RTC_STATUS_REG_ALARM_M 0x40
	124	#define BIT_RTC_STATUS_REG_POWER_UP_M 0x80
	125
	126	/* RTC_INTERRUPTS_REG bitfields */
	127	#define BIT_RTC_INTERRUPTS_REG_EVERY_M 0x03
	128	#define BIT_RTC_INTERRUPTS_REG_IT_TIMER_M 0x04
	129	#define BIT_RTC_INTERRUPTS_REG_IT_ALARM_M 0x08
	130
	131
	132	/* REG_SECONDS_REG through REG_YEARS_REG is how many registers? */
	133	#define ALL_TIME_REGS 6
	134
	135	/----------------------------------------------------------------------/
a6b49ffd	136	static u8 *rtc_reg_map;
f96411ab DB	137
f96411ab DB	138	/*
ef3b7d0d	139	* Supports 1 byte read from TWL RTC register.
f96411ab	140	*/
ef3b7d0d	141	static int twl_rtc_read_u8(u8 *data, u8 reg)
f96411ab DB	142	{
	143	int ret;
	144
a6b49ffd	145	ret = twl_i2c_read_u8(TWL_MODULE_RTC, data, (rtc_reg_map[reg]));
f96411ab	146	if (ret < 0)
ef3b7d0d	147	pr_err("twl_rtc: Could not read TWL"
f96411ab DB	148	"register %X - error %d\n", reg, ret);
	149	return ret;
	150	}
	151
	152	/*
ef3b7d0d	153	* Supports 1 byte write to TWL RTC registers.
f96411ab	154	*/
ef3b7d0d	155	static int twl_rtc_write_u8(u8 data, u8 reg)
f96411ab DB	156	{
	157	int ret;
	158
a6b49ffd	159	ret = twl_i2c_write_u8(TWL_MODULE_RTC, data, (rtc_reg_map[reg]));
f96411ab	160	if (ret < 0)
ef3b7d0d	161	pr_err("twl_rtc: Could not write TWL"
f96411ab DB	162	"register %X - error %d\n", reg, ret);
	163	return ret;
	164	}
	165
	166	/*
	167	* Cache the value for timer/alarm interrupts register; this is
	168	* only changed by callers holding rtc ops lock (or resume).
	169	*/
	170	static unsigned char rtc_irq_bits;
	171
	172	/*
a748384b	173	* Enable 1/second update and/or alarm interrupts.
f96411ab DB	174	*/
	175	static int set_rtc_irq_bit(unsigned char bit)
	176	{
	177	unsigned char val;
	178	int ret;
	179
ce9f6506 VB	180	/* if the bit is set, return from here */
	181	if (rtc_irq_bits & bit)
	182	return 0;
	183
f96411ab	184	val = rtc_irq_bits \| bit;
a748384b	185	val &= ~BIT_RTC_INTERRUPTS_REG_EVERY_M;
ef3b7d0d	186	ret = twl_rtc_write_u8(val, REG_RTC_INTERRUPTS_REG);
f96411ab DB	187	if (ret == 0)
	188	rtc_irq_bits = val;
	189
	190	return ret;
	191	}
	192
	193	/*
a748384b	194	* Disable update and/or alarm interrupts.
f96411ab DB	195	*/
	196	static int mask_rtc_irq_bit(unsigned char bit)
	197	{
	198	unsigned char val;
	199	int ret;
	200
ce9f6506 VB	201	/* if the bit is clear, return from here */
	202	if (!(rtc_irq_bits & bit))
	203	return 0;
	204
f96411ab	205	val = rtc_irq_bits & ~bit;
ef3b7d0d	206	ret = twl_rtc_write_u8(val, REG_RTC_INTERRUPTS_REG);
f96411ab DB	207	if (ret == 0)
	208	rtc_irq_bits = val;
	209
	210	return ret;
	211	}
	212
ef3b7d0d	213	static int twl_rtc_alarm_irq_enable(struct device *dev, unsigned enabled)
f96411ab DB	214	{
	215	int ret;
	216
	217	if (enabled)
	218	ret = set_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
	219	else
	220	ret = mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
	221
	222	return ret;
	223	}
	224
f96411ab	225	/*
ef3b7d0d	226	* Gets current TWL RTC time and date parameters.
f96411ab DB	227	*
	228	* The RTC's time/alarm representation is not what gmtime(3) requires
	229	* Linux to use:
	230	*
	231	* - Months are 1..12 vs Linux 0-11
	232	* - Years are 0..99 vs Linux 1900..N (we assume 21st century)
	233	*/
ef3b7d0d	234	static int twl_rtc_read_time(struct device dev, struct rtc_time tm)
f96411ab DB	235	{
	236	unsigned char rtc_data[ALL_TIME_REGS + 1];
	237	int ret;
	238	u8 save_control;
f3ec434c	239	u8 rtc_control;
f96411ab	240
ef3b7d0d	241	ret = twl_rtc_read_u8(&save_control, REG_RTC_CTRL_REG);
f3ec434c KS	242	if (ret < 0) {
f3ec434c KS	243	dev_err(dev, "%s: reading CTRL_REG, error %d\n", __func__, ret);
f96411ab	244	return ret;
f3ec434c KS	245	}
	246	/* for twl6030/32 make sure BIT_RTC_CTRL_REG_GET_TIME_M is clear */
	247	if (twl_class_is_6030()) {
	248	if (save_control & BIT_RTC_CTRL_REG_GET_TIME_M) {
	249	save_control &= ~BIT_RTC_CTRL_REG_GET_TIME_M;
	250	ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
	251	if (ret < 0) {
	252	dev_err(dev, "%s clr GET_TIME, error %d\n",
	253	__func__, ret);
	254	return ret;
	255	}
	256	}
	257	}
f96411ab	258
f3ec434c KS	259	/* Copy RTC counting registers to static registers or latches */
f3ec434c KS	260	rtc_control = save_control \| BIT_RTC_CTRL_REG_GET_TIME_M;
f96411ab	261
f3ec434c KS	262	/* for twl6030/32 enable read access to static shadowed registers */
	263	if (twl_class_is_6030())
	264	rtc_control \|= BIT_RTC_CTRL_REG_RTC_V_OPT;
	265
	266	ret = twl_rtc_write_u8(rtc_control, REG_RTC_CTRL_REG);
	267	if (ret < 0) {
	268	dev_err(dev, "%s: writing CTRL_REG, error %d\n", __func__, ret);
f96411ab	269	return ret;
f3ec434c	270	}
f96411ab	271
ef3b7d0d	272	ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data,
a6b49ffd	273	(rtc_reg_map[REG_SECONDS_REG]), ALL_TIME_REGS);
f96411ab DB	274
f96411ab DB	275	if (ret < 0) {
f3ec434c	276	dev_err(dev, "%s: reading data, error %d\n", __func__, ret);
f96411ab DB	277	return ret;
	278	}
	279
f3ec434c KS	280	/* for twl6030 restore original state of rtc control register */
	281	if (twl_class_is_6030()) {
	282	ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
	283	if (ret < 0) {
	284	dev_err(dev, "%s: restore CTRL_REG, error %d\n",
	285	__func__, ret);
	286	return ret;
	287	}
	288	}
	289
f96411ab DB	290	tm->tm_sec = bcd2bin(rtc_data[0]);
	291	tm->tm_min = bcd2bin(rtc_data[1]);
	292	tm->tm_hour = bcd2bin(rtc_data[2]);
	293	tm->tm_mday = bcd2bin(rtc_data[3]);
	294	tm->tm_mon = bcd2bin(rtc_data[4]) - 1;
	295	tm->tm_year = bcd2bin(rtc_data[5]) + 100;
	296
	297	return ret;
	298	}
	299
ef3b7d0d	300	static int twl_rtc_set_time(struct device dev, struct rtc_time tm)
f96411ab DB	301	{
	302	unsigned char save_control;
	303	unsigned char rtc_data[ALL_TIME_REGS + 1];
	304	int ret;
	305
	306	rtc_data[1] = bin2bcd(tm->tm_sec);
	307	rtc_data[2] = bin2bcd(tm->tm_min);
	308	rtc_data[3] = bin2bcd(tm->tm_hour);
	309	rtc_data[4] = bin2bcd(tm->tm_mday);
	310	rtc_data[5] = bin2bcd(tm->tm_mon + 1);
	311	rtc_data[6] = bin2bcd(tm->tm_year - 100);
	312
	313	/* Stop RTC while updating the TC registers */
ef3b7d0d	314	ret = twl_rtc_read_u8(&save_control, REG_RTC_CTRL_REG);
f96411ab DB	315	if (ret < 0)
	316	goto out;
	317
	318	save_control &= ~BIT_RTC_CTRL_REG_STOP_RTC_M;
8f6b0dd3	319	ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
f96411ab DB	320	if (ret < 0)
	321	goto out;
	322
	323	/* update all the time registers in one shot */
ef3b7d0d	324	ret = twl_i2c_write(TWL_MODULE_RTC, rtc_data,
a6b49ffd	325	(rtc_reg_map[REG_SECONDS_REG]), ALL_TIME_REGS);
f96411ab DB	326	if (ret < 0) {
	327	dev_err(dev, "rtc_set_time error %d\n", ret);
	328	goto out;
	329	}
	330
	331	/* Start back RTC */
	332	save_control \|= BIT_RTC_CTRL_REG_STOP_RTC_M;
ef3b7d0d	333	ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
f96411ab DB	334
	335	out:
	336	return ret;
	337	}
	338
	339	/*
ef3b7d0d	340	* Gets current TWL RTC alarm time.
f96411ab	341	*/
ef3b7d0d	342	static int twl_rtc_read_alarm(struct device dev, struct rtc_wkalrm alm)
f96411ab DB	343	{
	344	unsigned char rtc_data[ALL_TIME_REGS + 1];
	345	int ret;
	346
ef3b7d0d	347	ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data,
a6b49ffd	348	(rtc_reg_map[REG_ALARM_SECONDS_REG]), ALL_TIME_REGS);
f96411ab DB	349	if (ret < 0) {
	350	dev_err(dev, "rtc_read_alarm error %d\n", ret);
	351	return ret;
	352	}
	353
	354	/* some of these fields may be wildcard/"match all" */
	355	alm->time.tm_sec = bcd2bin(rtc_data[0]);
	356	alm->time.tm_min = bcd2bin(rtc_data[1]);
	357	alm->time.tm_hour = bcd2bin(rtc_data[2]);
	358	alm->time.tm_mday = bcd2bin(rtc_data[3]);
	359	alm->time.tm_mon = bcd2bin(rtc_data[4]) - 1;
	360	alm->time.tm_year = bcd2bin(rtc_data[5]) + 100;
	361
	362	/* report cached alarm enable state */
	363	if (rtc_irq_bits & BIT_RTC_INTERRUPTS_REG_IT_ALARM_M)
	364	alm->enabled = 1;
	365
	366	return ret;
	367	}
	368
ef3b7d0d	369	static int twl_rtc_set_alarm(struct device dev, struct rtc_wkalrm alm)
f96411ab DB	370	{
	371	unsigned char alarm_data[ALL_TIME_REGS + 1];
	372	int ret;
	373
ef3b7d0d	374	ret = twl_rtc_alarm_irq_enable(dev, 0);
f96411ab DB	375	if (ret)
	376	goto out;
	377
	378	alarm_data[1] = bin2bcd(alm->time.tm_sec);
	379	alarm_data[2] = bin2bcd(alm->time.tm_min);
	380	alarm_data[3] = bin2bcd(alm->time.tm_hour);
	381	alarm_data[4] = bin2bcd(alm->time.tm_mday);
	382	alarm_data[5] = bin2bcd(alm->time.tm_mon + 1);
	383	alarm_data[6] = bin2bcd(alm->time.tm_year - 100);
	384
	385	/* update all the alarm registers in one shot */
ef3b7d0d	386	ret = twl_i2c_write(TWL_MODULE_RTC, alarm_data,
a6b49ffd	387	(rtc_reg_map[REG_ALARM_SECONDS_REG]), ALL_TIME_REGS);
f96411ab DB	388	if (ret) {
	389	dev_err(dev, "rtc_set_alarm error %d\n", ret);
	390	goto out;
	391	}
	392
	393	if (alm->enabled)
ef3b7d0d	394	ret = twl_rtc_alarm_irq_enable(dev, 1);
f96411ab DB	395	out:
	396	return ret;
	397	}
	398
ef3b7d0d	399	static irqreturn_t twl_rtc_interrupt(int irq, void *rtc)
f96411ab	400	{
2778ebcc	401	unsigned long events;
f96411ab DB	402	int ret = IRQ_NONE;
	403	int res;
	404	u8 rd_reg;
	405
ef3b7d0d	406	res = twl_rtc_read_u8(&rd_reg, REG_RTC_STATUS_REG);
f96411ab DB	407	if (res)
	408	goto out;
	409	/*
	410	* Figure out source of interrupt: ALARM or TIMER in RTC_STATUS_REG.
	411	* only one (ALARM or RTC) interrupt source may be enabled
	412	* at time, we also could check our results
	413	* by reading RTS_INTERRUPTS_REGISTER[IT_TIMER,IT_ALARM]
	414	*/
	415	if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M)
2778ebcc	416	events = RTC_IRQF \| RTC_AF;
f96411ab	417	else
2778ebcc	418	events = RTC_IRQF \| RTC_PF;
f96411ab	419
94a339d0	420	res = twl_rtc_write_u8(BIT_RTC_STATUS_REG_ALARM_M,
f96411ab DB	421	REG_RTC_STATUS_REG);
	422	if (res)
	423	goto out;
	424
a6b49ffd B	425	if (twl_class_is_4030()) {
	426	/* Clear on Read enabled. RTC_IT bit of TWL4030_INT_PWR_ISR1
	427	* needs 2 reads to clear the interrupt. One read is done in
	428	* do_twl_pwrirq(). Doing the second read, to clear
	429	* the bit.
	430	*
	431	* FIXME the reason PWR_ISR1 needs an extra read is that
	432	* RTC_IF retriggered until we cleared REG_ALARM_M above.
	433	* But re-reading like this is a bad hack; by doing so we
	434	* risk wrongly clearing status for some other IRQ (losing
	435	* the interrupt). Be smarter about handling RTC_UF ...
	436	*/
	437	res = twl_i2c_read_u8(TWL4030_MODULE_INT,
f96411ab	438	&rd_reg, TWL4030_INT_PWR_ISR1);
a6b49ffd B	439	if (res)
	440	goto out;
	441	}
f96411ab DB	442
	443	/* Notify RTC core on event */
	444	rtc_update_irq(rtc, 1, events);
	445
	446	ret = IRQ_HANDLED;
	447	out:
	448	return ret;
	449	}
	450
ef3b7d0d B	451	static struct rtc_class_ops twl_rtc_ops = {
	452	.read_time = twl_rtc_read_time,
	453	.set_time = twl_rtc_set_time,
	454	.read_alarm = twl_rtc_read_alarm,
	455	.set_alarm = twl_rtc_set_alarm,
	456	.alarm_irq_enable = twl_rtc_alarm_irq_enable,
f96411ab DB	457	};
	458
	459	/----------------------------------------------------------------------/
	460
ef3b7d0d	461	static int __devinit twl_rtc_probe(struct platform_device *pdev)
f96411ab DB	462	{
f96411ab DB	463	struct rtc_device *rtc;
7e72c686	464	int ret = -EINVAL;
f96411ab DB	465	int irq = platform_get_irq(pdev, 0);
	466	u8 rd_reg;
	467
2fac6674	468	if (irq <= 0)
7e72c686	469	goto out1;
f96411ab	470
ef3b7d0d	471	ret = twl_rtc_read_u8(&rd_reg, REG_RTC_STATUS_REG);
f96411ab DB	472	if (ret < 0)
	473	goto out1;
	474
	475	if (rd_reg & BIT_RTC_STATUS_REG_POWER_UP_M)
	476	dev_warn(&pdev->dev, "Power up reset detected.\n");
	477
	478	if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M)
	479	dev_warn(&pdev->dev, "Pending Alarm interrupt detected.\n");
	480
	481	/* Clear RTC Power up reset and pending alarm interrupts */
ef3b7d0d	482	ret = twl_rtc_write_u8(rd_reg, REG_RTC_STATUS_REG);
f96411ab DB	483	if (ret < 0)
	484	goto out1;
	485
a6b49ffd B	486	if (twl_class_is_6030()) {
	487	twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK,
	488	REG_INT_MSK_LINE_A);
	489	twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK,
	490	REG_INT_MSK_STS_A);
	491	}
	492
f7439bcb VB	493	dev_info(&pdev->dev, "Enabling TWL-RTC\n");
f7439bcb VB	494	ret = twl_rtc_write_u8(BIT_RTC_CTRL_REG_STOP_RTC_M, REG_RTC_CTRL_REG);
f96411ab	495	if (ret < 0)
7e72c686	496	goto out1;
f96411ab	497
8dcebaa9 KH	498	/* ensure interrupts are disabled, bootloaders can be strange */
	499	ret = twl_rtc_write_u8(0, REG_RTC_INTERRUPTS_REG);
	500	if (ret < 0)
	501	dev_warn(&pdev->dev, "unable to disable interrupt\n");
	502
f96411ab	503	/* init cached IRQ enable bits */
ef3b7d0d	504	ret = twl_rtc_read_u8(&rtc_irq_bits, REG_RTC_INTERRUPTS_REG);
f96411ab	505	if (ret < 0)
7e72c686 TP	506	goto out1;
	507
	508	rtc = rtc_device_register(pdev->name,
	509	&pdev->dev, &twl_rtc_ops, THIS_MODULE);
	510	if (IS_ERR(rtc)) {
	511	ret = PTR_ERR(rtc);
	512	dev_err(&pdev->dev, "can't register RTC device, err %ld\n",
	513	PTR_ERR(rtc));
	514	goto out1;
	515	}
	516
	517	ret = request_threaded_irq(irq, NULL, twl_rtc_interrupt,
6b91bf1a	518	IRQF_TRIGGER_RISING \| IRQF_ONESHOT,
7e72c686 TP	519	dev_name(&rtc->dev), rtc);
	520	if (ret < 0) {
	521	dev_err(&pdev->dev, "IRQ is not free.\n");
f96411ab	522	goto out2;
7e72c686	523	}
f96411ab	524
7e72c686 TP	525	platform_set_drvdata(pdev, rtc);
7e72c686 TP	526	return 0;
f96411ab	527
f96411ab	528	out2:
f96411ab	529	rtc_device_unregister(rtc);
7e72c686	530	out1:
f96411ab DB	531	return ret;
	532	}
	533
	534	/*
ef3b7d0d	535	* Disable all TWL RTC module interrupts.
f96411ab DB	536	* Sets status flag to free.
f96411ab DB	537	*/
ef3b7d0d	538	static int __devexit twl_rtc_remove(struct platform_device *pdev)
f96411ab DB	539	{
	540	/* leave rtc running, but disable irqs */
	541	struct rtc_device *rtc = platform_get_drvdata(pdev);
	542	int irq = platform_get_irq(pdev, 0);
	543
	544	mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
	545	mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
a6b49ffd B	546	if (twl_class_is_6030()) {
	547	twl6030_interrupt_mask(TWL6030_RTC_INT_MASK,
	548	REG_INT_MSK_LINE_A);
	549	twl6030_interrupt_mask(TWL6030_RTC_INT_MASK,
	550	REG_INT_MSK_STS_A);
	551	}
	552
f96411ab DB	553
	554	free_irq(irq, rtc);
	555
	556	rtc_device_unregister(rtc);
	557	platform_set_drvdata(pdev, NULL);
	558	return 0;
	559	}
	560
ef3b7d0d	561	static void twl_rtc_shutdown(struct platform_device *pdev)
f96411ab	562	{
cafa1d8b MH	563	/* mask timer interrupts, but leave alarm interrupts on to enable
	564	power-on when alarm is triggered */
	565	mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
f96411ab DB	566	}
	567
	568	#ifdef CONFIG_PM
	569
	570	static unsigned char irqstat;
	571
ef3b7d0d	572	static int twl_rtc_suspend(struct platform_device *pdev, pm_message_t state)
f96411ab DB	573	{
	574	irqstat = rtc_irq_bits;
	575
f993004d	576	mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
f96411ab DB	577	return 0;
	578	}
	579
ef3b7d0d	580	static int twl_rtc_resume(struct platform_device *pdev)
f96411ab DB	581	{
	582	set_rtc_irq_bit(irqstat);
	583	return 0;
	584	}
	585
	586	#else
ef3b7d0d B	587	#define twl_rtc_suspend NULL
ef3b7d0d B	588	#define twl_rtc_resume NULL
f96411ab DB	589	#endif
f96411ab DB	590
948170f8 BC	591	static const struct of_device_id twl_rtc_of_match[] = {
	592	{.compatible = "ti,twl4030-rtc", },
	593	{ },
	594	};
	595	MODULE_DEVICE_TABLE(of, twl_rtc_of_match);
ef3b7d0d	596	MODULE_ALIAS("platform:twl_rtc");
f96411ab DB	597
f96411ab DB	598	static struct platform_driver twl4030rtc_driver = {
ef3b7d0d B	599	.probe = twl_rtc_probe,
	600	.remove = __devexit_p(twl_rtc_remove),
	601	.shutdown = twl_rtc_shutdown,
	602	.suspend = twl_rtc_suspend,
	603	.resume = twl_rtc_resume,
f96411ab	604	.driver = {
948170f8 BC	605	.owner = THIS_MODULE,
	606	.name = "twl_rtc",
	607	.of_match_table = twl_rtc_of_match,
f96411ab DB	608	},
	609	};
	610
ef3b7d0d	611	static int __init twl_rtc_init(void)
f96411ab	612	{
a6b49ffd B	613	if (twl_class_is_4030())
	614	rtc_reg_map = (u8 *) twl4030_rtc_reg_map;
	615	else
	616	rtc_reg_map = (u8 *) twl6030_rtc_reg_map;
	617
f96411ab DB	618	return platform_driver_register(&twl4030rtc_driver);
f96411ab DB	619	}
ef3b7d0d	620	module_init(twl_rtc_init);
f96411ab	621
ef3b7d0d	622	static void __exit twl_rtc_exit(void)
f96411ab DB	623	{
	624	platform_driver_unregister(&twl4030rtc_driver);
	625	}
ef3b7d0d	626	module_exit(twl_rtc_exit);
f96411ab DB	627
	628	MODULE_AUTHOR("Texas Instruments, MontaVista Software");
	629	MODULE_LICENSE("GPL");