Commit | Line | Data |
---|---|---|
1add6781 | 1 | /* drivers/rtc/rtc-s3c.c |
e48add8c AD |
2 | * |
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com/ | |
1add6781 BD |
5 | * |
6 | * Copyright (c) 2004,2006 Simtec Electronics | |
7 | * Ben Dooks, <ben@simtec.co.uk> | |
8 | * http://armlinux.simtec.co.uk/ | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * S3C2410/S3C2440/S3C24XX Internal RTC Driver | |
15 | */ | |
16 | ||
17 | #include <linux/module.h> | |
18 | #include <linux/fs.h> | |
19 | #include <linux/string.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/rtc.h> | |
24 | #include <linux/bcd.h> | |
25 | #include <linux/clk.h> | |
9974b6ea | 26 | #include <linux/log2.h> |
5a0e3ad6 | 27 | #include <linux/slab.h> |
39ce4084 | 28 | #include <linux/of.h> |
dbd9acbe SK |
29 | #include <linux/uaccess.h> |
30 | #include <linux/io.h> | |
1add6781 | 31 | |
a09e64fb | 32 | #include <mach/hardware.h> |
1add6781 | 33 | #include <asm/irq.h> |
e2cd00cf | 34 | #include <plat/regs-rtc.h> |
1add6781 | 35 | |
9f4123b7 MC |
36 | enum s3c_cpu_type { |
37 | TYPE_S3C2410, | |
25c1a246 HS |
38 | TYPE_S3C2416, |
39 | TYPE_S3C2443, | |
9f4123b7 MC |
40 | TYPE_S3C64XX, |
41 | }; | |
42 | ||
c3cba928 TB |
43 | struct s3c_rtc_drv_data { |
44 | int cpu_type; | |
45 | }; | |
46 | ||
1add6781 BD |
47 | /* I have yet to find an S3C implementation with more than one |
48 | * of these rtc blocks in */ | |
49 | ||
e48add8c | 50 | static struct clk *rtc_clk; |
1add6781 BD |
51 | static void __iomem *s3c_rtc_base; |
52 | static int s3c_rtc_alarmno = NO_IRQ; | |
53 | static int s3c_rtc_tickno = NO_IRQ; | |
9f4123b7 | 54 | static enum s3c_cpu_type s3c_rtc_cpu_type; |
1add6781 BD |
55 | |
56 | static DEFINE_SPINLOCK(s3c_rtc_pie_lock); | |
1add6781 | 57 | |
88cee8fd DK |
58 | static void s3c_rtc_alarm_clk_enable(bool enable) |
59 | { | |
60 | static DEFINE_SPINLOCK(s3c_rtc_alarm_clk_lock); | |
61 | static bool alarm_clk_enabled; | |
62 | unsigned long irq_flags; | |
63 | ||
64 | spin_lock_irqsave(&s3c_rtc_alarm_clk_lock, irq_flags); | |
65 | if (enable) { | |
66 | if (!alarm_clk_enabled) { | |
67 | clk_enable(rtc_clk); | |
68 | alarm_clk_enabled = true; | |
69 | } | |
70 | } else { | |
71 | if (alarm_clk_enabled) { | |
72 | clk_disable(rtc_clk); | |
73 | alarm_clk_enabled = false; | |
74 | } | |
75 | } | |
76 | spin_unlock_irqrestore(&s3c_rtc_alarm_clk_lock, irq_flags); | |
77 | } | |
78 | ||
1add6781 BD |
79 | /* IRQ Handlers */ |
80 | ||
7d12e780 | 81 | static irqreturn_t s3c_rtc_alarmirq(int irq, void *id) |
1add6781 BD |
82 | { |
83 | struct rtc_device *rdev = id; | |
84 | ||
cefe4fbb | 85 | clk_enable(rtc_clk); |
ab6a2d70 | 86 | rtc_update_irq(rdev, 1, RTC_AF | RTC_IRQF); |
2f3478f6 AD |
87 | |
88 | if (s3c_rtc_cpu_type == TYPE_S3C64XX) | |
89 | writeb(S3C2410_INTP_ALM, s3c_rtc_base + S3C2410_INTP); | |
90 | ||
cefe4fbb | 91 | clk_disable(rtc_clk); |
88cee8fd DK |
92 | |
93 | s3c_rtc_alarm_clk_enable(false); | |
94 | ||
1add6781 BD |
95 | return IRQ_HANDLED; |
96 | } | |
97 | ||
7d12e780 | 98 | static irqreturn_t s3c_rtc_tickirq(int irq, void *id) |
1add6781 BD |
99 | { |
100 | struct rtc_device *rdev = id; | |
101 | ||
cefe4fbb | 102 | clk_enable(rtc_clk); |
773be7ee | 103 | rtc_update_irq(rdev, 1, RTC_PF | RTC_IRQF); |
2f3478f6 AD |
104 | |
105 | if (s3c_rtc_cpu_type == TYPE_S3C64XX) | |
106 | writeb(S3C2410_INTP_TIC, s3c_rtc_base + S3C2410_INTP); | |
107 | ||
cefe4fbb | 108 | clk_disable(rtc_clk); |
1add6781 BD |
109 | return IRQ_HANDLED; |
110 | } | |
111 | ||
112 | /* Update control registers */ | |
2ec38a03 | 113 | static int s3c_rtc_setaie(struct device *dev, unsigned int enabled) |
1add6781 BD |
114 | { |
115 | unsigned int tmp; | |
116 | ||
d4a48c2a | 117 | dev_dbg(dev, "%s: aie=%d\n", __func__, enabled); |
1add6781 | 118 | |
cefe4fbb | 119 | clk_enable(rtc_clk); |
9a654518 | 120 | tmp = readb(s3c_rtc_base + S3C2410_RTCALM) & ~S3C2410_RTCALM_ALMEN; |
1add6781 | 121 | |
2ec38a03 | 122 | if (enabled) |
1add6781 BD |
123 | tmp |= S3C2410_RTCALM_ALMEN; |
124 | ||
9a654518 | 125 | writeb(tmp, s3c_rtc_base + S3C2410_RTCALM); |
cefe4fbb | 126 | clk_disable(rtc_clk); |
2ec38a03 | 127 | |
88cee8fd DK |
128 | s3c_rtc_alarm_clk_enable(enabled); |
129 | ||
2ec38a03 | 130 | return 0; |
1add6781 BD |
131 | } |
132 | ||
773be7ee | 133 | static int s3c_rtc_setfreq(struct device *dev, int freq) |
1add6781 | 134 | { |
9f4123b7 MC |
135 | struct platform_device *pdev = to_platform_device(dev); |
136 | struct rtc_device *rtc_dev = platform_get_drvdata(pdev); | |
137 | unsigned int tmp = 0; | |
25c1a246 | 138 | int val; |
1add6781 | 139 | |
5d2a5037 JC |
140 | if (!is_power_of_2(freq)) |
141 | return -EINVAL; | |
142 | ||
cefe4fbb | 143 | clk_enable(rtc_clk); |
1add6781 | 144 | spin_lock_irq(&s3c_rtc_pie_lock); |
1add6781 | 145 | |
25c1a246 | 146 | if (s3c_rtc_cpu_type != TYPE_S3C64XX) { |
9f4123b7 MC |
147 | tmp = readb(s3c_rtc_base + S3C2410_TICNT); |
148 | tmp &= S3C2410_TICNT_ENABLE; | |
149 | } | |
150 | ||
25c1a246 HS |
151 | val = (rtc_dev->max_user_freq / freq) - 1; |
152 | ||
153 | if (s3c_rtc_cpu_type == TYPE_S3C2416 || s3c_rtc_cpu_type == TYPE_S3C2443) { | |
154 | tmp |= S3C2443_TICNT_PART(val); | |
155 | writel(S3C2443_TICNT1_PART(val), s3c_rtc_base + S3C2443_TICNT1); | |
156 | ||
157 | if (s3c_rtc_cpu_type == TYPE_S3C2416) | |
158 | writel(S3C2416_TICNT2_PART(val), s3c_rtc_base + S3C2416_TICNT2); | |
159 | } else { | |
160 | tmp |= val; | |
161 | } | |
1add6781 | 162 | |
2f3478f6 | 163 | writel(tmp, s3c_rtc_base + S3C2410_TICNT); |
1add6781 | 164 | spin_unlock_irq(&s3c_rtc_pie_lock); |
cefe4fbb | 165 | clk_disable(rtc_clk); |
773be7ee BD |
166 | |
167 | return 0; | |
1add6781 BD |
168 | } |
169 | ||
170 | /* Time read/write */ | |
171 | ||
172 | static int s3c_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm) | |
173 | { | |
174 | unsigned int have_retried = 0; | |
9a654518 | 175 | void __iomem *base = s3c_rtc_base; |
1add6781 | 176 | |
cefe4fbb | 177 | clk_enable(rtc_clk); |
1add6781 | 178 | retry_get_time: |
9a654518 BD |
179 | rtc_tm->tm_min = readb(base + S3C2410_RTCMIN); |
180 | rtc_tm->tm_hour = readb(base + S3C2410_RTCHOUR); | |
181 | rtc_tm->tm_mday = readb(base + S3C2410_RTCDATE); | |
182 | rtc_tm->tm_mon = readb(base + S3C2410_RTCMON); | |
183 | rtc_tm->tm_year = readb(base + S3C2410_RTCYEAR); | |
184 | rtc_tm->tm_sec = readb(base + S3C2410_RTCSEC); | |
1add6781 | 185 | |
48fc7f7e | 186 | /* the only way to work out whether the system was mid-update |
1add6781 BD |
187 | * when we read it is to check the second counter, and if it |
188 | * is zero, then we re-try the entire read | |
189 | */ | |
190 | ||
191 | if (rtc_tm->tm_sec == 0 && !have_retried) { | |
192 | have_retried = 1; | |
193 | goto retry_get_time; | |
194 | } | |
195 | ||
fe20ba70 AB |
196 | rtc_tm->tm_sec = bcd2bin(rtc_tm->tm_sec); |
197 | rtc_tm->tm_min = bcd2bin(rtc_tm->tm_min); | |
198 | rtc_tm->tm_hour = bcd2bin(rtc_tm->tm_hour); | |
199 | rtc_tm->tm_mday = bcd2bin(rtc_tm->tm_mday); | |
200 | rtc_tm->tm_mon = bcd2bin(rtc_tm->tm_mon); | |
201 | rtc_tm->tm_year = bcd2bin(rtc_tm->tm_year); | |
1add6781 BD |
202 | |
203 | rtc_tm->tm_year += 100; | |
4e8896cd | 204 | |
d4a48c2a | 205 | dev_dbg(dev, "read time %04d.%02d.%02d %02d:%02d:%02d\n", |
4e8896cd MH |
206 | 1900 + rtc_tm->tm_year, rtc_tm->tm_mon, rtc_tm->tm_mday, |
207 | rtc_tm->tm_hour, rtc_tm->tm_min, rtc_tm->tm_sec); | |
208 | ||
1add6781 BD |
209 | rtc_tm->tm_mon -= 1; |
210 | ||
cefe4fbb | 211 | clk_disable(rtc_clk); |
5b3ffddd | 212 | return rtc_valid_tm(rtc_tm); |
1add6781 BD |
213 | } |
214 | ||
215 | static int s3c_rtc_settime(struct device *dev, struct rtc_time *tm) | |
216 | { | |
9a654518 | 217 | void __iomem *base = s3c_rtc_base; |
641741e0 | 218 | int year = tm->tm_year - 100; |
9a654518 | 219 | |
d4a48c2a | 220 | dev_dbg(dev, "set time %04d.%02d.%02d %02d:%02d:%02d\n", |
30ffc40c | 221 | 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday, |
641741e0 BD |
222 | tm->tm_hour, tm->tm_min, tm->tm_sec); |
223 | ||
224 | /* we get around y2k by simply not supporting it */ | |
1add6781 | 225 | |
641741e0 | 226 | if (year < 0 || year >= 100) { |
9a654518 | 227 | dev_err(dev, "rtc only supports 100 years\n"); |
1add6781 | 228 | return -EINVAL; |
9a654518 BD |
229 | } |
230 | ||
2dbcd05f | 231 | clk_enable(rtc_clk); |
fe20ba70 AB |
232 | writeb(bin2bcd(tm->tm_sec), base + S3C2410_RTCSEC); |
233 | writeb(bin2bcd(tm->tm_min), base + S3C2410_RTCMIN); | |
234 | writeb(bin2bcd(tm->tm_hour), base + S3C2410_RTCHOUR); | |
235 | writeb(bin2bcd(tm->tm_mday), base + S3C2410_RTCDATE); | |
236 | writeb(bin2bcd(tm->tm_mon + 1), base + S3C2410_RTCMON); | |
237 | writeb(bin2bcd(year), base + S3C2410_RTCYEAR); | |
cefe4fbb | 238 | clk_disable(rtc_clk); |
1add6781 BD |
239 | |
240 | return 0; | |
241 | } | |
242 | ||
243 | static int s3c_rtc_getalarm(struct device *dev, struct rtc_wkalrm *alrm) | |
244 | { | |
245 | struct rtc_time *alm_tm = &alrm->time; | |
9a654518 | 246 | void __iomem *base = s3c_rtc_base; |
1add6781 BD |
247 | unsigned int alm_en; |
248 | ||
cefe4fbb | 249 | clk_enable(rtc_clk); |
9a654518 BD |
250 | alm_tm->tm_sec = readb(base + S3C2410_ALMSEC); |
251 | alm_tm->tm_min = readb(base + S3C2410_ALMMIN); | |
252 | alm_tm->tm_hour = readb(base + S3C2410_ALMHOUR); | |
253 | alm_tm->tm_mon = readb(base + S3C2410_ALMMON); | |
254 | alm_tm->tm_mday = readb(base + S3C2410_ALMDATE); | |
255 | alm_tm->tm_year = readb(base + S3C2410_ALMYEAR); | |
1add6781 | 256 | |
9a654518 | 257 | alm_en = readb(base + S3C2410_RTCALM); |
1add6781 | 258 | |
a2db8dfc DB |
259 | alrm->enabled = (alm_en & S3C2410_RTCALM_ALMEN) ? 1 : 0; |
260 | ||
d4a48c2a | 261 | dev_dbg(dev, "read alarm %d, %04d.%02d.%02d %02d:%02d:%02d\n", |
1add6781 | 262 | alm_en, |
30ffc40c | 263 | 1900 + alm_tm->tm_year, alm_tm->tm_mon, alm_tm->tm_mday, |
1add6781 BD |
264 | alm_tm->tm_hour, alm_tm->tm_min, alm_tm->tm_sec); |
265 | ||
266 | ||
267 | /* decode the alarm enable field */ | |
268 | ||
269 | if (alm_en & S3C2410_RTCALM_SECEN) | |
fe20ba70 | 270 | alm_tm->tm_sec = bcd2bin(alm_tm->tm_sec); |
1add6781 | 271 | else |
dd061d1a | 272 | alm_tm->tm_sec = -1; |
1add6781 BD |
273 | |
274 | if (alm_en & S3C2410_RTCALM_MINEN) | |
fe20ba70 | 275 | alm_tm->tm_min = bcd2bin(alm_tm->tm_min); |
1add6781 | 276 | else |
dd061d1a | 277 | alm_tm->tm_min = -1; |
1add6781 BD |
278 | |
279 | if (alm_en & S3C2410_RTCALM_HOUREN) | |
fe20ba70 | 280 | alm_tm->tm_hour = bcd2bin(alm_tm->tm_hour); |
1add6781 | 281 | else |
dd061d1a | 282 | alm_tm->tm_hour = -1; |
1add6781 BD |
283 | |
284 | if (alm_en & S3C2410_RTCALM_DAYEN) | |
fe20ba70 | 285 | alm_tm->tm_mday = bcd2bin(alm_tm->tm_mday); |
1add6781 | 286 | else |
dd061d1a | 287 | alm_tm->tm_mday = -1; |
1add6781 BD |
288 | |
289 | if (alm_en & S3C2410_RTCALM_MONEN) { | |
fe20ba70 | 290 | alm_tm->tm_mon = bcd2bin(alm_tm->tm_mon); |
1add6781 BD |
291 | alm_tm->tm_mon -= 1; |
292 | } else { | |
dd061d1a | 293 | alm_tm->tm_mon = -1; |
1add6781 BD |
294 | } |
295 | ||
296 | if (alm_en & S3C2410_RTCALM_YEAREN) | |
fe20ba70 | 297 | alm_tm->tm_year = bcd2bin(alm_tm->tm_year); |
1add6781 | 298 | else |
dd061d1a | 299 | alm_tm->tm_year = -1; |
1add6781 | 300 | |
cefe4fbb | 301 | clk_disable(rtc_clk); |
1add6781 BD |
302 | return 0; |
303 | } | |
304 | ||
305 | static int s3c_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm) | |
306 | { | |
307 | struct rtc_time *tm = &alrm->time; | |
9a654518 | 308 | void __iomem *base = s3c_rtc_base; |
1add6781 BD |
309 | unsigned int alrm_en; |
310 | ||
cefe4fbb | 311 | clk_enable(rtc_clk); |
d4a48c2a | 312 | dev_dbg(dev, "s3c_rtc_setalarm: %d, %04d.%02d.%02d %02d:%02d:%02d\n", |
1add6781 | 313 | alrm->enabled, |
4e8896cd | 314 | 1900 + tm->tm_year, tm->tm_mon + 1, tm->tm_mday, |
30ffc40c | 315 | tm->tm_hour, tm->tm_min, tm->tm_sec); |
1add6781 | 316 | |
9a654518 BD |
317 | alrm_en = readb(base + S3C2410_RTCALM) & S3C2410_RTCALM_ALMEN; |
318 | writeb(0x00, base + S3C2410_RTCALM); | |
1add6781 BD |
319 | |
320 | if (tm->tm_sec < 60 && tm->tm_sec >= 0) { | |
321 | alrm_en |= S3C2410_RTCALM_SECEN; | |
fe20ba70 | 322 | writeb(bin2bcd(tm->tm_sec), base + S3C2410_ALMSEC); |
1add6781 BD |
323 | } |
324 | ||
325 | if (tm->tm_min < 60 && tm->tm_min >= 0) { | |
326 | alrm_en |= S3C2410_RTCALM_MINEN; | |
fe20ba70 | 327 | writeb(bin2bcd(tm->tm_min), base + S3C2410_ALMMIN); |
1add6781 BD |
328 | } |
329 | ||
330 | if (tm->tm_hour < 24 && tm->tm_hour >= 0) { | |
331 | alrm_en |= S3C2410_RTCALM_HOUREN; | |
fe20ba70 | 332 | writeb(bin2bcd(tm->tm_hour), base + S3C2410_ALMHOUR); |
1add6781 BD |
333 | } |
334 | ||
d4a48c2a | 335 | dev_dbg(dev, "setting S3C2410_RTCALM to %08x\n", alrm_en); |
1add6781 | 336 | |
9a654518 | 337 | writeb(alrm_en, base + S3C2410_RTCALM); |
1add6781 | 338 | |
2ec38a03 | 339 | s3c_rtc_setaie(dev, alrm->enabled); |
1add6781 | 340 | |
cefe4fbb | 341 | clk_disable(rtc_clk); |
1add6781 BD |
342 | return 0; |
343 | } | |
344 | ||
1add6781 BD |
345 | static int s3c_rtc_proc(struct device *dev, struct seq_file *seq) |
346 | { | |
9f4123b7 | 347 | unsigned int ticnt; |
1add6781 | 348 | |
cefe4fbb | 349 | clk_enable(rtc_clk); |
9f4123b7 | 350 | if (s3c_rtc_cpu_type == TYPE_S3C64XX) { |
f61ae671 | 351 | ticnt = readw(s3c_rtc_base + S3C2410_RTCCON); |
9f4123b7 MC |
352 | ticnt &= S3C64XX_RTCCON_TICEN; |
353 | } else { | |
354 | ticnt = readb(s3c_rtc_base + S3C2410_TICNT); | |
355 | ticnt &= S3C2410_TICNT_ENABLE; | |
356 | } | |
357 | ||
358 | seq_printf(seq, "periodic_IRQ\t: %s\n", ticnt ? "yes" : "no"); | |
cefe4fbb | 359 | clk_disable(rtc_clk); |
1add6781 BD |
360 | return 0; |
361 | } | |
362 | ||
ff8371ac | 363 | static const struct rtc_class_ops s3c_rtcops = { |
1add6781 BD |
364 | .read_time = s3c_rtc_gettime, |
365 | .set_time = s3c_rtc_settime, | |
366 | .read_alarm = s3c_rtc_getalarm, | |
367 | .set_alarm = s3c_rtc_setalarm, | |
e6eb524e CY |
368 | .proc = s3c_rtc_proc, |
369 | .alarm_irq_enable = s3c_rtc_setaie, | |
1add6781 BD |
370 | }; |
371 | ||
372 | static void s3c_rtc_enable(struct platform_device *pdev, int en) | |
373 | { | |
9a654518 | 374 | void __iomem *base = s3c_rtc_base; |
1add6781 BD |
375 | unsigned int tmp; |
376 | ||
377 | if (s3c_rtc_base == NULL) | |
378 | return; | |
379 | ||
cefe4fbb | 380 | clk_enable(rtc_clk); |
1add6781 | 381 | if (!en) { |
f61ae671 | 382 | tmp = readw(base + S3C2410_RTCCON); |
9f4123b7 MC |
383 | if (s3c_rtc_cpu_type == TYPE_S3C64XX) |
384 | tmp &= ~S3C64XX_RTCCON_TICEN; | |
385 | tmp &= ~S3C2410_RTCCON_RTCEN; | |
f61ae671 | 386 | writew(tmp, base + S3C2410_RTCCON); |
9f4123b7 | 387 | |
25c1a246 | 388 | if (s3c_rtc_cpu_type != TYPE_S3C64XX) { |
9f4123b7 MC |
389 | tmp = readb(base + S3C2410_TICNT); |
390 | tmp &= ~S3C2410_TICNT_ENABLE; | |
391 | writeb(tmp, base + S3C2410_TICNT); | |
392 | } | |
1add6781 BD |
393 | } else { |
394 | /* re-enable the device, and check it is ok */ | |
395 | ||
f61ae671 | 396 | if ((readw(base+S3C2410_RTCCON) & S3C2410_RTCCON_RTCEN) == 0) { |
1add6781 BD |
397 | dev_info(&pdev->dev, "rtc disabled, re-enabling\n"); |
398 | ||
f61ae671 CY |
399 | tmp = readw(base + S3C2410_RTCCON); |
400 | writew(tmp | S3C2410_RTCCON_RTCEN, | |
401 | base + S3C2410_RTCCON); | |
1add6781 BD |
402 | } |
403 | ||
f61ae671 | 404 | if ((readw(base + S3C2410_RTCCON) & S3C2410_RTCCON_CNTSEL)) { |
1add6781 BD |
405 | dev_info(&pdev->dev, "removing RTCCON_CNTSEL\n"); |
406 | ||
f61ae671 CY |
407 | tmp = readw(base + S3C2410_RTCCON); |
408 | writew(tmp & ~S3C2410_RTCCON_CNTSEL, | |
409 | base + S3C2410_RTCCON); | |
1add6781 BD |
410 | } |
411 | ||
f61ae671 | 412 | if ((readw(base + S3C2410_RTCCON) & S3C2410_RTCCON_CLKRST)) { |
1add6781 BD |
413 | dev_info(&pdev->dev, "removing RTCCON_CLKRST\n"); |
414 | ||
f61ae671 CY |
415 | tmp = readw(base + S3C2410_RTCCON); |
416 | writew(tmp & ~S3C2410_RTCCON_CLKRST, | |
417 | base + S3C2410_RTCCON); | |
1add6781 BD |
418 | } |
419 | } | |
cefe4fbb | 420 | clk_disable(rtc_clk); |
1add6781 BD |
421 | } |
422 | ||
5a167f45 | 423 | static int s3c_rtc_remove(struct platform_device *dev) |
1add6781 | 424 | { |
1add6781 | 425 | platform_set_drvdata(dev, NULL); |
1add6781 | 426 | |
2ec38a03 | 427 | s3c_rtc_setaie(&dev->dev, 0); |
1add6781 | 428 | |
1a3224f1 | 429 | clk_unprepare(rtc_clk); |
e48add8c AD |
430 | rtc_clk = NULL; |
431 | ||
1add6781 BD |
432 | return 0; |
433 | } | |
434 | ||
d2524caa HS |
435 | static const struct of_device_id s3c_rtc_dt_match[]; |
436 | ||
437 | static inline int s3c_rtc_get_driver_data(struct platform_device *pdev) | |
438 | { | |
439 | #ifdef CONFIG_OF | |
c3cba928 | 440 | struct s3c_rtc_drv_data *data; |
d2524caa HS |
441 | if (pdev->dev.of_node) { |
442 | const struct of_device_id *match; | |
443 | match = of_match_node(s3c_rtc_dt_match, pdev->dev.of_node); | |
c3cba928 TB |
444 | data = (struct s3c_rtc_drv_data *) match->data; |
445 | return data->cpu_type; | |
d2524caa HS |
446 | } |
447 | #endif | |
448 | return platform_get_device_id(pdev)->driver_data; | |
449 | } | |
450 | ||
5a167f45 | 451 | static int s3c_rtc_probe(struct platform_device *pdev) |
1add6781 BD |
452 | { |
453 | struct rtc_device *rtc; | |
e1df962e | 454 | struct rtc_time rtc_tm; |
1add6781 BD |
455 | struct resource *res; |
456 | int ret; | |
25c1a246 | 457 | int tmp; |
1add6781 | 458 | |
d4a48c2a | 459 | dev_dbg(&pdev->dev, "%s: probe=%p\n", __func__, pdev); |
1add6781 BD |
460 | |
461 | /* find the IRQs */ | |
462 | ||
463 | s3c_rtc_tickno = platform_get_irq(pdev, 1); | |
464 | if (s3c_rtc_tickno < 0) { | |
465 | dev_err(&pdev->dev, "no irq for rtc tick\n"); | |
1ee8c0ca | 466 | return s3c_rtc_tickno; |
1add6781 BD |
467 | } |
468 | ||
469 | s3c_rtc_alarmno = platform_get_irq(pdev, 0); | |
470 | if (s3c_rtc_alarmno < 0) { | |
471 | dev_err(&pdev->dev, "no irq for alarm\n"); | |
1ee8c0ca | 472 | return s3c_rtc_alarmno; |
1add6781 BD |
473 | } |
474 | ||
d4a48c2a | 475 | dev_dbg(&pdev->dev, "s3c2410_rtc: tick irq %d, alarm irq %d\n", |
1add6781 BD |
476 | s3c_rtc_tickno, s3c_rtc_alarmno); |
477 | ||
478 | /* get the memory region */ | |
479 | ||
480 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
481 | if (res == NULL) { | |
482 | dev_err(&pdev->dev, "failed to get memory region resource\n"); | |
483 | return -ENOENT; | |
484 | } | |
485 | ||
8cbce1e5 TR |
486 | s3c_rtc_base = devm_ioremap_resource(&pdev->dev, res); |
487 | if (IS_ERR(s3c_rtc_base)) | |
488 | return PTR_ERR(s3c_rtc_base); | |
1add6781 | 489 | |
1b997329 | 490 | rtc_clk = devm_clk_get(&pdev->dev, "rtc"); |
e48add8c AD |
491 | if (IS_ERR(rtc_clk)) { |
492 | dev_err(&pdev->dev, "failed to find rtc clock source\n"); | |
493 | ret = PTR_ERR(rtc_clk); | |
494 | rtc_clk = NULL; | |
1b997329 | 495 | return ret; |
e48add8c AD |
496 | } |
497 | ||
1a3224f1 | 498 | clk_prepare_enable(rtc_clk); |
e48add8c | 499 | |
1add6781 BD |
500 | /* check to see if everything is setup correctly */ |
501 | ||
502 | s3c_rtc_enable(pdev, 1); | |
503 | ||
d4a48c2a | 504 | dev_dbg(&pdev->dev, "s3c2410_rtc: RTCCON=%02x\n", |
f61ae671 | 505 | readw(s3c_rtc_base + S3C2410_RTCCON)); |
1add6781 | 506 | |
51b7616e YK |
507 | device_init_wakeup(&pdev->dev, 1); |
508 | ||
1add6781 BD |
509 | /* register RTC and exit */ |
510 | ||
4c99c13a | 511 | rtc = devm_rtc_device_register(&pdev->dev, "s3c", &s3c_rtcops, |
1add6781 BD |
512 | THIS_MODULE); |
513 | ||
514 | if (IS_ERR(rtc)) { | |
515 | dev_err(&pdev->dev, "cannot attach rtc\n"); | |
516 | ret = PTR_ERR(rtc); | |
517 | goto err_nortc; | |
518 | } | |
519 | ||
d2524caa | 520 | s3c_rtc_cpu_type = s3c_rtc_get_driver_data(pdev); |
eaa6e4dd | 521 | |
051fe54e TK |
522 | /* Check RTC Time */ |
523 | ||
e1df962e | 524 | s3c_rtc_gettime(NULL, &rtc_tm); |
051fe54e | 525 | |
e1df962e CY |
526 | if (rtc_valid_tm(&rtc_tm)) { |
527 | rtc_tm.tm_year = 100; | |
528 | rtc_tm.tm_mon = 0; | |
529 | rtc_tm.tm_mday = 1; | |
530 | rtc_tm.tm_hour = 0; | |
531 | rtc_tm.tm_min = 0; | |
532 | rtc_tm.tm_sec = 0; | |
533 | ||
534 | s3c_rtc_settime(NULL, &rtc_tm); | |
535 | ||
536 | dev_warn(&pdev->dev, "warning: invalid RTC value so initializing it\n"); | |
051fe54e TK |
537 | } |
538 | ||
25c1a246 | 539 | if (s3c_rtc_cpu_type != TYPE_S3C2410) |
9f4123b7 MC |
540 | rtc->max_user_freq = 32768; |
541 | else | |
542 | rtc->max_user_freq = 128; | |
543 | ||
25c1a246 HS |
544 | if (s3c_rtc_cpu_type == TYPE_S3C2416 || s3c_rtc_cpu_type == TYPE_S3C2443) { |
545 | tmp = readw(s3c_rtc_base + S3C2410_RTCCON); | |
546 | tmp |= S3C2443_RTCCON_TICSEL; | |
547 | writew(tmp, s3c_rtc_base + S3C2410_RTCCON); | |
548 | } | |
549 | ||
1add6781 | 550 | platform_set_drvdata(pdev, rtc); |
e893de59 MC |
551 | |
552 | s3c_rtc_setfreq(&pdev->dev, 1); | |
553 | ||
1b997329 | 554 | ret = devm_request_irq(&pdev->dev, s3c_rtc_alarmno, s3c_rtc_alarmirq, |
2f6e5f94 | 555 | 0, "s3c2410-rtc alarm", rtc); |
62d17601 MH |
556 | if (ret) { |
557 | dev_err(&pdev->dev, "IRQ%d error %d\n", s3c_rtc_alarmno, ret); | |
558 | goto err_alarm_irq; | |
559 | } | |
560 | ||
1b997329 | 561 | ret = devm_request_irq(&pdev->dev, s3c_rtc_tickno, s3c_rtc_tickirq, |
2f6e5f94 | 562 | 0, "s3c2410-rtc tick", rtc); |
62d17601 MH |
563 | if (ret) { |
564 | dev_err(&pdev->dev, "IRQ%d error %d\n", s3c_rtc_tickno, ret); | |
1b997329 | 565 | goto err_alarm_irq; |
62d17601 MH |
566 | } |
567 | ||
cefe4fbb DK |
568 | clk_disable(rtc_clk); |
569 | ||
1add6781 BD |
570 | return 0; |
571 | ||
62d17601 MH |
572 | err_alarm_irq: |
573 | platform_set_drvdata(pdev, NULL); | |
62d17601 | 574 | |
1add6781 BD |
575 | err_nortc: |
576 | s3c_rtc_enable(pdev, 0); | |
1a3224f1 | 577 | clk_disable_unprepare(rtc_clk); |
1add6781 | 578 | |
1add6781 BD |
579 | return ret; |
580 | } | |
581 | ||
32e445aa | 582 | #ifdef CONFIG_PM_SLEEP |
1add6781 BD |
583 | /* RTC Power management control */ |
584 | ||
9f4123b7 | 585 | static int ticnt_save, ticnt_en_save; |
32e445aa | 586 | static bool wake_en; |
1add6781 | 587 | |
32e445aa | 588 | static int s3c_rtc_suspend(struct device *dev) |
1add6781 | 589 | { |
32e445aa JH |
590 | struct platform_device *pdev = to_platform_device(dev); |
591 | ||
cefe4fbb | 592 | clk_enable(rtc_clk); |
1add6781 | 593 | /* save TICNT for anyone using periodic interrupts */ |
9a654518 | 594 | ticnt_save = readb(s3c_rtc_base + S3C2410_TICNT); |
9f4123b7 | 595 | if (s3c_rtc_cpu_type == TYPE_S3C64XX) { |
f61ae671 | 596 | ticnt_en_save = readw(s3c_rtc_base + S3C2410_RTCCON); |
9f4123b7 MC |
597 | ticnt_en_save &= S3C64XX_RTCCON_TICEN; |
598 | } | |
1add6781 | 599 | s3c_rtc_enable(pdev, 0); |
f501ed52 | 600 | |
32e445aa | 601 | if (device_may_wakeup(dev) && !wake_en) { |
52cd4e5c BD |
602 | if (enable_irq_wake(s3c_rtc_alarmno) == 0) |
603 | wake_en = true; | |
604 | else | |
32e445aa | 605 | dev_err(dev, "enable_irq_wake failed\n"); |
52cd4e5c | 606 | } |
cefe4fbb | 607 | clk_disable(rtc_clk); |
f501ed52 | 608 | |
1add6781 BD |
609 | return 0; |
610 | } | |
611 | ||
32e445aa | 612 | static int s3c_rtc_resume(struct device *dev) |
1add6781 | 613 | { |
32e445aa | 614 | struct platform_device *pdev = to_platform_device(dev); |
9f4123b7 MC |
615 | unsigned int tmp; |
616 | ||
cefe4fbb | 617 | clk_enable(rtc_clk); |
1add6781 | 618 | s3c_rtc_enable(pdev, 1); |
9a654518 | 619 | writeb(ticnt_save, s3c_rtc_base + S3C2410_TICNT); |
9f4123b7 | 620 | if (s3c_rtc_cpu_type == TYPE_S3C64XX && ticnt_en_save) { |
f61ae671 CY |
621 | tmp = readw(s3c_rtc_base + S3C2410_RTCCON); |
622 | writew(tmp | ticnt_en_save, s3c_rtc_base + S3C2410_RTCCON); | |
9f4123b7 | 623 | } |
f501ed52 | 624 | |
32e445aa | 625 | if (device_may_wakeup(dev) && wake_en) { |
f501ed52 | 626 | disable_irq_wake(s3c_rtc_alarmno); |
52cd4e5c BD |
627 | wake_en = false; |
628 | } | |
cefe4fbb | 629 | clk_disable(rtc_clk); |
f501ed52 | 630 | |
1add6781 BD |
631 | return 0; |
632 | } | |
1add6781 BD |
633 | #endif |
634 | ||
32e445aa JH |
635 | static SIMPLE_DEV_PM_OPS(s3c_rtc_pm_ops, s3c_rtc_suspend, s3c_rtc_resume); |
636 | ||
ecb41a77 | 637 | #ifdef CONFIG_OF |
c3cba928 TB |
638 | static struct s3c_rtc_drv_data s3c_rtc_drv_data_array[] = { |
639 | [TYPE_S3C2410] = { TYPE_S3C2410 }, | |
640 | [TYPE_S3C2416] = { TYPE_S3C2416 }, | |
641 | [TYPE_S3C2443] = { TYPE_S3C2443 }, | |
642 | [TYPE_S3C64XX] = { TYPE_S3C64XX }, | |
643 | }; | |
644 | ||
39ce4084 | 645 | static const struct of_device_id s3c_rtc_dt_match[] = { |
d2524caa | 646 | { |
cd1e6f9e | 647 | .compatible = "samsung,s3c2410-rtc", |
c3cba928 | 648 | .data = &s3c_rtc_drv_data_array[TYPE_S3C2410], |
25c1a246 | 649 | }, { |
cd1e6f9e | 650 | .compatible = "samsung,s3c2416-rtc", |
c3cba928 | 651 | .data = &s3c_rtc_drv_data_array[TYPE_S3C2416], |
25c1a246 | 652 | }, { |
cd1e6f9e | 653 | .compatible = "samsung,s3c2443-rtc", |
c3cba928 | 654 | .data = &s3c_rtc_drv_data_array[TYPE_S3C2443], |
d2524caa | 655 | }, { |
cd1e6f9e | 656 | .compatible = "samsung,s3c6410-rtc", |
c3cba928 | 657 | .data = &s3c_rtc_drv_data_array[TYPE_S3C64XX], |
d2524caa | 658 | }, |
39ce4084 TA |
659 | {}, |
660 | }; | |
661 | MODULE_DEVICE_TABLE(of, s3c_rtc_dt_match); | |
39ce4084 TA |
662 | #endif |
663 | ||
9f4123b7 MC |
664 | static struct platform_device_id s3c_rtc_driver_ids[] = { |
665 | { | |
666 | .name = "s3c2410-rtc", | |
667 | .driver_data = TYPE_S3C2410, | |
25c1a246 HS |
668 | }, { |
669 | .name = "s3c2416-rtc", | |
670 | .driver_data = TYPE_S3C2416, | |
671 | }, { | |
672 | .name = "s3c2443-rtc", | |
673 | .driver_data = TYPE_S3C2443, | |
9f4123b7 MC |
674 | }, { |
675 | .name = "s3c64xx-rtc", | |
676 | .driver_data = TYPE_S3C64XX, | |
677 | }, | |
678 | { } | |
679 | }; | |
680 | ||
681 | MODULE_DEVICE_TABLE(platform, s3c_rtc_driver_ids); | |
682 | ||
683 | static struct platform_driver s3c_rtc_driver = { | |
1add6781 | 684 | .probe = s3c_rtc_probe, |
5a167f45 | 685 | .remove = s3c_rtc_remove, |
9f4123b7 | 686 | .id_table = s3c_rtc_driver_ids, |
1add6781 | 687 | .driver = { |
9f4123b7 | 688 | .name = "s3c-rtc", |
1add6781 | 689 | .owner = THIS_MODULE, |
32e445aa | 690 | .pm = &s3c_rtc_pm_ops, |
04a373fd | 691 | .of_match_table = of_match_ptr(s3c_rtc_dt_match), |
1add6781 BD |
692 | }, |
693 | }; | |
694 | ||
0c4eae66 | 695 | module_platform_driver(s3c_rtc_driver); |
1add6781 BD |
696 | |
697 | MODULE_DESCRIPTION("Samsung S3C RTC Driver"); | |
698 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); | |
699 | MODULE_LICENSE("GPL"); | |
ad28a07b | 700 | MODULE_ALIAS("platform:s3c2410-rtc"); |