drivers/rtc/rtc-max8907.c: remove redundant code
[GitHub/LineageOS/android_kernel_samsung_universal7580.git] / drivers / rtc / rtc-s3c.c
CommitLineData
1add6781 1/* drivers/rtc/rtc-s3c.c
e48add8c
AD
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
1add6781
BD
5 *
6 * Copyright (c) 2004,2006 Simtec Electronics
7 * Ben Dooks, <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * S3C2410/S3C2440/S3C24XX Internal RTC Driver
15*/
16
17#include <linux/module.h>
18#include <linux/fs.h>
19#include <linux/string.h>
20#include <linux/init.h>
21#include <linux/platform_device.h>
22#include <linux/interrupt.h>
23#include <linux/rtc.h>
24#include <linux/bcd.h>
25#include <linux/clk.h>
9974b6ea 26#include <linux/log2.h>
5a0e3ad6 27#include <linux/slab.h>
39ce4084 28#include <linux/of.h>
dbd9acbe
SK
29#include <linux/uaccess.h>
30#include <linux/io.h>
1add6781 31
a09e64fb 32#include <mach/hardware.h>
1add6781 33#include <asm/irq.h>
e2cd00cf 34#include <plat/regs-rtc.h>
1add6781 35
9f4123b7
MC
36enum s3c_cpu_type {
37 TYPE_S3C2410,
25c1a246
HS
38 TYPE_S3C2416,
39 TYPE_S3C2443,
9f4123b7
MC
40 TYPE_S3C64XX,
41};
42
c3cba928
TB
43struct s3c_rtc_drv_data {
44 int cpu_type;
45};
46
1add6781
BD
47/* I have yet to find an S3C implementation with more than one
48 * of these rtc blocks in */
49
e48add8c 50static struct clk *rtc_clk;
1add6781
BD
51static void __iomem *s3c_rtc_base;
52static int s3c_rtc_alarmno = NO_IRQ;
53static int s3c_rtc_tickno = NO_IRQ;
9f4123b7 54static enum s3c_cpu_type s3c_rtc_cpu_type;
1add6781
BD
55
56static DEFINE_SPINLOCK(s3c_rtc_pie_lock);
1add6781 57
88cee8fd
DK
58static void s3c_rtc_alarm_clk_enable(bool enable)
59{
60 static DEFINE_SPINLOCK(s3c_rtc_alarm_clk_lock);
61 static bool alarm_clk_enabled;
62 unsigned long irq_flags;
63
64 spin_lock_irqsave(&s3c_rtc_alarm_clk_lock, irq_flags);
65 if (enable) {
66 if (!alarm_clk_enabled) {
67 clk_enable(rtc_clk);
68 alarm_clk_enabled = true;
69 }
70 } else {
71 if (alarm_clk_enabled) {
72 clk_disable(rtc_clk);
73 alarm_clk_enabled = false;
74 }
75 }
76 spin_unlock_irqrestore(&s3c_rtc_alarm_clk_lock, irq_flags);
77}
78
1add6781
BD
79/* IRQ Handlers */
80
7d12e780 81static irqreturn_t s3c_rtc_alarmirq(int irq, void *id)
1add6781
BD
82{
83 struct rtc_device *rdev = id;
84
cefe4fbb 85 clk_enable(rtc_clk);
ab6a2d70 86 rtc_update_irq(rdev, 1, RTC_AF | RTC_IRQF);
2f3478f6
AD
87
88 if (s3c_rtc_cpu_type == TYPE_S3C64XX)
89 writeb(S3C2410_INTP_ALM, s3c_rtc_base + S3C2410_INTP);
90
cefe4fbb 91 clk_disable(rtc_clk);
88cee8fd
DK
92
93 s3c_rtc_alarm_clk_enable(false);
94
1add6781
BD
95 return IRQ_HANDLED;
96}
97
7d12e780 98static irqreturn_t s3c_rtc_tickirq(int irq, void *id)
1add6781
BD
99{
100 struct rtc_device *rdev = id;
101
cefe4fbb 102 clk_enable(rtc_clk);
773be7ee 103 rtc_update_irq(rdev, 1, RTC_PF | RTC_IRQF);
2f3478f6
AD
104
105 if (s3c_rtc_cpu_type == TYPE_S3C64XX)
106 writeb(S3C2410_INTP_TIC, s3c_rtc_base + S3C2410_INTP);
107
cefe4fbb 108 clk_disable(rtc_clk);
1add6781
BD
109 return IRQ_HANDLED;
110}
111
112/* Update control registers */
2ec38a03 113static int s3c_rtc_setaie(struct device *dev, unsigned int enabled)
1add6781
BD
114{
115 unsigned int tmp;
116
d4a48c2a 117 dev_dbg(dev, "%s: aie=%d\n", __func__, enabled);
1add6781 118
cefe4fbb 119 clk_enable(rtc_clk);
9a654518 120 tmp = readb(s3c_rtc_base + S3C2410_RTCALM) & ~S3C2410_RTCALM_ALMEN;
1add6781 121
2ec38a03 122 if (enabled)
1add6781
BD
123 tmp |= S3C2410_RTCALM_ALMEN;
124
9a654518 125 writeb(tmp, s3c_rtc_base + S3C2410_RTCALM);
cefe4fbb 126 clk_disable(rtc_clk);
2ec38a03 127
88cee8fd
DK
128 s3c_rtc_alarm_clk_enable(enabled);
129
2ec38a03 130 return 0;
1add6781
BD
131}
132
773be7ee 133static int s3c_rtc_setfreq(struct device *dev, int freq)
1add6781 134{
9f4123b7
MC
135 struct platform_device *pdev = to_platform_device(dev);
136 struct rtc_device *rtc_dev = platform_get_drvdata(pdev);
137 unsigned int tmp = 0;
25c1a246 138 int val;
1add6781 139
5d2a5037
JC
140 if (!is_power_of_2(freq))
141 return -EINVAL;
142
cefe4fbb 143 clk_enable(rtc_clk);
1add6781 144 spin_lock_irq(&s3c_rtc_pie_lock);
1add6781 145
25c1a246 146 if (s3c_rtc_cpu_type != TYPE_S3C64XX) {
9f4123b7
MC
147 tmp = readb(s3c_rtc_base + S3C2410_TICNT);
148 tmp &= S3C2410_TICNT_ENABLE;
149 }
150
25c1a246
HS
151 val = (rtc_dev->max_user_freq / freq) - 1;
152
153 if (s3c_rtc_cpu_type == TYPE_S3C2416 || s3c_rtc_cpu_type == TYPE_S3C2443) {
154 tmp |= S3C2443_TICNT_PART(val);
155 writel(S3C2443_TICNT1_PART(val), s3c_rtc_base + S3C2443_TICNT1);
156
157 if (s3c_rtc_cpu_type == TYPE_S3C2416)
158 writel(S3C2416_TICNT2_PART(val), s3c_rtc_base + S3C2416_TICNT2);
159 } else {
160 tmp |= val;
161 }
1add6781 162
2f3478f6 163 writel(tmp, s3c_rtc_base + S3C2410_TICNT);
1add6781 164 spin_unlock_irq(&s3c_rtc_pie_lock);
cefe4fbb 165 clk_disable(rtc_clk);
773be7ee
BD
166
167 return 0;
1add6781
BD
168}
169
170/* Time read/write */
171
172static int s3c_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
173{
174 unsigned int have_retried = 0;
9a654518 175 void __iomem *base = s3c_rtc_base;
1add6781 176
cefe4fbb 177 clk_enable(rtc_clk);
1add6781 178 retry_get_time:
9a654518
BD
179 rtc_tm->tm_min = readb(base + S3C2410_RTCMIN);
180 rtc_tm->tm_hour = readb(base + S3C2410_RTCHOUR);
181 rtc_tm->tm_mday = readb(base + S3C2410_RTCDATE);
182 rtc_tm->tm_mon = readb(base + S3C2410_RTCMON);
183 rtc_tm->tm_year = readb(base + S3C2410_RTCYEAR);
184 rtc_tm->tm_sec = readb(base + S3C2410_RTCSEC);
1add6781 185
48fc7f7e 186 /* the only way to work out whether the system was mid-update
1add6781
BD
187 * when we read it is to check the second counter, and if it
188 * is zero, then we re-try the entire read
189 */
190
191 if (rtc_tm->tm_sec == 0 && !have_retried) {
192 have_retried = 1;
193 goto retry_get_time;
194 }
195
fe20ba70
AB
196 rtc_tm->tm_sec = bcd2bin(rtc_tm->tm_sec);
197 rtc_tm->tm_min = bcd2bin(rtc_tm->tm_min);
198 rtc_tm->tm_hour = bcd2bin(rtc_tm->tm_hour);
199 rtc_tm->tm_mday = bcd2bin(rtc_tm->tm_mday);
200 rtc_tm->tm_mon = bcd2bin(rtc_tm->tm_mon);
201 rtc_tm->tm_year = bcd2bin(rtc_tm->tm_year);
1add6781
BD
202
203 rtc_tm->tm_year += 100;
4e8896cd 204
d4a48c2a 205 dev_dbg(dev, "read time %04d.%02d.%02d %02d:%02d:%02d\n",
4e8896cd
MH
206 1900 + rtc_tm->tm_year, rtc_tm->tm_mon, rtc_tm->tm_mday,
207 rtc_tm->tm_hour, rtc_tm->tm_min, rtc_tm->tm_sec);
208
1add6781
BD
209 rtc_tm->tm_mon -= 1;
210
cefe4fbb 211 clk_disable(rtc_clk);
5b3ffddd 212 return rtc_valid_tm(rtc_tm);
1add6781
BD
213}
214
215static int s3c_rtc_settime(struct device *dev, struct rtc_time *tm)
216{
9a654518 217 void __iomem *base = s3c_rtc_base;
641741e0 218 int year = tm->tm_year - 100;
9a654518 219
d4a48c2a 220 dev_dbg(dev, "set time %04d.%02d.%02d %02d:%02d:%02d\n",
30ffc40c 221 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday,
641741e0
BD
222 tm->tm_hour, tm->tm_min, tm->tm_sec);
223
224 /* we get around y2k by simply not supporting it */
1add6781 225
641741e0 226 if (year < 0 || year >= 100) {
9a654518 227 dev_err(dev, "rtc only supports 100 years\n");
1add6781 228 return -EINVAL;
9a654518
BD
229 }
230
2dbcd05f 231 clk_enable(rtc_clk);
fe20ba70
AB
232 writeb(bin2bcd(tm->tm_sec), base + S3C2410_RTCSEC);
233 writeb(bin2bcd(tm->tm_min), base + S3C2410_RTCMIN);
234 writeb(bin2bcd(tm->tm_hour), base + S3C2410_RTCHOUR);
235 writeb(bin2bcd(tm->tm_mday), base + S3C2410_RTCDATE);
236 writeb(bin2bcd(tm->tm_mon + 1), base + S3C2410_RTCMON);
237 writeb(bin2bcd(year), base + S3C2410_RTCYEAR);
cefe4fbb 238 clk_disable(rtc_clk);
1add6781
BD
239
240 return 0;
241}
242
243static int s3c_rtc_getalarm(struct device *dev, struct rtc_wkalrm *alrm)
244{
245 struct rtc_time *alm_tm = &alrm->time;
9a654518 246 void __iomem *base = s3c_rtc_base;
1add6781
BD
247 unsigned int alm_en;
248
cefe4fbb 249 clk_enable(rtc_clk);
9a654518
BD
250 alm_tm->tm_sec = readb(base + S3C2410_ALMSEC);
251 alm_tm->tm_min = readb(base + S3C2410_ALMMIN);
252 alm_tm->tm_hour = readb(base + S3C2410_ALMHOUR);
253 alm_tm->tm_mon = readb(base + S3C2410_ALMMON);
254 alm_tm->tm_mday = readb(base + S3C2410_ALMDATE);
255 alm_tm->tm_year = readb(base + S3C2410_ALMYEAR);
1add6781 256
9a654518 257 alm_en = readb(base + S3C2410_RTCALM);
1add6781 258
a2db8dfc
DB
259 alrm->enabled = (alm_en & S3C2410_RTCALM_ALMEN) ? 1 : 0;
260
d4a48c2a 261 dev_dbg(dev, "read alarm %d, %04d.%02d.%02d %02d:%02d:%02d\n",
1add6781 262 alm_en,
30ffc40c 263 1900 + alm_tm->tm_year, alm_tm->tm_mon, alm_tm->tm_mday,
1add6781
BD
264 alm_tm->tm_hour, alm_tm->tm_min, alm_tm->tm_sec);
265
266
267 /* decode the alarm enable field */
268
269 if (alm_en & S3C2410_RTCALM_SECEN)
fe20ba70 270 alm_tm->tm_sec = bcd2bin(alm_tm->tm_sec);
1add6781 271 else
dd061d1a 272 alm_tm->tm_sec = -1;
1add6781
BD
273
274 if (alm_en & S3C2410_RTCALM_MINEN)
fe20ba70 275 alm_tm->tm_min = bcd2bin(alm_tm->tm_min);
1add6781 276 else
dd061d1a 277 alm_tm->tm_min = -1;
1add6781
BD
278
279 if (alm_en & S3C2410_RTCALM_HOUREN)
fe20ba70 280 alm_tm->tm_hour = bcd2bin(alm_tm->tm_hour);
1add6781 281 else
dd061d1a 282 alm_tm->tm_hour = -1;
1add6781
BD
283
284 if (alm_en & S3C2410_RTCALM_DAYEN)
fe20ba70 285 alm_tm->tm_mday = bcd2bin(alm_tm->tm_mday);
1add6781 286 else
dd061d1a 287 alm_tm->tm_mday = -1;
1add6781
BD
288
289 if (alm_en & S3C2410_RTCALM_MONEN) {
fe20ba70 290 alm_tm->tm_mon = bcd2bin(alm_tm->tm_mon);
1add6781
BD
291 alm_tm->tm_mon -= 1;
292 } else {
dd061d1a 293 alm_tm->tm_mon = -1;
1add6781
BD
294 }
295
296 if (alm_en & S3C2410_RTCALM_YEAREN)
fe20ba70 297 alm_tm->tm_year = bcd2bin(alm_tm->tm_year);
1add6781 298 else
dd061d1a 299 alm_tm->tm_year = -1;
1add6781 300
cefe4fbb 301 clk_disable(rtc_clk);
1add6781
BD
302 return 0;
303}
304
305static int s3c_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
306{
307 struct rtc_time *tm = &alrm->time;
9a654518 308 void __iomem *base = s3c_rtc_base;
1add6781
BD
309 unsigned int alrm_en;
310
cefe4fbb 311 clk_enable(rtc_clk);
d4a48c2a 312 dev_dbg(dev, "s3c_rtc_setalarm: %d, %04d.%02d.%02d %02d:%02d:%02d\n",
1add6781 313 alrm->enabled,
4e8896cd 314 1900 + tm->tm_year, tm->tm_mon + 1, tm->tm_mday,
30ffc40c 315 tm->tm_hour, tm->tm_min, tm->tm_sec);
1add6781 316
9a654518
BD
317 alrm_en = readb(base + S3C2410_RTCALM) & S3C2410_RTCALM_ALMEN;
318 writeb(0x00, base + S3C2410_RTCALM);
1add6781
BD
319
320 if (tm->tm_sec < 60 && tm->tm_sec >= 0) {
321 alrm_en |= S3C2410_RTCALM_SECEN;
fe20ba70 322 writeb(bin2bcd(tm->tm_sec), base + S3C2410_ALMSEC);
1add6781
BD
323 }
324
325 if (tm->tm_min < 60 && tm->tm_min >= 0) {
326 alrm_en |= S3C2410_RTCALM_MINEN;
fe20ba70 327 writeb(bin2bcd(tm->tm_min), base + S3C2410_ALMMIN);
1add6781
BD
328 }
329
330 if (tm->tm_hour < 24 && tm->tm_hour >= 0) {
331 alrm_en |= S3C2410_RTCALM_HOUREN;
fe20ba70 332 writeb(bin2bcd(tm->tm_hour), base + S3C2410_ALMHOUR);
1add6781
BD
333 }
334
d4a48c2a 335 dev_dbg(dev, "setting S3C2410_RTCALM to %08x\n", alrm_en);
1add6781 336
9a654518 337 writeb(alrm_en, base + S3C2410_RTCALM);
1add6781 338
2ec38a03 339 s3c_rtc_setaie(dev, alrm->enabled);
1add6781 340
cefe4fbb 341 clk_disable(rtc_clk);
1add6781
BD
342 return 0;
343}
344
1add6781
BD
345static int s3c_rtc_proc(struct device *dev, struct seq_file *seq)
346{
9f4123b7 347 unsigned int ticnt;
1add6781 348
cefe4fbb 349 clk_enable(rtc_clk);
9f4123b7 350 if (s3c_rtc_cpu_type == TYPE_S3C64XX) {
f61ae671 351 ticnt = readw(s3c_rtc_base + S3C2410_RTCCON);
9f4123b7
MC
352 ticnt &= S3C64XX_RTCCON_TICEN;
353 } else {
354 ticnt = readb(s3c_rtc_base + S3C2410_TICNT);
355 ticnt &= S3C2410_TICNT_ENABLE;
356 }
357
358 seq_printf(seq, "periodic_IRQ\t: %s\n", ticnt ? "yes" : "no");
cefe4fbb 359 clk_disable(rtc_clk);
1add6781
BD
360 return 0;
361}
362
ff8371ac 363static const struct rtc_class_ops s3c_rtcops = {
1add6781
BD
364 .read_time = s3c_rtc_gettime,
365 .set_time = s3c_rtc_settime,
366 .read_alarm = s3c_rtc_getalarm,
367 .set_alarm = s3c_rtc_setalarm,
e6eb524e
CY
368 .proc = s3c_rtc_proc,
369 .alarm_irq_enable = s3c_rtc_setaie,
1add6781
BD
370};
371
372static void s3c_rtc_enable(struct platform_device *pdev, int en)
373{
9a654518 374 void __iomem *base = s3c_rtc_base;
1add6781
BD
375 unsigned int tmp;
376
377 if (s3c_rtc_base == NULL)
378 return;
379
cefe4fbb 380 clk_enable(rtc_clk);
1add6781 381 if (!en) {
f61ae671 382 tmp = readw(base + S3C2410_RTCCON);
9f4123b7
MC
383 if (s3c_rtc_cpu_type == TYPE_S3C64XX)
384 tmp &= ~S3C64XX_RTCCON_TICEN;
385 tmp &= ~S3C2410_RTCCON_RTCEN;
f61ae671 386 writew(tmp, base + S3C2410_RTCCON);
9f4123b7 387
25c1a246 388 if (s3c_rtc_cpu_type != TYPE_S3C64XX) {
9f4123b7
MC
389 tmp = readb(base + S3C2410_TICNT);
390 tmp &= ~S3C2410_TICNT_ENABLE;
391 writeb(tmp, base + S3C2410_TICNT);
392 }
1add6781
BD
393 } else {
394 /* re-enable the device, and check it is ok */
395
f61ae671 396 if ((readw(base+S3C2410_RTCCON) & S3C2410_RTCCON_RTCEN) == 0) {
1add6781
BD
397 dev_info(&pdev->dev, "rtc disabled, re-enabling\n");
398
f61ae671
CY
399 tmp = readw(base + S3C2410_RTCCON);
400 writew(tmp | S3C2410_RTCCON_RTCEN,
401 base + S3C2410_RTCCON);
1add6781
BD
402 }
403
f61ae671 404 if ((readw(base + S3C2410_RTCCON) & S3C2410_RTCCON_CNTSEL)) {
1add6781
BD
405 dev_info(&pdev->dev, "removing RTCCON_CNTSEL\n");
406
f61ae671
CY
407 tmp = readw(base + S3C2410_RTCCON);
408 writew(tmp & ~S3C2410_RTCCON_CNTSEL,
409 base + S3C2410_RTCCON);
1add6781
BD
410 }
411
f61ae671 412 if ((readw(base + S3C2410_RTCCON) & S3C2410_RTCCON_CLKRST)) {
1add6781
BD
413 dev_info(&pdev->dev, "removing RTCCON_CLKRST\n");
414
f61ae671
CY
415 tmp = readw(base + S3C2410_RTCCON);
416 writew(tmp & ~S3C2410_RTCCON_CLKRST,
417 base + S3C2410_RTCCON);
1add6781
BD
418 }
419 }
cefe4fbb 420 clk_disable(rtc_clk);
1add6781
BD
421}
422
5a167f45 423static int s3c_rtc_remove(struct platform_device *dev)
1add6781 424{
1add6781 425 platform_set_drvdata(dev, NULL);
1add6781 426
2ec38a03 427 s3c_rtc_setaie(&dev->dev, 0);
1add6781 428
e48add8c
AD
429 rtc_clk = NULL;
430
1add6781
BD
431 return 0;
432}
433
d2524caa
HS
434static const struct of_device_id s3c_rtc_dt_match[];
435
436static inline int s3c_rtc_get_driver_data(struct platform_device *pdev)
437{
438#ifdef CONFIG_OF
c3cba928 439 struct s3c_rtc_drv_data *data;
d2524caa
HS
440 if (pdev->dev.of_node) {
441 const struct of_device_id *match;
442 match = of_match_node(s3c_rtc_dt_match, pdev->dev.of_node);
c3cba928
TB
443 data = (struct s3c_rtc_drv_data *) match->data;
444 return data->cpu_type;
d2524caa
HS
445 }
446#endif
447 return platform_get_device_id(pdev)->driver_data;
448}
449
5a167f45 450static int s3c_rtc_probe(struct platform_device *pdev)
1add6781
BD
451{
452 struct rtc_device *rtc;
e1df962e 453 struct rtc_time rtc_tm;
1add6781
BD
454 struct resource *res;
455 int ret;
25c1a246 456 int tmp;
1add6781 457
d4a48c2a 458 dev_dbg(&pdev->dev, "%s: probe=%p\n", __func__, pdev);
1add6781
BD
459
460 /* find the IRQs */
461
462 s3c_rtc_tickno = platform_get_irq(pdev, 1);
463 if (s3c_rtc_tickno < 0) {
464 dev_err(&pdev->dev, "no irq for rtc tick\n");
1ee8c0ca 465 return s3c_rtc_tickno;
1add6781
BD
466 }
467
468 s3c_rtc_alarmno = platform_get_irq(pdev, 0);
469 if (s3c_rtc_alarmno < 0) {
470 dev_err(&pdev->dev, "no irq for alarm\n");
1ee8c0ca 471 return s3c_rtc_alarmno;
1add6781
BD
472 }
473
d4a48c2a 474 dev_dbg(&pdev->dev, "s3c2410_rtc: tick irq %d, alarm irq %d\n",
1add6781
BD
475 s3c_rtc_tickno, s3c_rtc_alarmno);
476
477 /* get the memory region */
478
479 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
480 if (res == NULL) {
481 dev_err(&pdev->dev, "failed to get memory region resource\n");
482 return -ENOENT;
483 }
484
8cbce1e5
TR
485 s3c_rtc_base = devm_ioremap_resource(&pdev->dev, res);
486 if (IS_ERR(s3c_rtc_base))
487 return PTR_ERR(s3c_rtc_base);
1add6781 488
1b997329 489 rtc_clk = devm_clk_get(&pdev->dev, "rtc");
e48add8c
AD
490 if (IS_ERR(rtc_clk)) {
491 dev_err(&pdev->dev, "failed to find rtc clock source\n");
492 ret = PTR_ERR(rtc_clk);
493 rtc_clk = NULL;
1b997329 494 return ret;
e48add8c
AD
495 }
496
497 clk_enable(rtc_clk);
498
1add6781
BD
499 /* check to see if everything is setup correctly */
500
501 s3c_rtc_enable(pdev, 1);
502
d4a48c2a 503 dev_dbg(&pdev->dev, "s3c2410_rtc: RTCCON=%02x\n",
f61ae671 504 readw(s3c_rtc_base + S3C2410_RTCCON));
1add6781 505
51b7616e
YK
506 device_init_wakeup(&pdev->dev, 1);
507
1add6781
BD
508 /* register RTC and exit */
509
4c99c13a 510 rtc = devm_rtc_device_register(&pdev->dev, "s3c", &s3c_rtcops,
1add6781
BD
511 THIS_MODULE);
512
513 if (IS_ERR(rtc)) {
514 dev_err(&pdev->dev, "cannot attach rtc\n");
515 ret = PTR_ERR(rtc);
516 goto err_nortc;
517 }
518
d2524caa 519 s3c_rtc_cpu_type = s3c_rtc_get_driver_data(pdev);
eaa6e4dd 520
051fe54e
TK
521 /* Check RTC Time */
522
e1df962e 523 s3c_rtc_gettime(NULL, &rtc_tm);
051fe54e 524
e1df962e
CY
525 if (rtc_valid_tm(&rtc_tm)) {
526 rtc_tm.tm_year = 100;
527 rtc_tm.tm_mon = 0;
528 rtc_tm.tm_mday = 1;
529 rtc_tm.tm_hour = 0;
530 rtc_tm.tm_min = 0;
531 rtc_tm.tm_sec = 0;
532
533 s3c_rtc_settime(NULL, &rtc_tm);
534
535 dev_warn(&pdev->dev, "warning: invalid RTC value so initializing it\n");
051fe54e
TK
536 }
537
25c1a246 538 if (s3c_rtc_cpu_type != TYPE_S3C2410)
9f4123b7
MC
539 rtc->max_user_freq = 32768;
540 else
541 rtc->max_user_freq = 128;
542
25c1a246
HS
543 if (s3c_rtc_cpu_type == TYPE_S3C2416 || s3c_rtc_cpu_type == TYPE_S3C2443) {
544 tmp = readw(s3c_rtc_base + S3C2410_RTCCON);
545 tmp |= S3C2443_RTCCON_TICSEL;
546 writew(tmp, s3c_rtc_base + S3C2410_RTCCON);
547 }
548
1add6781 549 platform_set_drvdata(pdev, rtc);
e893de59
MC
550
551 s3c_rtc_setfreq(&pdev->dev, 1);
552
1b997329 553 ret = devm_request_irq(&pdev->dev, s3c_rtc_alarmno, s3c_rtc_alarmirq,
2f6e5f94 554 0, "s3c2410-rtc alarm", rtc);
62d17601
MH
555 if (ret) {
556 dev_err(&pdev->dev, "IRQ%d error %d\n", s3c_rtc_alarmno, ret);
557 goto err_alarm_irq;
558 }
559
1b997329 560 ret = devm_request_irq(&pdev->dev, s3c_rtc_tickno, s3c_rtc_tickirq,
2f6e5f94 561 0, "s3c2410-rtc tick", rtc);
62d17601
MH
562 if (ret) {
563 dev_err(&pdev->dev, "IRQ%d error %d\n", s3c_rtc_tickno, ret);
1b997329 564 goto err_alarm_irq;
62d17601
MH
565 }
566
cefe4fbb
DK
567 clk_disable(rtc_clk);
568
1add6781
BD
569 return 0;
570
62d17601
MH
571 err_alarm_irq:
572 platform_set_drvdata(pdev, NULL);
62d17601 573
1add6781
BD
574 err_nortc:
575 s3c_rtc_enable(pdev, 0);
e48add8c 576 clk_disable(rtc_clk);
1add6781 577
1add6781
BD
578 return ret;
579}
580
32e445aa 581#ifdef CONFIG_PM_SLEEP
1add6781
BD
582/* RTC Power management control */
583
9f4123b7 584static int ticnt_save, ticnt_en_save;
32e445aa 585static bool wake_en;
1add6781 586
32e445aa 587static int s3c_rtc_suspend(struct device *dev)
1add6781 588{
32e445aa
JH
589 struct platform_device *pdev = to_platform_device(dev);
590
cefe4fbb 591 clk_enable(rtc_clk);
1add6781 592 /* save TICNT for anyone using periodic interrupts */
9a654518 593 ticnt_save = readb(s3c_rtc_base + S3C2410_TICNT);
9f4123b7 594 if (s3c_rtc_cpu_type == TYPE_S3C64XX) {
f61ae671 595 ticnt_en_save = readw(s3c_rtc_base + S3C2410_RTCCON);
9f4123b7
MC
596 ticnt_en_save &= S3C64XX_RTCCON_TICEN;
597 }
1add6781 598 s3c_rtc_enable(pdev, 0);
f501ed52 599
32e445aa 600 if (device_may_wakeup(dev) && !wake_en) {
52cd4e5c
BD
601 if (enable_irq_wake(s3c_rtc_alarmno) == 0)
602 wake_en = true;
603 else
32e445aa 604 dev_err(dev, "enable_irq_wake failed\n");
52cd4e5c 605 }
cefe4fbb 606 clk_disable(rtc_clk);
f501ed52 607
1add6781
BD
608 return 0;
609}
610
32e445aa 611static int s3c_rtc_resume(struct device *dev)
1add6781 612{
32e445aa 613 struct platform_device *pdev = to_platform_device(dev);
9f4123b7
MC
614 unsigned int tmp;
615
cefe4fbb 616 clk_enable(rtc_clk);
1add6781 617 s3c_rtc_enable(pdev, 1);
9a654518 618 writeb(ticnt_save, s3c_rtc_base + S3C2410_TICNT);
9f4123b7 619 if (s3c_rtc_cpu_type == TYPE_S3C64XX && ticnt_en_save) {
f61ae671
CY
620 tmp = readw(s3c_rtc_base + S3C2410_RTCCON);
621 writew(tmp | ticnt_en_save, s3c_rtc_base + S3C2410_RTCCON);
9f4123b7 622 }
f501ed52 623
32e445aa 624 if (device_may_wakeup(dev) && wake_en) {
f501ed52 625 disable_irq_wake(s3c_rtc_alarmno);
52cd4e5c
BD
626 wake_en = false;
627 }
cefe4fbb 628 clk_disable(rtc_clk);
f501ed52 629
1add6781
BD
630 return 0;
631}
1add6781
BD
632#endif
633
32e445aa
JH
634static SIMPLE_DEV_PM_OPS(s3c_rtc_pm_ops, s3c_rtc_suspend, s3c_rtc_resume);
635
ecb41a77 636#ifdef CONFIG_OF
c3cba928
TB
637static struct s3c_rtc_drv_data s3c_rtc_drv_data_array[] = {
638 [TYPE_S3C2410] = { TYPE_S3C2410 },
639 [TYPE_S3C2416] = { TYPE_S3C2416 },
640 [TYPE_S3C2443] = { TYPE_S3C2443 },
641 [TYPE_S3C64XX] = { TYPE_S3C64XX },
642};
643
39ce4084 644static const struct of_device_id s3c_rtc_dt_match[] = {
d2524caa 645 {
cd1e6f9e 646 .compatible = "samsung,s3c2410-rtc",
c3cba928 647 .data = &s3c_rtc_drv_data_array[TYPE_S3C2410],
25c1a246 648 }, {
cd1e6f9e 649 .compatible = "samsung,s3c2416-rtc",
c3cba928 650 .data = &s3c_rtc_drv_data_array[TYPE_S3C2416],
25c1a246 651 }, {
cd1e6f9e 652 .compatible = "samsung,s3c2443-rtc",
c3cba928 653 .data = &s3c_rtc_drv_data_array[TYPE_S3C2443],
d2524caa 654 }, {
cd1e6f9e 655 .compatible = "samsung,s3c6410-rtc",
c3cba928 656 .data = &s3c_rtc_drv_data_array[TYPE_S3C64XX],
d2524caa 657 },
39ce4084
TA
658 {},
659};
660MODULE_DEVICE_TABLE(of, s3c_rtc_dt_match);
39ce4084
TA
661#endif
662
9f4123b7
MC
663static struct platform_device_id s3c_rtc_driver_ids[] = {
664 {
665 .name = "s3c2410-rtc",
666 .driver_data = TYPE_S3C2410,
25c1a246
HS
667 }, {
668 .name = "s3c2416-rtc",
669 .driver_data = TYPE_S3C2416,
670 }, {
671 .name = "s3c2443-rtc",
672 .driver_data = TYPE_S3C2443,
9f4123b7
MC
673 }, {
674 .name = "s3c64xx-rtc",
675 .driver_data = TYPE_S3C64XX,
676 },
677 { }
678};
679
680MODULE_DEVICE_TABLE(platform, s3c_rtc_driver_ids);
681
682static struct platform_driver s3c_rtc_driver = {
1add6781 683 .probe = s3c_rtc_probe,
5a167f45 684 .remove = s3c_rtc_remove,
9f4123b7 685 .id_table = s3c_rtc_driver_ids,
1add6781 686 .driver = {
9f4123b7 687 .name = "s3c-rtc",
1add6781 688 .owner = THIS_MODULE,
32e445aa 689 .pm = &s3c_rtc_pm_ops,
04a373fd 690 .of_match_table = of_match_ptr(s3c_rtc_dt_match),
1add6781
BD
691 },
692};
693
0c4eae66 694module_platform_driver(s3c_rtc_driver);
1add6781
BD
695
696MODULE_DESCRIPTION("Samsung S3C RTC Driver");
697MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
698MODULE_LICENSE("GPL");
ad28a07b 699MODULE_ALIAS("platform:s3c2410-rtc");