Commit | Line | Data |
---|---|---|
8ecf6c54 MA |
1 | /* |
2 | * DaVinci Power Management and Real Time Clock Driver for TI platforms | |
3 | * | |
4 | * Copyright (C) 2009 Texas Instruments, Inc | |
5 | * | |
6 | * Author: Miguel Aguilar <miguel.aguilar@ridgerun.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/ioport.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/spinlock.h> | |
28 | #include <linux/rtc.h> | |
29 | #include <linux/bcd.h> | |
30 | #include <linux/platform_device.h> | |
31 | #include <linux/io.h> | |
32 | ||
33 | /* | |
34 | * The DaVinci RTC is a simple RTC with the following | |
35 | * Sec: 0 - 59 : BCD count | |
36 | * Min: 0 - 59 : BCD count | |
37 | * Hour: 0 - 23 : BCD count | |
38 | * Day: 0 - 0x7FFF(32767) : Binary count ( Over 89 years ) | |
39 | */ | |
40 | ||
41 | /* PRTC interface registers */ | |
42 | #define DAVINCI_PRTCIF_PID 0x00 | |
43 | #define PRTCIF_CTLR 0x04 | |
44 | #define PRTCIF_LDATA 0x08 | |
45 | #define PRTCIF_UDATA 0x0C | |
46 | #define PRTCIF_INTEN 0x10 | |
47 | #define PRTCIF_INTFLG 0x14 | |
48 | ||
49 | /* PRTCIF_CTLR bit fields */ | |
50 | #define PRTCIF_CTLR_BUSY BIT(31) | |
51 | #define PRTCIF_CTLR_SIZE BIT(25) | |
52 | #define PRTCIF_CTLR_DIR BIT(24) | |
53 | #define PRTCIF_CTLR_BENU_MSB BIT(23) | |
54 | #define PRTCIF_CTLR_BENU_3RD_BYTE BIT(22) | |
55 | #define PRTCIF_CTLR_BENU_2ND_BYTE BIT(21) | |
56 | #define PRTCIF_CTLR_BENU_LSB BIT(20) | |
57 | #define PRTCIF_CTLR_BENU_MASK (0x00F00000) | |
58 | #define PRTCIF_CTLR_BENL_MSB BIT(19) | |
59 | #define PRTCIF_CTLR_BENL_3RD_BYTE BIT(18) | |
60 | #define PRTCIF_CTLR_BENL_2ND_BYTE BIT(17) | |
61 | #define PRTCIF_CTLR_BENL_LSB BIT(16) | |
62 | #define PRTCIF_CTLR_BENL_MASK (0x000F0000) | |
63 | ||
64 | /* PRTCIF_INTEN bit fields */ | |
65 | #define PRTCIF_INTEN_RTCSS BIT(1) | |
66 | #define PRTCIF_INTEN_RTCIF BIT(0) | |
67 | #define PRTCIF_INTEN_MASK (PRTCIF_INTEN_RTCSS \ | |
68 | | PRTCIF_INTEN_RTCIF) | |
69 | ||
70 | /* PRTCIF_INTFLG bit fields */ | |
71 | #define PRTCIF_INTFLG_RTCSS BIT(1) | |
72 | #define PRTCIF_INTFLG_RTCIF BIT(0) | |
73 | #define PRTCIF_INTFLG_MASK (PRTCIF_INTFLG_RTCSS \ | |
74 | | PRTCIF_INTFLG_RTCIF) | |
75 | ||
76 | /* PRTC subsystem registers */ | |
77 | #define PRTCSS_RTC_INTC_EXTENA1 (0x0C) | |
78 | #define PRTCSS_RTC_CTRL (0x10) | |
79 | #define PRTCSS_RTC_WDT (0x11) | |
80 | #define PRTCSS_RTC_TMR0 (0x12) | |
81 | #define PRTCSS_RTC_TMR1 (0x13) | |
82 | #define PRTCSS_RTC_CCTRL (0x14) | |
83 | #define PRTCSS_RTC_SEC (0x15) | |
84 | #define PRTCSS_RTC_MIN (0x16) | |
85 | #define PRTCSS_RTC_HOUR (0x17) | |
86 | #define PRTCSS_RTC_DAY0 (0x18) | |
87 | #define PRTCSS_RTC_DAY1 (0x19) | |
88 | #define PRTCSS_RTC_AMIN (0x1A) | |
89 | #define PRTCSS_RTC_AHOUR (0x1B) | |
90 | #define PRTCSS_RTC_ADAY0 (0x1C) | |
91 | #define PRTCSS_RTC_ADAY1 (0x1D) | |
92 | #define PRTCSS_RTC_CLKC_CNT (0x20) | |
93 | ||
94 | /* PRTCSS_RTC_INTC_EXTENA1 */ | |
95 | #define PRTCSS_RTC_INTC_EXTENA1_MASK (0x07) | |
96 | ||
97 | /* PRTCSS_RTC_CTRL bit fields */ | |
98 | #define PRTCSS_RTC_CTRL_WDTBUS BIT(7) | |
99 | #define PRTCSS_RTC_CTRL_WEN BIT(6) | |
100 | #define PRTCSS_RTC_CTRL_WDRT BIT(5) | |
101 | #define PRTCSS_RTC_CTRL_WDTFLG BIT(4) | |
102 | #define PRTCSS_RTC_CTRL_TE BIT(3) | |
103 | #define PRTCSS_RTC_CTRL_TIEN BIT(2) | |
104 | #define PRTCSS_RTC_CTRL_TMRFLG BIT(1) | |
105 | #define PRTCSS_RTC_CTRL_TMMD BIT(0) | |
106 | ||
107 | /* PRTCSS_RTC_CCTRL bit fields */ | |
108 | #define PRTCSS_RTC_CCTRL_CALBUSY BIT(7) | |
109 | #define PRTCSS_RTC_CCTRL_DAEN BIT(5) | |
110 | #define PRTCSS_RTC_CCTRL_HAEN BIT(4) | |
111 | #define PRTCSS_RTC_CCTRL_MAEN BIT(3) | |
112 | #define PRTCSS_RTC_CCTRL_ALMFLG BIT(2) | |
113 | #define PRTCSS_RTC_CCTRL_AIEN BIT(1) | |
114 | #define PRTCSS_RTC_CCTRL_CAEN BIT(0) | |
115 | ||
116 | static DEFINE_SPINLOCK(davinci_rtc_lock); | |
117 | ||
118 | struct davinci_rtc { | |
119 | struct rtc_device *rtc; | |
120 | void __iomem *base; | |
121 | resource_size_t pbase; | |
122 | size_t base_size; | |
123 | int irq; | |
124 | }; | |
125 | ||
126 | static inline void rtcif_write(struct davinci_rtc *davinci_rtc, | |
127 | u32 val, u32 addr) | |
128 | { | |
129 | writel(val, davinci_rtc->base + addr); | |
130 | } | |
131 | ||
132 | static inline u32 rtcif_read(struct davinci_rtc *davinci_rtc, u32 addr) | |
133 | { | |
134 | return readl(davinci_rtc->base + addr); | |
135 | } | |
136 | ||
137 | static inline void rtcif_wait(struct davinci_rtc *davinci_rtc) | |
138 | { | |
139 | while (rtcif_read(davinci_rtc, PRTCIF_CTLR) & PRTCIF_CTLR_BUSY) | |
140 | cpu_relax(); | |
141 | } | |
142 | ||
143 | static inline void rtcss_write(struct davinci_rtc *davinci_rtc, | |
144 | unsigned long val, u8 addr) | |
145 | { | |
146 | rtcif_wait(davinci_rtc); | |
147 | ||
148 | rtcif_write(davinci_rtc, PRTCIF_CTLR_BENL_LSB | addr, PRTCIF_CTLR); | |
149 | rtcif_write(davinci_rtc, val, PRTCIF_LDATA); | |
150 | ||
151 | rtcif_wait(davinci_rtc); | |
152 | } | |
153 | ||
154 | static inline u8 rtcss_read(struct davinci_rtc *davinci_rtc, u8 addr) | |
155 | { | |
156 | rtcif_wait(davinci_rtc); | |
157 | ||
158 | rtcif_write(davinci_rtc, PRTCIF_CTLR_DIR | PRTCIF_CTLR_BENL_LSB | addr, | |
159 | PRTCIF_CTLR); | |
160 | ||
161 | rtcif_wait(davinci_rtc); | |
162 | ||
163 | return rtcif_read(davinci_rtc, PRTCIF_LDATA); | |
164 | } | |
165 | ||
166 | static inline void davinci_rtcss_calendar_wait(struct davinci_rtc *davinci_rtc) | |
167 | { | |
168 | while (rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL) & | |
169 | PRTCSS_RTC_CCTRL_CALBUSY) | |
170 | cpu_relax(); | |
171 | } | |
172 | ||
173 | static irqreturn_t davinci_rtc_interrupt(int irq, void *class_dev) | |
174 | { | |
175 | struct davinci_rtc *davinci_rtc = class_dev; | |
176 | unsigned long events = 0; | |
177 | u32 irq_flg; | |
178 | u8 alm_irq, tmr_irq; | |
179 | u8 rtc_ctrl, rtc_cctrl; | |
180 | int ret = IRQ_NONE; | |
181 | ||
182 | irq_flg = rtcif_read(davinci_rtc, PRTCIF_INTFLG) & | |
183 | PRTCIF_INTFLG_RTCSS; | |
184 | ||
185 | alm_irq = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL) & | |
186 | PRTCSS_RTC_CCTRL_ALMFLG; | |
187 | ||
188 | tmr_irq = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL) & | |
189 | PRTCSS_RTC_CTRL_TMRFLG; | |
190 | ||
191 | if (irq_flg) { | |
192 | if (alm_irq) { | |
193 | events |= RTC_IRQF | RTC_AF; | |
194 | rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL); | |
195 | rtc_cctrl |= PRTCSS_RTC_CCTRL_ALMFLG; | |
196 | rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL); | |
197 | } else if (tmr_irq) { | |
198 | events |= RTC_IRQF | RTC_PF; | |
199 | rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL); | |
200 | rtc_ctrl |= PRTCSS_RTC_CTRL_TMRFLG; | |
201 | rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL); | |
202 | } | |
203 | ||
204 | rtcif_write(davinci_rtc, PRTCIF_INTFLG_RTCSS, | |
205 | PRTCIF_INTFLG); | |
206 | rtc_update_irq(davinci_rtc->rtc, 1, events); | |
207 | ||
208 | ret = IRQ_HANDLED; | |
209 | } | |
210 | ||
211 | return ret; | |
212 | } | |
213 | ||
214 | static int | |
215 | davinci_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg) | |
216 | { | |
217 | struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev); | |
218 | u8 rtc_ctrl; | |
219 | unsigned long flags; | |
220 | int ret = 0; | |
221 | ||
222 | spin_lock_irqsave(&davinci_rtc_lock, flags); | |
223 | ||
224 | rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL); | |
225 | ||
226 | switch (cmd) { | |
227 | case RTC_WIE_ON: | |
228 | rtc_ctrl |= PRTCSS_RTC_CTRL_WEN | PRTCSS_RTC_CTRL_WDTFLG; | |
229 | break; | |
230 | case RTC_WIE_OFF: | |
231 | rtc_ctrl &= ~PRTCSS_RTC_CTRL_WEN; | |
232 | break; | |
233 | case RTC_UIE_OFF: | |
234 | case RTC_UIE_ON: | |
235 | ret = -ENOTTY; | |
236 | break; | |
237 | default: | |
238 | ret = -ENOIOCTLCMD; | |
239 | } | |
240 | ||
241 | rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL); | |
242 | ||
243 | spin_unlock_irqrestore(&davinci_rtc_lock, flags); | |
244 | ||
245 | return ret; | |
246 | } | |
247 | ||
248 | static int convertfromdays(u16 days, struct rtc_time *tm) | |
249 | { | |
250 | int tmp_days, year, mon; | |
251 | ||
252 | for (year = 2000;; year++) { | |
253 | tmp_days = rtc_year_days(1, 12, year); | |
254 | if (days >= tmp_days) | |
255 | days -= tmp_days; | |
256 | else { | |
257 | for (mon = 0;; mon++) { | |
258 | tmp_days = rtc_month_days(mon, year); | |
259 | if (days >= tmp_days) { | |
260 | days -= tmp_days; | |
261 | } else { | |
262 | tm->tm_year = year - 1900; | |
263 | tm->tm_mon = mon; | |
264 | tm->tm_mday = days + 1; | |
265 | break; | |
266 | } | |
267 | } | |
268 | break; | |
269 | } | |
270 | } | |
271 | return 0; | |
272 | } | |
273 | ||
274 | static int convert2days(u16 *days, struct rtc_time *tm) | |
275 | { | |
276 | int i; | |
277 | *days = 0; | |
278 | ||
279 | /* epoch == 1900 */ | |
280 | if (tm->tm_year < 100 || tm->tm_year > 199) | |
281 | return -EINVAL; | |
282 | ||
283 | for (i = 2000; i < 1900 + tm->tm_year; i++) | |
284 | *days += rtc_year_days(1, 12, i); | |
285 | ||
286 | *days += rtc_year_days(tm->tm_mday, tm->tm_mon, 1900 + tm->tm_year); | |
287 | ||
288 | return 0; | |
289 | } | |
290 | ||
291 | static int davinci_rtc_read_time(struct device *dev, struct rtc_time *tm) | |
292 | { | |
293 | struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev); | |
294 | u16 days = 0; | |
295 | u8 day0, day1; | |
296 | unsigned long flags; | |
297 | ||
298 | spin_lock_irqsave(&davinci_rtc_lock, flags); | |
299 | ||
300 | davinci_rtcss_calendar_wait(davinci_rtc); | |
301 | tm->tm_sec = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_SEC)); | |
302 | ||
303 | davinci_rtcss_calendar_wait(davinci_rtc); | |
304 | tm->tm_min = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_MIN)); | |
305 | ||
306 | davinci_rtcss_calendar_wait(davinci_rtc); | |
307 | tm->tm_hour = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_HOUR)); | |
308 | ||
309 | davinci_rtcss_calendar_wait(davinci_rtc); | |
310 | day0 = rtcss_read(davinci_rtc, PRTCSS_RTC_DAY0); | |
311 | ||
312 | davinci_rtcss_calendar_wait(davinci_rtc); | |
313 | day1 = rtcss_read(davinci_rtc, PRTCSS_RTC_DAY1); | |
314 | ||
315 | spin_unlock_irqrestore(&davinci_rtc_lock, flags); | |
316 | ||
317 | days |= day1; | |
318 | days <<= 8; | |
319 | days |= day0; | |
320 | ||
321 | if (convertfromdays(days, tm) < 0) | |
322 | return -EINVAL; | |
323 | ||
324 | return 0; | |
325 | } | |
326 | ||
327 | static int davinci_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
328 | { | |
329 | struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev); | |
330 | u16 days; | |
331 | u8 rtc_cctrl; | |
332 | unsigned long flags; | |
333 | ||
334 | if (convert2days(&days, tm) < 0) | |
335 | return -EINVAL; | |
336 | ||
337 | spin_lock_irqsave(&davinci_rtc_lock, flags); | |
338 | ||
339 | davinci_rtcss_calendar_wait(davinci_rtc); | |
340 | rtcss_write(davinci_rtc, bin2bcd(tm->tm_sec), PRTCSS_RTC_SEC); | |
341 | ||
342 | davinci_rtcss_calendar_wait(davinci_rtc); | |
343 | rtcss_write(davinci_rtc, bin2bcd(tm->tm_min), PRTCSS_RTC_MIN); | |
344 | ||
345 | davinci_rtcss_calendar_wait(davinci_rtc); | |
346 | rtcss_write(davinci_rtc, bin2bcd(tm->tm_hour), PRTCSS_RTC_HOUR); | |
347 | ||
348 | davinci_rtcss_calendar_wait(davinci_rtc); | |
349 | rtcss_write(davinci_rtc, days & 0xFF, PRTCSS_RTC_DAY0); | |
350 | ||
351 | davinci_rtcss_calendar_wait(davinci_rtc); | |
352 | rtcss_write(davinci_rtc, (days & 0xFF00) >> 8, PRTCSS_RTC_DAY1); | |
353 | ||
354 | rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL); | |
355 | rtc_cctrl |= PRTCSS_RTC_CCTRL_CAEN; | |
356 | rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL); | |
357 | ||
358 | spin_unlock_irqrestore(&davinci_rtc_lock, flags); | |
359 | ||
360 | return 0; | |
361 | } | |
362 | ||
363 | static int davinci_rtc_alarm_irq_enable(struct device *dev, | |
364 | unsigned int enabled) | |
365 | { | |
366 | struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev); | |
367 | unsigned long flags; | |
368 | u8 rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL); | |
369 | ||
370 | spin_lock_irqsave(&davinci_rtc_lock, flags); | |
371 | ||
372 | if (enabled) | |
373 | rtc_cctrl |= PRTCSS_RTC_CCTRL_DAEN | | |
374 | PRTCSS_RTC_CCTRL_HAEN | | |
375 | PRTCSS_RTC_CCTRL_MAEN | | |
376 | PRTCSS_RTC_CCTRL_ALMFLG | | |
377 | PRTCSS_RTC_CCTRL_AIEN; | |
378 | else | |
379 | rtc_cctrl &= ~PRTCSS_RTC_CCTRL_AIEN; | |
380 | ||
381 | davinci_rtcss_calendar_wait(davinci_rtc); | |
382 | rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL); | |
383 | ||
384 | spin_unlock_irqrestore(&davinci_rtc_lock, flags); | |
385 | ||
386 | return 0; | |
387 | } | |
388 | ||
389 | static int davinci_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm) | |
390 | { | |
391 | struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev); | |
392 | u16 days = 0; | |
393 | u8 day0, day1; | |
394 | unsigned long flags; | |
395 | ||
396 | spin_lock_irqsave(&davinci_rtc_lock, flags); | |
397 | ||
398 | davinci_rtcss_calendar_wait(davinci_rtc); | |
399 | alm->time.tm_min = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_AMIN)); | |
400 | ||
401 | davinci_rtcss_calendar_wait(davinci_rtc); | |
402 | alm->time.tm_hour = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_AHOUR)); | |
403 | ||
404 | davinci_rtcss_calendar_wait(davinci_rtc); | |
405 | day0 = rtcss_read(davinci_rtc, PRTCSS_RTC_ADAY0); | |
406 | ||
407 | davinci_rtcss_calendar_wait(davinci_rtc); | |
408 | day1 = rtcss_read(davinci_rtc, PRTCSS_RTC_ADAY1); | |
409 | ||
410 | spin_unlock_irqrestore(&davinci_rtc_lock, flags); | |
411 | days |= day1; | |
412 | days <<= 8; | |
413 | days |= day0; | |
414 | ||
415 | if (convertfromdays(days, &alm->time) < 0) | |
416 | return -EINVAL; | |
417 | ||
418 | alm->pending = !!(rtcss_read(davinci_rtc, | |
419 | PRTCSS_RTC_CCTRL) & | |
420 | PRTCSS_RTC_CCTRL_AIEN); | |
421 | alm->enabled = alm->pending && device_may_wakeup(dev); | |
422 | ||
423 | return 0; | |
424 | } | |
425 | ||
426 | static int davinci_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm) | |
427 | { | |
428 | struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev); | |
429 | unsigned long flags; | |
430 | u16 days; | |
431 | ||
432 | if (alm->time.tm_mday <= 0 && alm->time.tm_mon < 0 | |
433 | && alm->time.tm_year < 0) { | |
434 | struct rtc_time tm; | |
435 | unsigned long now, then; | |
436 | ||
437 | davinci_rtc_read_time(dev, &tm); | |
438 | rtc_tm_to_time(&tm, &now); | |
439 | ||
440 | alm->time.tm_mday = tm.tm_mday; | |
441 | alm->time.tm_mon = tm.tm_mon; | |
442 | alm->time.tm_year = tm.tm_year; | |
443 | rtc_tm_to_time(&alm->time, &then); | |
444 | ||
445 | if (then < now) { | |
446 | rtc_time_to_tm(now + 24 * 60 * 60, &tm); | |
447 | alm->time.tm_mday = tm.tm_mday; | |
448 | alm->time.tm_mon = tm.tm_mon; | |
449 | alm->time.tm_year = tm.tm_year; | |
450 | } | |
451 | } | |
452 | ||
453 | if (convert2days(&days, &alm->time) < 0) | |
454 | return -EINVAL; | |
455 | ||
456 | spin_lock_irqsave(&davinci_rtc_lock, flags); | |
457 | ||
458 | davinci_rtcss_calendar_wait(davinci_rtc); | |
459 | rtcss_write(davinci_rtc, bin2bcd(alm->time.tm_min), PRTCSS_RTC_AMIN); | |
460 | ||
461 | davinci_rtcss_calendar_wait(davinci_rtc); | |
462 | rtcss_write(davinci_rtc, bin2bcd(alm->time.tm_hour), PRTCSS_RTC_AHOUR); | |
463 | ||
464 | davinci_rtcss_calendar_wait(davinci_rtc); | |
465 | rtcss_write(davinci_rtc, days & 0xFF, PRTCSS_RTC_ADAY0); | |
466 | ||
467 | davinci_rtcss_calendar_wait(davinci_rtc); | |
468 | rtcss_write(davinci_rtc, (days & 0xFF00) >> 8, PRTCSS_RTC_ADAY1); | |
469 | ||
470 | spin_unlock_irqrestore(&davinci_rtc_lock, flags); | |
471 | ||
472 | return 0; | |
473 | } | |
474 | ||
475 | static int davinci_rtc_irq_set_state(struct device *dev, int enabled) | |
476 | { | |
477 | struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev); | |
478 | unsigned long flags; | |
479 | u8 rtc_ctrl; | |
480 | ||
481 | spin_lock_irqsave(&davinci_rtc_lock, flags); | |
482 | ||
483 | rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL); | |
484 | ||
485 | if (enabled) { | |
486 | while (rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL) | |
487 | & PRTCSS_RTC_CTRL_WDTBUS) | |
488 | cpu_relax(); | |
489 | ||
490 | rtc_ctrl |= PRTCSS_RTC_CTRL_TE; | |
491 | rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL); | |
492 | ||
493 | rtcss_write(davinci_rtc, 0x0, PRTCSS_RTC_CLKC_CNT); | |
494 | ||
495 | rtc_ctrl |= PRTCSS_RTC_CTRL_TIEN | | |
496 | PRTCSS_RTC_CTRL_TMMD | | |
497 | PRTCSS_RTC_CTRL_TMRFLG; | |
498 | } else | |
499 | rtc_ctrl &= ~PRTCSS_RTC_CTRL_TIEN; | |
500 | ||
501 | rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL); | |
502 | ||
503 | spin_unlock_irqrestore(&davinci_rtc_lock, flags); | |
504 | ||
505 | return 0; | |
506 | } | |
507 | ||
508 | static int davinci_rtc_irq_set_freq(struct device *dev, int freq) | |
509 | { | |
510 | struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev); | |
511 | unsigned long flags; | |
512 | u16 tmr_counter = (0x8000 >> (ffs(freq) - 1)); | |
513 | ||
514 | spin_lock_irqsave(&davinci_rtc_lock, flags); | |
515 | ||
516 | rtcss_write(davinci_rtc, tmr_counter & 0xFF, PRTCSS_RTC_TMR0); | |
517 | rtcss_write(davinci_rtc, (tmr_counter & 0xFF00) >> 8, PRTCSS_RTC_TMR1); | |
518 | ||
519 | spin_unlock_irqrestore(&davinci_rtc_lock, flags); | |
520 | ||
521 | return 0; | |
522 | } | |
523 | ||
524 | static struct rtc_class_ops davinci_rtc_ops = { | |
525 | .ioctl = davinci_rtc_ioctl, | |
526 | .read_time = davinci_rtc_read_time, | |
527 | .set_time = davinci_rtc_set_time, | |
528 | .alarm_irq_enable = davinci_rtc_alarm_irq_enable, | |
529 | .read_alarm = davinci_rtc_read_alarm, | |
530 | .set_alarm = davinci_rtc_set_alarm, | |
531 | .irq_set_state = davinci_rtc_irq_set_state, | |
532 | .irq_set_freq = davinci_rtc_irq_set_freq, | |
533 | }; | |
534 | ||
535 | static int __init davinci_rtc_probe(struct platform_device *pdev) | |
536 | { | |
537 | struct device *dev = &pdev->dev; | |
538 | struct davinci_rtc *davinci_rtc; | |
539 | struct resource *res, *mem; | |
540 | int ret = 0; | |
541 | ||
542 | davinci_rtc = kzalloc(sizeof(struct davinci_rtc), GFP_KERNEL); | |
543 | if (!davinci_rtc) { | |
544 | dev_dbg(dev, "could not allocate memory for private data\n"); | |
545 | return -ENOMEM; | |
546 | } | |
547 | ||
548 | davinci_rtc->irq = platform_get_irq(pdev, 0); | |
549 | if (davinci_rtc->irq < 0) { | |
550 | dev_err(dev, "no RTC irq\n"); | |
551 | ret = davinci_rtc->irq; | |
552 | goto fail1; | |
553 | } | |
554 | ||
555 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
556 | if (!res) { | |
557 | dev_err(dev, "no mem resource\n"); | |
558 | ret = -EINVAL; | |
559 | goto fail1; | |
560 | } | |
561 | ||
562 | davinci_rtc->pbase = res->start; | |
563 | davinci_rtc->base_size = resource_size(res); | |
564 | ||
565 | mem = request_mem_region(davinci_rtc->pbase, davinci_rtc->base_size, | |
566 | pdev->name); | |
567 | if (!mem) { | |
568 | dev_err(dev, "RTC registers at %08x are not free\n", | |
569 | davinci_rtc->pbase); | |
570 | ret = -EBUSY; | |
571 | goto fail1; | |
572 | } | |
573 | ||
574 | davinci_rtc->base = ioremap(davinci_rtc->pbase, davinci_rtc->base_size); | |
575 | if (!davinci_rtc->base) { | |
576 | dev_err(dev, "unable to ioremap MEM resource\n"); | |
577 | ret = -ENOMEM; | |
578 | goto fail2; | |
579 | } | |
580 | ||
581 | davinci_rtc->rtc = rtc_device_register(pdev->name, &pdev->dev, | |
582 | &davinci_rtc_ops, THIS_MODULE); | |
583 | if (IS_ERR(davinci_rtc->rtc)) { | |
584 | dev_err(dev, "unable to register RTC device, err %ld\n", | |
585 | PTR_ERR(davinci_rtc->rtc)); | |
586 | goto fail3; | |
587 | } | |
588 | ||
589 | rtcif_write(davinci_rtc, PRTCIF_INTFLG_RTCSS, PRTCIF_INTFLG); | |
590 | rtcif_write(davinci_rtc, 0, PRTCIF_INTEN); | |
591 | rtcss_write(davinci_rtc, 0, PRTCSS_RTC_INTC_EXTENA1); | |
592 | ||
593 | rtcss_write(davinci_rtc, 0, PRTCSS_RTC_CTRL); | |
594 | rtcss_write(davinci_rtc, 0, PRTCSS_RTC_CCTRL); | |
595 | ||
596 | ret = request_irq(davinci_rtc->irq, davinci_rtc_interrupt, | |
597 | IRQF_DISABLED, "davinci_rtc", davinci_rtc); | |
598 | if (ret < 0) { | |
599 | dev_err(dev, "unable to register davinci RTC interrupt\n"); | |
600 | goto fail4; | |
601 | } | |
602 | ||
603 | /* Enable interrupts */ | |
604 | rtcif_write(davinci_rtc, PRTCIF_INTEN_RTCSS, PRTCIF_INTEN); | |
605 | rtcss_write(davinci_rtc, PRTCSS_RTC_INTC_EXTENA1_MASK, | |
606 | PRTCSS_RTC_INTC_EXTENA1); | |
607 | ||
608 | rtcss_write(davinci_rtc, PRTCSS_RTC_CCTRL_CAEN, PRTCSS_RTC_CCTRL); | |
609 | ||
610 | platform_set_drvdata(pdev, davinci_rtc); | |
611 | ||
612 | device_init_wakeup(&pdev->dev, 0); | |
613 | ||
614 | return 0; | |
615 | ||
616 | fail4: | |
617 | rtc_device_unregister(davinci_rtc->rtc); | |
618 | fail3: | |
619 | iounmap(davinci_rtc->base); | |
620 | fail2: | |
621 | release_mem_region(davinci_rtc->pbase, davinci_rtc->base_size); | |
622 | fail1: | |
623 | kfree(davinci_rtc); | |
624 | ||
625 | return ret; | |
626 | } | |
627 | ||
628 | static int __devexit davinci_rtc_remove(struct platform_device *pdev) | |
629 | { | |
630 | struct davinci_rtc *davinci_rtc = platform_get_drvdata(pdev); | |
631 | ||
632 | device_init_wakeup(&pdev->dev, 0); | |
633 | ||
634 | rtcif_write(davinci_rtc, 0, PRTCIF_INTEN); | |
635 | ||
636 | free_irq(davinci_rtc->irq, davinci_rtc); | |
637 | ||
638 | rtc_device_unregister(davinci_rtc->rtc); | |
639 | ||
640 | iounmap(davinci_rtc->base); | |
641 | release_mem_region(davinci_rtc->pbase, davinci_rtc->base_size); | |
642 | ||
643 | platform_set_drvdata(pdev, NULL); | |
644 | ||
645 | kfree(davinci_rtc); | |
646 | ||
647 | return 0; | |
648 | } | |
649 | ||
650 | static struct platform_driver davinci_rtc_driver = { | |
651 | .probe = davinci_rtc_probe, | |
652 | .remove = __devexit_p(davinci_rtc_remove), | |
653 | .driver = { | |
654 | .name = "rtc_davinci", | |
655 | .owner = THIS_MODULE, | |
656 | }, | |
657 | }; | |
658 | ||
659 | static int __init rtc_init(void) | |
660 | { | |
661 | return platform_driver_probe(&davinci_rtc_driver, davinci_rtc_probe); | |
662 | } | |
663 | module_init(rtc_init); | |
664 | ||
665 | static void __exit rtc_exit(void) | |
666 | { | |
667 | platform_driver_unregister(&davinci_rtc_driver); | |
668 | } | |
669 | module_exit(rtc_exit); | |
670 | ||
671 | MODULE_AUTHOR("Miguel Aguilar <miguel.aguilar@ridgerun.com>"); | |
672 | MODULE_DESCRIPTION("Texas Instruments DaVinci PRTC Driver"); | |
673 | MODULE_LICENSE("GPL"); |