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da09155a MB |
1 | /* |
2 | * wm8350.c -- Voltage and current regulation for the Wolfson WM8350 PMIC | |
3 | * | |
4 | * Copyright 2007, 2008 Wolfson Microelectronics PLC. | |
5 | * | |
6 | * Author: Liam Girdwood | |
7 | * linux@wolfsonmicro.com | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License as published by the | |
11 | * Free Software Foundation; either version 2 of the License, or (at your | |
12 | * option) any later version. | |
13 | */ | |
14 | ||
15 | #include <linux/module.h> | |
16 | #include <linux/moduleparam.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/bitops.h> | |
19 | #include <linux/err.h> | |
20 | #include <linux/i2c.h> | |
21 | #include <linux/mfd/wm8350/core.h> | |
22 | #include <linux/mfd/wm8350/pmic.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/regulator/driver.h> | |
25 | #include <linux/regulator/machine.h> | |
26 | ||
221a7c7c MB |
27 | /* Maximum value possible for VSEL */ |
28 | #define WM8350_DCDC_MAX_VSEL 0x66 | |
29 | ||
da09155a MB |
30 | /* Microamps */ |
31 | static const int isink_cur[] = { | |
32 | 4, | |
33 | 5, | |
34 | 6, | |
35 | 7, | |
36 | 8, | |
37 | 10, | |
38 | 11, | |
39 | 14, | |
40 | 16, | |
41 | 19, | |
42 | 23, | |
43 | 27, | |
44 | 32, | |
45 | 39, | |
46 | 46, | |
47 | 54, | |
48 | 65, | |
49 | 77, | |
50 | 92, | |
51 | 109, | |
52 | 130, | |
53 | 154, | |
54 | 183, | |
55 | 218, | |
56 | 259, | |
57 | 308, | |
58 | 367, | |
59 | 436, | |
60 | 518, | |
61 | 616, | |
62 | 733, | |
63 | 872, | |
64 | 1037, | |
65 | 1233, | |
66 | 1466, | |
67 | 1744, | |
68 | 2073, | |
69 | 2466, | |
70 | 2933, | |
71 | 3487, | |
72 | 4147, | |
73 | 4932, | |
74 | 5865, | |
75 | 6975, | |
76 | 8294, | |
77 | 9864, | |
78 | 11730, | |
79 | 13949, | |
80 | 16589, | |
81 | 19728, | |
82 | 23460, | |
83 | 27899, | |
84 | 33178, | |
85 | 39455, | |
86 | 46920, | |
87 | 55798, | |
88 | 66355, | |
89 | 78910, | |
90 | 93840, | |
91 | 111596, | |
92 | 132710, | |
93 | 157820, | |
94 | 187681, | |
95 | 223191 | |
96 | }; | |
97 | ||
98 | static int get_isink_val(int min_uA, int max_uA, u16 *setting) | |
99 | { | |
100 | int i; | |
101 | ||
3a744038 | 102 | for (i = 0; i < ARRAY_SIZE(isink_cur); i++) { |
da09155a MB |
103 | if (min_uA <= isink_cur[i] && max_uA >= isink_cur[i]) { |
104 | *setting = i; | |
105 | return 0; | |
106 | } | |
107 | } | |
108 | return -EINVAL; | |
109 | } | |
110 | ||
111 | static inline int wm8350_ldo_val_to_mvolts(unsigned int val) | |
112 | { | |
113 | if (val < 16) | |
114 | return (val * 50) + 900; | |
115 | else | |
116 | return ((val - 16) * 100) + 1800; | |
117 | ||
118 | } | |
119 | ||
120 | static inline unsigned int wm8350_ldo_mvolts_to_val(int mV) | |
121 | { | |
122 | if (mV < 1800) | |
123 | return (mV - 900) / 50; | |
124 | else | |
125 | return ((mV - 1800) / 100) + 16; | |
126 | } | |
127 | ||
128 | static inline int wm8350_dcdc_val_to_mvolts(unsigned int val) | |
129 | { | |
130 | return (val * 25) + 850; | |
131 | } | |
132 | ||
133 | static inline unsigned int wm8350_dcdc_mvolts_to_val(int mV) | |
134 | { | |
135 | return (mV - 850) / 25; | |
136 | } | |
137 | ||
138 | static int wm8350_isink_set_current(struct regulator_dev *rdev, int min_uA, | |
139 | int max_uA) | |
140 | { | |
141 | struct wm8350 *wm8350 = rdev_get_drvdata(rdev); | |
142 | int isink = rdev_get_id(rdev); | |
143 | u16 val, setting; | |
144 | int ret; | |
145 | ||
146 | ret = get_isink_val(min_uA, max_uA, &setting); | |
147 | if (ret != 0) | |
148 | return ret; | |
149 | ||
150 | switch (isink) { | |
151 | case WM8350_ISINK_A: | |
152 | val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_A) & | |
153 | ~WM8350_CS1_ISEL_MASK; | |
154 | wm8350_reg_write(wm8350, WM8350_CURRENT_SINK_DRIVER_A, | |
155 | val | setting); | |
156 | break; | |
157 | case WM8350_ISINK_B: | |
158 | val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_B) & | |
159 | ~WM8350_CS1_ISEL_MASK; | |
160 | wm8350_reg_write(wm8350, WM8350_CURRENT_SINK_DRIVER_B, | |
161 | val | setting); | |
162 | break; | |
163 | default: | |
164 | return -EINVAL; | |
165 | } | |
166 | ||
167 | return 0; | |
168 | } | |
169 | ||
170 | static int wm8350_isink_get_current(struct regulator_dev *rdev) | |
171 | { | |
172 | struct wm8350 *wm8350 = rdev_get_drvdata(rdev); | |
173 | int isink = rdev_get_id(rdev); | |
174 | u16 val; | |
175 | ||
176 | switch (isink) { | |
177 | case WM8350_ISINK_A: | |
178 | val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_A) & | |
179 | WM8350_CS1_ISEL_MASK; | |
180 | break; | |
181 | case WM8350_ISINK_B: | |
182 | val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_B) & | |
183 | WM8350_CS1_ISEL_MASK; | |
184 | break; | |
185 | default: | |
186 | return 0; | |
187 | } | |
188 | ||
fa5a97bb | 189 | return isink_cur[val]; |
da09155a MB |
190 | } |
191 | ||
192 | /* turn on ISINK followed by DCDC */ | |
193 | static int wm8350_isink_enable(struct regulator_dev *rdev) | |
194 | { | |
195 | struct wm8350 *wm8350 = rdev_get_drvdata(rdev); | |
196 | int isink = rdev_get_id(rdev); | |
197 | ||
198 | switch (isink) { | |
199 | case WM8350_ISINK_A: | |
200 | switch (wm8350->pmic.isink_A_dcdc) { | |
201 | case WM8350_DCDC_2: | |
202 | case WM8350_DCDC_5: | |
203 | wm8350_set_bits(wm8350, WM8350_POWER_MGMT_7, | |
204 | WM8350_CS1_ENA); | |
205 | wm8350_set_bits(wm8350, WM8350_CSA_FLASH_CONTROL, | |
206 | WM8350_CS1_DRIVE); | |
207 | wm8350_set_bits(wm8350, WM8350_DCDC_LDO_REQUESTED, | |
208 | 1 << (wm8350->pmic.isink_A_dcdc - | |
209 | WM8350_DCDC_1)); | |
210 | break; | |
211 | default: | |
212 | return -EINVAL; | |
213 | } | |
214 | break; | |
215 | case WM8350_ISINK_B: | |
216 | switch (wm8350->pmic.isink_B_dcdc) { | |
217 | case WM8350_DCDC_2: | |
218 | case WM8350_DCDC_5: | |
219 | wm8350_set_bits(wm8350, WM8350_POWER_MGMT_7, | |
220 | WM8350_CS2_ENA); | |
221 | wm8350_set_bits(wm8350, WM8350_CSB_FLASH_CONTROL, | |
222 | WM8350_CS2_DRIVE); | |
223 | wm8350_set_bits(wm8350, WM8350_DCDC_LDO_REQUESTED, | |
224 | 1 << (wm8350->pmic.isink_B_dcdc - | |
225 | WM8350_DCDC_1)); | |
226 | break; | |
227 | default: | |
228 | return -EINVAL; | |
229 | } | |
230 | break; | |
231 | default: | |
232 | return -EINVAL; | |
233 | } | |
234 | return 0; | |
235 | } | |
236 | ||
237 | static int wm8350_isink_disable(struct regulator_dev *rdev) | |
238 | { | |
239 | struct wm8350 *wm8350 = rdev_get_drvdata(rdev); | |
240 | int isink = rdev_get_id(rdev); | |
241 | ||
242 | switch (isink) { | |
243 | case WM8350_ISINK_A: | |
244 | switch (wm8350->pmic.isink_A_dcdc) { | |
245 | case WM8350_DCDC_2: | |
246 | case WM8350_DCDC_5: | |
247 | wm8350_clear_bits(wm8350, WM8350_DCDC_LDO_REQUESTED, | |
248 | 1 << (wm8350->pmic.isink_A_dcdc - | |
249 | WM8350_DCDC_1)); | |
250 | wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_7, | |
251 | WM8350_CS1_ENA); | |
252 | break; | |
253 | default: | |
254 | return -EINVAL; | |
255 | } | |
256 | break; | |
257 | case WM8350_ISINK_B: | |
258 | switch (wm8350->pmic.isink_B_dcdc) { | |
259 | case WM8350_DCDC_2: | |
260 | case WM8350_DCDC_5: | |
261 | wm8350_clear_bits(wm8350, WM8350_DCDC_LDO_REQUESTED, | |
262 | 1 << (wm8350->pmic.isink_B_dcdc - | |
263 | WM8350_DCDC_1)); | |
264 | wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_7, | |
265 | WM8350_CS2_ENA); | |
266 | break; | |
267 | default: | |
268 | return -EINVAL; | |
269 | } | |
270 | break; | |
271 | default: | |
272 | return -EINVAL; | |
273 | } | |
274 | return 0; | |
275 | } | |
276 | ||
277 | static int wm8350_isink_is_enabled(struct regulator_dev *rdev) | |
278 | { | |
279 | struct wm8350 *wm8350 = rdev_get_drvdata(rdev); | |
280 | int isink = rdev_get_id(rdev); | |
281 | ||
282 | switch (isink) { | |
283 | case WM8350_ISINK_A: | |
284 | return wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_A) & | |
285 | 0x8000; | |
286 | case WM8350_ISINK_B: | |
287 | return wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_B) & | |
288 | 0x8000; | |
289 | } | |
290 | return -EINVAL; | |
291 | } | |
292 | ||
75c8ac22 MB |
293 | static int wm8350_isink_enable_time(struct regulator_dev *rdev) |
294 | { | |
295 | struct wm8350 *wm8350 = rdev_get_drvdata(rdev); | |
296 | int isink = rdev_get_id(rdev); | |
297 | int reg; | |
298 | ||
299 | switch (isink) { | |
300 | case WM8350_ISINK_A: | |
301 | reg = wm8350_reg_read(wm8350, WM8350_CSA_FLASH_CONTROL); | |
302 | break; | |
303 | case WM8350_ISINK_B: | |
304 | reg = wm8350_reg_read(wm8350, WM8350_CSB_FLASH_CONTROL); | |
305 | break; | |
306 | default: | |
307 | return -EINVAL; | |
308 | } | |
309 | ||
310 | if (reg & WM8350_CS1_FLASH_MODE) { | |
311 | switch (reg & WM8350_CS1_ON_RAMP_MASK) { | |
312 | case 0: | |
313 | return 0; | |
314 | case 1: | |
315 | return 1950; | |
316 | case 2: | |
317 | return 3910; | |
318 | case 3: | |
319 | return 7800; | |
320 | } | |
321 | } else { | |
322 | switch (reg & WM8350_CS1_ON_RAMP_MASK) { | |
323 | case 0: | |
324 | return 0; | |
325 | case 1: | |
326 | return 250000; | |
327 | case 2: | |
328 | return 500000; | |
329 | case 3: | |
330 | return 1000000; | |
331 | } | |
332 | } | |
333 | ||
334 | return -EINVAL; | |
335 | } | |
336 | ||
337 | ||
da09155a MB |
338 | int wm8350_isink_set_flash(struct wm8350 *wm8350, int isink, u16 mode, |
339 | u16 trigger, u16 duration, u16 on_ramp, u16 off_ramp, | |
340 | u16 drive) | |
341 | { | |
342 | switch (isink) { | |
343 | case WM8350_ISINK_A: | |
344 | wm8350_reg_write(wm8350, WM8350_CSA_FLASH_CONTROL, | |
345 | (mode ? WM8350_CS1_FLASH_MODE : 0) | | |
346 | (trigger ? WM8350_CS1_TRIGSRC : 0) | | |
347 | duration | on_ramp | off_ramp | drive); | |
348 | break; | |
349 | case WM8350_ISINK_B: | |
350 | wm8350_reg_write(wm8350, WM8350_CSB_FLASH_CONTROL, | |
351 | (mode ? WM8350_CS2_FLASH_MODE : 0) | | |
352 | (trigger ? WM8350_CS2_TRIGSRC : 0) | | |
353 | duration | on_ramp | off_ramp | drive); | |
354 | break; | |
355 | default: | |
356 | return -EINVAL; | |
357 | } | |
358 | return 0; | |
359 | } | |
360 | EXPORT_SYMBOL_GPL(wm8350_isink_set_flash); | |
361 | ||
da09155a MB |
362 | static int wm8350_dcdc_set_suspend_voltage(struct regulator_dev *rdev, int uV) |
363 | { | |
364 | struct wm8350 *wm8350 = rdev_get_drvdata(rdev); | |
365 | int volt_reg, mV = uV / 1000, dcdc = rdev_get_id(rdev); | |
366 | u16 val; | |
367 | ||
368 | dev_dbg(wm8350->dev, "%s %d mV %d\n", __func__, dcdc, mV); | |
369 | ||
370 | if (mV && (mV < 850 || mV > 4025)) { | |
371 | dev_err(wm8350->dev, | |
372 | "DCDC%d suspend voltage %d mV out of range\n", | |
373 | dcdc, mV); | |
374 | return -EINVAL; | |
375 | } | |
376 | if (mV == 0) | |
377 | mV = 850; | |
378 | ||
379 | switch (dcdc) { | |
380 | case WM8350_DCDC_1: | |
381 | volt_reg = WM8350_DCDC1_LOW_POWER; | |
382 | break; | |
383 | case WM8350_DCDC_3: | |
384 | volt_reg = WM8350_DCDC3_LOW_POWER; | |
385 | break; | |
386 | case WM8350_DCDC_4: | |
387 | volt_reg = WM8350_DCDC4_LOW_POWER; | |
388 | break; | |
389 | case WM8350_DCDC_6: | |
390 | volt_reg = WM8350_DCDC6_LOW_POWER; | |
391 | break; | |
392 | case WM8350_DCDC_2: | |
393 | case WM8350_DCDC_5: | |
394 | default: | |
395 | return -EINVAL; | |
396 | } | |
397 | ||
398 | /* all DCDCs have same mV bits */ | |
399 | val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_DC1_VSEL_MASK; | |
400 | wm8350_reg_write(wm8350, volt_reg, | |
401 | val | wm8350_dcdc_mvolts_to_val(mV)); | |
402 | return 0; | |
403 | } | |
404 | ||
405 | static int wm8350_dcdc_set_suspend_enable(struct regulator_dev *rdev) | |
406 | { | |
407 | struct wm8350 *wm8350 = rdev_get_drvdata(rdev); | |
408 | int dcdc = rdev_get_id(rdev); | |
409 | u16 val; | |
410 | ||
411 | switch (dcdc) { | |
412 | case WM8350_DCDC_1: | |
413 | val = wm8350_reg_read(wm8350, WM8350_DCDC1_LOW_POWER) | |
414 | & ~WM8350_DCDC_HIB_MODE_MASK; | |
415 | wm8350_reg_write(wm8350, WM8350_DCDC1_LOW_POWER, | |
eb416815 | 416 | val | wm8350->pmic.dcdc1_hib_mode); |
da09155a MB |
417 | break; |
418 | case WM8350_DCDC_3: | |
419 | val = wm8350_reg_read(wm8350, WM8350_DCDC3_LOW_POWER) | |
420 | & ~WM8350_DCDC_HIB_MODE_MASK; | |
421 | wm8350_reg_write(wm8350, WM8350_DCDC3_LOW_POWER, | |
eb416815 | 422 | val | wm8350->pmic.dcdc3_hib_mode); |
da09155a MB |
423 | break; |
424 | case WM8350_DCDC_4: | |
425 | val = wm8350_reg_read(wm8350, WM8350_DCDC4_LOW_POWER) | |
426 | & ~WM8350_DCDC_HIB_MODE_MASK; | |
427 | wm8350_reg_write(wm8350, WM8350_DCDC4_LOW_POWER, | |
eb416815 | 428 | val | wm8350->pmic.dcdc4_hib_mode); |
da09155a MB |
429 | break; |
430 | case WM8350_DCDC_6: | |
431 | val = wm8350_reg_read(wm8350, WM8350_DCDC6_LOW_POWER) | |
432 | & ~WM8350_DCDC_HIB_MODE_MASK; | |
433 | wm8350_reg_write(wm8350, WM8350_DCDC6_LOW_POWER, | |
eb416815 | 434 | val | wm8350->pmic.dcdc6_hib_mode); |
da09155a MB |
435 | break; |
436 | case WM8350_DCDC_2: | |
437 | case WM8350_DCDC_5: | |
438 | default: | |
439 | return -EINVAL; | |
440 | } | |
441 | ||
442 | return 0; | |
443 | } | |
444 | ||
445 | static int wm8350_dcdc_set_suspend_disable(struct regulator_dev *rdev) | |
446 | { | |
447 | struct wm8350 *wm8350 = rdev_get_drvdata(rdev); | |
448 | int dcdc = rdev_get_id(rdev); | |
449 | u16 val; | |
450 | ||
451 | switch (dcdc) { | |
452 | case WM8350_DCDC_1: | |
453 | val = wm8350_reg_read(wm8350, WM8350_DCDC1_LOW_POWER); | |
454 | wm8350->pmic.dcdc1_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK; | |
455 | wm8350_reg_write(wm8350, WM8350_DCDC1_LOW_POWER, | |
cee1a799 | 456 | val | WM8350_DCDC_HIB_MODE_DIS); |
da09155a MB |
457 | break; |
458 | case WM8350_DCDC_3: | |
459 | val = wm8350_reg_read(wm8350, WM8350_DCDC3_LOW_POWER); | |
460 | wm8350->pmic.dcdc3_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK; | |
461 | wm8350_reg_write(wm8350, WM8350_DCDC3_LOW_POWER, | |
cee1a799 | 462 | val | WM8350_DCDC_HIB_MODE_DIS); |
da09155a MB |
463 | break; |
464 | case WM8350_DCDC_4: | |
465 | val = wm8350_reg_read(wm8350, WM8350_DCDC4_LOW_POWER); | |
466 | wm8350->pmic.dcdc4_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK; | |
467 | wm8350_reg_write(wm8350, WM8350_DCDC4_LOW_POWER, | |
cee1a799 | 468 | val | WM8350_DCDC_HIB_MODE_DIS); |
da09155a MB |
469 | break; |
470 | case WM8350_DCDC_6: | |
471 | val = wm8350_reg_read(wm8350, WM8350_DCDC6_LOW_POWER); | |
472 | wm8350->pmic.dcdc6_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK; | |
473 | wm8350_reg_write(wm8350, WM8350_DCDC6_LOW_POWER, | |
cee1a799 | 474 | val | WM8350_DCDC_HIB_MODE_DIS); |
da09155a MB |
475 | break; |
476 | case WM8350_DCDC_2: | |
477 | case WM8350_DCDC_5: | |
478 | default: | |
479 | return -EINVAL; | |
480 | } | |
481 | ||
482 | return 0; | |
483 | } | |
484 | ||
485 | static int wm8350_dcdc25_set_suspend_enable(struct regulator_dev *rdev) | |
486 | { | |
487 | struct wm8350 *wm8350 = rdev_get_drvdata(rdev); | |
488 | int dcdc = rdev_get_id(rdev); | |
489 | u16 val; | |
490 | ||
491 | switch (dcdc) { | |
492 | case WM8350_DCDC_2: | |
493 | val = wm8350_reg_read(wm8350, WM8350_DCDC2_CONTROL) | |
494 | & ~WM8350_DC2_HIB_MODE_MASK; | |
495 | wm8350_reg_write(wm8350, WM8350_DCDC2_CONTROL, val | | |
93009286 | 496 | (WM8350_DC2_HIB_MODE_ACTIVE << WM8350_DC2_HIB_MODE_SHIFT)); |
da09155a MB |
497 | break; |
498 | case WM8350_DCDC_5: | |
499 | val = wm8350_reg_read(wm8350, WM8350_DCDC5_CONTROL) | |
93009286 | 500 | & ~WM8350_DC5_HIB_MODE_MASK; |
da09155a | 501 | wm8350_reg_write(wm8350, WM8350_DCDC5_CONTROL, val | |
93009286 | 502 | (WM8350_DC5_HIB_MODE_ACTIVE << WM8350_DC5_HIB_MODE_SHIFT)); |
da09155a MB |
503 | break; |
504 | default: | |
505 | return -EINVAL; | |
506 | } | |
507 | return 0; | |
508 | } | |
509 | ||
510 | static int wm8350_dcdc25_set_suspend_disable(struct regulator_dev *rdev) | |
511 | { | |
512 | struct wm8350 *wm8350 = rdev_get_drvdata(rdev); | |
513 | int dcdc = rdev_get_id(rdev); | |
514 | u16 val; | |
515 | ||
516 | switch (dcdc) { | |
517 | case WM8350_DCDC_2: | |
518 | val = wm8350_reg_read(wm8350, WM8350_DCDC2_CONTROL) | |
519 | & ~WM8350_DC2_HIB_MODE_MASK; | |
520 | wm8350_reg_write(wm8350, WM8350_DCDC2_CONTROL, val | | |
93009286 | 521 | (WM8350_DC2_HIB_MODE_DISABLE << WM8350_DC2_HIB_MODE_SHIFT)); |
da09155a MB |
522 | break; |
523 | case WM8350_DCDC_5: | |
524 | val = wm8350_reg_read(wm8350, WM8350_DCDC5_CONTROL) | |
93009286 | 525 | & ~WM8350_DC5_HIB_MODE_MASK; |
da09155a | 526 | wm8350_reg_write(wm8350, WM8350_DCDC5_CONTROL, val | |
93009286 | 527 | (WM8350_DC5_HIB_MODE_DISABLE << WM8350_DC5_HIB_MODE_SHIFT)); |
da09155a MB |
528 | break; |
529 | default: | |
530 | return -EINVAL; | |
531 | } | |
532 | return 0; | |
533 | } | |
534 | ||
535 | static int wm8350_dcdc_set_suspend_mode(struct regulator_dev *rdev, | |
536 | unsigned int mode) | |
537 | { | |
538 | struct wm8350 *wm8350 = rdev_get_drvdata(rdev); | |
539 | int dcdc = rdev_get_id(rdev); | |
540 | u16 *hib_mode; | |
541 | ||
542 | switch (dcdc) { | |
543 | case WM8350_DCDC_1: | |
544 | hib_mode = &wm8350->pmic.dcdc1_hib_mode; | |
545 | break; | |
546 | case WM8350_DCDC_3: | |
547 | hib_mode = &wm8350->pmic.dcdc3_hib_mode; | |
548 | break; | |
549 | case WM8350_DCDC_4: | |
550 | hib_mode = &wm8350->pmic.dcdc4_hib_mode; | |
551 | break; | |
552 | case WM8350_DCDC_6: | |
553 | hib_mode = &wm8350->pmic.dcdc6_hib_mode; | |
554 | break; | |
555 | case WM8350_DCDC_2: | |
556 | case WM8350_DCDC_5: | |
557 | default: | |
558 | return -EINVAL; | |
559 | } | |
560 | ||
561 | switch (mode) { | |
562 | case REGULATOR_MODE_NORMAL: | |
563 | *hib_mode = WM8350_DCDC_HIB_MODE_IMAGE; | |
564 | break; | |
565 | case REGULATOR_MODE_IDLE: | |
566 | *hib_mode = WM8350_DCDC_HIB_MODE_STANDBY; | |
567 | break; | |
568 | case REGULATOR_MODE_STANDBY: | |
569 | *hib_mode = WM8350_DCDC_HIB_MODE_LDO_IM; | |
570 | break; | |
571 | default: | |
572 | return -EINVAL; | |
573 | } | |
574 | ||
575 | return 0; | |
576 | } | |
577 | ||
578 | static int wm8350_ldo_set_suspend_voltage(struct regulator_dev *rdev, int uV) | |
579 | { | |
580 | struct wm8350 *wm8350 = rdev_get_drvdata(rdev); | |
581 | int volt_reg, mV = uV / 1000, ldo = rdev_get_id(rdev); | |
582 | u16 val; | |
583 | ||
584 | dev_dbg(wm8350->dev, "%s %d mV %d\n", __func__, ldo, mV); | |
585 | ||
586 | if (mV < 900 || mV > 3300) { | |
587 | dev_err(wm8350->dev, "LDO%d voltage %d mV out of range\n", | |
588 | ldo, mV); | |
589 | return -EINVAL; | |
590 | } | |
591 | ||
592 | switch (ldo) { | |
593 | case WM8350_LDO_1: | |
594 | volt_reg = WM8350_LDO1_LOW_POWER; | |
595 | break; | |
596 | case WM8350_LDO_2: | |
597 | volt_reg = WM8350_LDO2_LOW_POWER; | |
598 | break; | |
599 | case WM8350_LDO_3: | |
600 | volt_reg = WM8350_LDO3_LOW_POWER; | |
601 | break; | |
602 | case WM8350_LDO_4: | |
603 | volt_reg = WM8350_LDO4_LOW_POWER; | |
604 | break; | |
605 | default: | |
606 | return -EINVAL; | |
607 | } | |
608 | ||
609 | /* all LDOs have same mV bits */ | |
610 | val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_VSEL_MASK; | |
611 | wm8350_reg_write(wm8350, volt_reg, | |
612 | val | wm8350_ldo_mvolts_to_val(mV)); | |
613 | return 0; | |
614 | } | |
615 | ||
616 | static int wm8350_ldo_set_suspend_enable(struct regulator_dev *rdev) | |
617 | { | |
618 | struct wm8350 *wm8350 = rdev_get_drvdata(rdev); | |
619 | int volt_reg, ldo = rdev_get_id(rdev); | |
620 | u16 val; | |
621 | ||
622 | switch (ldo) { | |
623 | case WM8350_LDO_1: | |
624 | volt_reg = WM8350_LDO1_LOW_POWER; | |
625 | break; | |
626 | case WM8350_LDO_2: | |
627 | volt_reg = WM8350_LDO2_LOW_POWER; | |
628 | break; | |
629 | case WM8350_LDO_3: | |
630 | volt_reg = WM8350_LDO3_LOW_POWER; | |
631 | break; | |
632 | case WM8350_LDO_4: | |
633 | volt_reg = WM8350_LDO4_LOW_POWER; | |
634 | break; | |
635 | default: | |
636 | return -EINVAL; | |
637 | } | |
638 | ||
639 | /* all LDOs have same mV bits */ | |
640 | val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_HIB_MODE_MASK; | |
641 | wm8350_reg_write(wm8350, volt_reg, val); | |
642 | return 0; | |
643 | } | |
644 | ||
645 | static int wm8350_ldo_set_suspend_disable(struct regulator_dev *rdev) | |
646 | { | |
647 | struct wm8350 *wm8350 = rdev_get_drvdata(rdev); | |
648 | int volt_reg, ldo = rdev_get_id(rdev); | |
649 | u16 val; | |
650 | ||
651 | switch (ldo) { | |
652 | case WM8350_LDO_1: | |
653 | volt_reg = WM8350_LDO1_LOW_POWER; | |
654 | break; | |
655 | case WM8350_LDO_2: | |
656 | volt_reg = WM8350_LDO2_LOW_POWER; | |
657 | break; | |
658 | case WM8350_LDO_3: | |
659 | volt_reg = WM8350_LDO3_LOW_POWER; | |
660 | break; | |
661 | case WM8350_LDO_4: | |
662 | volt_reg = WM8350_LDO4_LOW_POWER; | |
663 | break; | |
664 | default: | |
665 | return -EINVAL; | |
666 | } | |
667 | ||
668 | /* all LDOs have same mV bits */ | |
669 | val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_HIB_MODE_MASK; | |
cee1a799 | 670 | wm8350_reg_write(wm8350, volt_reg, val | WM8350_LDO1_HIB_MODE_DIS); |
da09155a MB |
671 | return 0; |
672 | } | |
673 | ||
fc492f9b MB |
674 | static int wm8350_ldo_map_voltage(struct regulator_dev *rdev, int min_uV, |
675 | int max_uV) | |
da09155a | 676 | { |
fc492f9b MB |
677 | int mV; |
678 | int min_mV = min_uV / 1000; | |
679 | int max_mV = max_uV / 1000; | |
da09155a MB |
680 | |
681 | if (min_mV < 900 || min_mV > 3300) | |
682 | return -EINVAL; | |
683 | if (max_mV < 900 || max_mV > 3300) | |
684 | return -EINVAL; | |
685 | ||
686 | if (min_mV < 1800) { | |
687 | /* step size is 50mV < 1800mV */ | |
688 | mV = (min_mV - 851) / 50; | |
689 | if (wm8350_ldo_val_to_mvolts(mV) > max_mV) | |
690 | return -EINVAL; | |
691 | BUG_ON(wm8350_ldo_val_to_mvolts(mV) < min_mV); | |
692 | } else { | |
693 | /* step size is 100mV > 1800mV */ | |
694 | mV = ((min_mV - 1701) / 100) + 16; | |
695 | if (wm8350_ldo_val_to_mvolts(mV) > max_mV) | |
696 | return -EINVAL; | |
697 | BUG_ON(wm8350_ldo_val_to_mvolts(mV) < min_mV); | |
698 | } | |
699 | ||
fc492f9b | 700 | return mV; |
da09155a MB |
701 | } |
702 | ||
221a7c7c MB |
703 | static int wm8350_ldo_list_voltage(struct regulator_dev *rdev, |
704 | unsigned selector) | |
705 | { | |
706 | if (selector > WM8350_LDO1_VSEL_MASK) | |
707 | return -EINVAL; | |
708 | return wm8350_ldo_val_to_mvolts(selector) * 1000; | |
709 | } | |
710 | ||
da09155a MB |
711 | int wm8350_dcdc_set_slot(struct wm8350 *wm8350, int dcdc, u16 start, |
712 | u16 stop, u16 fault) | |
713 | { | |
714 | int slot_reg; | |
715 | u16 val; | |
716 | ||
717 | dev_dbg(wm8350->dev, "%s %d start %d stop %d\n", | |
718 | __func__, dcdc, start, stop); | |
719 | ||
720 | /* slot valid ? */ | |
721 | if (start > 15 || stop > 15) | |
722 | return -EINVAL; | |
723 | ||
724 | switch (dcdc) { | |
725 | case WM8350_DCDC_1: | |
726 | slot_reg = WM8350_DCDC1_TIMEOUTS; | |
727 | break; | |
728 | case WM8350_DCDC_2: | |
729 | slot_reg = WM8350_DCDC2_TIMEOUTS; | |
730 | break; | |
731 | case WM8350_DCDC_3: | |
732 | slot_reg = WM8350_DCDC3_TIMEOUTS; | |
733 | break; | |
734 | case WM8350_DCDC_4: | |
735 | slot_reg = WM8350_DCDC4_TIMEOUTS; | |
736 | break; | |
737 | case WM8350_DCDC_5: | |
738 | slot_reg = WM8350_DCDC5_TIMEOUTS; | |
739 | break; | |
740 | case WM8350_DCDC_6: | |
741 | slot_reg = WM8350_DCDC6_TIMEOUTS; | |
742 | break; | |
743 | default: | |
744 | return -EINVAL; | |
745 | } | |
746 | ||
747 | val = wm8350_reg_read(wm8350, slot_reg) & | |
748 | ~(WM8350_DC1_ENSLOT_MASK | WM8350_DC1_SDSLOT_MASK | | |
749 | WM8350_DC1_ERRACT_MASK); | |
750 | wm8350_reg_write(wm8350, slot_reg, | |
751 | val | (start << WM8350_DC1_ENSLOT_SHIFT) | | |
752 | (stop << WM8350_DC1_SDSLOT_SHIFT) | | |
753 | (fault << WM8350_DC1_ERRACT_SHIFT)); | |
754 | ||
755 | return 0; | |
756 | } | |
757 | EXPORT_SYMBOL_GPL(wm8350_dcdc_set_slot); | |
758 | ||
759 | int wm8350_ldo_set_slot(struct wm8350 *wm8350, int ldo, u16 start, u16 stop) | |
760 | { | |
761 | int slot_reg; | |
762 | u16 val; | |
763 | ||
764 | dev_dbg(wm8350->dev, "%s %d start %d stop %d\n", | |
765 | __func__, ldo, start, stop); | |
766 | ||
767 | /* slot valid ? */ | |
768 | if (start > 15 || stop > 15) | |
769 | return -EINVAL; | |
770 | ||
771 | switch (ldo) { | |
772 | case WM8350_LDO_1: | |
773 | slot_reg = WM8350_LDO1_TIMEOUTS; | |
774 | break; | |
775 | case WM8350_LDO_2: | |
776 | slot_reg = WM8350_LDO2_TIMEOUTS; | |
777 | break; | |
778 | case WM8350_LDO_3: | |
779 | slot_reg = WM8350_LDO3_TIMEOUTS; | |
780 | break; | |
781 | case WM8350_LDO_4: | |
782 | slot_reg = WM8350_LDO4_TIMEOUTS; | |
783 | break; | |
784 | default: | |
785 | return -EINVAL; | |
786 | } | |
787 | ||
788 | val = wm8350_reg_read(wm8350, slot_reg) & ~WM8350_LDO1_SDSLOT_MASK; | |
789 | wm8350_reg_write(wm8350, slot_reg, val | ((start << 10) | (stop << 6))); | |
790 | return 0; | |
791 | } | |
792 | EXPORT_SYMBOL_GPL(wm8350_ldo_set_slot); | |
793 | ||
794 | int wm8350_dcdc25_set_mode(struct wm8350 *wm8350, int dcdc, u16 mode, | |
795 | u16 ilim, u16 ramp, u16 feedback) | |
796 | { | |
797 | u16 val; | |
798 | ||
799 | dev_dbg(wm8350->dev, "%s %d mode: %s %s\n", __func__, dcdc, | |
800 | mode ? "normal" : "boost", ilim ? "low" : "normal"); | |
801 | ||
802 | switch (dcdc) { | |
803 | case WM8350_DCDC_2: | |
804 | val = wm8350_reg_read(wm8350, WM8350_DCDC2_CONTROL) | |
805 | & ~(WM8350_DC2_MODE_MASK | WM8350_DC2_ILIM_MASK | | |
806 | WM8350_DC2_RMP_MASK | WM8350_DC2_FBSRC_MASK); | |
807 | wm8350_reg_write(wm8350, WM8350_DCDC2_CONTROL, val | | |
808 | (mode << WM8350_DC2_MODE_SHIFT) | | |
809 | (ilim << WM8350_DC2_ILIM_SHIFT) | | |
810 | (ramp << WM8350_DC2_RMP_SHIFT) | | |
811 | (feedback << WM8350_DC2_FBSRC_SHIFT)); | |
812 | break; | |
813 | case WM8350_DCDC_5: | |
814 | val = wm8350_reg_read(wm8350, WM8350_DCDC5_CONTROL) | |
815 | & ~(WM8350_DC5_MODE_MASK | WM8350_DC5_ILIM_MASK | | |
816 | WM8350_DC5_RMP_MASK | WM8350_DC5_FBSRC_MASK); | |
817 | wm8350_reg_write(wm8350, WM8350_DCDC5_CONTROL, val | | |
818 | (mode << WM8350_DC5_MODE_SHIFT) | | |
819 | (ilim << WM8350_DC5_ILIM_SHIFT) | | |
820 | (ramp << WM8350_DC5_RMP_SHIFT) | | |
821 | (feedback << WM8350_DC5_FBSRC_SHIFT)); | |
822 | break; | |
823 | default: | |
824 | return -EINVAL; | |
825 | } | |
826 | ||
827 | return 0; | |
828 | } | |
829 | EXPORT_SYMBOL_GPL(wm8350_dcdc25_set_mode); | |
830 | ||
da09155a MB |
831 | static int force_continuous_enable(struct wm8350 *wm8350, int dcdc, int enable) |
832 | { | |
833 | int reg = 0, ret; | |
834 | ||
835 | switch (dcdc) { | |
836 | case WM8350_DCDC_1: | |
837 | reg = WM8350_DCDC1_FORCE_PWM; | |
838 | break; | |
839 | case WM8350_DCDC_3: | |
840 | reg = WM8350_DCDC3_FORCE_PWM; | |
841 | break; | |
842 | case WM8350_DCDC_4: | |
843 | reg = WM8350_DCDC4_FORCE_PWM; | |
844 | break; | |
845 | case WM8350_DCDC_6: | |
846 | reg = WM8350_DCDC6_FORCE_PWM; | |
847 | break; | |
848 | default: | |
849 | return -EINVAL; | |
850 | } | |
851 | ||
852 | if (enable) | |
853 | ret = wm8350_set_bits(wm8350, reg, | |
854 | WM8350_DCDC1_FORCE_PWM_ENA); | |
855 | else | |
856 | ret = wm8350_clear_bits(wm8350, reg, | |
857 | WM8350_DCDC1_FORCE_PWM_ENA); | |
858 | return ret; | |
859 | } | |
860 | ||
861 | static int wm8350_dcdc_set_mode(struct regulator_dev *rdev, unsigned int mode) | |
862 | { | |
863 | struct wm8350 *wm8350 = rdev_get_drvdata(rdev); | |
864 | int dcdc = rdev_get_id(rdev); | |
865 | u16 val; | |
866 | ||
867 | if (dcdc < WM8350_DCDC_1 || dcdc > WM8350_DCDC_6) | |
868 | return -EINVAL; | |
869 | ||
870 | if (dcdc == WM8350_DCDC_2 || dcdc == WM8350_DCDC_5) | |
871 | return -EINVAL; | |
872 | ||
873 | val = 1 << (dcdc - WM8350_DCDC_1); | |
874 | ||
875 | switch (mode) { | |
876 | case REGULATOR_MODE_FAST: | |
877 | /* force continuous mode */ | |
878 | wm8350_set_bits(wm8350, WM8350_DCDC_ACTIVE_OPTIONS, val); | |
879 | wm8350_clear_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val); | |
880 | force_continuous_enable(wm8350, dcdc, 1); | |
881 | break; | |
882 | case REGULATOR_MODE_NORMAL: | |
883 | /* active / pulse skipping */ | |
884 | wm8350_set_bits(wm8350, WM8350_DCDC_ACTIVE_OPTIONS, val); | |
885 | wm8350_clear_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val); | |
886 | force_continuous_enable(wm8350, dcdc, 0); | |
887 | break; | |
888 | case REGULATOR_MODE_IDLE: | |
889 | /* standby mode */ | |
890 | force_continuous_enable(wm8350, dcdc, 0); | |
891 | wm8350_clear_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val); | |
892 | wm8350_clear_bits(wm8350, WM8350_DCDC_ACTIVE_OPTIONS, val); | |
893 | break; | |
894 | case REGULATOR_MODE_STANDBY: | |
895 | /* LDO mode */ | |
896 | force_continuous_enable(wm8350, dcdc, 0); | |
897 | wm8350_set_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val); | |
898 | break; | |
899 | } | |
900 | ||
901 | return 0; | |
902 | } | |
903 | ||
904 | static unsigned int wm8350_dcdc_get_mode(struct regulator_dev *rdev) | |
905 | { | |
906 | struct wm8350 *wm8350 = rdev_get_drvdata(rdev); | |
907 | int dcdc = rdev_get_id(rdev); | |
908 | u16 mask, sleep, active, force; | |
909 | int mode = REGULATOR_MODE_NORMAL; | |
33f301af | 910 | int reg; |
da09155a | 911 | |
33f301af MB |
912 | switch (dcdc) { |
913 | case WM8350_DCDC_1: | |
914 | reg = WM8350_DCDC1_FORCE_PWM; | |
915 | break; | |
916 | case WM8350_DCDC_3: | |
917 | reg = WM8350_DCDC3_FORCE_PWM; | |
918 | break; | |
919 | case WM8350_DCDC_4: | |
920 | reg = WM8350_DCDC4_FORCE_PWM; | |
921 | break; | |
922 | case WM8350_DCDC_6: | |
923 | reg = WM8350_DCDC6_FORCE_PWM; | |
924 | break; | |
925 | default: | |
da09155a | 926 | return -EINVAL; |
33f301af | 927 | } |
da09155a MB |
928 | |
929 | mask = 1 << (dcdc - WM8350_DCDC_1); | |
930 | active = wm8350_reg_read(wm8350, WM8350_DCDC_ACTIVE_OPTIONS) & mask; | |
33f301af | 931 | force = wm8350_reg_read(wm8350, reg) & WM8350_DCDC1_FORCE_PWM_ENA; |
da09155a | 932 | sleep = wm8350_reg_read(wm8350, WM8350_DCDC_SLEEP_OPTIONS) & mask; |
33f301af | 933 | |
da09155a MB |
934 | dev_dbg(wm8350->dev, "mask %x active %x sleep %x force %x", |
935 | mask, active, sleep, force); | |
936 | ||
937 | if (active && !sleep) { | |
938 | if (force) | |
939 | mode = REGULATOR_MODE_FAST; | |
940 | else | |
941 | mode = REGULATOR_MODE_NORMAL; | |
942 | } else if (!active && !sleep) | |
943 | mode = REGULATOR_MODE_IDLE; | |
8ecee36a | 944 | else if (sleep) |
da09155a MB |
945 | mode = REGULATOR_MODE_STANDBY; |
946 | ||
947 | return mode; | |
948 | } | |
949 | ||
950 | static unsigned int wm8350_ldo_get_mode(struct regulator_dev *rdev) | |
951 | { | |
952 | return REGULATOR_MODE_NORMAL; | |
953 | } | |
954 | ||
955 | struct wm8350_dcdc_efficiency { | |
956 | int uA_load_min; | |
957 | int uA_load_max; | |
958 | unsigned int mode; | |
959 | }; | |
960 | ||
961 | static const struct wm8350_dcdc_efficiency dcdc1_6_efficiency[] = { | |
962 | {0, 10000, REGULATOR_MODE_STANDBY}, /* 0 - 10mA - LDO */ | |
963 | {10000, 100000, REGULATOR_MODE_IDLE}, /* 10mA - 100mA - Standby */ | |
964 | {100000, 1000000, REGULATOR_MODE_NORMAL}, /* > 100mA - Active */ | |
965 | {-1, -1, REGULATOR_MODE_NORMAL}, | |
966 | }; | |
967 | ||
968 | static const struct wm8350_dcdc_efficiency dcdc3_4_efficiency[] = { | |
969 | {0, 10000, REGULATOR_MODE_STANDBY}, /* 0 - 10mA - LDO */ | |
970 | {10000, 100000, REGULATOR_MODE_IDLE}, /* 10mA - 100mA - Standby */ | |
971 | {100000, 800000, REGULATOR_MODE_NORMAL}, /* > 100mA - Active */ | |
972 | {-1, -1, REGULATOR_MODE_NORMAL}, | |
973 | }; | |
974 | ||
975 | static unsigned int get_mode(int uA, const struct wm8350_dcdc_efficiency *eff) | |
976 | { | |
977 | int i = 0; | |
978 | ||
979 | while (eff[i].uA_load_min != -1) { | |
980 | if (uA >= eff[i].uA_load_min && uA <= eff[i].uA_load_max) | |
981 | return eff[i].mode; | |
982 | } | |
983 | return REGULATOR_MODE_NORMAL; | |
984 | } | |
985 | ||
986 | /* Query the regulator for it's most efficient mode @ uV,uA | |
987 | * WM8350 regulator efficiency is pretty similar over | |
988 | * different input and output uV. | |
989 | */ | |
990 | static unsigned int wm8350_dcdc_get_optimum_mode(struct regulator_dev *rdev, | |
991 | int input_uV, int output_uV, | |
992 | int output_uA) | |
993 | { | |
994 | int dcdc = rdev_get_id(rdev), mode; | |
995 | ||
996 | switch (dcdc) { | |
997 | case WM8350_DCDC_1: | |
998 | case WM8350_DCDC_6: | |
999 | mode = get_mode(output_uA, dcdc1_6_efficiency); | |
1000 | break; | |
1001 | case WM8350_DCDC_3: | |
1002 | case WM8350_DCDC_4: | |
1003 | mode = get_mode(output_uA, dcdc3_4_efficiency); | |
1004 | break; | |
1005 | default: | |
1006 | mode = REGULATOR_MODE_NORMAL; | |
1007 | break; | |
1008 | } | |
1009 | return mode; | |
1010 | } | |
1011 | ||
da09155a | 1012 | static struct regulator_ops wm8350_dcdc_ops = { |
107a3967 | 1013 | .set_voltage_sel = regulator_set_voltage_sel_regmap, |
b4ec87ae | 1014 | .get_voltage_sel = regulator_get_voltage_sel_regmap, |
107a3967 | 1015 | .list_voltage = regulator_list_voltage_linear, |
fcbb71f6 | 1016 | .map_voltage = regulator_map_voltage_linear, |
a540f682 MB |
1017 | .enable = regulator_enable_regmap, |
1018 | .disable = regulator_disable_regmap, | |
1019 | .is_enabled = regulator_is_enabled_regmap, | |
da09155a MB |
1020 | .get_mode = wm8350_dcdc_get_mode, |
1021 | .set_mode = wm8350_dcdc_set_mode, | |
1022 | .get_optimum_mode = wm8350_dcdc_get_optimum_mode, | |
da09155a MB |
1023 | .set_suspend_voltage = wm8350_dcdc_set_suspend_voltage, |
1024 | .set_suspend_enable = wm8350_dcdc_set_suspend_enable, | |
1025 | .set_suspend_disable = wm8350_dcdc_set_suspend_disable, | |
1026 | .set_suspend_mode = wm8350_dcdc_set_suspend_mode, | |
1027 | }; | |
1028 | ||
1029 | static struct regulator_ops wm8350_dcdc2_5_ops = { | |
a540f682 MB |
1030 | .enable = regulator_enable_regmap, |
1031 | .disable = regulator_disable_regmap, | |
1032 | .is_enabled = regulator_is_enabled_regmap, | |
da09155a MB |
1033 | .set_suspend_enable = wm8350_dcdc25_set_suspend_enable, |
1034 | .set_suspend_disable = wm8350_dcdc25_set_suspend_disable, | |
1035 | }; | |
1036 | ||
1037 | static struct regulator_ops wm8350_ldo_ops = { | |
fc492f9b MB |
1038 | .map_voltage = wm8350_ldo_map_voltage, |
1039 | .set_voltage_sel = regulator_set_voltage_sel_regmap, | |
b4ec87ae | 1040 | .get_voltage_sel = regulator_get_voltage_sel_regmap, |
221a7c7c | 1041 | .list_voltage = wm8350_ldo_list_voltage, |
a540f682 MB |
1042 | .enable = regulator_enable_regmap, |
1043 | .disable = regulator_disable_regmap, | |
1044 | .is_enabled = regulator_is_enabled_regmap, | |
da09155a MB |
1045 | .get_mode = wm8350_ldo_get_mode, |
1046 | .set_suspend_voltage = wm8350_ldo_set_suspend_voltage, | |
1047 | .set_suspend_enable = wm8350_ldo_set_suspend_enable, | |
1048 | .set_suspend_disable = wm8350_ldo_set_suspend_disable, | |
1049 | }; | |
1050 | ||
1051 | static struct regulator_ops wm8350_isink_ops = { | |
1052 | .set_current_limit = wm8350_isink_set_current, | |
1053 | .get_current_limit = wm8350_isink_get_current, | |
1054 | .enable = wm8350_isink_enable, | |
1055 | .disable = wm8350_isink_disable, | |
1056 | .is_enabled = wm8350_isink_is_enabled, | |
75c8ac22 | 1057 | .enable_time = wm8350_isink_enable_time, |
da09155a MB |
1058 | }; |
1059 | ||
47924b6a | 1060 | static const struct regulator_desc wm8350_reg[NUM_WM8350_REGULATORS] = { |
da09155a MB |
1061 | { |
1062 | .name = "DCDC1", | |
1063 | .id = WM8350_DCDC_1, | |
1064 | .ops = &wm8350_dcdc_ops, | |
1065 | .irq = WM8350_IRQ_UV_DC1, | |
1066 | .type = REGULATOR_VOLTAGE, | |
221a7c7c | 1067 | .n_voltages = WM8350_DCDC_MAX_VSEL + 1, |
107a3967 MB |
1068 | .min_uV = 850000, |
1069 | .uV_step = 25000, | |
b4ec87ae MB |
1070 | .vsel_reg = WM8350_DCDC1_CONTROL, |
1071 | .vsel_mask = WM8350_DC1_VSEL_MASK, | |
a540f682 MB |
1072 | .enable_reg = WM8350_DCDC_LDO_REQUESTED, |
1073 | .enable_mask = WM8350_DC1_ENA, | |
da09155a MB |
1074 | .owner = THIS_MODULE, |
1075 | }, | |
1076 | { | |
1077 | .name = "DCDC2", | |
1078 | .id = WM8350_DCDC_2, | |
1079 | .ops = &wm8350_dcdc2_5_ops, | |
1080 | .irq = WM8350_IRQ_UV_DC2, | |
1081 | .type = REGULATOR_VOLTAGE, | |
a540f682 MB |
1082 | .enable_reg = WM8350_DCDC_LDO_REQUESTED, |
1083 | .enable_mask = WM8350_DC2_ENA, | |
da09155a MB |
1084 | .owner = THIS_MODULE, |
1085 | }, | |
1086 | { | |
1087 | .name = "DCDC3", | |
1088 | .id = WM8350_DCDC_3, | |
1089 | .ops = &wm8350_dcdc_ops, | |
1090 | .irq = WM8350_IRQ_UV_DC3, | |
1091 | .type = REGULATOR_VOLTAGE, | |
221a7c7c | 1092 | .n_voltages = WM8350_DCDC_MAX_VSEL + 1, |
107a3967 MB |
1093 | .min_uV = 850000, |
1094 | .uV_step = 25000, | |
b4ec87ae MB |
1095 | .vsel_reg = WM8350_DCDC3_CONTROL, |
1096 | .vsel_mask = WM8350_DC3_VSEL_MASK, | |
a540f682 MB |
1097 | .enable_reg = WM8350_DCDC_LDO_REQUESTED, |
1098 | .enable_mask = WM8350_DC3_ENA, | |
da09155a MB |
1099 | .owner = THIS_MODULE, |
1100 | }, | |
1101 | { | |
1102 | .name = "DCDC4", | |
1103 | .id = WM8350_DCDC_4, | |
1104 | .ops = &wm8350_dcdc_ops, | |
1105 | .irq = WM8350_IRQ_UV_DC4, | |
1106 | .type = REGULATOR_VOLTAGE, | |
221a7c7c | 1107 | .n_voltages = WM8350_DCDC_MAX_VSEL + 1, |
b4ec87ae MB |
1108 | .vsel_reg = WM8350_DCDC4_CONTROL, |
1109 | .vsel_mask = WM8350_DC4_VSEL_MASK, | |
a540f682 MB |
1110 | .enable_reg = WM8350_DCDC_LDO_REQUESTED, |
1111 | .enable_mask = WM8350_DC4_ENA, | |
da09155a MB |
1112 | .owner = THIS_MODULE, |
1113 | }, | |
1114 | { | |
1115 | .name = "DCDC5", | |
1116 | .id = WM8350_DCDC_5, | |
1117 | .ops = &wm8350_dcdc2_5_ops, | |
1118 | .irq = WM8350_IRQ_UV_DC5, | |
1119 | .type = REGULATOR_VOLTAGE, | |
a540f682 MB |
1120 | .enable_reg = WM8350_DCDC_LDO_REQUESTED, |
1121 | .enable_mask = WM8350_DC5_ENA, | |
da09155a MB |
1122 | .owner = THIS_MODULE, |
1123 | }, | |
1124 | { | |
1125 | .name = "DCDC6", | |
1126 | .id = WM8350_DCDC_6, | |
1127 | .ops = &wm8350_dcdc_ops, | |
1128 | .irq = WM8350_IRQ_UV_DC6, | |
1129 | .type = REGULATOR_VOLTAGE, | |
221a7c7c | 1130 | .n_voltages = WM8350_DCDC_MAX_VSEL + 1, |
107a3967 MB |
1131 | .min_uV = 850000, |
1132 | .uV_step = 25000, | |
b4ec87ae MB |
1133 | .vsel_reg = WM8350_DCDC6_CONTROL, |
1134 | .vsel_mask = WM8350_DC6_VSEL_MASK, | |
a540f682 MB |
1135 | .enable_reg = WM8350_DCDC_LDO_REQUESTED, |
1136 | .enable_mask = WM8350_DC6_ENA, | |
da09155a MB |
1137 | .owner = THIS_MODULE, |
1138 | }, | |
1139 | { | |
1140 | .name = "LDO1", | |
1141 | .id = WM8350_LDO_1, | |
1142 | .ops = &wm8350_ldo_ops, | |
1143 | .irq = WM8350_IRQ_UV_LDO1, | |
1144 | .type = REGULATOR_VOLTAGE, | |
221a7c7c | 1145 | .n_voltages = WM8350_LDO1_VSEL_MASK + 1, |
b4ec87ae MB |
1146 | .vsel_reg = WM8350_LDO1_CONTROL, |
1147 | .vsel_mask = WM8350_LDO1_VSEL_MASK, | |
a540f682 MB |
1148 | .enable_reg = WM8350_DCDC_LDO_REQUESTED, |
1149 | .enable_mask = WM8350_LDO1_ENA, | |
da09155a MB |
1150 | .owner = THIS_MODULE, |
1151 | }, | |
1152 | { | |
1153 | .name = "LDO2", | |
1154 | .id = WM8350_LDO_2, | |
1155 | .ops = &wm8350_ldo_ops, | |
1156 | .irq = WM8350_IRQ_UV_LDO2, | |
1157 | .type = REGULATOR_VOLTAGE, | |
221a7c7c | 1158 | .n_voltages = WM8350_LDO2_VSEL_MASK + 1, |
b4ec87ae MB |
1159 | .vsel_reg = WM8350_LDO2_CONTROL, |
1160 | .vsel_mask = WM8350_LDO2_VSEL_MASK, | |
a540f682 MB |
1161 | .enable_reg = WM8350_DCDC_LDO_REQUESTED, |
1162 | .enable_mask = WM8350_LDO2_ENA, | |
da09155a MB |
1163 | .owner = THIS_MODULE, |
1164 | }, | |
1165 | { | |
1166 | .name = "LDO3", | |
1167 | .id = WM8350_LDO_3, | |
1168 | .ops = &wm8350_ldo_ops, | |
1169 | .irq = WM8350_IRQ_UV_LDO3, | |
1170 | .type = REGULATOR_VOLTAGE, | |
221a7c7c | 1171 | .n_voltages = WM8350_LDO3_VSEL_MASK + 1, |
b4ec87ae MB |
1172 | .vsel_reg = WM8350_LDO3_CONTROL, |
1173 | .vsel_mask = WM8350_LDO3_VSEL_MASK, | |
a540f682 MB |
1174 | .enable_reg = WM8350_DCDC_LDO_REQUESTED, |
1175 | .enable_mask = WM8350_LDO3_ENA, | |
da09155a MB |
1176 | .owner = THIS_MODULE, |
1177 | }, | |
1178 | { | |
1179 | .name = "LDO4", | |
1180 | .id = WM8350_LDO_4, | |
1181 | .ops = &wm8350_ldo_ops, | |
1182 | .irq = WM8350_IRQ_UV_LDO4, | |
1183 | .type = REGULATOR_VOLTAGE, | |
221a7c7c | 1184 | .n_voltages = WM8350_LDO4_VSEL_MASK + 1, |
b4ec87ae MB |
1185 | .vsel_reg = WM8350_LDO4_CONTROL, |
1186 | .vsel_mask = WM8350_LDO4_VSEL_MASK, | |
a540f682 MB |
1187 | .enable_reg = WM8350_DCDC_LDO_REQUESTED, |
1188 | .enable_mask = WM8350_LDO4_ENA, | |
da09155a MB |
1189 | .owner = THIS_MODULE, |
1190 | }, | |
1191 | { | |
1192 | .name = "ISINKA", | |
1193 | .id = WM8350_ISINK_A, | |
1194 | .ops = &wm8350_isink_ops, | |
1195 | .irq = WM8350_IRQ_CS1, | |
1196 | .type = REGULATOR_CURRENT, | |
1197 | .owner = THIS_MODULE, | |
1198 | }, | |
1199 | { | |
1200 | .name = "ISINKB", | |
1201 | .id = WM8350_ISINK_B, | |
1202 | .ops = &wm8350_isink_ops, | |
1203 | .irq = WM8350_IRQ_CS2, | |
1204 | .type = REGULATOR_CURRENT, | |
1205 | .owner = THIS_MODULE, | |
1206 | }, | |
1207 | }; | |
1208 | ||
5a65edbc | 1209 | static irqreturn_t pmic_uv_handler(int irq, void *data) |
da09155a MB |
1210 | { |
1211 | struct regulator_dev *rdev = (struct regulator_dev *)data; | |
5a65edbc | 1212 | struct wm8350 *wm8350 = rdev_get_drvdata(rdev); |
da09155a | 1213 | |
b136fb44 | 1214 | mutex_lock(&rdev->mutex); |
da09155a MB |
1215 | if (irq == WM8350_IRQ_CS1 || irq == WM8350_IRQ_CS2) |
1216 | regulator_notifier_call_chain(rdev, | |
1217 | REGULATOR_EVENT_REGULATION_OUT, | |
1218 | wm8350); | |
1219 | else | |
1220 | regulator_notifier_call_chain(rdev, | |
1221 | REGULATOR_EVENT_UNDER_VOLTAGE, | |
1222 | wm8350); | |
b136fb44 | 1223 | mutex_unlock(&rdev->mutex); |
5a65edbc MB |
1224 | |
1225 | return IRQ_HANDLED; | |
da09155a MB |
1226 | } |
1227 | ||
1228 | static int wm8350_regulator_probe(struct platform_device *pdev) | |
1229 | { | |
1230 | struct wm8350 *wm8350 = dev_get_drvdata(&pdev->dev); | |
c172708d | 1231 | struct regulator_config config = { }; |
da09155a MB |
1232 | struct regulator_dev *rdev; |
1233 | int ret; | |
1234 | u16 val; | |
1235 | ||
1236 | if (pdev->id < WM8350_DCDC_1 || pdev->id > WM8350_ISINK_B) | |
1237 | return -ENODEV; | |
1238 | ||
1239 | /* do any regulatior specific init */ | |
1240 | switch (pdev->id) { | |
1241 | case WM8350_DCDC_1: | |
1242 | val = wm8350_reg_read(wm8350, WM8350_DCDC1_LOW_POWER); | |
1243 | wm8350->pmic.dcdc1_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK; | |
1244 | break; | |
1245 | case WM8350_DCDC_3: | |
1246 | val = wm8350_reg_read(wm8350, WM8350_DCDC3_LOW_POWER); | |
1247 | wm8350->pmic.dcdc3_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK; | |
1248 | break; | |
1249 | case WM8350_DCDC_4: | |
1250 | val = wm8350_reg_read(wm8350, WM8350_DCDC4_LOW_POWER); | |
1251 | wm8350->pmic.dcdc4_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK; | |
1252 | break; | |
1253 | case WM8350_DCDC_6: | |
1254 | val = wm8350_reg_read(wm8350, WM8350_DCDC6_LOW_POWER); | |
1255 | wm8350->pmic.dcdc6_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK; | |
1256 | break; | |
1257 | } | |
1258 | ||
c172708d MB |
1259 | config.dev = &pdev->dev; |
1260 | config.init_data = pdev->dev.platform_data; | |
1261 | config.driver_data = dev_get_drvdata(&pdev->dev); | |
b4ec87ae | 1262 | config.regmap = wm8350->regmap; |
c172708d | 1263 | |
da09155a | 1264 | /* register regulator */ |
c172708d | 1265 | rdev = regulator_register(&wm8350_reg[pdev->id], &config); |
da09155a MB |
1266 | if (IS_ERR(rdev)) { |
1267 | dev_err(&pdev->dev, "failed to register %s\n", | |
1268 | wm8350_reg[pdev->id].name); | |
1269 | return PTR_ERR(rdev); | |
1270 | } | |
1271 | ||
1272 | /* register regulator IRQ */ | |
1273 | ret = wm8350_register_irq(wm8350, wm8350_reg[pdev->id].irq, | |
5a65edbc | 1274 | pmic_uv_handler, 0, "UV", rdev); |
da09155a MB |
1275 | if (ret < 0) { |
1276 | regulator_unregister(rdev); | |
1277 | dev_err(&pdev->dev, "failed to register regulator %s IRQ\n", | |
1278 | wm8350_reg[pdev->id].name); | |
1279 | return ret; | |
1280 | } | |
1281 | ||
da09155a MB |
1282 | return 0; |
1283 | } | |
1284 | ||
1285 | static int wm8350_regulator_remove(struct platform_device *pdev) | |
1286 | { | |
1287 | struct regulator_dev *rdev = platform_get_drvdata(pdev); | |
1288 | struct wm8350 *wm8350 = rdev_get_drvdata(rdev); | |
1289 | ||
f99344fc | 1290 | wm8350_free_irq(wm8350, wm8350_reg[pdev->id].irq, rdev); |
da09155a MB |
1291 | |
1292 | regulator_unregister(rdev); | |
1293 | ||
1294 | return 0; | |
1295 | } | |
1296 | ||
1297 | int wm8350_register_regulator(struct wm8350 *wm8350, int reg, | |
1298 | struct regulator_init_data *initdata) | |
1299 | { | |
1300 | struct platform_device *pdev; | |
1301 | int ret; | |
4dee4d44 RK |
1302 | if (reg < 0 || reg >= NUM_WM8350_REGULATORS) |
1303 | return -EINVAL; | |
da09155a MB |
1304 | |
1305 | if (wm8350->pmic.pdev[reg]) | |
1306 | return -EBUSY; | |
1307 | ||
645524a9 MB |
1308 | if (reg >= WM8350_DCDC_1 && reg <= WM8350_DCDC_6 && |
1309 | reg > wm8350->pmic.max_dcdc) | |
1310 | return -ENODEV; | |
1311 | if (reg >= WM8350_ISINK_A && reg <= WM8350_ISINK_B && | |
1312 | reg > wm8350->pmic.max_isink) | |
1313 | return -ENODEV; | |
1314 | ||
da09155a MB |
1315 | pdev = platform_device_alloc("wm8350-regulator", reg); |
1316 | if (!pdev) | |
1317 | return -ENOMEM; | |
1318 | ||
1319 | wm8350->pmic.pdev[reg] = pdev; | |
1320 | ||
1321 | initdata->driver_data = wm8350; | |
1322 | ||
1323 | pdev->dev.platform_data = initdata; | |
1324 | pdev->dev.parent = wm8350->dev; | |
1325 | platform_set_drvdata(pdev, wm8350); | |
1326 | ||
1327 | ret = platform_device_add(pdev); | |
1328 | ||
1329 | if (ret != 0) { | |
1330 | dev_err(wm8350->dev, "Failed to register regulator %d: %d\n", | |
1331 | reg, ret); | |
e9a1c512 | 1332 | platform_device_put(pdev); |
da09155a MB |
1333 | wm8350->pmic.pdev[reg] = NULL; |
1334 | } | |
1335 | ||
1336 | return ret; | |
1337 | } | |
1338 | EXPORT_SYMBOL_GPL(wm8350_register_regulator); | |
1339 | ||
0081e802 MB |
1340 | /** |
1341 | * wm8350_register_led - Register a WM8350 LED output | |
1342 | * | |
1343 | * @param wm8350 The WM8350 device to configure. | |
1344 | * @param lednum LED device index to create. | |
1345 | * @param dcdc The DCDC to use for the LED. | |
1346 | * @param isink The ISINK to use for the LED. | |
1347 | * @param pdata Configuration for the LED. | |
1348 | * | |
1349 | * The WM8350 supports the use of an ISINK together with a DCDC to | |
1350 | * provide a power-efficient LED driver. This function registers the | |
1351 | * regulators and instantiates the platform device for a LED. The | |
1352 | * operating modes for the LED regulators must be configured using | |
1353 | * wm8350_isink_set_flash(), wm8350_dcdc25_set_mode() and | |
1354 | * wm8350_dcdc_set_slot() prior to calling this function. | |
1355 | */ | |
1356 | int wm8350_register_led(struct wm8350 *wm8350, int lednum, int dcdc, int isink, | |
1357 | struct wm8350_led_platform_data *pdata) | |
1358 | { | |
1359 | struct wm8350_led *led; | |
1360 | struct platform_device *pdev; | |
1361 | int ret; | |
1362 | ||
8dd2c9e3 | 1363 | if (lednum >= ARRAY_SIZE(wm8350->pmic.led) || lednum < 0) { |
0081e802 MB |
1364 | dev_err(wm8350->dev, "Invalid LED index %d\n", lednum); |
1365 | return -ENODEV; | |
1366 | } | |
1367 | ||
1368 | led = &wm8350->pmic.led[lednum]; | |
1369 | ||
1370 | if (led->pdev) { | |
1371 | dev_err(wm8350->dev, "LED %d already allocated\n", lednum); | |
1372 | return -EINVAL; | |
1373 | } | |
1374 | ||
1375 | pdev = platform_device_alloc("wm8350-led", lednum); | |
1376 | if (pdev == NULL) { | |
1377 | dev_err(wm8350->dev, "Failed to allocate LED %d\n", lednum); | |
1378 | return -ENOMEM; | |
1379 | } | |
1380 | ||
34ce8d07 | 1381 | led->isink_consumer.dev_name = dev_name(&pdev->dev); |
0081e802 MB |
1382 | led->isink_consumer.supply = "led_isink"; |
1383 | led->isink_init.num_consumer_supplies = 1; | |
1384 | led->isink_init.consumer_supplies = &led->isink_consumer; | |
1385 | led->isink_init.constraints.min_uA = 0; | |
1386 | led->isink_init.constraints.max_uA = pdata->max_uA; | |
a2fad9bf MB |
1387 | led->isink_init.constraints.valid_ops_mask |
1388 | = REGULATOR_CHANGE_CURRENT | REGULATOR_CHANGE_STATUS; | |
0081e802 MB |
1389 | led->isink_init.constraints.valid_modes_mask = REGULATOR_MODE_NORMAL; |
1390 | ret = wm8350_register_regulator(wm8350, isink, &led->isink_init); | |
1391 | if (ret != 0) { | |
1392 | platform_device_put(pdev); | |
1393 | return ret; | |
1394 | } | |
1395 | ||
34ce8d07 | 1396 | led->dcdc_consumer.dev_name = dev_name(&pdev->dev); |
0081e802 MB |
1397 | led->dcdc_consumer.supply = "led_vcc"; |
1398 | led->dcdc_init.num_consumer_supplies = 1; | |
1399 | led->dcdc_init.consumer_supplies = &led->dcdc_consumer; | |
1400 | led->dcdc_init.constraints.valid_modes_mask = REGULATOR_MODE_NORMAL; | |
a2fad9bf | 1401 | led->dcdc_init.constraints.valid_ops_mask = REGULATOR_CHANGE_STATUS; |
0081e802 MB |
1402 | ret = wm8350_register_regulator(wm8350, dcdc, &led->dcdc_init); |
1403 | if (ret != 0) { | |
1404 | platform_device_put(pdev); | |
1405 | return ret; | |
1406 | } | |
1407 | ||
1408 | switch (isink) { | |
1409 | case WM8350_ISINK_A: | |
1410 | wm8350->pmic.isink_A_dcdc = dcdc; | |
1411 | break; | |
1412 | case WM8350_ISINK_B: | |
1413 | wm8350->pmic.isink_B_dcdc = dcdc; | |
1414 | break; | |
1415 | } | |
1416 | ||
1417 | pdev->dev.platform_data = pdata; | |
1418 | pdev->dev.parent = wm8350->dev; | |
1419 | ret = platform_device_add(pdev); | |
1420 | if (ret != 0) { | |
1421 | dev_err(wm8350->dev, "Failed to register LED %d: %d\n", | |
1422 | lednum, ret); | |
1423 | platform_device_put(pdev); | |
1424 | return ret; | |
1425 | } | |
1426 | ||
1427 | led->pdev = pdev; | |
1428 | ||
1429 | return 0; | |
1430 | } | |
1431 | EXPORT_SYMBOL_GPL(wm8350_register_led); | |
1432 | ||
da09155a MB |
1433 | static struct platform_driver wm8350_regulator_driver = { |
1434 | .probe = wm8350_regulator_probe, | |
1435 | .remove = wm8350_regulator_remove, | |
1436 | .driver = { | |
1437 | .name = "wm8350-regulator", | |
1438 | }, | |
1439 | }; | |
1440 | ||
1441 | static int __init wm8350_regulator_init(void) | |
1442 | { | |
1443 | return platform_driver_register(&wm8350_regulator_driver); | |
1444 | } | |
1445 | subsys_initcall(wm8350_regulator_init); | |
1446 | ||
1447 | static void __exit wm8350_regulator_exit(void) | |
1448 | { | |
1449 | platform_driver_unregister(&wm8350_regulator_driver); | |
1450 | } | |
1451 | module_exit(wm8350_regulator_exit); | |
1452 | ||
1453 | /* Module information */ | |
1454 | MODULE_AUTHOR("Liam Girdwood"); | |
1455 | MODULE_DESCRIPTION("WM8350 voltage and current regulator driver"); | |
1456 | MODULE_LICENSE("GPL"); | |
38c53c89 | 1457 | MODULE_ALIAS("platform:wm8350-regulator"); |