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Linux 3.6-rc4
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / regulator / wm831x-dcdc.c
CommitLineData
e4ee831f
MB		 1/*
2 * wm831x-dcdc.c -- DC-DC buck convertor driver for the WM831x series
3 *
4 * Copyright 2009 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/bitops.h>
18#include <linux/err.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
21#include <linux/regulator/driver.h>
e24a04c4
MB		 22#include <linux/regulator/machine.h>
23#include <linux/gpio.h>
5a0e3ad6 24#include <linux/slab.h>
e4ee831f
MB		 25
26#include <linux/mfd/wm831x/core.h>
27#include <linux/mfd/wm831x/regulator.h>
28#include <linux/mfd/wm831x/pdata.h>
29
30#define WM831X_BUCKV_MAX_SELECTOR 0x68
31#define WM831X_BUCKP_MAX_SELECTOR 0x66
32
33#define WM831X_DCDC_MODE_FAST 0
34#define WM831X_DCDC_MODE_NORMAL 1
35#define WM831X_DCDC_MODE_IDLE 2
36#define WM831X_DCDC_MODE_STANDBY 3
37
82caa978 38#define WM831X_DCDC_MAX_NAME 9
e4ee831f
MB		 39
40/* Register offsets in control block */
41#define WM831X_DCDC_CONTROL_1 0
42#define WM831X_DCDC_CONTROL_2 1
43#define WM831X_DCDC_ON_CONFIG 2
44#define WM831X_DCDC_SLEEP_CONTROL 3
e24a04c4 45#define WM831X_DCDC_DVS_CONTROL 4
e4ee831f
MB		 46
47/*
48 * Shared
49 */
50
51struct wm831x_dcdc {
52 char name[WM831X_DCDC_MAX_NAME];
82caa978 53 char supply_name[WM831X_DCDC_MAX_NAME];
e4ee831f
MB		 54 struct regulator_desc desc;
55 int base;
56 struct wm831x *wm831x;
57 struct regulator_dev *regulator;
e24a04c4
MB		 58 int dvs_gpio;
59 int dvs_gpio_state;
60 int on_vsel;
61 int dvs_vsel;
e4ee831f
MB		 62};
63
e4ee831f
MB		 64static unsigned int wm831x_dcdc_get_mode(struct regulator_dev *rdev)
65
66{
67 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
68 struct wm831x *wm831x = dcdc->wm831x;
69 u16 reg = dcdc->base + WM831X_DCDC_ON_CONFIG;
70 int val;
71
72 val = wm831x_reg_read(wm831x, reg);
73 if (val < 0)
74 return val;
75
76 val = (val & WM831X_DC1_ON_MODE_MASK) >> WM831X_DC1_ON_MODE_SHIFT;
77
78 switch (val) {
79 case WM831X_DCDC_MODE_FAST:
80 return REGULATOR_MODE_FAST;
81 case WM831X_DCDC_MODE_NORMAL:
82 return REGULATOR_MODE_NORMAL;
83 case WM831X_DCDC_MODE_STANDBY:
84 return REGULATOR_MODE_STANDBY;
85 case WM831X_DCDC_MODE_IDLE:
86 return REGULATOR_MODE_IDLE;
87 default:
88 BUG();
9ee291a4 89 return -EINVAL;
e4ee831f
MB		 90 }
91}
92
93static int wm831x_dcdc_set_mode_int(struct wm831x *wm831x, int reg,
94 unsigned int mode)
95{
96 int val;
97
98 switch (mode) {
99 case REGULATOR_MODE_FAST:
100 val = WM831X_DCDC_MODE_FAST;
101 break;
102 case REGULATOR_MODE_NORMAL:
103 val = WM831X_DCDC_MODE_NORMAL;
104 break;
105 case REGULATOR_MODE_STANDBY:
106 val = WM831X_DCDC_MODE_STANDBY;
107 break;
108 case REGULATOR_MODE_IDLE:
109 val = WM831X_DCDC_MODE_IDLE;
110 break;
111 default:
112 return -EINVAL;
113 }
114
115 return wm831x_set_bits(wm831x, reg, WM831X_DC1_ON_MODE_MASK,
116 val << WM831X_DC1_ON_MODE_SHIFT);
117}
118
119static int wm831x_dcdc_set_mode(struct regulator_dev *rdev, unsigned int mode)
120{
121 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
122 struct wm831x *wm831x = dcdc->wm831x;
123 u16 reg = dcdc->base + WM831X_DCDC_ON_CONFIG;
124
125 return wm831x_dcdc_set_mode_int(wm831x, reg, mode);
126}
127
128static int wm831x_dcdc_set_suspend_mode(struct regulator_dev *rdev,
129 unsigned int mode)
130{
131 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
132 struct wm831x *wm831x = dcdc->wm831x;
133 u16 reg = dcdc->base + WM831X_DCDC_SLEEP_CONTROL;
134
135 return wm831x_dcdc_set_mode_int(wm831x, reg, mode);
136}
137
138static int wm831x_dcdc_get_status(struct regulator_dev *rdev)
139{
140 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
141 struct wm831x *wm831x = dcdc->wm831x;
142 int ret;
143
144 /* First, check for errors */
145 ret = wm831x_reg_read(wm831x, WM831X_DCDC_UV_STATUS);
146 if (ret < 0)
147 return ret;
148
149 if (ret & (1 << rdev_get_id(rdev))) {
150 dev_dbg(wm831x->dev, "DCDC%d under voltage\n",
151 rdev_get_id(rdev) + 1);
152 return REGULATOR_STATUS_ERROR;
153 }
154
155 /* DCDC1 and DCDC2 can additionally detect high voltage/current */
156 if (rdev_get_id(rdev) < 2) {
157 if (ret & (WM831X_DC1_OV_STS << rdev_get_id(rdev))) {
158 dev_dbg(wm831x->dev, "DCDC%d over voltage\n",
159 rdev_get_id(rdev) + 1);
160 return REGULATOR_STATUS_ERROR;
161 }
162
163 if (ret & (WM831X_DC1_HC_STS << rdev_get_id(rdev))) {
164 dev_dbg(wm831x->dev, "DCDC%d over current\n",
165 rdev_get_id(rdev) + 1);
166 return REGULATOR_STATUS_ERROR;
167 }
168 }
169
170 /* Is the regulator on? */
171 ret = wm831x_reg_read(wm831x, WM831X_DCDC_STATUS);
172 if (ret < 0)
173 return ret;
174 if (!(ret & (1 << rdev_get_id(rdev))))
175 return REGULATOR_STATUS_OFF;
176
177 /* TODO: When we handle hardware control modes so we can report the
178 * current mode. */
179 return REGULATOR_STATUS_ON;
180}
181
182static irqreturn_t wm831x_dcdc_uv_irq(int irq, void *data)
183{
184 struct wm831x_dcdc *dcdc = data;
185
186 regulator_notifier_call_chain(dcdc->regulator,
187 REGULATOR_EVENT_UNDER_VOLTAGE,
188 NULL);
189
190 return IRQ_HANDLED;
191}
192
193static irqreturn_t wm831x_dcdc_oc_irq(int irq, void *data)
194{
195 struct wm831x_dcdc *dcdc = data;
196
197 regulator_notifier_call_chain(dcdc->regulator,
198 REGULATOR_EVENT_OVER_CURRENT,
199 NULL);
200
201 return IRQ_HANDLED;
202}
203
204/*
205 * BUCKV specifics
206 */
207
208static int wm831x_buckv_list_voltage(struct regulator_dev *rdev,
209 unsigned selector)
210{
211 if (selector <= 0x8)
212 return 600000;
213 if (selector <= WM831X_BUCKV_MAX_SELECTOR)
214 return 600000 + ((selector - 0x8) * 12500);
215 return -EINVAL;
216}
217
b5fb77e0
AL		 218static int wm831x_buckv_map_voltage(struct regulator_dev *rdev,
219 int min_uV, int max_uV)
e4ee831f 220{
e4ee831f
MB		 221 u16 vsel;
222
223 if (min_uV < 600000)
224 vsel = 0;
225 else if (min_uV <= 1800000)
226 vsel = ((min_uV - 600000) / 12500) + 8;
227 else
228 return -EINVAL;
229
230 if (wm831x_buckv_list_voltage(rdev, vsel) > max_uV)
231 return -EINVAL;
232
e24a04c4
MB		 233 return vsel;
234}
235
e24a04c4
MB		 236static int wm831x_buckv_set_dvs(struct regulator_dev *rdev, int state)
237{
238 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
239
240 if (state == dcdc->dvs_gpio_state)
241 return 0;
242
243 dcdc->dvs_gpio_state = state;
244 gpio_set_value(dcdc->dvs_gpio, state);
245
246 /* Should wait for DVS state change to be asserted if we have
247 * a GPIO for it, for now assume the device is configured
248 * for the fastest possible transition.
249 */
250
251 return 0;
e4ee831f
MB		 252}
253
b5fb77e0
AL		 254static int wm831x_buckv_set_voltage_sel(struct regulator_dev *rdev,
255 unsigned vsel)
e4ee831f
MB		 256{
257 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
e24a04c4
MB		 258 struct wm831x *wm831x = dcdc->wm831x;
259 int on_reg = dcdc->base + WM831X_DCDC_ON_CONFIG;
260 int dvs_reg = dcdc->base + WM831X_DCDC_DVS_CONTROL;
b5fb77e0 261 int ret;
3a93f2a9 262
e24a04c4
MB		 263 /* If this value is already set then do a GPIO update if we can */
264 if (dcdc->dvs_gpio && dcdc->on_vsel == vsel)
265 return wm831x_buckv_set_dvs(rdev, 0);
266
267 if (dcdc->dvs_gpio && dcdc->dvs_vsel == vsel)
268 return wm831x_buckv_set_dvs(rdev, 1);
269
270 /* Always set the ON status to the minimum voltage */
271 ret = wm831x_set_bits(wm831x, on_reg, WM831X_DC1_ON_VSEL_MASK, vsel);
272 if (ret < 0)
273 return ret;
274 dcdc->on_vsel = vsel;
275
276 if (!dcdc->dvs_gpio)
277 return ret;
278
279 /* Kick the voltage transition now */
280 ret = wm831x_buckv_set_dvs(rdev, 0);
281 if (ret < 0)
282 return ret;
283
88cda60e
MB		 284 /*
285 * If this VSEL is higher than the last one we've seen then
286 * remember it as the DVS VSEL. This is optimised for CPUfreq
287 * usage where we want to get to the highest voltage very
288 * quickly.
289 */
290 if (vsel > dcdc->dvs_vsel) {
291 ret = wm831x_set_bits(wm831x, dvs_reg,
292 WM831X_DC1_DVS_VSEL_MASK,
293 dcdc->dvs_vsel);
294 if (ret == 0)
295 dcdc->dvs_vsel = vsel;
296 else
297 dev_warn(wm831x->dev,
298 "Failed to set DCDC DVS VSEL: %d\n", ret);
e24a04c4
MB		 299 }
300
e24a04c4 301 return 0;
e4ee831f
MB		 302}
303
304static int wm831x_buckv_set_suspend_voltage(struct regulator_dev *rdev,
e24a04c4 305 int uV)
e4ee831f
MB		 306{
307 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
e24a04c4 308 struct wm831x *wm831x = dcdc->wm831x;
e4ee831f 309 u16 reg = dcdc->base + WM831X_DCDC_SLEEP_CONTROL;
e24a04c4
MB		 310 int vsel;
311
b5fb77e0 312 vsel = wm831x_buckv_map_voltage(rdev, uV, uV);
e24a04c4
MB		 313 if (vsel < 0)
314 return vsel;
e4ee831f 315
e24a04c4 316 return wm831x_set_bits(wm831x, reg, WM831X_DC1_SLP_VSEL_MASK, vsel);
e4ee831f
MB		 317}
318
afb8bb80 319static int wm831x_buckv_get_voltage_sel(struct regulator_dev *rdev)
e4ee831f
MB		 320{
321 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
e4ee831f 322
e24a04c4 323 if (dcdc->dvs_gpio && dcdc->dvs_gpio_state)
afb8bb80 324 return dcdc->dvs_vsel;
e24a04c4 325 else
afb8bb80 326 return dcdc->on_vsel;
e4ee831f
MB		 327}
328
329/* Current limit options */
330static u16 wm831x_dcdc_ilim[] = {
331 125, 250, 375, 500, 625, 750, 875, 1000
332};
333
334static int wm831x_buckv_set_current_limit(struct regulator_dev *rdev,
335 int min_uA, int max_uA)
336{
337 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
338 struct wm831x *wm831x = dcdc->wm831x;
339 u16 reg = dcdc->base + WM831X_DCDC_CONTROL_2;
340 int i;
341
342 for (i = 0; i < ARRAY_SIZE(wm831x_dcdc_ilim); i++) {
a171e782
AL		 343 if ((min_uA <= wm831x_dcdc_ilim[i]) &&
344 (wm831x_dcdc_ilim[i] <= max_uA))
e4ee831f
MB		 345 break;
346 }
347 if (i == ARRAY_SIZE(wm831x_dcdc_ilim))
348 return -EINVAL;
349
09bf14b9
AL		 350 return wm831x_set_bits(wm831x, reg, WM831X_DC1_HC_THR_MASK,
351 i << WM831X_DC1_HC_THR_SHIFT);
e4ee831f
MB		 352}
353
354static int wm831x_buckv_get_current_limit(struct regulator_dev *rdev)
355{
356 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
357 struct wm831x *wm831x = dcdc->wm831x;
358 u16 reg = dcdc->base + WM831X_DCDC_CONTROL_2;
359 int val;
360
361 val = wm831x_reg_read(wm831x, reg);
362 if (val < 0)
363 return val;
364
09bf14b9
AL		 365 val = (val & WM831X_DC1_HC_THR_MASK) >> WM831X_DC1_HC_THR_SHIFT;
366 return wm831x_dcdc_ilim[val];
e4ee831f
MB		 367}
368
369static struct regulator_ops wm831x_buckv_ops = {
b5fb77e0 370 .set_voltage_sel = wm831x_buckv_set_voltage_sel,
afb8bb80 371 .get_voltage_sel = wm831x_buckv_get_voltage_sel,
e4ee831f 372 .list_voltage = wm831x_buckv_list_voltage,
b5fb77e0 373 .map_voltage = wm831x_buckv_map_voltage,
e4ee831f
MB		 374 .set_suspend_voltage = wm831x_buckv_set_suspend_voltage,
375 .set_current_limit = wm831x_buckv_set_current_limit,
376 .get_current_limit = wm831x_buckv_get_current_limit,
377
3d138fcc
MB		 378 .is_enabled = regulator_is_enabled_regmap,
379 .enable = regulator_enable_regmap,
380 .disable = regulator_disable_regmap,
e4ee831f
MB		 381 .get_status = wm831x_dcdc_get_status,
382 .get_mode = wm831x_dcdc_get_mode,
383 .set_mode = wm831x_dcdc_set_mode,
384 .set_suspend_mode = wm831x_dcdc_set_suspend_mode,
385};
386
e24a04c4
MB		 387/*
388 * Set up DVS control. We just log errors since we can still run
389 * (with reduced performance) if we fail.
390 */
391static __devinit void wm831x_buckv_dvs_init(struct wm831x_dcdc *dcdc,
392 struct wm831x_buckv_pdata *pdata)
393{
394 struct wm831x *wm831x = dcdc->wm831x;
395 int ret;
396 u16 ctrl;
397
398 if (!pdata || !pdata->dvs_gpio)
399 return;
400
e24a04c4
MB		 401 /* gpiolib won't let us read the GPIO status so pick the higher
402 * of the two existing voltages so we take it as platform data.
403 */
404 dcdc->dvs_gpio_state = pdata->dvs_init_state;
405
053fa1b7
MB		 406 ret = gpio_request_one(pdata->dvs_gpio,
407 dcdc->dvs_gpio_state ? GPIOF_INIT_HIGH : 0,
408 "DCDC DVS");
e24a04c4 409 if (ret < 0) {
053fa1b7 410 dev_err(wm831x->dev, "Failed to get %s DVS GPIO: %d\n",
e24a04c4 411 dcdc->name, ret);
e24a04c4
MB		 412 return;
413 }
414
415 dcdc->dvs_gpio = pdata->dvs_gpio;
b47ba9fd
MB		 416
417 switch (pdata->dvs_control_src) {
418 case 1:
419 ctrl = 2 << WM831X_DC1_DVS_SRC_SHIFT;
420 break;
421 case 2:
422 ctrl = 3 << WM831X_DC1_DVS_SRC_SHIFT;
423 break;
424 default:
425 dev_err(wm831x->dev, "Invalid DVS control source %d for %s\n",
426 pdata->dvs_control_src, dcdc->name);
427 return;
428 }
429
c439b8f4
MB		 430 /* If DVS_VSEL is set to the minimum value then raise it to ON_VSEL
431 * to make bootstrapping a bit smoother.
432 */
433 if (!dcdc->dvs_vsel) {
434 ret = wm831x_set_bits(wm831x,
435 dcdc->base + WM831X_DCDC_DVS_CONTROL,
436 WM831X_DC1_DVS_VSEL_MASK, dcdc->on_vsel);
437 if (ret == 0)
438 dcdc->dvs_vsel = dcdc->on_vsel;
439 else
440 dev_warn(wm831x->dev, "Failed to set DVS_VSEL: %d\n",
441 ret);
442 }
443
b47ba9fd
MB		 444 ret = wm831x_set_bits(wm831x, dcdc->base + WM831X_DCDC_DVS_CONTROL,
445 WM831X_DC1_DVS_SRC_MASK, ctrl);
446 if (ret < 0) {
447 dev_err(wm831x->dev, "Failed to set %s DVS source: %d\n",
448 dcdc->name, ret);
449 }
e24a04c4
MB		 450}
451
e4ee831f
MB		 452static __devinit int wm831x_buckv_probe(struct platform_device *pdev)
453{
454 struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
455 struct wm831x_pdata *pdata = wm831x->dev->platform_data;
c172708d 456 struct regulator_config config = { };
137a6354 457 int id;
e4ee831f
MB		 458 struct wm831x_dcdc *dcdc;
459 struct resource *res;
460 int ret, irq;
461
137a6354
MB		 462 if (pdata && pdata->wm831x_num)
463 id = (pdata->wm831x_num * 10) + 1;
464 else
465 id = 0;
466 id = pdev->id - id;
467
e4ee831f
MB		 468 dev_dbg(&pdev->dev, "Probing DCDC%d\n", id + 1);
469
fded2f4f
MB		 470 dcdc = devm_kzalloc(&pdev->dev, sizeof(struct wm831x_dcdc),
471 GFP_KERNEL);
e4ee831f
MB		 472 if (dcdc == NULL) {
473 dev_err(&pdev->dev, "Unable to allocate private data\n");
474 return -ENOMEM;
475 }
476
477 dcdc->wm831x = wm831x;
478
479 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
480 if (res == NULL) {
481 dev_err(&pdev->dev, "No I/O resource\n");
482 ret = -EINVAL;
483 goto err;
484 }
485 dcdc->base = res->start;
486
487 snprintf(dcdc->name, sizeof(dcdc->name), "DCDC%d", id + 1);
488 dcdc->desc.name = dcdc->name;
82caa978
MB		 489
490 snprintf(dcdc->supply_name, sizeof(dcdc->supply_name),
491 "DC%dVDD", id + 1);
492 dcdc->desc.supply_name = dcdc->supply_name;
493
e4ee831f
MB		 494 dcdc->desc.id = id;
495 dcdc->desc.type = REGULATOR_VOLTAGE;
496 dcdc->desc.n_voltages = WM831X_BUCKV_MAX_SELECTOR + 1;
497 dcdc->desc.ops = &wm831x_buckv_ops;
498 dcdc->desc.owner = THIS_MODULE;
3d138fcc
MB		 499 dcdc->desc.enable_reg = WM831X_DCDC_ENABLE;
500 dcdc->desc.enable_mask = 1 << id;
e4ee831f 501
e24a04c4
MB		 502 ret = wm831x_reg_read(wm831x, dcdc->base + WM831X_DCDC_ON_CONFIG);
503 if (ret < 0) {
504 dev_err(wm831x->dev, "Failed to read ON VSEL: %d\n", ret);
505 goto err;
506 }
507 dcdc->on_vsel = ret & WM831X_DC1_ON_VSEL_MASK;
508
a1b81dd3 509 ret = wm831x_reg_read(wm831x, dcdc->base + WM831X_DCDC_DVS_CONTROL);
e24a04c4
MB		 510 if (ret < 0) {
511 dev_err(wm831x->dev, "Failed to read DVS VSEL: %d\n", ret);
512 goto err;
513 }
514 dcdc->dvs_vsel = ret & WM831X_DC1_DVS_VSEL_MASK;
515
f0b067d9 516 if (pdata && pdata->dcdc[id])
e24a04c4
MB		 517 wm831x_buckv_dvs_init(dcdc, pdata->dcdc[id]->driver_data);
518
c172708d 519 config.dev = pdev->dev.parent;
b7ca8788
MB		 520 if (pdata)
521 config.init_data = pdata->dcdc[id];
c172708d 522 config.driver_data = dcdc;
3d138fcc 523 config.regmap = wm831x->regmap;
c172708d
MB		 524
525 dcdc->regulator = regulator_register(&dcdc->desc, &config);
e4ee831f
MB		 526 if (IS_ERR(dcdc->regulator)) {
527 ret = PTR_ERR(dcdc->regulator);
528 dev_err(wm831x->dev, "Failed to register DCDC%d: %d\n",
529 id + 1, ret);
530 goto err;
531 }
532
cd99758b 533 irq = wm831x_irq(wm831x, platform_get_irq_byname(pdev, "UV"));
dfda9c27
MB		 534 ret = request_threaded_irq(irq, NULL, wm831x_dcdc_uv_irq,
535 IRQF_TRIGGER_RISING, dcdc->name, dcdc);
e4ee831f
MB		 536 if (ret != 0) {
537 dev_err(&pdev->dev, "Failed to request UV IRQ %d: %d\n",
538 irq, ret);
539 goto err_regulator;
540 }
541
cd99758b 542 irq = wm831x_irq(wm831x, platform_get_irq_byname(pdev, "HC"));
dfda9c27
MB		 543 ret = request_threaded_irq(irq, NULL, wm831x_dcdc_oc_irq,
544 IRQF_TRIGGER_RISING, dcdc->name, dcdc);
e4ee831f
MB		 545 if (ret != 0) {
546 dev_err(&pdev->dev, "Failed to request HC IRQ %d: %d\n",
547 irq, ret);
548 goto err_uv;
549 }
550
551 platform_set_drvdata(pdev, dcdc);
552
553 return 0;
554
555err_uv:
cd99758b
MB		 556 free_irq(wm831x_irq(wm831x, platform_get_irq_byname(pdev, "UV")),
557 dcdc);
e4ee831f
MB		 558err_regulator:
559 regulator_unregister(dcdc->regulator);
560err:
e24a04c4
MB		 561 if (dcdc->dvs_gpio)
562 gpio_free(dcdc->dvs_gpio);
e4ee831f
MB		 563 return ret;
564}
565
566static __devexit int wm831x_buckv_remove(struct platform_device *pdev)
567{
568 struct wm831x_dcdc *dcdc = platform_get_drvdata(pdev);
cd99758b 569 struct wm831x *wm831x = dcdc->wm831x;
e4ee831f 570
eb66d565
DT		 571 platform_set_drvdata(pdev, NULL);
572
cd99758b
MB		 573 free_irq(wm831x_irq(wm831x, platform_get_irq_byname(pdev, "HC")),
574 dcdc);
575 free_irq(wm831x_irq(wm831x, platform_get_irq_byname(pdev, "UV")),
576 dcdc);
e4ee831f 577 regulator_unregister(dcdc->regulator);
e24a04c4
MB		 578 if (dcdc->dvs_gpio)
579 gpio_free(dcdc->dvs_gpio);
e4ee831f
MB		 580
581 return 0;
582}
583
584static struct platform_driver wm831x_buckv_driver = {
585 .probe = wm831x_buckv_probe,
586 .remove = __devexit_p(wm831x_buckv_remove),
587 .driver = {
588 .name = "wm831x-buckv",
eb66d565 589 .owner = THIS_MODULE,
e4ee831f
MB		 590 },
591};
592
593/*
594 * BUCKP specifics
595 */
596
d580cb5e 597static int wm831x_buckp_set_suspend_voltage(struct regulator_dev *rdev, int uV)
e4ee831f
MB		 598{
599 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
600 struct wm831x *wm831x = dcdc->wm831x;
e4ee831f 601 u16 reg = dcdc->base + WM831X_DCDC_SLEEP_CONTROL;
d580cb5e
AL		 602 int sel;
603
604 sel = regulator_map_voltage_linear(rdev, uV, uV);
605 if (sel < 0)
606 return sel;
e4ee831f 607
d580cb5e 608 return wm831x_set_bits(wm831x, reg, WM831X_DC3_ON_VSEL_MASK, sel);
e4ee831f
MB		 609}
610
e4ee831f 611static struct regulator_ops wm831x_buckp_ops = {
d580cb5e 612 .set_voltage_sel = regulator_set_voltage_sel_regmap,
817436e7 613 .get_voltage_sel = regulator_get_voltage_sel_regmap,
c70ad9dc 614 .list_voltage = regulator_list_voltage_linear,
d580cb5e 615 .map_voltage = regulator_map_voltage_linear,
e4ee831f
MB		 616 .set_suspend_voltage = wm831x_buckp_set_suspend_voltage,
617
3d138fcc
MB		 618 .is_enabled = regulator_is_enabled_regmap,
619 .enable = regulator_enable_regmap,
620 .disable = regulator_disable_regmap,
e4ee831f
MB		 621 .get_status = wm831x_dcdc_get_status,
622 .get_mode = wm831x_dcdc_get_mode,
623 .set_mode = wm831x_dcdc_set_mode,
624 .set_suspend_mode = wm831x_dcdc_set_suspend_mode,
625};
626
627static __devinit int wm831x_buckp_probe(struct platform_device *pdev)
628{
629 struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
630 struct wm831x_pdata *pdata = wm831x->dev->platform_data;
c172708d 631 struct regulator_config config = { };
137a6354 632 int id;
e4ee831f
MB		 633 struct wm831x_dcdc *dcdc;
634 struct resource *res;
635 int ret, irq;
636
137a6354
MB		 637 if (pdata && pdata->wm831x_num)
638 id = (pdata->wm831x_num * 10) + 1;
639 else
640 id = 0;
641 id = pdev->id - id;
642
e4ee831f
MB		 643 dev_dbg(&pdev->dev, "Probing DCDC%d\n", id + 1);
644
fded2f4f
MB		 645 dcdc = devm_kzalloc(&pdev->dev, sizeof(struct wm831x_dcdc),
646 GFP_KERNEL);
e4ee831f
MB		 647 if (dcdc == NULL) {
648 dev_err(&pdev->dev, "Unable to allocate private data\n");
649 return -ENOMEM;
650 }
651
652 dcdc->wm831x = wm831x;
653
654 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
655 if (res == NULL) {
656 dev_err(&pdev->dev, "No I/O resource\n");
657 ret = -EINVAL;
658 goto err;
659 }
660 dcdc->base = res->start;
661
662 snprintf(dcdc->name, sizeof(dcdc->name), "DCDC%d", id + 1);
663 dcdc->desc.name = dcdc->name;
82caa978
MB		 664
665 snprintf(dcdc->supply_name, sizeof(dcdc->supply_name),
666 "DC%dVDD", id + 1);
667 dcdc->desc.supply_name = dcdc->supply_name;
668
e4ee831f
MB		 669 dcdc->desc.id = id;
670 dcdc->desc.type = REGULATOR_VOLTAGE;
671 dcdc->desc.n_voltages = WM831X_BUCKP_MAX_SELECTOR + 1;
672 dcdc->desc.ops = &wm831x_buckp_ops;
673 dcdc->desc.owner = THIS_MODULE;
817436e7
MB		 674 dcdc->desc.vsel_reg = dcdc->base + WM831X_DCDC_ON_CONFIG;
675 dcdc->desc.vsel_mask = WM831X_DC3_ON_VSEL_MASK;
3d138fcc
MB		 676 dcdc->desc.enable_reg = WM831X_DCDC_ENABLE;
677 dcdc->desc.enable_mask = 1 << id;
c70ad9dc
AL		 678 dcdc->desc.min_uV = 850000;
679 dcdc->desc.uV_step = 25000;
e4ee831f 680
c172708d 681 config.dev = pdev->dev.parent;
b7ca8788
MB		 682 if (pdata)
683 config.init_data = pdata->dcdc[id];
c172708d 684 config.driver_data = dcdc;
817436e7 685 config.regmap = wm831x->regmap;
c172708d
MB		 686
687 dcdc->regulator = regulator_register(&dcdc->desc, &config);
e4ee831f
MB		 688 if (IS_ERR(dcdc->regulator)) {
689 ret = PTR_ERR(dcdc->regulator);
690 dev_err(wm831x->dev, "Failed to register DCDC%d: %d\n",
691 id + 1, ret);
692 goto err;
693 }
694
cd99758b 695 irq = wm831x_irq(wm831x, platform_get_irq_byname(pdev, "UV"));
dfda9c27
MB		 696 ret = request_threaded_irq(irq, NULL, wm831x_dcdc_uv_irq,
697 IRQF_TRIGGER_RISING, dcdc->name, dcdc);
e4ee831f
MB		 698 if (ret != 0) {
699 dev_err(&pdev->dev, "Failed to request UV IRQ %d: %d\n",
700 irq, ret);
701 goto err_regulator;
702 }
703
704 platform_set_drvdata(pdev, dcdc);
705
706 return 0;
707
708err_regulator:
709 regulator_unregister(dcdc->regulator);
710err:
e4ee831f
MB		 711 return ret;
712}
713
714static __devexit int wm831x_buckp_remove(struct platform_device *pdev)
715{
716 struct wm831x_dcdc *dcdc = platform_get_drvdata(pdev);
e4ee831f 717
eb66d565
DT		 718 platform_set_drvdata(pdev, NULL);
719
cd99758b
MB		 720 free_irq(wm831x_irq(dcdc->wm831x, platform_get_irq_byname(pdev, "UV")),
721 dcdc);
e4ee831f 722 regulator_unregister(dcdc->regulator);
e4ee831f
MB		 723
724 return 0;
725}
726
727static struct platform_driver wm831x_buckp_driver = {
728 .probe = wm831x_buckp_probe,
729 .remove = __devexit_p(wm831x_buckp_remove),
730 .driver = {
731 .name = "wm831x-buckp",
eb66d565 732 .owner = THIS_MODULE,
e4ee831f
MB		 733 },
734};
735
1304850d
MB		 736/*
737 * DCDC boost convertors
738 */
739
740static int wm831x_boostp_get_status(struct regulator_dev *rdev)
741{
742 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
743 struct wm831x *wm831x = dcdc->wm831x;
744 int ret;
745
746 /* First, check for errors */
747 ret = wm831x_reg_read(wm831x, WM831X_DCDC_UV_STATUS);
748 if (ret < 0)
749 return ret;
750
751 if (ret & (1 << rdev_get_id(rdev))) {
752 dev_dbg(wm831x->dev, "DCDC%d under voltage\n",
753 rdev_get_id(rdev) + 1);
754 return REGULATOR_STATUS_ERROR;
755 }
756
757 /* Is the regulator on? */
758 ret = wm831x_reg_read(wm831x, WM831X_DCDC_STATUS);
759 if (ret < 0)
760 return ret;
761 if (ret & (1 << rdev_get_id(rdev)))
762 return REGULATOR_STATUS_ON;
763 else
764 return REGULATOR_STATUS_OFF;
765}
766
767static struct regulator_ops wm831x_boostp_ops = {
768 .get_status = wm831x_boostp_get_status,
769
3d138fcc
MB		 770 .is_enabled = regulator_is_enabled_regmap,
771 .enable = regulator_enable_regmap,
772 .disable = regulator_disable_regmap,
1304850d
MB		 773};
774
775static __devinit int wm831x_boostp_probe(struct platform_device *pdev)
776{
777 struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
778 struct wm831x_pdata *pdata = wm831x->dev->platform_data;
c172708d 779 struct regulator_config config = { };
1304850d
MB		 780 int id = pdev->id % ARRAY_SIZE(pdata->dcdc);
781 struct wm831x_dcdc *dcdc;
782 struct resource *res;
783 int ret, irq;
784
785 dev_dbg(&pdev->dev, "Probing DCDC%d\n", id + 1);
786
787 if (pdata == NULL || pdata->dcdc[id] == NULL)
788 return -ENODEV;
789
4c60165d 790 dcdc = devm_kzalloc(&pdev->dev, sizeof(struct wm831x_dcdc), GFP_KERNEL);
1304850d
MB		 791 if (dcdc == NULL) {
792 dev_err(&pdev->dev, "Unable to allocate private data\n");
793 return -ENOMEM;
794 }
795
796 dcdc->wm831x = wm831x;
797
798 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
799 if (res == NULL) {
800 dev_err(&pdev->dev, "No I/O resource\n");
801 ret = -EINVAL;
802 goto err;
803 }
804 dcdc->base = res->start;
805
806 snprintf(dcdc->name, sizeof(dcdc->name), "DCDC%d", id + 1);
807 dcdc->desc.name = dcdc->name;
808 dcdc->desc.id = id;
809 dcdc->desc.type = REGULATOR_VOLTAGE;
810 dcdc->desc.ops = &wm831x_boostp_ops;
811 dcdc->desc.owner = THIS_MODULE;
3d138fcc
MB		 812 dcdc->desc.enable_reg = WM831X_DCDC_ENABLE;
813 dcdc->desc.enable_mask = 1 << id;
1304850d 814
c172708d 815 config.dev = pdev->dev.parent;
f0b067d9
MB		 816 if (pdata)
817 config.init_data = pdata->dcdc[id];
c172708d 818 config.driver_data = dcdc;
3d138fcc 819 config.regmap = wm831x->regmap;
c172708d
MB		 820
821 dcdc->regulator = regulator_register(&dcdc->desc, &config);
1304850d
MB		 822 if (IS_ERR(dcdc->regulator)) {
823 ret = PTR_ERR(dcdc->regulator);
824 dev_err(wm831x->dev, "Failed to register DCDC%d: %d\n",
825 id + 1, ret);
826 goto err;
827 }
828
cd99758b 829 irq = wm831x_irq(wm831x, platform_get_irq_byname(pdev, "UV"));
dfda9c27
MB		 830 ret = request_threaded_irq(irq, NULL, wm831x_dcdc_uv_irq,
831 IRQF_TRIGGER_RISING, dcdc->name,
832 dcdc);
1304850d
MB		 833 if (ret != 0) {
834 dev_err(&pdev->dev, "Failed to request UV IRQ %d: %d\n",
835 irq, ret);
836 goto err_regulator;
837 }
838
839 platform_set_drvdata(pdev, dcdc);
840
841 return 0;
842
843err_regulator:
844 regulator_unregister(dcdc->regulator);
845err:
1304850d
MB		 846 return ret;
847}
848
849static __devexit int wm831x_boostp_remove(struct platform_device *pdev)
850{
851 struct wm831x_dcdc *dcdc = platform_get_drvdata(pdev);
1304850d 852
eb66d565
DT		 853 platform_set_drvdata(pdev, NULL);
854
cd99758b
MB		 855 free_irq(wm831x_irq(dcdc->wm831x, platform_get_irq_byname(pdev, "UV")),
856 dcdc);
1304850d 857 regulator_unregister(dcdc->regulator);
1304850d
MB		 858
859 return 0;
860}
861
862static struct platform_driver wm831x_boostp_driver = {
863 .probe = wm831x_boostp_probe,
864 .remove = __devexit_p(wm831x_boostp_remove),
865 .driver = {
866 .name = "wm831x-boostp",
eb66d565 867 .owner = THIS_MODULE,
1304850d
MB		 868 },
869};
870
8267a9ba
MB		 871/*
872 * External Power Enable
873 *
874 * These aren't actually DCDCs but look like them in hardware so share
875 * code.
876 */
877
878#define WM831X_EPE_BASE 6
879
880static struct regulator_ops wm831x_epe_ops = {
3d138fcc
MB		 881 .is_enabled = regulator_is_enabled_regmap,
882 .enable = regulator_enable_regmap,
883 .disable = regulator_disable_regmap,
8267a9ba
MB		 884 .get_status = wm831x_dcdc_get_status,
885};
886
887static __devinit int wm831x_epe_probe(struct platform_device *pdev)
888{
889 struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
890 struct wm831x_pdata *pdata = wm831x->dev->platform_data;
c172708d 891 struct regulator_config config = { };
8267a9ba
MB		 892 int id = pdev->id % ARRAY_SIZE(pdata->epe);
893 struct wm831x_dcdc *dcdc;
894 int ret;
895
896 dev_dbg(&pdev->dev, "Probing EPE%d\n", id + 1);
897
4c60165d 898 dcdc = devm_kzalloc(&pdev->dev, sizeof(struct wm831x_dcdc), GFP_KERNEL);
8267a9ba
MB		 899 if (dcdc == NULL) {
900 dev_err(&pdev->dev, "Unable to allocate private data\n");
901 return -ENOMEM;
902 }
903
904 dcdc->wm831x = wm831x;
905
906 /* For current parts this is correct; probably need to revisit
907 * in future.
908 */
909 snprintf(dcdc->name, sizeof(dcdc->name), "EPE%d", id + 1);
910 dcdc->desc.name = dcdc->name;
911 dcdc->desc.id = id + WM831X_EPE_BASE; /* Offset in DCDC registers */
912 dcdc->desc.ops = &wm831x_epe_ops;
913 dcdc->desc.type = REGULATOR_VOLTAGE;
914 dcdc->desc.owner = THIS_MODULE;
3d138fcc
MB		 915 dcdc->desc.enable_reg = WM831X_DCDC_ENABLE;
916 dcdc->desc.enable_mask = 1 << dcdc->desc.id;
8267a9ba 917
c172708d 918 config.dev = pdev->dev.parent;
b7ca8788
MB		 919 if (pdata)
920 config.init_data = pdata->epe[id];
c172708d 921 config.driver_data = dcdc;
3d138fcc 922 config.regmap = wm831x->regmap;
c172708d
MB		 923
924 dcdc->regulator = regulator_register(&dcdc->desc, &config);
8267a9ba
MB		 925 if (IS_ERR(dcdc->regulator)) {
926 ret = PTR_ERR(dcdc->regulator);
927 dev_err(wm831x->dev, "Failed to register EPE%d: %d\n",
928 id + 1, ret);
929 goto err;
930 }
931
932 platform_set_drvdata(pdev, dcdc);
933
934 return 0;
935
936err:
8267a9ba
MB		 937 return ret;
938}
939
940static __devexit int wm831x_epe_remove(struct platform_device *pdev)
941{
942 struct wm831x_dcdc *dcdc = platform_get_drvdata(pdev);
943
eb66d565 944 platform_set_drvdata(pdev, NULL);
8267a9ba 945 regulator_unregister(dcdc->regulator);
8267a9ba
MB		 946
947 return 0;
948}
949
950static struct platform_driver wm831x_epe_driver = {
951 .probe = wm831x_epe_probe,
952 .remove = __devexit_p(wm831x_epe_remove),
953 .driver = {
954 .name = "wm831x-epe",
eb66d565 955 .owner = THIS_MODULE,
8267a9ba
MB		 956 },
957};
958
e4ee831f
MB		 959static int __init wm831x_dcdc_init(void)
960{
961 int ret;
962 ret = platform_driver_register(&wm831x_buckv_driver);
963 if (ret != 0)
964 pr_err("Failed to register WM831x BUCKV driver: %d\n", ret);
965
966 ret = platform_driver_register(&wm831x_buckp_driver);
967 if (ret != 0)
968 pr_err("Failed to register WM831x BUCKP driver: %d\n", ret);
969
1304850d
MB		 970 ret = platform_driver_register(&wm831x_boostp_driver);
971 if (ret != 0)
972 pr_err("Failed to register WM831x BOOST driver: %d\n", ret);
973
8267a9ba
MB		 974 ret = platform_driver_register(&wm831x_epe_driver);
975 if (ret != 0)
976 pr_err("Failed to register WM831x EPE driver: %d\n", ret);
977
e4ee831f
MB		 978 return 0;
979}
980subsys_initcall(wm831x_dcdc_init);
981
982static void __exit wm831x_dcdc_exit(void)
983{
8267a9ba 984 platform_driver_unregister(&wm831x_epe_driver);
1304850d 985 platform_driver_unregister(&wm831x_boostp_driver);
e4ee831f
MB		 986 platform_driver_unregister(&wm831x_buckp_driver);
987 platform_driver_unregister(&wm831x_buckv_driver);
988}
989module_exit(wm831x_dcdc_exit);
990
991/* Module information */
992MODULE_AUTHOR("Mark Brown");
993MODULE_DESCRIPTION("WM831x DC-DC convertor driver");
994MODULE_LICENSE("GPL");
995MODULE_ALIAS("platform:wm831x-buckv");
996MODULE_ALIAS("platform:wm831x-buckp");
24b43150 997MODULE_ALIAS("platform:wm831x-epe");
kernel source for telekom puls (alcatel/mediatek)