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518fb721 GG |
1 | /* |
2 | * tps65910.c -- TI tps65910 | |
3 | * | |
4 | * Copyright 2010 Texas Instruments Inc. | |
5 | * | |
6 | * Author: Graeme Gregory <gg@slimlogic.co.uk> | |
7 | * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License as published by the | |
11 | * Free Software Foundation; either version 2 of the License, or (at your | |
12 | * option) any later version. | |
13 | * | |
14 | */ | |
15 | ||
16 | #include <linux/kernel.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/err.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/regulator/driver.h> | |
22 | #include <linux/regulator/machine.h> | |
518fb721 GG |
23 | #include <linux/slab.h> |
24 | #include <linux/gpio.h> | |
25 | #include <linux/mfd/tps65910.h> | |
6790178f | 26 | #include <linux/regulator/of_regulator.h> |
518fb721 | 27 | |
518fb721 | 28 | #define TPS65910_SUPPLY_STATE_ENABLED 0x1 |
1e0c66f4 LD |
29 | #define EXT_SLEEP_CONTROL (TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1 | \ |
30 | TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2 | \ | |
f30b0716 LD |
31 | TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3 | \ |
32 | TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP) | |
518fb721 | 33 | |
91fe4d50 | 34 | /* supported VIO voltages in millivolts */ |
518fb721 GG |
35 | static const u16 VIO_VSEL_table[] = { |
36 | 1500, 1800, 2500, 3300, | |
37 | }; | |
38 | ||
a320e3c3 JEC |
39 | /* VSEL tables for TPS65910 specific LDOs and dcdc's */ |
40 | ||
91fe4d50 | 41 | /* supported VDD3 voltages in millivolts */ |
518fb721 GG |
42 | static const u16 VDD3_VSEL_table[] = { |
43 | 5000, | |
44 | }; | |
45 | ||
91fe4d50 | 46 | /* supported VDIG1 voltages in millivolts */ |
518fb721 GG |
47 | static const u16 VDIG1_VSEL_table[] = { |
48 | 1200, 1500, 1800, 2700, | |
49 | }; | |
50 | ||
91fe4d50 | 51 | /* supported VDIG2 voltages in millivolts */ |
518fb721 GG |
52 | static const u16 VDIG2_VSEL_table[] = { |
53 | 1000, 1100, 1200, 1800, | |
54 | }; | |
55 | ||
91fe4d50 | 56 | /* supported VPLL voltages in millivolts */ |
518fb721 GG |
57 | static const u16 VPLL_VSEL_table[] = { |
58 | 1000, 1100, 1800, 2500, | |
59 | }; | |
60 | ||
91fe4d50 | 61 | /* supported VDAC voltages in millivolts */ |
518fb721 GG |
62 | static const u16 VDAC_VSEL_table[] = { |
63 | 1800, 2600, 2800, 2850, | |
64 | }; | |
65 | ||
91fe4d50 | 66 | /* supported VAUX1 voltages in millivolts */ |
518fb721 GG |
67 | static const u16 VAUX1_VSEL_table[] = { |
68 | 1800, 2500, 2800, 2850, | |
69 | }; | |
70 | ||
91fe4d50 | 71 | /* supported VAUX2 voltages in millivolts */ |
518fb721 GG |
72 | static const u16 VAUX2_VSEL_table[] = { |
73 | 1800, 2800, 2900, 3300, | |
74 | }; | |
75 | ||
91fe4d50 | 76 | /* supported VAUX33 voltages in millivolts */ |
518fb721 GG |
77 | static const u16 VAUX33_VSEL_table[] = { |
78 | 1800, 2000, 2800, 3300, | |
79 | }; | |
80 | ||
91fe4d50 | 81 | /* supported VMMC voltages in millivolts */ |
518fb721 GG |
82 | static const u16 VMMC_VSEL_table[] = { |
83 | 1800, 2800, 3000, 3300, | |
84 | }; | |
85 | ||
86 | struct tps_info { | |
87 | const char *name; | |
7d38a3cb LD |
88 | u8 n_voltages; |
89 | const u16 *voltage_table; | |
0651eed5 | 90 | int enable_time_us; |
518fb721 GG |
91 | }; |
92 | ||
93 | static struct tps_info tps65910_regs[] = { | |
94 | { | |
33a6943d | 95 | .name = "vrtc", |
0651eed5 | 96 | .enable_time_us = 2200, |
518fb721 GG |
97 | }, |
98 | { | |
33a6943d | 99 | .name = "vio", |
7d38a3cb LD |
100 | .n_voltages = ARRAY_SIZE(VIO_VSEL_table), |
101 | .voltage_table = VIO_VSEL_table, | |
0651eed5 | 102 | .enable_time_us = 350, |
518fb721 GG |
103 | }, |
104 | { | |
33a6943d | 105 | .name = "vdd1", |
0651eed5 | 106 | .enable_time_us = 350, |
518fb721 GG |
107 | }, |
108 | { | |
33a6943d | 109 | .name = "vdd2", |
0651eed5 | 110 | .enable_time_us = 350, |
518fb721 GG |
111 | }, |
112 | { | |
33a6943d | 113 | .name = "vdd3", |
7d38a3cb LD |
114 | .n_voltages = ARRAY_SIZE(VDD3_VSEL_table), |
115 | .voltage_table = VDD3_VSEL_table, | |
0651eed5 | 116 | .enable_time_us = 200, |
518fb721 GG |
117 | }, |
118 | { | |
33a6943d | 119 | .name = "vdig1", |
7d38a3cb LD |
120 | .n_voltages = ARRAY_SIZE(VDIG1_VSEL_table), |
121 | .voltage_table = VDIG1_VSEL_table, | |
0651eed5 | 122 | .enable_time_us = 100, |
518fb721 GG |
123 | }, |
124 | { | |
33a6943d | 125 | .name = "vdig2", |
7d38a3cb LD |
126 | .n_voltages = ARRAY_SIZE(VDIG2_VSEL_table), |
127 | .voltage_table = VDIG2_VSEL_table, | |
0651eed5 | 128 | .enable_time_us = 100, |
518fb721 GG |
129 | }, |
130 | { | |
33a6943d | 131 | .name = "vpll", |
7d38a3cb LD |
132 | .n_voltages = ARRAY_SIZE(VPLL_VSEL_table), |
133 | .voltage_table = VPLL_VSEL_table, | |
0651eed5 | 134 | .enable_time_us = 100, |
518fb721 GG |
135 | }, |
136 | { | |
33a6943d | 137 | .name = "vdac", |
7d38a3cb LD |
138 | .n_voltages = ARRAY_SIZE(VDAC_VSEL_table), |
139 | .voltage_table = VDAC_VSEL_table, | |
0651eed5 | 140 | .enable_time_us = 100, |
518fb721 GG |
141 | }, |
142 | { | |
33a6943d | 143 | .name = "vaux1", |
7d38a3cb LD |
144 | .n_voltages = ARRAY_SIZE(VAUX1_VSEL_table), |
145 | .voltage_table = VAUX1_VSEL_table, | |
0651eed5 | 146 | .enable_time_us = 100, |
518fb721 GG |
147 | }, |
148 | { | |
33a6943d | 149 | .name = "vaux2", |
7d38a3cb LD |
150 | .n_voltages = ARRAY_SIZE(VAUX2_VSEL_table), |
151 | .voltage_table = VAUX2_VSEL_table, | |
0651eed5 | 152 | .enable_time_us = 100, |
518fb721 GG |
153 | }, |
154 | { | |
33a6943d | 155 | .name = "vaux33", |
7d38a3cb LD |
156 | .n_voltages = ARRAY_SIZE(VAUX33_VSEL_table), |
157 | .voltage_table = VAUX33_VSEL_table, | |
0651eed5 | 158 | .enable_time_us = 100, |
518fb721 GG |
159 | }, |
160 | { | |
33a6943d | 161 | .name = "vmmc", |
7d38a3cb LD |
162 | .n_voltages = ARRAY_SIZE(VMMC_VSEL_table), |
163 | .voltage_table = VMMC_VSEL_table, | |
0651eed5 | 164 | .enable_time_us = 100, |
518fb721 GG |
165 | }, |
166 | }; | |
167 | ||
a320e3c3 | 168 | static struct tps_info tps65911_regs[] = { |
c2f8efd7 | 169 | { |
33a6943d | 170 | .name = "vrtc", |
0651eed5 | 171 | .enable_time_us = 2200, |
c2f8efd7 | 172 | }, |
a320e3c3 | 173 | { |
33a6943d | 174 | .name = "vio", |
7d38a3cb LD |
175 | .n_voltages = ARRAY_SIZE(VIO_VSEL_table), |
176 | .voltage_table = VIO_VSEL_table, | |
0651eed5 | 177 | .enable_time_us = 350, |
a320e3c3 JEC |
178 | }, |
179 | { | |
33a6943d | 180 | .name = "vdd1", |
7d38a3cb | 181 | .n_voltages = 73, |
0651eed5 | 182 | .enable_time_us = 350, |
a320e3c3 JEC |
183 | }, |
184 | { | |
33a6943d | 185 | .name = "vdd2", |
7d38a3cb | 186 | .n_voltages = 73, |
0651eed5 | 187 | .enable_time_us = 350, |
a320e3c3 JEC |
188 | }, |
189 | { | |
33a6943d | 190 | .name = "vddctrl", |
7d38a3cb | 191 | .n_voltages = 65, |
0651eed5 | 192 | .enable_time_us = 900, |
a320e3c3 JEC |
193 | }, |
194 | { | |
33a6943d | 195 | .name = "ldo1", |
7d38a3cb | 196 | .n_voltages = 47, |
0651eed5 | 197 | .enable_time_us = 420, |
a320e3c3 JEC |
198 | }, |
199 | { | |
33a6943d | 200 | .name = "ldo2", |
7d38a3cb | 201 | .n_voltages = 47, |
0651eed5 | 202 | .enable_time_us = 420, |
a320e3c3 JEC |
203 | }, |
204 | { | |
33a6943d | 205 | .name = "ldo3", |
7d38a3cb | 206 | .n_voltages = 24, |
0651eed5 | 207 | .enable_time_us = 230, |
a320e3c3 JEC |
208 | }, |
209 | { | |
33a6943d | 210 | .name = "ldo4", |
7d38a3cb | 211 | .n_voltages = 47, |
0651eed5 | 212 | .enable_time_us = 230, |
a320e3c3 JEC |
213 | }, |
214 | { | |
33a6943d | 215 | .name = "ldo5", |
7d38a3cb | 216 | .n_voltages = 24, |
0651eed5 | 217 | .enable_time_us = 230, |
a320e3c3 JEC |
218 | }, |
219 | { | |
33a6943d | 220 | .name = "ldo6", |
7d38a3cb | 221 | .n_voltages = 24, |
0651eed5 | 222 | .enable_time_us = 230, |
a320e3c3 JEC |
223 | }, |
224 | { | |
33a6943d | 225 | .name = "ldo7", |
7d38a3cb | 226 | .n_voltages = 24, |
0651eed5 | 227 | .enable_time_us = 230, |
a320e3c3 JEC |
228 | }, |
229 | { | |
33a6943d | 230 | .name = "ldo8", |
7d38a3cb | 231 | .n_voltages = 24, |
0651eed5 | 232 | .enable_time_us = 230, |
a320e3c3 JEC |
233 | }, |
234 | }; | |
235 | ||
1e0c66f4 LD |
236 | #define EXT_CONTROL_REG_BITS(id, regs_offs, bits) (((regs_offs) << 8) | (bits)) |
237 | static unsigned int tps65910_ext_sleep_control[] = { | |
238 | 0, | |
239 | EXT_CONTROL_REG_BITS(VIO, 1, 0), | |
240 | EXT_CONTROL_REG_BITS(VDD1, 1, 1), | |
241 | EXT_CONTROL_REG_BITS(VDD2, 1, 2), | |
242 | EXT_CONTROL_REG_BITS(VDD3, 1, 3), | |
243 | EXT_CONTROL_REG_BITS(VDIG1, 0, 1), | |
244 | EXT_CONTROL_REG_BITS(VDIG2, 0, 2), | |
245 | EXT_CONTROL_REG_BITS(VPLL, 0, 6), | |
246 | EXT_CONTROL_REG_BITS(VDAC, 0, 7), | |
247 | EXT_CONTROL_REG_BITS(VAUX1, 0, 3), | |
248 | EXT_CONTROL_REG_BITS(VAUX2, 0, 4), | |
249 | EXT_CONTROL_REG_BITS(VAUX33, 0, 5), | |
250 | EXT_CONTROL_REG_BITS(VMMC, 0, 0), | |
251 | }; | |
252 | ||
253 | static unsigned int tps65911_ext_sleep_control[] = { | |
254 | 0, | |
255 | EXT_CONTROL_REG_BITS(VIO, 1, 0), | |
256 | EXT_CONTROL_REG_BITS(VDD1, 1, 1), | |
257 | EXT_CONTROL_REG_BITS(VDD2, 1, 2), | |
258 | EXT_CONTROL_REG_BITS(VDDCTRL, 1, 3), | |
259 | EXT_CONTROL_REG_BITS(LDO1, 0, 1), | |
260 | EXT_CONTROL_REG_BITS(LDO2, 0, 2), | |
261 | EXT_CONTROL_REG_BITS(LDO3, 0, 7), | |
262 | EXT_CONTROL_REG_BITS(LDO4, 0, 6), | |
263 | EXT_CONTROL_REG_BITS(LDO5, 0, 3), | |
264 | EXT_CONTROL_REG_BITS(LDO6, 0, 0), | |
265 | EXT_CONTROL_REG_BITS(LDO7, 0, 5), | |
266 | EXT_CONTROL_REG_BITS(LDO8, 0, 4), | |
267 | }; | |
268 | ||
518fb721 | 269 | struct tps65910_reg { |
39aa9b6e | 270 | struct regulator_desc *desc; |
518fb721 | 271 | struct tps65910 *mfd; |
39aa9b6e AL |
272 | struct regulator_dev **rdev; |
273 | struct tps_info **info; | |
518fb721 | 274 | struct mutex mutex; |
39aa9b6e | 275 | int num_regulators; |
518fb721 | 276 | int mode; |
a320e3c3 | 277 | int (*get_ctrl_reg)(int); |
1e0c66f4 LD |
278 | unsigned int *ext_sleep_control; |
279 | unsigned int board_ext_control[TPS65910_NUM_REGS]; | |
518fb721 GG |
280 | }; |
281 | ||
282 | static inline int tps65910_read(struct tps65910_reg *pmic, u8 reg) | |
283 | { | |
3f7e8275 | 284 | unsigned int val; |
518fb721 GG |
285 | int err; |
286 | ||
3f7e8275 | 287 | err = tps65910_reg_read(pmic->mfd, reg, &val); |
518fb721 GG |
288 | if (err) |
289 | return err; | |
290 | ||
291 | return val; | |
292 | } | |
293 | ||
518fb721 GG |
294 | static int tps65910_modify_bits(struct tps65910_reg *pmic, u8 reg, |
295 | u8 set_mask, u8 clear_mask) | |
296 | { | |
297 | int err, data; | |
298 | ||
299 | mutex_lock(&pmic->mutex); | |
300 | ||
301 | data = tps65910_read(pmic, reg); | |
302 | if (data < 0) { | |
303 | dev_err(pmic->mfd->dev, "Read from reg 0x%x failed\n", reg); | |
304 | err = data; | |
305 | goto out; | |
306 | } | |
307 | ||
308 | data &= ~clear_mask; | |
309 | data |= set_mask; | |
3f7e8275 | 310 | err = tps65910_reg_write(pmic->mfd, reg, data); |
518fb721 GG |
311 | if (err) |
312 | dev_err(pmic->mfd->dev, "Write for reg 0x%x failed\n", reg); | |
313 | ||
314 | out: | |
315 | mutex_unlock(&pmic->mutex); | |
316 | return err; | |
317 | } | |
318 | ||
3f7e8275 | 319 | static int tps65910_reg_read_locked(struct tps65910_reg *pmic, u8 reg) |
518fb721 GG |
320 | { |
321 | int data; | |
322 | ||
323 | mutex_lock(&pmic->mutex); | |
324 | ||
325 | data = tps65910_read(pmic, reg); | |
326 | if (data < 0) | |
327 | dev_err(pmic->mfd->dev, "Read from reg 0x%x failed\n", reg); | |
328 | ||
329 | mutex_unlock(&pmic->mutex); | |
330 | return data; | |
331 | } | |
332 | ||
3f7e8275 | 333 | static int tps65910_reg_write_locked(struct tps65910_reg *pmic, u8 reg, u8 val) |
518fb721 GG |
334 | { |
335 | int err; | |
336 | ||
337 | mutex_lock(&pmic->mutex); | |
338 | ||
3f7e8275 | 339 | err = tps65910_reg_write(pmic->mfd, reg, val); |
518fb721 GG |
340 | if (err < 0) |
341 | dev_err(pmic->mfd->dev, "Write for reg 0x%x failed\n", reg); | |
342 | ||
343 | mutex_unlock(&pmic->mutex); | |
344 | return err; | |
345 | } | |
346 | ||
347 | static int tps65910_get_ctrl_register(int id) | |
348 | { | |
349 | switch (id) { | |
350 | case TPS65910_REG_VRTC: | |
351 | return TPS65910_VRTC; | |
352 | case TPS65910_REG_VIO: | |
353 | return TPS65910_VIO; | |
354 | case TPS65910_REG_VDD1: | |
355 | return TPS65910_VDD1; | |
356 | case TPS65910_REG_VDD2: | |
357 | return TPS65910_VDD2; | |
358 | case TPS65910_REG_VDD3: | |
359 | return TPS65910_VDD3; | |
360 | case TPS65910_REG_VDIG1: | |
361 | return TPS65910_VDIG1; | |
362 | case TPS65910_REG_VDIG2: | |
363 | return TPS65910_VDIG2; | |
364 | case TPS65910_REG_VPLL: | |
365 | return TPS65910_VPLL; | |
366 | case TPS65910_REG_VDAC: | |
367 | return TPS65910_VDAC; | |
368 | case TPS65910_REG_VAUX1: | |
369 | return TPS65910_VAUX1; | |
370 | case TPS65910_REG_VAUX2: | |
371 | return TPS65910_VAUX2; | |
372 | case TPS65910_REG_VAUX33: | |
373 | return TPS65910_VAUX33; | |
374 | case TPS65910_REG_VMMC: | |
375 | return TPS65910_VMMC; | |
376 | default: | |
377 | return -EINVAL; | |
378 | } | |
379 | } | |
380 | ||
a320e3c3 JEC |
381 | static int tps65911_get_ctrl_register(int id) |
382 | { | |
383 | switch (id) { | |
384 | case TPS65910_REG_VRTC: | |
385 | return TPS65910_VRTC; | |
386 | case TPS65910_REG_VIO: | |
387 | return TPS65910_VIO; | |
388 | case TPS65910_REG_VDD1: | |
389 | return TPS65910_VDD1; | |
390 | case TPS65910_REG_VDD2: | |
391 | return TPS65910_VDD2; | |
392 | case TPS65911_REG_VDDCTRL: | |
393 | return TPS65911_VDDCTRL; | |
394 | case TPS65911_REG_LDO1: | |
395 | return TPS65911_LDO1; | |
396 | case TPS65911_REG_LDO2: | |
397 | return TPS65911_LDO2; | |
398 | case TPS65911_REG_LDO3: | |
399 | return TPS65911_LDO3; | |
400 | case TPS65911_REG_LDO4: | |
401 | return TPS65911_LDO4; | |
402 | case TPS65911_REG_LDO5: | |
403 | return TPS65911_LDO5; | |
404 | case TPS65911_REG_LDO6: | |
405 | return TPS65911_LDO6; | |
406 | case TPS65911_REG_LDO7: | |
407 | return TPS65911_LDO7; | |
408 | case TPS65911_REG_LDO8: | |
409 | return TPS65911_LDO8; | |
410 | default: | |
411 | return -EINVAL; | |
412 | } | |
413 | } | |
414 | ||
0651eed5 LD |
415 | static int tps65910_enable_time(struct regulator_dev *dev) |
416 | { | |
417 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
418 | int id = rdev_get_id(dev); | |
419 | return pmic->info[id]->enable_time_us; | |
420 | } | |
518fb721 GG |
421 | |
422 | static int tps65910_set_mode(struct regulator_dev *dev, unsigned int mode) | |
423 | { | |
424 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
425 | struct tps65910 *mfd = pmic->mfd; | |
426 | int reg, value, id = rdev_get_id(dev); | |
a320e3c3 JEC |
427 | |
428 | reg = pmic->get_ctrl_reg(id); | |
518fb721 GG |
429 | if (reg < 0) |
430 | return reg; | |
431 | ||
432 | switch (mode) { | |
433 | case REGULATOR_MODE_NORMAL: | |
434 | return tps65910_modify_bits(pmic, reg, LDO_ST_ON_BIT, | |
435 | LDO_ST_MODE_BIT); | |
436 | case REGULATOR_MODE_IDLE: | |
437 | value = LDO_ST_ON_BIT | LDO_ST_MODE_BIT; | |
3f7e8275 | 438 | return tps65910_reg_set_bits(mfd, reg, value); |
518fb721 | 439 | case REGULATOR_MODE_STANDBY: |
3f7e8275 | 440 | return tps65910_reg_clear_bits(mfd, reg, LDO_ST_ON_BIT); |
518fb721 GG |
441 | } |
442 | ||
443 | return -EINVAL; | |
444 | } | |
445 | ||
446 | static unsigned int tps65910_get_mode(struct regulator_dev *dev) | |
447 | { | |
448 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
449 | int reg, value, id = rdev_get_id(dev); | |
450 | ||
a320e3c3 | 451 | reg = pmic->get_ctrl_reg(id); |
518fb721 GG |
452 | if (reg < 0) |
453 | return reg; | |
454 | ||
3f7e8275 | 455 | value = tps65910_reg_read_locked(pmic, reg); |
518fb721 GG |
456 | if (value < 0) |
457 | return value; | |
458 | ||
58599393 | 459 | if (!(value & LDO_ST_ON_BIT)) |
518fb721 GG |
460 | return REGULATOR_MODE_STANDBY; |
461 | else if (value & LDO_ST_MODE_BIT) | |
462 | return REGULATOR_MODE_IDLE; | |
463 | else | |
464 | return REGULATOR_MODE_NORMAL; | |
465 | } | |
466 | ||
18039e0f | 467 | static int tps65910_get_voltage_dcdc_sel(struct regulator_dev *dev) |
518fb721 GG |
468 | { |
469 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
18039e0f | 470 | int id = rdev_get_id(dev); |
a320e3c3 | 471 | int opvsel = 0, srvsel = 0, vselmax = 0, mult = 0, sr = 0; |
518fb721 GG |
472 | |
473 | switch (id) { | |
474 | case TPS65910_REG_VDD1: | |
3f7e8275 RK |
475 | opvsel = tps65910_reg_read_locked(pmic, TPS65910_VDD1_OP); |
476 | mult = tps65910_reg_read_locked(pmic, TPS65910_VDD1); | |
518fb721 | 477 | mult = (mult & VDD1_VGAIN_SEL_MASK) >> VDD1_VGAIN_SEL_SHIFT; |
3f7e8275 | 478 | srvsel = tps65910_reg_read_locked(pmic, TPS65910_VDD1_SR); |
518fb721 GG |
479 | sr = opvsel & VDD1_OP_CMD_MASK; |
480 | opvsel &= VDD1_OP_SEL_MASK; | |
481 | srvsel &= VDD1_SR_SEL_MASK; | |
a320e3c3 | 482 | vselmax = 75; |
518fb721 GG |
483 | break; |
484 | case TPS65910_REG_VDD2: | |
3f7e8275 RK |
485 | opvsel = tps65910_reg_read_locked(pmic, TPS65910_VDD2_OP); |
486 | mult = tps65910_reg_read_locked(pmic, TPS65910_VDD2); | |
518fb721 | 487 | mult = (mult & VDD2_VGAIN_SEL_MASK) >> VDD2_VGAIN_SEL_SHIFT; |
3f7e8275 | 488 | srvsel = tps65910_reg_read_locked(pmic, TPS65910_VDD2_SR); |
518fb721 GG |
489 | sr = opvsel & VDD2_OP_CMD_MASK; |
490 | opvsel &= VDD2_OP_SEL_MASK; | |
491 | srvsel &= VDD2_SR_SEL_MASK; | |
a320e3c3 JEC |
492 | vselmax = 75; |
493 | break; | |
494 | case TPS65911_REG_VDDCTRL: | |
3f7e8275 RK |
495 | opvsel = tps65910_reg_read_locked(pmic, TPS65911_VDDCTRL_OP); |
496 | srvsel = tps65910_reg_read_locked(pmic, TPS65911_VDDCTRL_SR); | |
a320e3c3 JEC |
497 | sr = opvsel & VDDCTRL_OP_CMD_MASK; |
498 | opvsel &= VDDCTRL_OP_SEL_MASK; | |
499 | srvsel &= VDDCTRL_SR_SEL_MASK; | |
500 | vselmax = 64; | |
518fb721 GG |
501 | break; |
502 | } | |
503 | ||
504 | /* multiplier 0 == 1 but 2,3 normal */ | |
505 | if (!mult) | |
506 | mult=1; | |
507 | ||
508 | if (sr) { | |
a320e3c3 JEC |
509 | /* normalise to valid range */ |
510 | if (srvsel < 3) | |
511 | srvsel = 3; | |
512 | if (srvsel > vselmax) | |
513 | srvsel = vselmax; | |
18039e0f | 514 | return srvsel - 3; |
518fb721 GG |
515 | } else { |
516 | ||
a320e3c3 JEC |
517 | /* normalise to valid range*/ |
518 | if (opvsel < 3) | |
519 | opvsel = 3; | |
520 | if (opvsel > vselmax) | |
521 | opvsel = vselmax; | |
18039e0f | 522 | return opvsel - 3; |
518fb721 | 523 | } |
18039e0f | 524 | return -EINVAL; |
518fb721 GG |
525 | } |
526 | ||
1f904fd1 | 527 | static int tps65910_get_voltage_sel(struct regulator_dev *dev) |
518fb721 GG |
528 | { |
529 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
1f904fd1 | 530 | int reg, value, id = rdev_get_id(dev); |
518fb721 | 531 | |
a320e3c3 | 532 | reg = pmic->get_ctrl_reg(id); |
518fb721 GG |
533 | if (reg < 0) |
534 | return reg; | |
535 | ||
3f7e8275 | 536 | value = tps65910_reg_read_locked(pmic, reg); |
518fb721 GG |
537 | if (value < 0) |
538 | return value; | |
539 | ||
540 | switch (id) { | |
541 | case TPS65910_REG_VIO: | |
542 | case TPS65910_REG_VDIG1: | |
543 | case TPS65910_REG_VDIG2: | |
544 | case TPS65910_REG_VPLL: | |
545 | case TPS65910_REG_VDAC: | |
546 | case TPS65910_REG_VAUX1: | |
547 | case TPS65910_REG_VAUX2: | |
548 | case TPS65910_REG_VAUX33: | |
549 | case TPS65910_REG_VMMC: | |
550 | value &= LDO_SEL_MASK; | |
551 | value >>= LDO_SEL_SHIFT; | |
552 | break; | |
553 | default: | |
554 | return -EINVAL; | |
555 | } | |
556 | ||
1f904fd1 | 557 | return value; |
518fb721 GG |
558 | } |
559 | ||
560 | static int tps65910_get_voltage_vdd3(struct regulator_dev *dev) | |
561 | { | |
562 | return 5 * 1000 * 1000; | |
563 | } | |
564 | ||
1f904fd1 | 565 | static int tps65911_get_voltage_sel(struct regulator_dev *dev) |
a320e3c3 JEC |
566 | { |
567 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
1f904fd1 | 568 | int id = rdev_get_id(dev); |
a320e3c3 JEC |
569 | u8 value, reg; |
570 | ||
571 | reg = pmic->get_ctrl_reg(id); | |
572 | ||
3f7e8275 | 573 | value = tps65910_reg_read_locked(pmic, reg); |
a320e3c3 JEC |
574 | |
575 | switch (id) { | |
576 | case TPS65911_REG_LDO1: | |
577 | case TPS65911_REG_LDO2: | |
578 | case TPS65911_REG_LDO4: | |
579 | value &= LDO1_SEL_MASK; | |
580 | value >>= LDO_SEL_SHIFT; | |
a320e3c3 JEC |
581 | break; |
582 | case TPS65911_REG_LDO3: | |
583 | case TPS65911_REG_LDO5: | |
584 | case TPS65911_REG_LDO6: | |
585 | case TPS65911_REG_LDO7: | |
586 | case TPS65911_REG_LDO8: | |
587 | value &= LDO3_SEL_MASK; | |
588 | value >>= LDO_SEL_SHIFT; | |
a320e3c3 JEC |
589 | break; |
590 | case TPS65910_REG_VIO: | |
e882eae8 LD |
591 | value &= LDO_SEL_MASK; |
592 | value >>= LDO_SEL_SHIFT; | |
1f904fd1 | 593 | break; |
a320e3c3 JEC |
594 | default: |
595 | return -EINVAL; | |
596 | } | |
597 | ||
1f904fd1 | 598 | return value; |
a320e3c3 JEC |
599 | } |
600 | ||
94732b97 AL |
601 | static int tps65910_set_voltage_dcdc_sel(struct regulator_dev *dev, |
602 | unsigned selector) | |
518fb721 GG |
603 | { |
604 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
605 | int id = rdev_get_id(dev), vsel; | |
a320e3c3 | 606 | int dcdc_mult = 0; |
518fb721 | 607 | |
a320e3c3 JEC |
608 | switch (id) { |
609 | case TPS65910_REG_VDD1: | |
780dc9ba | 610 | dcdc_mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1; |
a320e3c3 JEC |
611 | if (dcdc_mult == 1) |
612 | dcdc_mult--; | |
780dc9ba | 613 | vsel = (selector % VDD1_2_NUM_VOLT_FINE) + 3; |
518fb721 | 614 | |
518fb721 GG |
615 | tps65910_modify_bits(pmic, TPS65910_VDD1, |
616 | (dcdc_mult << VDD1_VGAIN_SEL_SHIFT), | |
617 | VDD1_VGAIN_SEL_MASK); | |
3f7e8275 | 618 | tps65910_reg_write_locked(pmic, TPS65910_VDD1_OP, vsel); |
a320e3c3 JEC |
619 | break; |
620 | case TPS65910_REG_VDD2: | |
780dc9ba | 621 | dcdc_mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1; |
a320e3c3 JEC |
622 | if (dcdc_mult == 1) |
623 | dcdc_mult--; | |
780dc9ba | 624 | vsel = (selector % VDD1_2_NUM_VOLT_FINE) + 3; |
a320e3c3 | 625 | |
518fb721 GG |
626 | tps65910_modify_bits(pmic, TPS65910_VDD2, |
627 | (dcdc_mult << VDD2_VGAIN_SEL_SHIFT), | |
628 | VDD1_VGAIN_SEL_MASK); | |
3f7e8275 | 629 | tps65910_reg_write_locked(pmic, TPS65910_VDD2_OP, vsel); |
a320e3c3 JEC |
630 | break; |
631 | case TPS65911_REG_VDDCTRL: | |
c4632aed | 632 | vsel = selector + 3; |
3f7e8275 | 633 | tps65910_reg_write_locked(pmic, TPS65911_VDDCTRL_OP, vsel); |
518fb721 GG |
634 | } |
635 | ||
636 | return 0; | |
637 | } | |
638 | ||
94732b97 AL |
639 | static int tps65910_set_voltage_sel(struct regulator_dev *dev, |
640 | unsigned selector) | |
518fb721 GG |
641 | { |
642 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
643 | int reg, id = rdev_get_id(dev); | |
644 | ||
a320e3c3 | 645 | reg = pmic->get_ctrl_reg(id); |
518fb721 GG |
646 | if (reg < 0) |
647 | return reg; | |
648 | ||
649 | switch (id) { | |
650 | case TPS65910_REG_VIO: | |
651 | case TPS65910_REG_VDIG1: | |
652 | case TPS65910_REG_VDIG2: | |
653 | case TPS65910_REG_VPLL: | |
654 | case TPS65910_REG_VDAC: | |
655 | case TPS65910_REG_VAUX1: | |
656 | case TPS65910_REG_VAUX2: | |
657 | case TPS65910_REG_VAUX33: | |
658 | case TPS65910_REG_VMMC: | |
659 | return tps65910_modify_bits(pmic, reg, | |
660 | (selector << LDO_SEL_SHIFT), LDO_SEL_MASK); | |
661 | } | |
662 | ||
663 | return -EINVAL; | |
664 | } | |
665 | ||
94732b97 AL |
666 | static int tps65911_set_voltage_sel(struct regulator_dev *dev, |
667 | unsigned selector) | |
a320e3c3 JEC |
668 | { |
669 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
670 | int reg, id = rdev_get_id(dev); | |
671 | ||
672 | reg = pmic->get_ctrl_reg(id); | |
673 | if (reg < 0) | |
674 | return reg; | |
675 | ||
676 | switch (id) { | |
677 | case TPS65911_REG_LDO1: | |
678 | case TPS65911_REG_LDO2: | |
679 | case TPS65911_REG_LDO4: | |
680 | return tps65910_modify_bits(pmic, reg, | |
681 | (selector << LDO_SEL_SHIFT), LDO1_SEL_MASK); | |
682 | case TPS65911_REG_LDO3: | |
683 | case TPS65911_REG_LDO5: | |
684 | case TPS65911_REG_LDO6: | |
685 | case TPS65911_REG_LDO7: | |
686 | case TPS65911_REG_LDO8: | |
a320e3c3 JEC |
687 | return tps65910_modify_bits(pmic, reg, |
688 | (selector << LDO_SEL_SHIFT), LDO3_SEL_MASK); | |
e882eae8 LD |
689 | case TPS65910_REG_VIO: |
690 | return tps65910_modify_bits(pmic, reg, | |
691 | (selector << LDO_SEL_SHIFT), LDO_SEL_MASK); | |
a320e3c3 JEC |
692 | } |
693 | ||
694 | return -EINVAL; | |
695 | } | |
696 | ||
697 | ||
518fb721 GG |
698 | static int tps65910_list_voltage_dcdc(struct regulator_dev *dev, |
699 | unsigned selector) | |
700 | { | |
a320e3c3 | 701 | int volt, mult = 1, id = rdev_get_id(dev); |
518fb721 | 702 | |
a320e3c3 JEC |
703 | switch (id) { |
704 | case TPS65910_REG_VDD1: | |
705 | case TPS65910_REG_VDD2: | |
780dc9ba | 706 | mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1; |
a320e3c3 | 707 | volt = VDD1_2_MIN_VOLT + |
780dc9ba | 708 | (selector % VDD1_2_NUM_VOLT_FINE) * VDD1_2_OFFSET; |
d04156bc | 709 | break; |
a320e3c3 JEC |
710 | case TPS65911_REG_VDDCTRL: |
711 | volt = VDDCTRL_MIN_VOLT + (selector * VDDCTRL_OFFSET); | |
d04156bc AL |
712 | break; |
713 | default: | |
714 | BUG(); | |
715 | return -EINVAL; | |
a320e3c3 | 716 | } |
518fb721 GG |
717 | |
718 | return volt * 100 * mult; | |
719 | } | |
720 | ||
721 | static int tps65910_list_voltage(struct regulator_dev *dev, | |
722 | unsigned selector) | |
723 | { | |
724 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
725 | int id = rdev_get_id(dev), voltage; | |
726 | ||
727 | if (id < TPS65910_REG_VIO || id > TPS65910_REG_VMMC) | |
728 | return -EINVAL; | |
729 | ||
7d38a3cb | 730 | if (selector >= pmic->info[id]->n_voltages) |
518fb721 GG |
731 | return -EINVAL; |
732 | else | |
7d38a3cb | 733 | voltage = pmic->info[id]->voltage_table[selector] * 1000; |
518fb721 GG |
734 | |
735 | return voltage; | |
736 | } | |
737 | ||
a320e3c3 JEC |
738 | static int tps65911_list_voltage(struct regulator_dev *dev, unsigned selector) |
739 | { | |
740 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
741 | int step_mv = 0, id = rdev_get_id(dev); | |
742 | ||
743 | switch(id) { | |
744 | case TPS65911_REG_LDO1: | |
745 | case TPS65911_REG_LDO2: | |
746 | case TPS65911_REG_LDO4: | |
747 | /* The first 5 values of the selector correspond to 1V */ | |
748 | if (selector < 5) | |
749 | selector = 0; | |
750 | else | |
751 | selector -= 4; | |
752 | ||
753 | step_mv = 50; | |
754 | break; | |
755 | case TPS65911_REG_LDO3: | |
756 | case TPS65911_REG_LDO5: | |
757 | case TPS65911_REG_LDO6: | |
758 | case TPS65911_REG_LDO7: | |
759 | case TPS65911_REG_LDO8: | |
760 | /* The first 3 values of the selector correspond to 1V */ | |
761 | if (selector < 3) | |
762 | selector = 0; | |
763 | else | |
764 | selector -= 2; | |
765 | ||
766 | step_mv = 100; | |
767 | break; | |
768 | case TPS65910_REG_VIO: | |
7d38a3cb | 769 | return pmic->info[id]->voltage_table[selector] * 1000; |
a320e3c3 JEC |
770 | default: |
771 | return -EINVAL; | |
772 | } | |
773 | ||
774 | return (LDO_MIN_VOLT + selector * step_mv) * 1000; | |
775 | } | |
776 | ||
518fb721 GG |
777 | /* Regulator ops (except VRTC) */ |
778 | static struct regulator_ops tps65910_ops_dcdc = { | |
a40a9c43 AL |
779 | .is_enabled = regulator_is_enabled_regmap, |
780 | .enable = regulator_enable_regmap, | |
781 | .disable = regulator_disable_regmap, | |
0651eed5 | 782 | .enable_time = tps65910_enable_time, |
518fb721 GG |
783 | .set_mode = tps65910_set_mode, |
784 | .get_mode = tps65910_get_mode, | |
18039e0f | 785 | .get_voltage_sel = tps65910_get_voltage_dcdc_sel, |
94732b97 | 786 | .set_voltage_sel = tps65910_set_voltage_dcdc_sel, |
01bc3a14 | 787 | .set_voltage_time_sel = regulator_set_voltage_time_sel, |
518fb721 GG |
788 | .list_voltage = tps65910_list_voltage_dcdc, |
789 | }; | |
790 | ||
791 | static struct regulator_ops tps65910_ops_vdd3 = { | |
a40a9c43 AL |
792 | .is_enabled = regulator_is_enabled_regmap, |
793 | .enable = regulator_enable_regmap, | |
794 | .disable = regulator_disable_regmap, | |
0651eed5 | 795 | .enable_time = tps65910_enable_time, |
518fb721 GG |
796 | .set_mode = tps65910_set_mode, |
797 | .get_mode = tps65910_get_mode, | |
798 | .get_voltage = tps65910_get_voltage_vdd3, | |
799 | .list_voltage = tps65910_list_voltage, | |
800 | }; | |
801 | ||
802 | static struct regulator_ops tps65910_ops = { | |
a40a9c43 AL |
803 | .is_enabled = regulator_is_enabled_regmap, |
804 | .enable = regulator_enable_regmap, | |
805 | .disable = regulator_disable_regmap, | |
0651eed5 | 806 | .enable_time = tps65910_enable_time, |
518fb721 GG |
807 | .set_mode = tps65910_set_mode, |
808 | .get_mode = tps65910_get_mode, | |
1f904fd1 | 809 | .get_voltage_sel = tps65910_get_voltage_sel, |
94732b97 | 810 | .set_voltage_sel = tps65910_set_voltage_sel, |
518fb721 GG |
811 | .list_voltage = tps65910_list_voltage, |
812 | }; | |
813 | ||
a320e3c3 | 814 | static struct regulator_ops tps65911_ops = { |
a40a9c43 AL |
815 | .is_enabled = regulator_is_enabled_regmap, |
816 | .enable = regulator_enable_regmap, | |
817 | .disable = regulator_disable_regmap, | |
0651eed5 | 818 | .enable_time = tps65910_enable_time, |
a320e3c3 JEC |
819 | .set_mode = tps65910_set_mode, |
820 | .get_mode = tps65910_get_mode, | |
1f904fd1 | 821 | .get_voltage_sel = tps65911_get_voltage_sel, |
94732b97 | 822 | .set_voltage_sel = tps65911_set_voltage_sel, |
a320e3c3 JEC |
823 | .list_voltage = tps65911_list_voltage, |
824 | }; | |
825 | ||
1e0c66f4 LD |
826 | static int tps65910_set_ext_sleep_config(struct tps65910_reg *pmic, |
827 | int id, int ext_sleep_config) | |
828 | { | |
829 | struct tps65910 *mfd = pmic->mfd; | |
830 | u8 regoffs = (pmic->ext_sleep_control[id] >> 8) & 0xFF; | |
831 | u8 bit_pos = (1 << pmic->ext_sleep_control[id] & 0xFF); | |
832 | int ret; | |
833 | ||
834 | /* | |
835 | * Regulator can not be control from multiple external input EN1, EN2 | |
836 | * and EN3 together. | |
837 | */ | |
838 | if (ext_sleep_config & EXT_SLEEP_CONTROL) { | |
839 | int en_count; | |
840 | en_count = ((ext_sleep_config & | |
841 | TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1) != 0); | |
842 | en_count += ((ext_sleep_config & | |
843 | TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2) != 0); | |
844 | en_count += ((ext_sleep_config & | |
845 | TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3) != 0); | |
f30b0716 LD |
846 | en_count += ((ext_sleep_config & |
847 | TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP) != 0); | |
1e0c66f4 LD |
848 | if (en_count > 1) { |
849 | dev_err(mfd->dev, | |
850 | "External sleep control flag is not proper\n"); | |
851 | return -EINVAL; | |
852 | } | |
853 | } | |
854 | ||
855 | pmic->board_ext_control[id] = ext_sleep_config; | |
856 | ||
857 | /* External EN1 control */ | |
858 | if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1) | |
3f7e8275 | 859 | ret = tps65910_reg_set_bits(mfd, |
1e0c66f4 LD |
860 | TPS65910_EN1_LDO_ASS + regoffs, bit_pos); |
861 | else | |
3f7e8275 | 862 | ret = tps65910_reg_clear_bits(mfd, |
1e0c66f4 LD |
863 | TPS65910_EN1_LDO_ASS + regoffs, bit_pos); |
864 | if (ret < 0) { | |
865 | dev_err(mfd->dev, | |
866 | "Error in configuring external control EN1\n"); | |
867 | return ret; | |
868 | } | |
869 | ||
870 | /* External EN2 control */ | |
871 | if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2) | |
3f7e8275 | 872 | ret = tps65910_reg_set_bits(mfd, |
1e0c66f4 LD |
873 | TPS65910_EN2_LDO_ASS + regoffs, bit_pos); |
874 | else | |
3f7e8275 | 875 | ret = tps65910_reg_clear_bits(mfd, |
1e0c66f4 LD |
876 | TPS65910_EN2_LDO_ASS + regoffs, bit_pos); |
877 | if (ret < 0) { | |
878 | dev_err(mfd->dev, | |
879 | "Error in configuring external control EN2\n"); | |
880 | return ret; | |
881 | } | |
882 | ||
883 | /* External EN3 control for TPS65910 LDO only */ | |
884 | if ((tps65910_chip_id(mfd) == TPS65910) && | |
885 | (id >= TPS65910_REG_VDIG1)) { | |
886 | if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3) | |
3f7e8275 | 887 | ret = tps65910_reg_set_bits(mfd, |
1e0c66f4 LD |
888 | TPS65910_EN3_LDO_ASS + regoffs, bit_pos); |
889 | else | |
3f7e8275 | 890 | ret = tps65910_reg_clear_bits(mfd, |
1e0c66f4 LD |
891 | TPS65910_EN3_LDO_ASS + regoffs, bit_pos); |
892 | if (ret < 0) { | |
893 | dev_err(mfd->dev, | |
894 | "Error in configuring external control EN3\n"); | |
895 | return ret; | |
896 | } | |
897 | } | |
898 | ||
899 | /* Return if no external control is selected */ | |
900 | if (!(ext_sleep_config & EXT_SLEEP_CONTROL)) { | |
901 | /* Clear all sleep controls */ | |
3f7e8275 | 902 | ret = tps65910_reg_clear_bits(mfd, |
1e0c66f4 LD |
903 | TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos); |
904 | if (!ret) | |
3f7e8275 | 905 | ret = tps65910_reg_clear_bits(mfd, |
1e0c66f4 LD |
906 | TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos); |
907 | if (ret < 0) | |
908 | dev_err(mfd->dev, | |
909 | "Error in configuring SLEEP register\n"); | |
910 | return ret; | |
911 | } | |
912 | ||
913 | /* | |
914 | * For regulator that has separate operational and sleep register make | |
915 | * sure that operational is used and clear sleep register to turn | |
916 | * regulator off when external control is inactive | |
917 | */ | |
918 | if ((id == TPS65910_REG_VDD1) || | |
919 | (id == TPS65910_REG_VDD2) || | |
920 | ((id == TPS65911_REG_VDDCTRL) && | |
921 | (tps65910_chip_id(mfd) == TPS65911))) { | |
922 | int op_reg_add = pmic->get_ctrl_reg(id) + 1; | |
923 | int sr_reg_add = pmic->get_ctrl_reg(id) + 2; | |
3f7e8275 RK |
924 | int opvsel = tps65910_reg_read_locked(pmic, op_reg_add); |
925 | int srvsel = tps65910_reg_read_locked(pmic, sr_reg_add); | |
1e0c66f4 LD |
926 | if (opvsel & VDD1_OP_CMD_MASK) { |
927 | u8 reg_val = srvsel & VDD1_OP_SEL_MASK; | |
3f7e8275 RK |
928 | ret = tps65910_reg_write_locked(pmic, op_reg_add, |
929 | reg_val); | |
1e0c66f4 LD |
930 | if (ret < 0) { |
931 | dev_err(mfd->dev, | |
932 | "Error in configuring op register\n"); | |
933 | return ret; | |
934 | } | |
935 | } | |
3f7e8275 | 936 | ret = tps65910_reg_write_locked(pmic, sr_reg_add, 0); |
1e0c66f4 LD |
937 | if (ret < 0) { |
938 | dev_err(mfd->dev, "Error in settting sr register\n"); | |
939 | return ret; | |
940 | } | |
941 | } | |
942 | ||
3f7e8275 | 943 | ret = tps65910_reg_clear_bits(mfd, |
1e0c66f4 | 944 | TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos); |
f30b0716 LD |
945 | if (!ret) { |
946 | if (ext_sleep_config & TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP) | |
3f7e8275 | 947 | ret = tps65910_reg_set_bits(mfd, |
f30b0716 LD |
948 | TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos); |
949 | else | |
3f7e8275 | 950 | ret = tps65910_reg_clear_bits(mfd, |
f30b0716 LD |
951 | TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos); |
952 | } | |
1e0c66f4 LD |
953 | if (ret < 0) |
954 | dev_err(mfd->dev, | |
955 | "Error in configuring SLEEP register\n"); | |
f30b0716 | 956 | |
1e0c66f4 LD |
957 | return ret; |
958 | } | |
959 | ||
6790178f RK |
960 | #ifdef CONFIG_OF |
961 | ||
962 | static struct of_regulator_match tps65910_matches[] = { | |
33a6943d LD |
963 | { .name = "vrtc", .driver_data = (void *) &tps65910_regs[0] }, |
964 | { .name = "vio", .driver_data = (void *) &tps65910_regs[1] }, | |
965 | { .name = "vdd1", .driver_data = (void *) &tps65910_regs[2] }, | |
966 | { .name = "vdd2", .driver_data = (void *) &tps65910_regs[3] }, | |
967 | { .name = "vdd3", .driver_data = (void *) &tps65910_regs[4] }, | |
968 | { .name = "vdig1", .driver_data = (void *) &tps65910_regs[5] }, | |
969 | { .name = "vdig2", .driver_data = (void *) &tps65910_regs[6] }, | |
970 | { .name = "vpll", .driver_data = (void *) &tps65910_regs[7] }, | |
971 | { .name = "vdac", .driver_data = (void *) &tps65910_regs[8] }, | |
972 | { .name = "vaux1", .driver_data = (void *) &tps65910_regs[9] }, | |
973 | { .name = "vaux2", .driver_data = (void *) &tps65910_regs[10] }, | |
974 | { .name = "vaux33", .driver_data = (void *) &tps65910_regs[11] }, | |
975 | { .name = "vmmc", .driver_data = (void *) &tps65910_regs[12] }, | |
6790178f RK |
976 | }; |
977 | ||
978 | static struct of_regulator_match tps65911_matches[] = { | |
33a6943d LD |
979 | { .name = "vrtc", .driver_data = (void *) &tps65911_regs[0] }, |
980 | { .name = "vio", .driver_data = (void *) &tps65911_regs[1] }, | |
981 | { .name = "vdd1", .driver_data = (void *) &tps65911_regs[2] }, | |
982 | { .name = "vdd2", .driver_data = (void *) &tps65911_regs[3] }, | |
983 | { .name = "vddctrl", .driver_data = (void *) &tps65911_regs[4] }, | |
984 | { .name = "ldo1", .driver_data = (void *) &tps65911_regs[5] }, | |
985 | { .name = "ldo2", .driver_data = (void *) &tps65911_regs[6] }, | |
986 | { .name = "ldo3", .driver_data = (void *) &tps65911_regs[7] }, | |
987 | { .name = "ldo4", .driver_data = (void *) &tps65911_regs[8] }, | |
988 | { .name = "ldo5", .driver_data = (void *) &tps65911_regs[9] }, | |
989 | { .name = "ldo6", .driver_data = (void *) &tps65911_regs[10] }, | |
990 | { .name = "ldo7", .driver_data = (void *) &tps65911_regs[11] }, | |
991 | { .name = "ldo8", .driver_data = (void *) &tps65911_regs[12] }, | |
6790178f RK |
992 | }; |
993 | ||
994 | static struct tps65910_board *tps65910_parse_dt_reg_data( | |
84df8c12 LD |
995 | struct platform_device *pdev, |
996 | struct of_regulator_match **tps65910_reg_matches) | |
6790178f RK |
997 | { |
998 | struct tps65910_board *pmic_plat_data; | |
999 | struct tps65910 *tps65910 = dev_get_drvdata(pdev->dev.parent); | |
1000 | struct device_node *np = pdev->dev.parent->of_node; | |
1001 | struct device_node *regulators; | |
1002 | struct of_regulator_match *matches; | |
1003 | unsigned int prop; | |
1004 | int idx = 0, ret, count; | |
1005 | ||
1006 | pmic_plat_data = devm_kzalloc(&pdev->dev, sizeof(*pmic_plat_data), | |
1007 | GFP_KERNEL); | |
1008 | ||
1009 | if (!pmic_plat_data) { | |
1010 | dev_err(&pdev->dev, "Failure to alloc pdata for regulators.\n"); | |
1011 | return NULL; | |
1012 | } | |
1013 | ||
1014 | regulators = of_find_node_by_name(np, "regulators"); | |
92ab953b LD |
1015 | if (!regulators) { |
1016 | dev_err(&pdev->dev, "regulator node not found\n"); | |
1017 | return NULL; | |
1018 | } | |
6790178f RK |
1019 | |
1020 | switch (tps65910_chip_id(tps65910)) { | |
1021 | case TPS65910: | |
1022 | count = ARRAY_SIZE(tps65910_matches); | |
1023 | matches = tps65910_matches; | |
1024 | break; | |
1025 | case TPS65911: | |
1026 | count = ARRAY_SIZE(tps65911_matches); | |
1027 | matches = tps65911_matches; | |
1028 | break; | |
1029 | default: | |
7e9a57e6 | 1030 | dev_err(&pdev->dev, "Invalid tps chip version\n"); |
6790178f RK |
1031 | return NULL; |
1032 | } | |
1033 | ||
1034 | ret = of_regulator_match(pdev->dev.parent, regulators, matches, count); | |
1035 | if (ret < 0) { | |
1036 | dev_err(&pdev->dev, "Error parsing regulator init data: %d\n", | |
1037 | ret); | |
1038 | return NULL; | |
1039 | } | |
1040 | ||
84df8c12 LD |
1041 | *tps65910_reg_matches = matches; |
1042 | ||
6790178f RK |
1043 | for (idx = 0; idx < count; idx++) { |
1044 | if (!matches[idx].init_data || !matches[idx].of_node) | |
1045 | continue; | |
1046 | ||
1047 | pmic_plat_data->tps65910_pmic_init_data[idx] = | |
1048 | matches[idx].init_data; | |
1049 | ||
1050 | ret = of_property_read_u32(matches[idx].of_node, | |
1051 | "ti,regulator-ext-sleep-control", &prop); | |
1052 | if (!ret) | |
1053 | pmic_plat_data->regulator_ext_sleep_control[idx] = prop; | |
1054 | } | |
1055 | ||
1056 | return pmic_plat_data; | |
1057 | } | |
1058 | #else | |
1059 | static inline struct tps65910_board *tps65910_parse_dt_reg_data( | |
84df8c12 LD |
1060 | struct platform_device *pdev, |
1061 | struct of_regulator_match **tps65910_reg_matches) | |
6790178f | 1062 | { |
84df8c12 | 1063 | *tps65910_reg_matches = NULL; |
74ea0e59 | 1064 | return NULL; |
6790178f RK |
1065 | } |
1066 | #endif | |
1067 | ||
518fb721 GG |
1068 | static __devinit int tps65910_probe(struct platform_device *pdev) |
1069 | { | |
1070 | struct tps65910 *tps65910 = dev_get_drvdata(pdev->dev.parent); | |
c172708d | 1071 | struct regulator_config config = { }; |
a320e3c3 | 1072 | struct tps_info *info; |
518fb721 GG |
1073 | struct regulator_init_data *reg_data; |
1074 | struct regulator_dev *rdev; | |
1075 | struct tps65910_reg *pmic; | |
1076 | struct tps65910_board *pmic_plat_data; | |
84df8c12 | 1077 | struct of_regulator_match *tps65910_reg_matches = NULL; |
518fb721 GG |
1078 | int i, err; |
1079 | ||
1080 | pmic_plat_data = dev_get_platdata(tps65910->dev); | |
6790178f | 1081 | if (!pmic_plat_data && tps65910->dev->of_node) |
84df8c12 LD |
1082 | pmic_plat_data = tps65910_parse_dt_reg_data(pdev, |
1083 | &tps65910_reg_matches); | |
6790178f | 1084 | |
7e9a57e6 LD |
1085 | if (!pmic_plat_data) { |
1086 | dev_err(&pdev->dev, "Platform data not found\n"); | |
518fb721 | 1087 | return -EINVAL; |
7e9a57e6 | 1088 | } |
518fb721 | 1089 | |
9eb0c421 | 1090 | pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL); |
7e9a57e6 LD |
1091 | if (!pmic) { |
1092 | dev_err(&pdev->dev, "Memory allocation failed for pmic\n"); | |
518fb721 | 1093 | return -ENOMEM; |
7e9a57e6 | 1094 | } |
518fb721 GG |
1095 | |
1096 | mutex_init(&pmic->mutex); | |
1097 | pmic->mfd = tps65910; | |
1098 | platform_set_drvdata(pdev, pmic); | |
1099 | ||
1100 | /* Give control of all register to control port */ | |
3f7e8275 | 1101 | tps65910_reg_set_bits(pmic->mfd, TPS65910_DEVCTRL, |
518fb721 GG |
1102 | DEVCTRL_SR_CTL_I2C_SEL_MASK); |
1103 | ||
a320e3c3 JEC |
1104 | switch(tps65910_chip_id(tps65910)) { |
1105 | case TPS65910: | |
1106 | pmic->get_ctrl_reg = &tps65910_get_ctrl_register; | |
39aa9b6e | 1107 | pmic->num_regulators = ARRAY_SIZE(tps65910_regs); |
1e0c66f4 | 1108 | pmic->ext_sleep_control = tps65910_ext_sleep_control; |
a320e3c3 | 1109 | info = tps65910_regs; |
d04156bc | 1110 | break; |
a320e3c3 JEC |
1111 | case TPS65911: |
1112 | pmic->get_ctrl_reg = &tps65911_get_ctrl_register; | |
39aa9b6e | 1113 | pmic->num_regulators = ARRAY_SIZE(tps65911_regs); |
1e0c66f4 | 1114 | pmic->ext_sleep_control = tps65911_ext_sleep_control; |
a320e3c3 | 1115 | info = tps65911_regs; |
d04156bc | 1116 | break; |
a320e3c3 | 1117 | default: |
7e9a57e6 | 1118 | dev_err(&pdev->dev, "Invalid tps chip version\n"); |
a320e3c3 JEC |
1119 | return -ENODEV; |
1120 | } | |
1121 | ||
68d8c1cd | 1122 | pmic->desc = devm_kzalloc(&pdev->dev, pmic->num_regulators * |
39aa9b6e AL |
1123 | sizeof(struct regulator_desc), GFP_KERNEL); |
1124 | if (!pmic->desc) { | |
68d8c1cd LD |
1125 | dev_err(&pdev->dev, "Memory alloc fails for desc\n"); |
1126 | return -ENOMEM; | |
39aa9b6e AL |
1127 | } |
1128 | ||
68d8c1cd | 1129 | pmic->info = devm_kzalloc(&pdev->dev, pmic->num_regulators * |
39aa9b6e AL |
1130 | sizeof(struct tps_info *), GFP_KERNEL); |
1131 | if (!pmic->info) { | |
68d8c1cd LD |
1132 | dev_err(&pdev->dev, "Memory alloc fails for info\n"); |
1133 | return -ENOMEM; | |
39aa9b6e AL |
1134 | } |
1135 | ||
68d8c1cd | 1136 | pmic->rdev = devm_kzalloc(&pdev->dev, pmic->num_regulators * |
39aa9b6e AL |
1137 | sizeof(struct regulator_dev *), GFP_KERNEL); |
1138 | if (!pmic->rdev) { | |
68d8c1cd LD |
1139 | dev_err(&pdev->dev, "Memory alloc fails for rdev\n"); |
1140 | return -ENOMEM; | |
39aa9b6e AL |
1141 | } |
1142 | ||
c1fc1480 KM |
1143 | for (i = 0; i < pmic->num_regulators && i < TPS65910_NUM_REGS; |
1144 | i++, info++) { | |
1145 | ||
1146 | reg_data = pmic_plat_data->tps65910_pmic_init_data[i]; | |
1147 | ||
1148 | /* Regulator API handles empty constraints but not NULL | |
1149 | * constraints */ | |
1150 | if (!reg_data) | |
1151 | continue; | |
1152 | ||
518fb721 GG |
1153 | /* Register the regulators */ |
1154 | pmic->info[i] = info; | |
1155 | ||
1156 | pmic->desc[i].name = info->name; | |
77fa44d0 | 1157 | pmic->desc[i].id = i; |
7d38a3cb | 1158 | pmic->desc[i].n_voltages = info->n_voltages; |
518fb721 | 1159 | |
a320e3c3 | 1160 | if (i == TPS65910_REG_VDD1 || i == TPS65910_REG_VDD2) { |
518fb721 | 1161 | pmic->desc[i].ops = &tps65910_ops_dcdc; |
780dc9ba AM |
1162 | pmic->desc[i].n_voltages = VDD1_2_NUM_VOLT_FINE * |
1163 | VDD1_2_NUM_VOLT_COARSE; | |
01bc3a14 | 1164 | pmic->desc[i].ramp_delay = 12500; |
a320e3c3 | 1165 | } else if (i == TPS65910_REG_VDD3) { |
01bc3a14 | 1166 | if (tps65910_chip_id(tps65910) == TPS65910) { |
a320e3c3 | 1167 | pmic->desc[i].ops = &tps65910_ops_vdd3; |
01bc3a14 | 1168 | } else { |
a320e3c3 | 1169 | pmic->desc[i].ops = &tps65910_ops_dcdc; |
01bc3a14 AL |
1170 | pmic->desc[i].ramp_delay = 5000; |
1171 | } | |
a320e3c3 JEC |
1172 | } else { |
1173 | if (tps65910_chip_id(tps65910) == TPS65910) | |
1174 | pmic->desc[i].ops = &tps65910_ops; | |
1175 | else | |
1176 | pmic->desc[i].ops = &tps65911_ops; | |
1177 | } | |
518fb721 | 1178 | |
1e0c66f4 LD |
1179 | err = tps65910_set_ext_sleep_config(pmic, i, |
1180 | pmic_plat_data->regulator_ext_sleep_control[i]); | |
1181 | /* | |
1182 | * Failing on regulator for configuring externally control | |
1183 | * is not a serious issue, just throw warning. | |
1184 | */ | |
1185 | if (err < 0) | |
1186 | dev_warn(tps65910->dev, | |
1187 | "Failed to initialise ext control config\n"); | |
1188 | ||
518fb721 GG |
1189 | pmic->desc[i].type = REGULATOR_VOLTAGE; |
1190 | pmic->desc[i].owner = THIS_MODULE; | |
a40a9c43 AL |
1191 | pmic->desc[i].enable_reg = pmic->get_ctrl_reg(i); |
1192 | pmic->desc[i].enable_mask = TPS65910_SUPPLY_STATE_ENABLED; | |
518fb721 | 1193 | |
c172708d MB |
1194 | config.dev = tps65910->dev; |
1195 | config.init_data = reg_data; | |
1196 | config.driver_data = pmic; | |
a40a9c43 | 1197 | config.regmap = tps65910->regmap; |
c172708d | 1198 | |
84df8c12 LD |
1199 | if (tps65910_reg_matches) |
1200 | config.of_node = tps65910_reg_matches[i].of_node; | |
6790178f | 1201 | |
c172708d | 1202 | rdev = regulator_register(&pmic->desc[i], &config); |
518fb721 GG |
1203 | if (IS_ERR(rdev)) { |
1204 | dev_err(tps65910->dev, | |
1205 | "failed to register %s regulator\n", | |
1206 | pdev->name); | |
1207 | err = PTR_ERR(rdev); | |
39aa9b6e | 1208 | goto err_unregister_regulator; |
518fb721 GG |
1209 | } |
1210 | ||
1211 | /* Save regulator for cleanup */ | |
1212 | pmic->rdev[i] = rdev; | |
1213 | } | |
1214 | return 0; | |
1215 | ||
39aa9b6e | 1216 | err_unregister_regulator: |
518fb721 GG |
1217 | while (--i >= 0) |
1218 | regulator_unregister(pmic->rdev[i]); | |
518fb721 GG |
1219 | return err; |
1220 | } | |
1221 | ||
1222 | static int __devexit tps65910_remove(struct platform_device *pdev) | |
1223 | { | |
39aa9b6e | 1224 | struct tps65910_reg *pmic = platform_get_drvdata(pdev); |
518fb721 GG |
1225 | int i; |
1226 | ||
39aa9b6e AL |
1227 | for (i = 0; i < pmic->num_regulators; i++) |
1228 | regulator_unregister(pmic->rdev[i]); | |
518fb721 | 1229 | |
518fb721 GG |
1230 | return 0; |
1231 | } | |
1232 | ||
1e0c66f4 LD |
1233 | static void tps65910_shutdown(struct platform_device *pdev) |
1234 | { | |
1235 | struct tps65910_reg *pmic = platform_get_drvdata(pdev); | |
1236 | int i; | |
1237 | ||
1238 | /* | |
1239 | * Before bootloader jumps to kernel, it makes sure that required | |
1240 | * external control signals are in desired state so that given rails | |
1241 | * can be configure accordingly. | |
1242 | * If rails are configured to be controlled from external control | |
1243 | * then before shutting down/rebooting the system, the external | |
1244 | * control configuration need to be remove from the rails so that | |
1245 | * its output will be available as per register programming even | |
1246 | * if external controls are removed. This is require when the POR | |
1247 | * value of the control signals are not in active state and before | |
1248 | * bootloader initializes it, the system requires the rail output | |
1249 | * to be active for booting. | |
1250 | */ | |
1251 | for (i = 0; i < pmic->num_regulators; i++) { | |
1252 | int err; | |
1253 | if (!pmic->rdev[i]) | |
1254 | continue; | |
1255 | ||
1256 | err = tps65910_set_ext_sleep_config(pmic, i, 0); | |
1257 | if (err < 0) | |
1258 | dev_err(&pdev->dev, | |
1259 | "Error in clearing external control\n"); | |
1260 | } | |
1261 | } | |
1262 | ||
518fb721 GG |
1263 | static struct platform_driver tps65910_driver = { |
1264 | .driver = { | |
1265 | .name = "tps65910-pmic", | |
1266 | .owner = THIS_MODULE, | |
1267 | }, | |
1268 | .probe = tps65910_probe, | |
1269 | .remove = __devexit_p(tps65910_remove), | |
1e0c66f4 | 1270 | .shutdown = tps65910_shutdown, |
518fb721 GG |
1271 | }; |
1272 | ||
1273 | static int __init tps65910_init(void) | |
1274 | { | |
1275 | return platform_driver_register(&tps65910_driver); | |
1276 | } | |
1277 | subsys_initcall(tps65910_init); | |
1278 | ||
1279 | static void __exit tps65910_cleanup(void) | |
1280 | { | |
1281 | platform_driver_unregister(&tps65910_driver); | |
1282 | } | |
1283 | module_exit(tps65910_cleanup); | |
1284 | ||
1285 | MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>"); | |
ae0e6544 | 1286 | MODULE_DESCRIPTION("TPS65910/TPS65911 voltage regulator driver"); |
518fb721 GG |
1287 | MODULE_LICENSE("GPL v2"); |
1288 | MODULE_ALIAS("platform:tps65910-pmic"); |