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scsi: zfcp: fix payload with full FCP_RSP IU in SCSI trace records
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / regulator / palmas-regulator.c
CommitLineData
e5ce4208
GG		 1/*
2 * Driver for Regulator part of Palmas PMIC Chips
3 *
7be859f7 4 * Copyright 2011-2013 Texas Instruments Inc.
e5ce4208
GG		 5 *
6 * Author: Graeme Gregory <gg@slimlogic.co.uk>
a7dddf27 7 * Author: Ian Lartey <ian@slimlogic.co.uk>
e5ce4208
GG		 8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/err.h>
20#include <linux/platform_device.h>
21#include <linux/regulator/driver.h>
22#include <linux/regulator/machine.h>
23#include <linux/slab.h>
24#include <linux/regmap.h>
25#include <linux/mfd/palmas.h>
a361cd9f
GG		 26#include <linux/of.h>
27#include <linux/of_platform.h>
28#include <linux/regulator/of_regulator.h>
e5ce4208
GG		 29
30struct regs_info {
31 char *name;
504382c9 32 char *sname;
e5ce4208
GG		 33 u8 vsel_addr;
34 u8 ctrl_addr;
35 u8 tstep_addr;
36};
37
38static const struct regs_info palmas_regs_info[] = {
39 {
40 .name = "SMPS12",
504382c9 41 .sname = "smps1-in",
e5ce4208
GG		 42 .vsel_addr = PALMAS_SMPS12_VOLTAGE,
43 .ctrl_addr = PALMAS_SMPS12_CTRL,
44 .tstep_addr = PALMAS_SMPS12_TSTEP,
45 },
46 {
47 .name = "SMPS123",
504382c9 48 .sname = "smps1-in",
e5ce4208
GG		 49 .vsel_addr = PALMAS_SMPS12_VOLTAGE,
50 .ctrl_addr = PALMAS_SMPS12_CTRL,
51 .tstep_addr = PALMAS_SMPS12_TSTEP,
52 },
53 {
54 .name = "SMPS3",
504382c9 55 .sname = "smps3-in",
e5ce4208
GG		 56 .vsel_addr = PALMAS_SMPS3_VOLTAGE,
57 .ctrl_addr = PALMAS_SMPS3_CTRL,
58 },
59 {
60 .name = "SMPS45",
504382c9 61 .sname = "smps4-in",
e5ce4208
GG		 62 .vsel_addr = PALMAS_SMPS45_VOLTAGE,
63 .ctrl_addr = PALMAS_SMPS45_CTRL,
64 .tstep_addr = PALMAS_SMPS45_TSTEP,
65 },
66 {
67 .name = "SMPS457",
504382c9 68 .sname = "smps4-in",
e5ce4208
GG		 69 .vsel_addr = PALMAS_SMPS45_VOLTAGE,
70 .ctrl_addr = PALMAS_SMPS45_CTRL,
71 .tstep_addr = PALMAS_SMPS45_TSTEP,
72 },
73 {
74 .name = "SMPS6",
504382c9 75 .sname = "smps6-in",
e5ce4208
GG		 76 .vsel_addr = PALMAS_SMPS6_VOLTAGE,
77 .ctrl_addr = PALMAS_SMPS6_CTRL,
78 .tstep_addr = PALMAS_SMPS6_TSTEP,
79 },
80 {
81 .name = "SMPS7",
504382c9 82 .sname = "smps7-in",
e5ce4208
GG		 83 .vsel_addr = PALMAS_SMPS7_VOLTAGE,
84 .ctrl_addr = PALMAS_SMPS7_CTRL,
85 },
86 {
87 .name = "SMPS8",
504382c9 88 .sname = "smps8-in",
e5ce4208
GG		 89 .vsel_addr = PALMAS_SMPS8_VOLTAGE,
90 .ctrl_addr = PALMAS_SMPS8_CTRL,
91 .tstep_addr = PALMAS_SMPS8_TSTEP,
92 },
93 {
94 .name = "SMPS9",
504382c9 95 .sname = "smps9-in",
e5ce4208
GG		 96 .vsel_addr = PALMAS_SMPS9_VOLTAGE,
97 .ctrl_addr = PALMAS_SMPS9_CTRL,
98 },
99 {
100 .name = "SMPS10",
504382c9 101 .sname = "smps10-in",
e31089c6 102 .ctrl_addr = PALMAS_SMPS10_CTRL,
e5ce4208
GG		 103 },
104 {
105 .name = "LDO1",
504382c9 106 .sname = "ldo1-in",
e5ce4208
GG		 107 .vsel_addr = PALMAS_LDO1_VOLTAGE,
108 .ctrl_addr = PALMAS_LDO1_CTRL,
109 },
110 {
111 .name = "LDO2",
504382c9 112 .sname = "ldo2-in",
e5ce4208
GG		 113 .vsel_addr = PALMAS_LDO2_VOLTAGE,
114 .ctrl_addr = PALMAS_LDO2_CTRL,
115 },
116 {
117 .name = "LDO3",
504382c9 118 .sname = "ldo3-in",
e5ce4208
GG		 119 .vsel_addr = PALMAS_LDO3_VOLTAGE,
120 .ctrl_addr = PALMAS_LDO3_CTRL,
121 },
122 {
123 .name = "LDO4",
504382c9 124 .sname = "ldo4-in",
e5ce4208
GG		 125 .vsel_addr = PALMAS_LDO4_VOLTAGE,
126 .ctrl_addr = PALMAS_LDO4_CTRL,
127 },
128 {
129 .name = "LDO5",
504382c9 130 .sname = "ldo5-in",
e5ce4208
GG		 131 .vsel_addr = PALMAS_LDO5_VOLTAGE,
132 .ctrl_addr = PALMAS_LDO5_CTRL,
133 },
134 {
135 .name = "LDO6",
504382c9 136 .sname = "ldo6-in",
e5ce4208
GG		 137 .vsel_addr = PALMAS_LDO6_VOLTAGE,
138 .ctrl_addr = PALMAS_LDO6_CTRL,
139 },
140 {
141 .name = "LDO7",
504382c9 142 .sname = "ldo7-in",
e5ce4208
GG		 143 .vsel_addr = PALMAS_LDO7_VOLTAGE,
144 .ctrl_addr = PALMAS_LDO7_CTRL,
145 },
146 {
147 .name = "LDO8",
504382c9 148 .sname = "ldo8-in",
e5ce4208
GG		 149 .vsel_addr = PALMAS_LDO8_VOLTAGE,
150 .ctrl_addr = PALMAS_LDO8_CTRL,
151 },
152 {
153 .name = "LDO9",
504382c9 154 .sname = "ldo9-in",
e5ce4208
GG		 155 .vsel_addr = PALMAS_LDO9_VOLTAGE,
156 .ctrl_addr = PALMAS_LDO9_CTRL,
157 },
158 {
159 .name = "LDOLN",
504382c9 160 .sname = "ldoln-in",
e5ce4208
GG		 161 .vsel_addr = PALMAS_LDOLN_VOLTAGE,
162 .ctrl_addr = PALMAS_LDOLN_CTRL,
163 },
164 {
165 .name = "LDOUSB",
504382c9 166 .sname = "ldousb-in",
e5ce4208
GG		 167 .vsel_addr = PALMAS_LDOUSB_VOLTAGE,
168 .ctrl_addr = PALMAS_LDOUSB_CTRL,
169 },
aa07f027
LD		 170 {
171 .name = "REGEN1",
172 .ctrl_addr = PALMAS_REGEN1_CTRL,
173 },
174 {
175 .name = "REGEN2",
176 .ctrl_addr = PALMAS_REGEN2_CTRL,
177 },
178 {
179 .name = "REGEN3",
180 .ctrl_addr = PALMAS_REGEN3_CTRL,
181 },
182 {
183 .name = "SYSEN1",
184 .ctrl_addr = PALMAS_SYSEN1_CTRL,
185 },
186 {
187 .name = "SYSEN2",
188 .ctrl_addr = PALMAS_SYSEN2_CTRL,
189 },
e5ce4208
GG		 190};
191
28d1e8cd
LD		 192static unsigned int palmas_smps_ramp_delay[4] = {0, 10000, 5000, 2500};
193
e5ce4208
GG		 194#define SMPS_CTRL_MODE_OFF 0x00
195#define SMPS_CTRL_MODE_ON 0x01
196#define SMPS_CTRL_MODE_ECO 0x02
197#define SMPS_CTRL_MODE_PWM 0x03
198
199/* These values are derived from the data sheet. And are the number of steps
200 * where there is a voltage change, the ranges at beginning and end of register
201 * max/min values where there are no change are ommitted.
202 *
203 * So they are basically (maxV-minV)/stepV
204 */
a7dddf27 205#define PALMAS_SMPS_NUM_VOLTAGES 117
e5ce4208
GG		 206#define PALMAS_SMPS10_NUM_VOLTAGES 2
207#define PALMAS_LDO_NUM_VOLTAGES 50
208
209#define SMPS10_VSEL (1<<3)
210#define SMPS10_BOOST_EN (1<<2)
211#define SMPS10_BYPASS_EN (1<<1)
212#define SMPS10_SWITCH_EN (1<<0)
213
214#define REGULATOR_SLAVE 0
215
216static int palmas_smps_read(struct palmas *palmas, unsigned int reg,
217 unsigned int *dest)
218{
219 unsigned int addr;
220
221 addr = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, reg);
222
223 return regmap_read(palmas->regmap[REGULATOR_SLAVE], addr, dest);
224}
225
226static int palmas_smps_write(struct palmas *palmas, unsigned int reg,
227 unsigned int value)
228{
229 unsigned int addr;
230
231 addr = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, reg);
232
233 return regmap_write(palmas->regmap[REGULATOR_SLAVE], addr, value);
234}
235
236static int palmas_ldo_read(struct palmas *palmas, unsigned int reg,
237 unsigned int *dest)
238{
239 unsigned int addr;
240
241 addr = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, reg);
242
243 return regmap_read(palmas->regmap[REGULATOR_SLAVE], addr, dest);
244}
245
246static int palmas_ldo_write(struct palmas *palmas, unsigned int reg,
247 unsigned int value)
248{
249 unsigned int addr;
250
251 addr = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, reg);
252
253 return regmap_write(palmas->regmap[REGULATOR_SLAVE], addr, value);
254}
255
256static int palmas_is_enabled_smps(struct regulator_dev *dev)
257{
258 struct palmas_pmic *pmic = rdev_get_drvdata(dev);
259 int id = rdev_get_id(dev);
260 unsigned int reg;
261
262 palmas_smps_read(pmic->palmas, palmas_regs_info[id].ctrl_addr, &reg);
263
264 reg &= PALMAS_SMPS12_CTRL_STATUS_MASK;
265 reg >>= PALMAS_SMPS12_CTRL_STATUS_SHIFT;
266
267 return !!(reg);
268}
269
270static int palmas_enable_smps(struct regulator_dev *dev)
271{
272 struct palmas_pmic *pmic = rdev_get_drvdata(dev);
273 int id = rdev_get_id(dev);
274 unsigned int reg;
275
276 palmas_smps_read(pmic->palmas, palmas_regs_info[id].ctrl_addr, &reg);
277
278 reg &= ~PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
51d3a0c9
LD		 279 if (pmic->current_reg_mode[id])
280 reg |= pmic->current_reg_mode[id];
281 else
282 reg |= SMPS_CTRL_MODE_ON;
e5ce4208
GG		 283
284 palmas_smps_write(pmic->palmas, palmas_regs_info[id].ctrl_addr, reg);
285
286 return 0;
287}
288
289static int palmas_disable_smps(struct regulator_dev *dev)
290{
291 struct palmas_pmic *pmic = rdev_get_drvdata(dev);
292 int id = rdev_get_id(dev);
293 unsigned int reg;
294
295 palmas_smps_read(pmic->palmas, palmas_regs_info[id].ctrl_addr, &reg);
296
297 reg &= ~PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
298
299 palmas_smps_write(pmic->palmas, palmas_regs_info[id].ctrl_addr, reg);
300
301 return 0;
302}
303
e5ce4208
GG		 304static int palmas_set_mode_smps(struct regulator_dev *dev, unsigned int mode)
305{
306 struct palmas_pmic *pmic = rdev_get_drvdata(dev);
307 int id = rdev_get_id(dev);
308 unsigned int reg;
51d3a0c9 309 bool rail_enable = true;
e5ce4208
GG		 310
311 palmas_smps_read(pmic->palmas, palmas_regs_info[id].ctrl_addr, &reg);
999f0c7c 312 reg &= ~PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
e5ce4208 313
51d3a0c9
LD		 314 if (reg == SMPS_CTRL_MODE_OFF)
315 rail_enable = false;
316
e5ce4208
GG		 317 switch (mode) {
318 case REGULATOR_MODE_NORMAL:
319 reg |= SMPS_CTRL_MODE_ON;
320 break;
321 case REGULATOR_MODE_IDLE:
322 reg |= SMPS_CTRL_MODE_ECO;
323 break;
324 case REGULATOR_MODE_FAST:
325 reg |= SMPS_CTRL_MODE_PWM;
326 break;
327 default:
328 return -EINVAL;
329 }
e5ce4208 330
51d3a0c9
LD		 331 pmic->current_reg_mode[id] = reg & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
332 if (rail_enable)
333 palmas_smps_write(pmic->palmas,
334 palmas_regs_info[id].ctrl_addr, reg);
e5ce4208
GG		 335 return 0;
336}
337
338static unsigned int palmas_get_mode_smps(struct regulator_dev *dev)
339{
340 struct palmas_pmic *pmic = rdev_get_drvdata(dev);
341 int id = rdev_get_id(dev);
342 unsigned int reg;
343
51d3a0c9 344 reg = pmic->current_reg_mode[id] & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
e5ce4208
GG		 345
346 switch (reg) {
347 case SMPS_CTRL_MODE_ON:
348 return REGULATOR_MODE_NORMAL;
349 case SMPS_CTRL_MODE_ECO:
350 return REGULATOR_MODE_IDLE;
351 case SMPS_CTRL_MODE_PWM:
352 return REGULATOR_MODE_FAST;
353 }
354
355 return 0;
356}
357
358static int palmas_list_voltage_smps(struct regulator_dev *dev,
359 unsigned selector)
360{
361 struct palmas_pmic *pmic = rdev_get_drvdata(dev);
362 int id = rdev_get_id(dev);
363 int mult = 1;
364
e5ce4208
GG		 365 /* Read the multiplier set in VSEL register to return
366 * the correct voltage.
367 */
368 if (pmic->range[id])
369 mult = 2;
370
ad02e846
AL		 371 if (selector == 0)
372 return 0;
373 else if (selector < 6)
374 return 500000 * mult;
375 else
376 /* Voltage is linear mapping starting from selector 6,
377 * volt = (0.49V + ((selector - 5) * 0.01V)) * RANGE
378 * RANGE is either x1 or x2
379 */
380 return (490000 + ((selector - 5) * 10000)) * mult;
e5ce4208
GG		 381}
382
383static int palmas_map_voltage_smps(struct regulator_dev *rdev,
384 int min_uV, int max_uV)
385{
8a165df7
AL		 386 struct palmas_pmic *pmic = rdev_get_drvdata(rdev);
387 int id = rdev_get_id(rdev);
e5ce4208
GG		 388 int ret, voltage;
389
8a165df7
AL		 390 if (min_uV == 0)
391 return 0;
392
393 if (pmic->range[id]) { /* RANGE is x2 */
394 if (min_uV < 1000000)
395 min_uV = 1000000;
ad02e846 396 ret = DIV_ROUND_UP(min_uV - 1000000, 20000) + 6;
8a165df7
AL		 397 } else { /* RANGE is x1 */
398 if (min_uV < 500000)
399 min_uV = 500000;
ad02e846 400 ret = DIV_ROUND_UP(min_uV - 500000, 10000) + 6;
8a165df7 401 }
e5ce4208
GG		 402
403 /* Map back into a voltage to verify we're still in bounds */
404 voltage = palmas_list_voltage_smps(rdev, ret);
405 if (voltage < min_uV || voltage > max_uV)
406 return -EINVAL;
407
408 return ret;
409}
410
28d1e8cd
LD		 411static int palma_smps_set_voltage_smps_time_sel(struct regulator_dev *rdev,
412 unsigned int old_selector, unsigned int new_selector)
413{
414 struct palmas_pmic *pmic = rdev_get_drvdata(rdev);
415 int id = rdev_get_id(rdev);
416 int old_uv, new_uv;
417 unsigned int ramp_delay = pmic->ramp_delay[id];
418
419 if (!ramp_delay)
420 return 0;
421
422 old_uv = palmas_list_voltage_smps(rdev, old_selector);
423 if (old_uv < 0)
424 return old_uv;
425
426 new_uv = palmas_list_voltage_smps(rdev, new_selector);
427 if (new_uv < 0)
428 return new_uv;
429
430 return DIV_ROUND_UP(abs(old_uv - new_uv), ramp_delay);
431}
432
433static int palmas_smps_set_ramp_delay(struct regulator_dev *rdev,
434 int ramp_delay)
435{
436 struct palmas_pmic *pmic = rdev_get_drvdata(rdev);
437 int id = rdev_get_id(rdev);
438 unsigned int reg = 0;
439 unsigned int addr = palmas_regs_info[id].tstep_addr;
440 int ret;
441
f22c2bae
AL		 442 /* SMPS3 and SMPS7 do not have tstep_addr setting */
443 switch (id) {
444 case PALMAS_REG_SMPS3:
445 case PALMAS_REG_SMPS7:
446 return 0;
447 }
448
28d1e8cd
LD		 449 if (ramp_delay <= 0)
450 reg = 0;
0ea34b57 451 else if (ramp_delay <= 2500)
28d1e8cd 452 reg = 3;
0ea34b57 453 else if (ramp_delay <= 5000)
28d1e8cd
LD		 454 reg = 2;
455 else
456 reg = 1;
457
458 ret = palmas_smps_write(pmic->palmas, addr, reg);
459 if (ret < 0) {
460 dev_err(pmic->palmas->dev, "TSTEP write failed: %d\n", ret);
461 return ret;
462 }
463
464 pmic->ramp_delay[id] = palmas_smps_ramp_delay[reg];
465 return ret;
466}
467
e5ce4208
GG		 468static struct regulator_ops palmas_ops_smps = {
469 .is_enabled = palmas_is_enabled_smps,
470 .enable = palmas_enable_smps,
471 .disable = palmas_disable_smps,
472 .set_mode = palmas_set_mode_smps,
473 .get_mode = palmas_get_mode_smps,
bdc4baac
AL		 474 .get_voltage_sel = regulator_get_voltage_sel_regmap,
475 .set_voltage_sel = regulator_set_voltage_sel_regmap,
e5ce4208
GG		 476 .list_voltage = palmas_list_voltage_smps,
477 .map_voltage = palmas_map_voltage_smps,
28d1e8cd
LD		 478 .set_voltage_time_sel = palma_smps_set_voltage_smps_time_sel,
479 .set_ramp_delay = palmas_smps_set_ramp_delay,
e5ce4208
GG		 480};
481
e5ce4208
GG		 482static struct regulator_ops palmas_ops_smps10 = {
483 .is_enabled = regulator_is_enabled_regmap,
484 .enable = regulator_enable_regmap,
485 .disable = regulator_disable_regmap,
486 .get_voltage_sel = regulator_get_voltage_sel_regmap,
487 .set_voltage_sel = regulator_set_voltage_sel_regmap,
8029a006
AL		 488 .list_voltage = regulator_list_voltage_linear,
489 .map_voltage = regulator_map_voltage_linear,
e5ce4208
GG		 490};
491
492static int palmas_is_enabled_ldo(struct regulator_dev *dev)
493{
494 struct palmas_pmic *pmic = rdev_get_drvdata(dev);
495 int id = rdev_get_id(dev);
496 unsigned int reg;
497
498 palmas_ldo_read(pmic->palmas, palmas_regs_info[id].ctrl_addr, &reg);
499
500 reg &= PALMAS_LDO1_CTRL_STATUS;
501
502 return !!(reg);
503}
504
e5ce4208
GG		 505static struct regulator_ops palmas_ops_ldo = {
506 .is_enabled = palmas_is_enabled_ldo,
507 .enable = regulator_enable_regmap,
508 .disable = regulator_disable_regmap,
4a247a96
AL		 509 .get_voltage_sel = regulator_get_voltage_sel_regmap,
510 .set_voltage_sel = regulator_set_voltage_sel_regmap,
9119ff6a
AL		 511 .list_voltage = regulator_list_voltage_linear,
512 .map_voltage = regulator_map_voltage_linear,
e5ce4208
GG		 513};
514
aa07f027
LD		 515static struct regulator_ops palmas_ops_extreg = {
516 .is_enabled = regulator_is_enabled_regmap,
517 .enable = regulator_enable_regmap,
518 .disable = regulator_disable_regmap,
519};
520
e5ce4208
GG		 521/*
522 * setup the hardware based sleep configuration of the SMPS/LDO regulators
523 * from the platform data. This is different to the software based control
524 * supported by the regulator framework as it is controlled by toggling
525 * pins on the PMIC such as PREQ, SYSEN, ...
526 */
527static int palmas_smps_init(struct palmas *palmas, int id,
528 struct palmas_reg_init *reg_init)
529{
530 unsigned int reg;
531 unsigned int addr;
532 int ret;
533
534 addr = palmas_regs_info[id].ctrl_addr;
535
536 ret = palmas_smps_read(palmas, addr, &reg);
537 if (ret)
538 return ret;
539
fedd89b1
AL		 540 switch (id) {
541 case PALMAS_REG_SMPS10:
30590d04
LD		 542 reg &= ~PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK;
543 if (reg_init->mode_sleep)
fedd89b1
AL		 544 reg |= reg_init->mode_sleep <<
545 PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT;
fedd89b1
AL		 546 break;
547 default:
e5ce4208
GG		 548 if (reg_init->warm_reset)
549 reg |= PALMAS_SMPS12_CTRL_WR_S;
30590d04
LD		 550 else
551 reg &= ~PALMAS_SMPS12_CTRL_WR_S;
e5ce4208
GG		 552
553 if (reg_init->roof_floor)
554 reg |= PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN;
30590d04
LD		 555 else
556 reg &= ~PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN;
e5ce4208 557
30590d04
LD		 558 reg &= ~PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK;
559 if (reg_init->mode_sleep)
e5ce4208
GG		 560 reg |= reg_init->mode_sleep <<
561 PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT;
e5ce4208 562 }
fedd89b1 563
e5ce4208
GG		 564 ret = palmas_smps_write(palmas, addr, reg);
565 if (ret)
566 return ret;
567
e5ce4208
GG		 568 if (palmas_regs_info[id].vsel_addr && reg_init->vsel) {
569 addr = palmas_regs_info[id].vsel_addr;
570
571 reg = reg_init->vsel;
572
573 ret = palmas_smps_write(palmas, addr, reg);
574 if (ret)
575 return ret;
576 }
577
578
579 return 0;
580}
581
582static int palmas_ldo_init(struct palmas *palmas, int id,
583 struct palmas_reg_init *reg_init)
584{
585 unsigned int reg;
586 unsigned int addr;
587 int ret;
588
589 addr = palmas_regs_info[id].ctrl_addr;
590
2735daeb 591 ret = palmas_ldo_read(palmas, addr, &reg);
e5ce4208
GG		 592 if (ret)
593 return ret;
594
595 if (reg_init->warm_reset)
596 reg |= PALMAS_LDO1_CTRL_WR_S;
30590d04
LD		 597 else
598 reg &= ~PALMAS_LDO1_CTRL_WR_S;
e5ce4208
GG		 599
600 if (reg_init->mode_sleep)
601 reg |= PALMAS_LDO1_CTRL_MODE_SLEEP;
30590d04
LD		 602 else
603 reg &= ~PALMAS_LDO1_CTRL_MODE_SLEEP;
e5ce4208 604
2735daeb 605 ret = palmas_ldo_write(palmas, addr, reg);
e5ce4208
GG		 606 if (ret)
607 return ret;
608
609 return 0;
610}
611
aa07f027
LD		 612static int palmas_extreg_init(struct palmas *palmas, int id,
613 struct palmas_reg_init *reg_init)
614{
615 unsigned int addr;
616 int ret;
617 unsigned int val = 0;
618
619 addr = palmas_regs_info[id].ctrl_addr;
620
621 if (reg_init->mode_sleep)
622 val = PALMAS_REGEN1_CTRL_MODE_SLEEP;
623
624 ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
625 addr, PALMAS_REGEN1_CTRL_MODE_SLEEP, val);
626 if (ret < 0) {
627 dev_err(palmas->dev, "Resource reg 0x%02x update failed %d\n",
628 addr, ret);
629 return ret;
630 }
631 return 0;
632}
633
17c11a76
LD		 634static void palmas_enable_ldo8_track(struct palmas *palmas)
635{
636 unsigned int reg;
637 unsigned int addr;
638 int ret;
639
640 addr = palmas_regs_info[PALMAS_REG_LDO8].ctrl_addr;
641
642 ret = palmas_ldo_read(palmas, addr, &reg);
643 if (ret) {
644 dev_err(palmas->dev, "Error in reading ldo8 control reg\n");
645 return;
646 }
647
648 reg |= PALMAS_LDO8_CTRL_LDO_TRACKING_EN;
649 ret = palmas_ldo_write(palmas, addr, reg);
650 if (ret < 0) {
651 dev_err(palmas->dev, "Error in enabling tracking mode\n");
652 return;
653 }
654 /*
655 * When SMPS45 is set to off and LDO8 tracking is enabled, the LDO8
656 * output is defined by the LDO8_VOLTAGE.VSEL register divided by two,
657 * and can be set from 0.45 to 1.65 V.
658 */
659 addr = palmas_regs_info[PALMAS_REG_LDO8].vsel_addr;
660 ret = palmas_ldo_read(palmas, addr, &reg);
661 if (ret) {
662 dev_err(palmas->dev, "Error in reading ldo8 voltage reg\n");
663 return;
664 }
665
666 reg = (reg << 1) & PALMAS_LDO8_VOLTAGE_VSEL_MASK;
667 ret = palmas_ldo_write(palmas, addr, reg);
668 if (ret < 0)
669 dev_err(palmas->dev, "Error in setting ldo8 voltage reg\n");
670
671 return;
672}
673
a361cd9f
GG		 674static struct of_regulator_match palmas_matches[] = {
675 { .name = "smps12", },
676 { .name = "smps123", },
677 { .name = "smps3", },
678 { .name = "smps45", },
679 { .name = "smps457", },
680 { .name = "smps6", },
681 { .name = "smps7", },
682 { .name = "smps8", },
683 { .name = "smps9", },
684 { .name = "smps10", },
685 { .name = "ldo1", },
686 { .name = "ldo2", },
687 { .name = "ldo3", },
688 { .name = "ldo4", },
689 { .name = "ldo5", },
690 { .name = "ldo6", },
691 { .name = "ldo7", },
692 { .name = "ldo8", },
693 { .name = "ldo9", },
694 { .name = "ldoln", },
695 { .name = "ldousb", },
aa07f027
LD		 696 { .name = "regen1", },
697 { .name = "regen2", },
698 { .name = "regen3", },
699 { .name = "sysen1", },
700 { .name = "sysen2", },
a361cd9f
GG		 701};
702
a5023574 703static void palmas_dt_to_pdata(struct device *dev,
a361cd9f
GG		 704 struct device_node *node,
705 struct palmas_pmic_platform_data *pdata)
706{
707 struct device_node *regulators;
708 u32 prop;
709 int idx, ret;
710
c92f5dd2 711 node = of_node_get(node);
a361cd9f
GG		 712 regulators = of_find_node_by_name(node, "regulators");
713 if (!regulators) {
714 dev_info(dev, "regulator node not found\n");
715 return;
716 }
717
718 ret = of_regulator_match(dev, regulators, palmas_matches,
719 PALMAS_NUM_REGS);
c92f5dd2 720 of_node_put(regulators);
a361cd9f
GG		 721 if (ret < 0) {
722 dev_err(dev, "Error parsing regulator init data: %d\n", ret);
723 return;
724 }
725
726 for (idx = 0; idx < PALMAS_NUM_REGS; idx++) {
727 if (!palmas_matches[idx].init_data ||
728 !palmas_matches[idx].of_node)
729 continue;
730
731 pdata->reg_data[idx] = palmas_matches[idx].init_data;
732
733 pdata->reg_init[idx] = devm_kzalloc(dev,
734 sizeof(struct palmas_reg_init), GFP_KERNEL);
735
7be859f7 736 pdata->reg_init[idx]->warm_reset =
71f2146f
AL		 737 of_property_read_bool(palmas_matches[idx].of_node,
738 "ti,warm-reset");
a361cd9f 739
7be859f7
GG		 740 pdata->reg_init[idx]->roof_floor =
741 of_property_read_bool(palmas_matches[idx].of_node,
742 "ti,roof-floor");
a361cd9f
GG		 743
744 ret = of_property_read_u32(palmas_matches[idx].of_node,
3c870e3f 745 "ti,mode-sleep", &prop);
a361cd9f
GG		 746 if (!ret)
747 pdata->reg_init[idx]->mode_sleep = prop;
748
7be859f7
GG		 749 ret = of_property_read_bool(palmas_matches[idx].of_node,
750 "ti,smps-range");
751 if (ret)
752 pdata->reg_init[idx]->vsel =
753 PALMAS_SMPS12_VOLTAGE_RANGE;
a361cd9f 754
17c11a76
LD		 755 if (idx == PALMAS_REG_LDO8)
756 pdata->enable_ldo8_tracking = of_property_read_bool(
757 palmas_matches[idx].of_node,
758 "ti,enable-ldo8-tracking");
a361cd9f
GG		 759 }
760
7be859f7 761 pdata->ldo6_vibrator = of_property_read_bool(node, "ti,ldo6-vibrator");
a361cd9f
GG		 762}
763
764
bbcf50b1 765static int palmas_regulators_probe(struct platform_device *pdev)
e5ce4208
GG		 766{
767 struct palmas *palmas = dev_get_drvdata(pdev->dev.parent);
768 struct palmas_pmic_platform_data *pdata = pdev->dev.platform_data;
a361cd9f 769 struct device_node *node = pdev->dev.of_node;
e5ce4208
GG		 770 struct regulator_dev *rdev;
771 struct regulator_config config = { };
772 struct palmas_pmic *pmic;
773 struct palmas_reg_init *reg_init;
774 int id = 0, ret;
775 unsigned int addr, reg;
776
a361cd9f
GG		 777 if (node && !pdata) {
778 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
779
780 if (!pdata)
781 return -ENOMEM;
782
783 palmas_dt_to_pdata(&pdev->dev, node, pdata);
784 }
e5ce4208
GG		 785
786 pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
787 if (!pmic)
788 return -ENOMEM;
789
790 pmic->dev = &pdev->dev;
791 pmic->palmas = palmas;
792 palmas->pmic = pmic;
793 platform_set_drvdata(pdev, pmic);
794
795 ret = palmas_smps_read(palmas, PALMAS_SMPS_CTRL, &reg);
796 if (ret)
1c9d2d71 797 return ret;
e5ce4208
GG		 798
799 if (reg & PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN)
800 pmic->smps123 = 1;
801
802 if (reg & PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN)
803 pmic->smps457 = 1;
804
805 config.regmap = palmas->regmap[REGULATOR_SLAVE];
806 config.dev = &pdev->dev;
807 config.driver_data = pmic;
808
809 for (id = 0; id < PALMAS_REG_LDO1; id++) {
28d1e8cd 810 bool ramp_delay_support = false;
e5ce4208
GG		 811
812 /*
813 * Miss out regulators which are not available due
814 * to slaving configurations.
815 */
816 switch (id) {
817 case PALMAS_REG_SMPS12:
818 case PALMAS_REG_SMPS3:
819 if (pmic->smps123)
820 continue;
28d1e8cd
LD		 821 if (id == PALMAS_REG_SMPS12)
822 ramp_delay_support = true;
e5ce4208
GG		 823 break;
824 case PALMAS_REG_SMPS123:
825 if (!pmic->smps123)
826 continue;
28d1e8cd 827 ramp_delay_support = true;
e5ce4208
GG		 828 break;
829 case PALMAS_REG_SMPS45:
830 case PALMAS_REG_SMPS7:
831 if (pmic->smps457)
832 continue;
28d1e8cd
LD		 833 if (id == PALMAS_REG_SMPS45)
834 ramp_delay_support = true;
e5ce4208
GG		 835 break;
836 case PALMAS_REG_SMPS457:
837 if (!pmic->smps457)
838 continue;
28d1e8cd
LD		 839 ramp_delay_support = true;
840 break;
841 }
842
3f4d6364 843 if ((id == PALMAS_REG_SMPS6) || (id == PALMAS_REG_SMPS8))
28d1e8cd
LD		 844 ramp_delay_support = true;
845
846 if (ramp_delay_support) {
847 addr = palmas_regs_info[id].tstep_addr;
848 ret = palmas_smps_read(pmic->palmas, addr, &reg);
849 if (ret < 0) {
850 dev_err(&pdev->dev,
851 "reading TSTEP reg failed: %d\n", ret);
852 goto err_unregister_regulator;
853 }
854 pmic->desc[id].ramp_delay =
855 palmas_smps_ramp_delay[reg & 0x3];
856 pmic->ramp_delay[id] = pmic->desc[id].ramp_delay;
e5ce4208
GG		 857 }
858
bdc4baac
AL		 859 /* Initialise sleep/init values from platform data */
860 if (pdata && pdata->reg_init[id]) {
861 reg_init = pdata->reg_init[id];
862 ret = palmas_smps_init(palmas, id, reg_init);
863 if (ret)
864 goto err_unregister_regulator;
865 }
866
e5ce4208
GG		 867 /* Register the regulators */
868 pmic->desc[id].name = palmas_regs_info[id].name;
869 pmic->desc[id].id = id;
870
fedd89b1
AL		 871 switch (id) {
872 case PALMAS_REG_SMPS10:
e5ce4208
GG		 873 pmic->desc[id].n_voltages = PALMAS_SMPS10_NUM_VOLTAGES;
874 pmic->desc[id].ops = &palmas_ops_smps10;
12565b16
AL		 875 pmic->desc[id].vsel_reg =
876 PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
877 PALMAS_SMPS10_CTRL);
e5ce4208 878 pmic->desc[id].vsel_mask = SMPS10_VSEL;
a68de074
GG		 879 pmic->desc[id].enable_reg =
880 PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
f232168d 881 PALMAS_SMPS10_CTRL);
e5ce4208 882 pmic->desc[id].enable_mask = SMPS10_BOOST_EN;
8029a006
AL		 883 pmic->desc[id].min_uV = 3750000;
884 pmic->desc[id].uV_step = 1250000;
fedd89b1
AL		 885 break;
886 default:
bdc4baac
AL		 887 /*
888 * Read and store the RANGE bit for later use
889 * This must be done before regulator is probed,
51d3a0c9
LD		 890 * otherwise we error in probe with unsupportable
891 * ranges. Read the current smps mode for later use.
bdc4baac 892 */
e5ce4208
GG		 893 addr = palmas_regs_info[id].vsel_addr;
894
895 ret = palmas_smps_read(pmic->palmas, addr, &reg);
896 if (ret)
897 goto err_unregister_regulator;
898 if (reg & PALMAS_SMPS12_VOLTAGE_RANGE)
899 pmic->range[id] = 1;
bdc4baac
AL		 900
901 pmic->desc[id].ops = &palmas_ops_smps;
902 pmic->desc[id].n_voltages = PALMAS_SMPS_NUM_VOLTAGES;
903 pmic->desc[id].vsel_reg =
904 PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
905 palmas_regs_info[id].vsel_addr);
906 pmic->desc[id].vsel_mask =
907 PALMAS_SMPS12_VOLTAGE_VSEL_MASK;
51d3a0c9
LD		 908
909 /* Read the smps mode for later use. */
910 addr = palmas_regs_info[id].ctrl_addr;
911 ret = palmas_smps_read(pmic->palmas, addr, &reg);
912 if (ret)
913 goto err_unregister_regulator;
914 pmic->current_reg_mode[id] = reg &
915 PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
e5ce4208
GG		 916 }
917
bdc4baac
AL		 918 pmic->desc[id].type = REGULATOR_VOLTAGE;
919 pmic->desc[id].owner = THIS_MODULE;
920
a361cd9f 921 if (pdata)
e5ce4208
GG		 922 config.init_data = pdata->reg_data[id];
923 else
924 config.init_data = NULL;
925
504382c9 926 pmic->desc[id].supply_name = palmas_regs_info[id].sname;
a361cd9f
GG		 927 config.of_node = palmas_matches[id].of_node;
928
e5ce4208
GG		 929 rdev = regulator_register(&pmic->desc[id], &config);
930 if (IS_ERR(rdev)) {
931 dev_err(&pdev->dev,
932 "failed to register %s regulator\n",
933 pdev->name);
934 ret = PTR_ERR(rdev);
935 goto err_unregister_regulator;
936 }
937
938 /* Save regulator for cleanup */
939 pmic->rdev[id] = rdev;
940 }
941
942 /* Start this loop from the id left from previous loop */
943 for (; id < PALMAS_NUM_REGS; id++) {
944
945 /* Miss out regulators which are not available due
946 * to alternate functions.
947 */
948
949 /* Register the regulators */
950 pmic->desc[id].name = palmas_regs_info[id].name;
951 pmic->desc[id].id = id;
e5ce4208
GG		 952 pmic->desc[id].type = REGULATOR_VOLTAGE;
953 pmic->desc[id].owner = THIS_MODULE;
aa07f027
LD		 954
955 if (id < PALMAS_REG_REGEN1) {
956 pmic->desc[id].n_voltages = PALMAS_LDO_NUM_VOLTAGES;
957 pmic->desc[id].ops = &palmas_ops_ldo;
958 pmic->desc[id].min_uV = 900000;
959 pmic->desc[id].uV_step = 50000;
960 pmic->desc[id].linear_min_sel = 1;
961 pmic->desc[id].vsel_reg =
962 PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
4a247a96 963 palmas_regs_info[id].vsel_addr);
aa07f027
LD		 964 pmic->desc[id].vsel_mask =
965 PALMAS_LDO1_VOLTAGE_VSEL_MASK;
966 pmic->desc[id].enable_reg =
967 PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
968 palmas_regs_info[id].ctrl_addr);
969 pmic->desc[id].enable_mask =
970 PALMAS_LDO1_CTRL_MODE_ACTIVE;
17c11a76
LD		 971
972 /* Check if LDO8 is in tracking mode or not */
973 if (pdata && (id == PALMAS_REG_LDO8) &&
974 pdata->enable_ldo8_tracking) {
975 palmas_enable_ldo8_track(palmas);
3df4a81c 976 pmic->desc[id].min_uV = 450000;
17c11a76
LD		 977 pmic->desc[id].uV_step = 25000;
978 }
aa07f027
LD		 979 } else {
980 pmic->desc[id].n_voltages = 1;
981 pmic->desc[id].ops = &palmas_ops_extreg;
982 pmic->desc[id].enable_reg =
983 PALMAS_BASE_TO_REG(PALMAS_RESOURCE_BASE,
a68de074 984 palmas_regs_info[id].ctrl_addr);
aa07f027
LD		 985 pmic->desc[id].enable_mask =
986 PALMAS_REGEN1_CTRL_MODE_ACTIVE;
987 }
e5ce4208 988
a361cd9f 989 if (pdata)
e5ce4208
GG		 990 config.init_data = pdata->reg_data[id];
991 else
992 config.init_data = NULL;
993
504382c9 994 pmic->desc[id].supply_name = palmas_regs_info[id].sname;
a361cd9f
GG		 995 config.of_node = palmas_matches[id].of_node;
996
e5ce4208
GG		 997 rdev = regulator_register(&pmic->desc[id], &config);
998 if (IS_ERR(rdev)) {
999 dev_err(&pdev->dev,
1000 "failed to register %s regulator\n",
1001 pdev->name);
1002 ret = PTR_ERR(rdev);
1003 goto err_unregister_regulator;
1004 }
1005
1006 /* Save regulator for cleanup */
1007 pmic->rdev[id] = rdev;
1008
1009 /* Initialise sleep/init values from platform data */
a361cd9f 1010 if (pdata) {
e5ce4208
GG		 1011 reg_init = pdata->reg_init[id];
1012 if (reg_init) {
aa07f027
LD		 1013 if (id < PALMAS_REG_REGEN1)
1014 ret = palmas_ldo_init(palmas,
1015 id, reg_init);
1016 else
1017 ret = palmas_extreg_init(palmas,
1018 id, reg_init);
1c9d2d71
AL		 1019 if (ret) {
1020 regulator_unregister(pmic->rdev[id]);
e5ce4208 1021 goto err_unregister_regulator;
1c9d2d71 1022 }
e5ce4208
GG		 1023 }
1024 }
1025 }
1026
17c11a76 1027
e5ce4208
GG		 1028 return 0;
1029
1030err_unregister_regulator:
1031 while (--id >= 0)
1032 regulator_unregister(pmic->rdev[id]);
e5ce4208
GG		 1033 return ret;
1034}
1035
bbcf50b1 1036static int palmas_regulators_remove(struct platform_device *pdev)
e5ce4208
GG		 1037{
1038 struct palmas_pmic *pmic = platform_get_drvdata(pdev);
1039 int id;
1040
1041 for (id = 0; id < PALMAS_NUM_REGS; id++)
1042 regulator_unregister(pmic->rdev[id]);
e5ce4208
GG		 1043 return 0;
1044}
1045
3d68dfe3 1046static struct of_device_id of_palmas_match_tbl[] = {
a361cd9f 1047 { .compatible = "ti,palmas-pmic", },
7be859f7
GG		 1048 { .compatible = "ti,twl6035-pmic", },
1049 { .compatible = "ti,twl6036-pmic", },
1050 { .compatible = "ti,twl6037-pmic", },
1051 { .compatible = "ti,tps65913-pmic", },
1052 { .compatible = "ti,tps65914-pmic", },
1053 { .compatible = "ti,tps80036-pmic", },
a361cd9f
GG		 1054 { /* end */ }
1055};
1056
e5ce4208
GG		 1057static struct platform_driver palmas_driver = {
1058 .driver = {
1059 .name = "palmas-pmic",
a361cd9f 1060 .of_match_table = of_palmas_match_tbl,
e5ce4208
GG		 1061 .owner = THIS_MODULE,
1062 },
bbcf50b1
LD		 1063 .probe = palmas_regulators_probe,
1064 .remove = palmas_regulators_remove,
e5ce4208
GG		 1065};
1066
1067static int __init palmas_init(void)
1068{
1069 return platform_driver_register(&palmas_driver);
1070}
1071subsys_initcall(palmas_init);
1072
1073static void __exit palmas_exit(void)
1074{
1075 platform_driver_unregister(&palmas_driver);
1076}
1077module_exit(palmas_exit);
1078
1079MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>");
1080MODULE_DESCRIPTION("Palmas voltage regulator driver");
1081MODULE_LICENSE("GPL");
1082MODULE_ALIAS("platform:palmas-pmic");
a361cd9f 1083MODULE_DEVICE_TABLE(of, of_palmas_match_tbl);
kernel source for telekom puls (alcatel/mediatek)