Commit | Line | Data |
---|---|---|
295c08bc SH |
1 | /* |
2 | * Regulator Driver for Freescale MC13783 PMIC | |
3 | * | |
167e3d8a | 4 | * Copyright 2010 Yong Shen <yong.shen@linaro.org> |
295c08bc | 5 | * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> |
1bd588fd | 6 | * Copyright 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com> |
295c08bc SH |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
a10099bc | 13 | #include <linux/mfd/mc13783.h> |
295c08bc SH |
14 | #include <linux/regulator/machine.h> |
15 | #include <linux/regulator/driver.h> | |
16 | #include <linux/platform_device.h> | |
295c08bc | 17 | #include <linux/kernel.h> |
5a0e3ad6 | 18 | #include <linux/slab.h> |
295c08bc SH |
19 | #include <linux/init.h> |
20 | #include <linux/err.h> | |
65602c32 | 21 | #include <linux/module.h> |
167e3d8a | 22 | #include "mc13xxx.h" |
295c08bc | 23 | |
a10099bc UKK |
24 | #define MC13783_REG_SWITCHERS5 29 |
25 | #define MC13783_REG_SWITCHERS5_SW3EN (1 << 20) | |
1bd588fd AP |
26 | #define MC13783_REG_SWITCHERS5_SW3VSEL 18 |
27 | #define MC13783_REG_SWITCHERS5_SW3VSEL_M (3 << 18) | |
28 | ||
29 | #define MC13783_REG_REGULATORSETTING0 30 | |
30 | #define MC13783_REG_REGULATORSETTING0_VIOLOVSEL 2 | |
31 | #define MC13783_REG_REGULATORSETTING0_VDIGVSEL 4 | |
32 | #define MC13783_REG_REGULATORSETTING0_VGENVSEL 6 | |
33 | #define MC13783_REG_REGULATORSETTING0_VRFDIGVSEL 9 | |
34 | #define MC13783_REG_REGULATORSETTING0_VRFREFVSEL 11 | |
35 | #define MC13783_REG_REGULATORSETTING0_VRFCPVSEL 13 | |
36 | #define MC13783_REG_REGULATORSETTING0_VSIMVSEL 14 | |
37 | #define MC13783_REG_REGULATORSETTING0_VESIMVSEL 15 | |
38 | #define MC13783_REG_REGULATORSETTING0_VCAMVSEL 16 | |
39 | ||
40 | #define MC13783_REG_REGULATORSETTING0_VIOLOVSEL_M (3 << 2) | |
41 | #define MC13783_REG_REGULATORSETTING0_VDIGVSEL_M (3 << 4) | |
42 | #define MC13783_REG_REGULATORSETTING0_VGENVSEL_M (7 << 6) | |
43 | #define MC13783_REG_REGULATORSETTING0_VRFDIGVSEL_M (3 << 9) | |
44 | #define MC13783_REG_REGULATORSETTING0_VRFREFVSEL_M (3 << 11) | |
45 | #define MC13783_REG_REGULATORSETTING0_VRFCPVSEL_M (1 << 13) | |
46 | #define MC13783_REG_REGULATORSETTING0_VSIMVSEL_M (1 << 14) | |
47 | #define MC13783_REG_REGULATORSETTING0_VESIMVSEL_M (1 << 15) | |
48 | #define MC13783_REG_REGULATORSETTING0_VCAMVSEL_M (7 << 16) | |
49 | ||
50 | #define MC13783_REG_REGULATORSETTING1 31 | |
51 | #define MC13783_REG_REGULATORSETTING1_VVIBVSEL 0 | |
52 | #define MC13783_REG_REGULATORSETTING1_VRF1VSEL 2 | |
53 | #define MC13783_REG_REGULATORSETTING1_VRF2VSEL 4 | |
54 | #define MC13783_REG_REGULATORSETTING1_VMMC1VSEL 6 | |
55 | #define MC13783_REG_REGULATORSETTING1_VMMC2VSEL 9 | |
56 | ||
57 | #define MC13783_REG_REGULATORSETTING1_VVIBVSEL_M (3 << 0) | |
58 | #define MC13783_REG_REGULATORSETTING1_VRF1VSEL_M (3 << 2) | |
59 | #define MC13783_REG_REGULATORSETTING1_VRF2VSEL_M (3 << 4) | |
60 | #define MC13783_REG_REGULATORSETTING1_VMMC1VSEL_M (7 << 6) | |
61 | #define MC13783_REG_REGULATORSETTING1_VMMC2VSEL_M (7 << 9) | |
a10099bc UKK |
62 | |
63 | #define MC13783_REG_REGULATORMODE0 32 | |
64 | #define MC13783_REG_REGULATORMODE0_VAUDIOEN (1 << 0) | |
65 | #define MC13783_REG_REGULATORMODE0_VIOHIEN (1 << 3) | |
66 | #define MC13783_REG_REGULATORMODE0_VIOLOEN (1 << 6) | |
67 | #define MC13783_REG_REGULATORMODE0_VDIGEN (1 << 9) | |
68 | #define MC13783_REG_REGULATORMODE0_VGENEN (1 << 12) | |
69 | #define MC13783_REG_REGULATORMODE0_VRFDIGEN (1 << 15) | |
70 | #define MC13783_REG_REGULATORMODE0_VRFREFEN (1 << 18) | |
71 | #define MC13783_REG_REGULATORMODE0_VRFCPEN (1 << 21) | |
72 | ||
73 | #define MC13783_REG_REGULATORMODE1 33 | |
74 | #define MC13783_REG_REGULATORMODE1_VSIMEN (1 << 0) | |
75 | #define MC13783_REG_REGULATORMODE1_VESIMEN (1 << 3) | |
76 | #define MC13783_REG_REGULATORMODE1_VCAMEN (1 << 6) | |
77 | #define MC13783_REG_REGULATORMODE1_VRFBGEN (1 << 9) | |
78 | #define MC13783_REG_REGULATORMODE1_VVIBEN (1 << 11) | |
79 | #define MC13783_REG_REGULATORMODE1_VRF1EN (1 << 12) | |
80 | #define MC13783_REG_REGULATORMODE1_VRF2EN (1 << 15) | |
81 | #define MC13783_REG_REGULATORMODE1_VMMC1EN (1 << 18) | |
82 | #define MC13783_REG_REGULATORMODE1_VMMC2EN (1 << 21) | |
83 | ||
84 | #define MC13783_REG_POWERMISC 34 | |
85 | #define MC13783_REG_POWERMISC_GPO1EN (1 << 6) | |
86 | #define MC13783_REG_POWERMISC_GPO2EN (1 << 8) | |
87 | #define MC13783_REG_POWERMISC_GPO3EN (1 << 10) | |
88 | #define MC13783_REG_POWERMISC_GPO4EN (1 << 12) | |
f4b97b36 AP |
89 | #define MC13783_REG_POWERMISC_PWGT1SPIEN (1 << 15) |
90 | #define MC13783_REG_POWERMISC_PWGT2SPIEN (1 << 16) | |
91 | ||
92 | #define MC13783_REG_POWERMISC_PWGTSPI_M (3 << 15) | |
93 | ||
a10099bc | 94 | |
1bd588fd | 95 | /* Voltage Values */ |
34e74f39 | 96 | static const unsigned int mc13783_sw3_val[] = { |
1bd588fd AP |
97 | 5000000, 5000000, 5000000, 5500000, |
98 | }; | |
99 | ||
34e74f39 | 100 | static const unsigned int mc13783_vaudio_val[] = { |
1bd588fd AP |
101 | 2775000, |
102 | }; | |
103 | ||
34e74f39 | 104 | static const unsigned int mc13783_viohi_val[] = { |
1bd588fd AP |
105 | 2775000, |
106 | }; | |
107 | ||
34e74f39 | 108 | static const unsigned int mc13783_violo_val[] = { |
1bd588fd AP |
109 | 1200000, 1300000, 1500000, 1800000, |
110 | }; | |
111 | ||
34e74f39 | 112 | static const unsigned int mc13783_vdig_val[] = { |
1bd588fd AP |
113 | 1200000, 1300000, 1500000, 1800000, |
114 | }; | |
115 | ||
34e74f39 | 116 | static const unsigned int mc13783_vgen_val[] = { |
1bd588fd AP |
117 | 1200000, 1300000, 1500000, 1800000, |
118 | 1100000, 2000000, 2775000, 2400000, | |
119 | }; | |
120 | ||
34e74f39 | 121 | static const unsigned int mc13783_vrfdig_val[] = { |
1bd588fd AP |
122 | 1200000, 1500000, 1800000, 1875000, |
123 | }; | |
124 | ||
34e74f39 | 125 | static const unsigned int mc13783_vrfref_val[] = { |
1bd588fd AP |
126 | 2475000, 2600000, 2700000, 2775000, |
127 | }; | |
128 | ||
34e74f39 | 129 | static const unsigned int mc13783_vrfcp_val[] = { |
1bd588fd AP |
130 | 2700000, 2775000, |
131 | }; | |
132 | ||
34e74f39 | 133 | static const unsigned int mc13783_vsim_val[] = { |
1bd588fd AP |
134 | 1800000, 2900000, 3000000, |
135 | }; | |
136 | ||
34e74f39 | 137 | static const unsigned int mc13783_vesim_val[] = { |
1bd588fd AP |
138 | 1800000, 2900000, |
139 | }; | |
140 | ||
34e74f39 | 141 | static const unsigned int mc13783_vcam_val[] = { |
1bd588fd AP |
142 | 1500000, 1800000, 2500000, 2550000, |
143 | 2600000, 2750000, 2800000, 3000000, | |
144 | }; | |
145 | ||
34e74f39 | 146 | static const unsigned int mc13783_vrfbg_val[] = { |
1bd588fd AP |
147 | 1250000, |
148 | }; | |
149 | ||
34e74f39 | 150 | static const unsigned int mc13783_vvib_val[] = { |
1bd588fd AP |
151 | 1300000, 1800000, 2000000, 3000000, |
152 | }; | |
153 | ||
34e74f39 | 154 | static const unsigned int mc13783_vmmc_val[] = { |
1bd588fd AP |
155 | 1600000, 1800000, 2000000, 2600000, |
156 | 2700000, 2800000, 2900000, 3000000, | |
157 | }; | |
158 | ||
34e74f39 | 159 | static const unsigned int mc13783_vrf_val[] = { |
1bd588fd | 160 | 1500000, 1875000, 2700000, 2775000, |
295c08bc SH |
161 | }; |
162 | ||
34e74f39 | 163 | static const unsigned int mc13783_gpo_val[] = { |
f4b97b36 AP |
164 | 3100000, |
165 | }; | |
166 | ||
34e74f39 | 167 | static const unsigned int mc13783_pwgtdrv_val[] = { |
f4b97b36 AP |
168 | 5500000, |
169 | }; | |
170 | ||
f4b97b36 | 171 | static struct regulator_ops mc13783_gpo_regulator_ops; |
1bd588fd | 172 | |
167e3d8a YS |
173 | #define MC13783_DEFINE(prefix, name, reg, vsel_reg, voltages) \ |
174 | MC13xxx_DEFINE(MC13783_REG_, name, reg, vsel_reg, voltages, \ | |
175 | mc13xxx_regulator_ops) | |
295c08bc | 176 | |
167e3d8a YS |
177 | #define MC13783_FIXED_DEFINE(prefix, name, reg, voltages) \ |
178 | MC13xxx_FIXED_DEFINE(MC13783_REG_, name, reg, voltages, \ | |
179 | mc13xxx_fixed_regulator_ops) | |
1bd588fd | 180 | |
167e3d8a YS |
181 | #define MC13783_GPO_DEFINE(prefix, name, reg, voltages) \ |
182 | MC13xxx_GPO_DEFINE(MC13783_REG_, name, reg, voltages, \ | |
183 | mc13783_gpo_regulator_ops) | |
a10099bc | 184 | |
1bd588fd | 185 | #define MC13783_DEFINE_SW(_name, _reg, _vsel_reg, _voltages) \ |
57c78e35 | 186 | MC13783_DEFINE(REG, _name, _reg, _vsel_reg, _voltages) |
1bd588fd | 187 | #define MC13783_DEFINE_REGU(_name, _reg, _vsel_reg, _voltages) \ |
57c78e35 | 188 | MC13783_DEFINE(REG, _name, _reg, _vsel_reg, _voltages) |
a10099bc | 189 | |
167e3d8a | 190 | static struct mc13xxx_regulator mc13783_regulators[] = { |
1bd588fd AP |
191 | MC13783_DEFINE_SW(SW3, SWITCHERS5, SWITCHERS5, mc13783_sw3_val), |
192 | ||
57c78e35 YS |
193 | MC13783_FIXED_DEFINE(REG, VAUDIO, REGULATORMODE0, mc13783_vaudio_val), |
194 | MC13783_FIXED_DEFINE(REG, VIOHI, REGULATORMODE0, mc13783_viohi_val), | |
1bd588fd AP |
195 | MC13783_DEFINE_REGU(VIOLO, REGULATORMODE0, REGULATORSETTING0, \ |
196 | mc13783_violo_val), | |
197 | MC13783_DEFINE_REGU(VDIG, REGULATORMODE0, REGULATORSETTING0, \ | |
198 | mc13783_vdig_val), | |
199 | MC13783_DEFINE_REGU(VGEN, REGULATORMODE0, REGULATORSETTING0, \ | |
200 | mc13783_vgen_val), | |
201 | MC13783_DEFINE_REGU(VRFDIG, REGULATORMODE0, REGULATORSETTING0, \ | |
202 | mc13783_vrfdig_val), | |
203 | MC13783_DEFINE_REGU(VRFREF, REGULATORMODE0, REGULATORSETTING0, \ | |
204 | mc13783_vrfref_val), | |
205 | MC13783_DEFINE_REGU(VRFCP, REGULATORMODE0, REGULATORSETTING0, \ | |
206 | mc13783_vrfcp_val), | |
207 | MC13783_DEFINE_REGU(VSIM, REGULATORMODE1, REGULATORSETTING0, \ | |
208 | mc13783_vsim_val), | |
209 | MC13783_DEFINE_REGU(VESIM, REGULATORMODE1, REGULATORSETTING0, \ | |
210 | mc13783_vesim_val), | |
211 | MC13783_DEFINE_REGU(VCAM, REGULATORMODE1, REGULATORSETTING0, \ | |
212 | mc13783_vcam_val), | |
57c78e35 | 213 | MC13783_FIXED_DEFINE(REG, VRFBG, REGULATORMODE1, mc13783_vrfbg_val), |
1bd588fd AP |
214 | MC13783_DEFINE_REGU(VVIB, REGULATORMODE1, REGULATORSETTING1, \ |
215 | mc13783_vvib_val), | |
216 | MC13783_DEFINE_REGU(VRF1, REGULATORMODE1, REGULATORSETTING1, \ | |
217 | mc13783_vrf_val), | |
218 | MC13783_DEFINE_REGU(VRF2, REGULATORMODE1, REGULATORSETTING1, \ | |
219 | mc13783_vrf_val), | |
220 | MC13783_DEFINE_REGU(VMMC1, REGULATORMODE1, REGULATORSETTING1, \ | |
221 | mc13783_vmmc_val), | |
222 | MC13783_DEFINE_REGU(VMMC2, REGULATORMODE1, REGULATORSETTING1, \ | |
223 | mc13783_vmmc_val), | |
57c78e35 YS |
224 | MC13783_GPO_DEFINE(REG, GPO1, POWERMISC, mc13783_gpo_val), |
225 | MC13783_GPO_DEFINE(REG, GPO2, POWERMISC, mc13783_gpo_val), | |
226 | MC13783_GPO_DEFINE(REG, GPO3, POWERMISC, mc13783_gpo_val), | |
227 | MC13783_GPO_DEFINE(REG, GPO4, POWERMISC, mc13783_gpo_val), | |
228 | MC13783_GPO_DEFINE(REG, PWGT1SPI, POWERMISC, mc13783_pwgtdrv_val), | |
229 | MC13783_GPO_DEFINE(REG, PWGT2SPI, POWERMISC, mc13783_pwgtdrv_val), | |
295c08bc SH |
230 | }; |
231 | ||
167e3d8a YS |
232 | static int mc13783_powermisc_rmw(struct mc13xxx_regulator_priv *priv, u32 mask, |
233 | u32 val) | |
f4b97b36 | 234 | { |
167e3d8a | 235 | struct mc13xxx *mc13783 = priv->mc13xxx; |
f4b97b36 AP |
236 | int ret; |
237 | u32 valread; | |
238 | ||
239 | BUG_ON(val & ~mask); | |
240 | ||
2a2c3ac0 | 241 | mc13xxx_lock(priv->mc13xxx); |
167e3d8a | 242 | ret = mc13xxx_reg_read(mc13783, MC13783_REG_POWERMISC, &valread); |
f4b97b36 | 243 | if (ret) |
2a2c3ac0 | 244 | goto out; |
f4b97b36 AP |
245 | |
246 | /* Update the stored state for Power Gates. */ | |
247 | priv->powermisc_pwgt_state = | |
248 | (priv->powermisc_pwgt_state & ~mask) | val; | |
249 | priv->powermisc_pwgt_state &= MC13783_REG_POWERMISC_PWGTSPI_M; | |
250 | ||
251 | /* Construct the new register value */ | |
252 | valread = (valread & ~mask) | val; | |
253 | /* Overwrite the PWGTxEN with the stored version */ | |
254 | valread = (valread & ~MC13783_REG_POWERMISC_PWGTSPI_M) | | |
255 | priv->powermisc_pwgt_state; | |
256 | ||
2a2c3ac0 AL |
257 | ret = mc13xxx_reg_write(mc13783, MC13783_REG_POWERMISC, valread); |
258 | out: | |
259 | mc13xxx_unlock(priv->mc13xxx); | |
260 | return ret; | |
f4b97b36 AP |
261 | } |
262 | ||
263 | static int mc13783_gpo_regulator_enable(struct regulator_dev *rdev) | |
264 | { | |
167e3d8a YS |
265 | struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev); |
266 | struct mc13xxx_regulator *mc13xxx_regulators = priv->mc13xxx_regulators; | |
f4b97b36 | 267 | int id = rdev_get_id(rdev); |
167e3d8a | 268 | u32 en_val = mc13xxx_regulators[id].enable_bit; |
f4b97b36 AP |
269 | |
270 | dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id); | |
271 | ||
272 | /* Power Gate enable value is 0 */ | |
57c78e35 YS |
273 | if (id == MC13783_REG_PWGT1SPI || |
274 | id == MC13783_REG_PWGT2SPI) | |
f4b97b36 AP |
275 | en_val = 0; |
276 | ||
2a2c3ac0 | 277 | return mc13783_powermisc_rmw(priv, mc13xxx_regulators[id].enable_bit, |
f4b97b36 | 278 | en_val); |
f4b97b36 AP |
279 | } |
280 | ||
281 | static int mc13783_gpo_regulator_disable(struct regulator_dev *rdev) | |
282 | { | |
167e3d8a YS |
283 | struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev); |
284 | struct mc13xxx_regulator *mc13xxx_regulators = priv->mc13xxx_regulators; | |
f4b97b36 | 285 | int id = rdev_get_id(rdev); |
f4b97b36 AP |
286 | u32 dis_val = 0; |
287 | ||
288 | dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id); | |
289 | ||
290 | /* Power Gate disable value is 1 */ | |
57c78e35 YS |
291 | if (id == MC13783_REG_PWGT1SPI || |
292 | id == MC13783_REG_PWGT2SPI) | |
167e3d8a | 293 | dis_val = mc13xxx_regulators[id].enable_bit; |
f4b97b36 | 294 | |
2a2c3ac0 | 295 | return mc13783_powermisc_rmw(priv, mc13xxx_regulators[id].enable_bit, |
f4b97b36 | 296 | dis_val); |
f4b97b36 AP |
297 | } |
298 | ||
299 | static int mc13783_gpo_regulator_is_enabled(struct regulator_dev *rdev) | |
300 | { | |
167e3d8a YS |
301 | struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev); |
302 | struct mc13xxx_regulator *mc13xxx_regulators = priv->mc13xxx_regulators; | |
f4b97b36 AP |
303 | int ret, id = rdev_get_id(rdev); |
304 | unsigned int val; | |
305 | ||
167e3d8a YS |
306 | mc13xxx_lock(priv->mc13xxx); |
307 | ret = mc13xxx_reg_read(priv->mc13xxx, mc13xxx_regulators[id].reg, &val); | |
308 | mc13xxx_unlock(priv->mc13xxx); | |
f4b97b36 AP |
309 | |
310 | if (ret) | |
311 | return ret; | |
312 | ||
313 | /* Power Gates state is stored in powermisc_pwgt_state | |
314 | * where the meaning of bits is negated */ | |
315 | val = (val & ~MC13783_REG_POWERMISC_PWGTSPI_M) | | |
316 | (priv->powermisc_pwgt_state ^ MC13783_REG_POWERMISC_PWGTSPI_M); | |
317 | ||
167e3d8a | 318 | return (val & mc13xxx_regulators[id].enable_bit) != 0; |
f4b97b36 AP |
319 | } |
320 | ||
321 | static struct regulator_ops mc13783_gpo_regulator_ops = { | |
322 | .enable = mc13783_gpo_regulator_enable, | |
323 | .disable = mc13783_gpo_regulator_disable, | |
324 | .is_enabled = mc13783_gpo_regulator_is_enabled, | |
34e74f39 | 325 | .list_voltage = regulator_list_voltage_table, |
167e3d8a | 326 | .set_voltage = mc13xxx_fixed_regulator_set_voltage, |
f4b97b36 AP |
327 | }; |
328 | ||
295c08bc SH |
329 | static int __devinit mc13783_regulator_probe(struct platform_device *pdev) |
330 | { | |
167e3d8a YS |
331 | struct mc13xxx_regulator_priv *priv; |
332 | struct mc13xxx *mc13783 = dev_get_drvdata(pdev->dev.parent); | |
8f1585aa | 333 | struct mc13xxx_regulator_platform_data *pdata = |
c8a03c96 | 334 | dev_get_platdata(&pdev->dev); |
8f1585aa | 335 | struct mc13xxx_regulator_init_data *init_data; |
a9d58010 | 336 | struct regulator_config config = { }; |
295c08bc SH |
337 | int i, ret; |
338 | ||
c719864f | 339 | dev_dbg(&pdev->dev, "%s id %d\n", __func__, pdev->id); |
295c08bc | 340 | |
0757b602 SH |
341 | if (!pdata) |
342 | return -EINVAL; | |
343 | ||
cbe10a36 | 344 | priv = devm_kzalloc(&pdev->dev, sizeof(*priv) + |
a10099bc | 345 | pdata->num_regulators * sizeof(priv->regulators[0]), |
295c08bc SH |
346 | GFP_KERNEL); |
347 | if (!priv) | |
348 | return -ENOMEM; | |
349 | ||
167e3d8a YS |
350 | priv->mc13xxx_regulators = mc13783_regulators; |
351 | priv->mc13xxx = mc13783; | |
295c08bc | 352 | |
a10099bc | 353 | for (i = 0; i < pdata->num_regulators; i++) { |
a9d58010 AL |
354 | struct regulator_desc *desc; |
355 | ||
a10099bc | 356 | init_data = &pdata->regulators[i]; |
a9d58010 AL |
357 | desc = &mc13783_regulators[init_data->id].desc; |
358 | ||
359 | config.dev = &pdev->dev; | |
360 | config.init_data = init_data->init_data; | |
361 | config.driver_data = priv; | |
295c08bc | 362 | |
a9d58010 | 363 | priv->regulators[i] = regulator_register(desc, &config); |
295c08bc SH |
364 | if (IS_ERR(priv->regulators[i])) { |
365 | dev_err(&pdev->dev, "failed to register regulator %s\n", | |
366 | mc13783_regulators[i].desc.name); | |
367 | ret = PTR_ERR(priv->regulators[i]); | |
368 | goto err; | |
369 | } | |
370 | } | |
371 | ||
372 | platform_set_drvdata(pdev, priv); | |
373 | ||
374 | return 0; | |
375 | err: | |
376 | while (--i >= 0) | |
377 | regulator_unregister(priv->regulators[i]); | |
378 | ||
295c08bc SH |
379 | return ret; |
380 | } | |
381 | ||
382 | static int __devexit mc13783_regulator_remove(struct platform_device *pdev) | |
383 | { | |
167e3d8a | 384 | struct mc13xxx_regulator_priv *priv = platform_get_drvdata(pdev); |
8f1585aa | 385 | struct mc13xxx_regulator_platform_data *pdata = |
c8a03c96 | 386 | dev_get_platdata(&pdev->dev); |
295c08bc SH |
387 | int i; |
388 | ||
58d57658 AL |
389 | platform_set_drvdata(pdev, NULL); |
390 | ||
a10099bc | 391 | for (i = 0; i < pdata->num_regulators; i++) |
295c08bc SH |
392 | regulator_unregister(priv->regulators[i]); |
393 | ||
394 | return 0; | |
395 | } | |
396 | ||
397 | static struct platform_driver mc13783_regulator_driver = { | |
398 | .driver = { | |
399 | .name = "mc13783-regulator", | |
400 | .owner = THIS_MODULE, | |
401 | }, | |
402 | .remove = __devexit_p(mc13783_regulator_remove), | |
735eb93a | 403 | .probe = mc13783_regulator_probe, |
295c08bc SH |
404 | }; |
405 | ||
406 | static int __init mc13783_regulator_init(void) | |
407 | { | |
735eb93a | 408 | return platform_driver_register(&mc13783_regulator_driver); |
295c08bc SH |
409 | } |
410 | subsys_initcall(mc13783_regulator_init); | |
411 | ||
412 | static void __exit mc13783_regulator_exit(void) | |
413 | { | |
414 | platform_driver_unregister(&mc13783_regulator_driver); | |
415 | } | |
416 | module_exit(mc13783_regulator_exit); | |
417 | ||
a10099bc | 418 | MODULE_LICENSE("GPL v2"); |
1dcc434b | 419 | MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); |
295c08bc SH |
420 | MODULE_DESCRIPTION("Regulator Driver for Freescale MC13783 PMIC"); |
421 | MODULE_ALIAS("platform:mc13783-regulator"); |