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regulator: ab8500: Amend the update value for AB8500_LDO_INTCORE regulator
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / regulator / ab8500.c
CommitLineData
c789ca20
SI		 1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License v2
5 *
e1159e6d
BJ		 6 * Authors: Sundar Iyer <sundar.iyer@stericsson.com> for ST-Ericsson
7 * Bengt Jonsson <bengt.g.jonsson@stericsson.com> for ST-Ericsson
c789ca20
SI		 8 *
9 * AB8500 peripheral regulators
10 *
e1159e6d 11 * AB8500 supports the following regulators:
ea05ef31 12 * VAUX1/2/3, VINTCORE, VTVOUT, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA
c789ca20
SI		 13 */
14#include <linux/init.h>
15#include <linux/kernel.h>
65602c32 16#include <linux/module.h>
c789ca20
SI		 17#include <linux/err.h>
18#include <linux/platform_device.h>
47c16975 19#include <linux/mfd/abx500.h>
ee66e653 20#include <linux/mfd/abx500/ab8500.h>
3a8334b9
LJ		 21#include <linux/of.h>
22#include <linux/regulator/of_regulator.h>
c789ca20
SI		 23#include <linux/regulator/driver.h>
24#include <linux/regulator/machine.h>
25#include <linux/regulator/ab8500.h>
3a8334b9 26#include <linux/slab.h>
c789ca20
SI		 27
28/**
29 * struct ab8500_regulator_info - ab8500 regulator information
e1159e6d 30 * @dev: device pointer
c789ca20 31 * @desc: regulator description
c789ca20 32 * @regulator_dev: regulator device
bd28a157 33 * @is_enabled: status of regulator (on/off)
7ce4669c 34 * @load_lp_uA: maximum load in idle (low power) mode
47c16975 35 * @update_bank: bank to control on/off
c789ca20 36 * @update_reg: register to control on/off
bd28a157
EV		 37 * @update_mask: mask to enable/disable and set mode of regulator
38 * @update_val: bits holding the regulator current mode
39 * @update_val_idle: bits to enable the regulator in idle (low power) mode
40 * @update_val_normal: bits to enable the regulator in normal (high power) mode
47c16975 41 * @voltage_bank: bank to control regulator voltage
c789ca20
SI		 42 * @voltage_reg: register to control regulator voltage
43 * @voltage_mask: mask to control regulator voltage
a0a7014c 44 * @voltage_shift: shift to control regulator voltage
c789ca20
SI		 45 */
46struct ab8500_regulator_info {
47 struct device *dev;
48 struct regulator_desc desc;
c789ca20 49 struct regulator_dev *regulator;
bd28a157 50 bool is_enabled;
7ce4669c 51 int load_lp_uA;
47c16975
MW		 52 u8 update_bank;
53 u8 update_reg;
e1159e6d 54 u8 update_mask;
bd28a157
EV		 55 u8 update_val;
56 u8 update_val_idle;
57 u8 update_val_normal;
47c16975
MW		 58 u8 voltage_bank;
59 u8 voltage_reg;
60 u8 voltage_mask;
a0a7014c 61 u8 voltage_shift;
c789ca20
SI		 62};
63
64/* voltage tables for the vauxn/vintcore supplies */
ec1cc4d9 65static const unsigned int ldo_vauxn_voltages[] = {
c789ca20
SI		 66 1100000,
67 1200000,
68 1300000,
69 1400000,
70 1500000,
71 1800000,
72 1850000,
73 1900000,
74 2500000,
75 2650000,
76 2700000,
77 2750000,
78 2800000,
79 2900000,
80 3000000,
81 3300000,
82};
83
ec1cc4d9 84static const unsigned int ldo_vaux3_voltages[] = {
2b75151a
BJ		 85 1200000,
86 1500000,
87 1800000,
88 2100000,
89 2500000,
90 2750000,
91 2790000,
92 2910000,
93};
94
ec1cc4d9 95static const unsigned int ldo_vintcore_voltages[] = {
c789ca20
SI		 96 1200000,
97 1225000,
98 1250000,
99 1275000,
100 1300000,
101 1325000,
102 1350000,
103};
104
105static int ab8500_regulator_enable(struct regulator_dev *rdev)
106{
fc24b426 107 int ret;
c789ca20
SI		 108 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
109
fc24b426
BJ		 110 if (info == NULL) {
111 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 112 return -EINVAL;
fc24b426 113 }
c789ca20 114
47c16975 115 ret = abx500_mask_and_set_register_interruptible(info->dev,
e1159e6d 116 info->update_bank, info->update_reg,
bd28a157 117 info->update_mask, info->update_val);
f71bf528 118 if (ret < 0) {
c789ca20
SI		 119 dev_err(rdev_get_dev(rdev),
120 "couldn't set enable bits for regulator\n");
f71bf528
AL		 121 return ret;
122 }
09aefa12 123
bd28a157
EV		 124 info->is_enabled = true;
125
09aefa12
BJ		 126 dev_vdbg(rdev_get_dev(rdev),
127 "%s-enable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
128 info->desc.name, info->update_bank, info->update_reg,
bd28a157 129 info->update_mask, info->update_val);
09aefa12 130
c789ca20
SI		 131 return ret;
132}
133
134static int ab8500_regulator_disable(struct regulator_dev *rdev)
135{
fc24b426 136 int ret;
c789ca20
SI		 137 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
138
fc24b426
BJ		 139 if (info == NULL) {
140 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 141 return -EINVAL;
fc24b426 142 }
c789ca20 143
47c16975 144 ret = abx500_mask_and_set_register_interruptible(info->dev,
e1159e6d
BJ		 145 info->update_bank, info->update_reg,
146 info->update_mask, 0x0);
f71bf528 147 if (ret < 0) {
c789ca20
SI		 148 dev_err(rdev_get_dev(rdev),
149 "couldn't set disable bits for regulator\n");
f71bf528
AL		 150 return ret;
151 }
09aefa12 152
bd28a157
EV		 153 info->is_enabled = false;
154
09aefa12
BJ		 155 dev_vdbg(rdev_get_dev(rdev),
156 "%s-disable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
157 info->desc.name, info->update_bank, info->update_reg,
158 info->update_mask, 0x0);
159
c789ca20
SI		 160 return ret;
161}
162
7ce4669c
BJ		 163static unsigned int ab8500_regulator_get_optimum_mode(
164 struct regulator_dev *rdev, int input_uV,
165 int output_uV, int load_uA)
166{
167 unsigned int mode;
168
169 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
170
171 if (info == NULL) {
172 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
173 return -EINVAL;
174 }
175
176 if (load_uA <= info->load_lp_uA)
177 mode = REGULATOR_MODE_IDLE;
178 else
179 mode = REGULATOR_MODE_NORMAL;
180
181 return mode;
182}
183
bd28a157
EV		 184static int ab8500_regulator_set_mode(struct regulator_dev *rdev,
185 unsigned int mode)
186{
187 int ret = 0;
188
189 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
190
191 if (info == NULL) {
192 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
193 return -EINVAL;
194 }
195
196 switch (mode) {
197 case REGULATOR_MODE_NORMAL:
198 info->update_val = info->update_val_normal;
199 break;
200 case REGULATOR_MODE_IDLE:
201 info->update_val = info->update_val_idle;
202 break;
203 default:
204 return -EINVAL;
205 }
206
207 if (info->is_enabled) {
208 ret = abx500_mask_and_set_register_interruptible(info->dev,
209 info->update_bank, info->update_reg,
210 info->update_mask, info->update_val);
211 if (ret < 0)
212 dev_err(rdev_get_dev(rdev),
213 "couldn't set regulator mode\n");
7ce4669c
BJ		 214
215 dev_vdbg(rdev_get_dev(rdev),
216 "%s-set_mode (bank, reg, mask, value): "
217 "0x%x, 0x%x, 0x%x, 0x%x\n",
218 info->desc.name, info->update_bank, info->update_reg,
219 info->update_mask, info->update_val);
bd28a157
EV		 220 }
221
222 return ret;
223}
224
225static unsigned int ab8500_regulator_get_mode(struct regulator_dev *rdev)
226{
227 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
228 int ret;
229
230 if (info == NULL) {
231 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
232 return -EINVAL;
233 }
234
235 if (info->update_val == info->update_val_normal)
236 ret = REGULATOR_MODE_NORMAL;
237 else if (info->update_val == info->update_val_idle)
238 ret = REGULATOR_MODE_IDLE;
239 else
240 ret = -EINVAL;
241
242 return ret;
243}
244
c789ca20
SI		 245static int ab8500_regulator_is_enabled(struct regulator_dev *rdev)
246{
fc24b426 247 int ret;
c789ca20 248 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
09aefa12 249 u8 regval;
c789ca20 250
fc24b426
BJ		 251 if (info == NULL) {
252 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 253 return -EINVAL;
fc24b426 254 }
c789ca20 255
47c16975 256 ret = abx500_get_register_interruptible(info->dev,
09aefa12 257 info->update_bank, info->update_reg, &regval);
c789ca20
SI		 258 if (ret < 0) {
259 dev_err(rdev_get_dev(rdev),
260 "couldn't read 0x%x register\n", info->update_reg);
261 return ret;
262 }
263
09aefa12
BJ		 264 dev_vdbg(rdev_get_dev(rdev),
265 "%s-is_enabled (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
266 " 0x%x\n",
267 info->desc.name, info->update_bank, info->update_reg,
268 info->update_mask, regval);
269
270 if (regval & info->update_mask)
bd28a157 271 info->is_enabled = true;
c789ca20 272 else
bd28a157
EV		 273 info->is_enabled = false;
274
275 return info->is_enabled;
c789ca20
SI		 276}
277
3bf6e90e 278static int ab8500_regulator_get_voltage_sel(struct regulator_dev *rdev)
c789ca20 279{
09aefa12 280 int ret, val;
c789ca20 281 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
09aefa12 282 u8 regval;
c789ca20 283
fc24b426
BJ		 284 if (info == NULL) {
285 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 286 return -EINVAL;
fc24b426 287 }
c789ca20 288
09aefa12
BJ		 289 ret = abx500_get_register_interruptible(info->dev,
290 info->voltage_bank, info->voltage_reg, &regval);
c789ca20
SI		 291 if (ret < 0) {
292 dev_err(rdev_get_dev(rdev),
293 "couldn't read voltage reg for regulator\n");
294 return ret;
295 }
296
09aefa12 297 dev_vdbg(rdev_get_dev(rdev),
a0a7014c
LW		 298 "%s-get_voltage (bank, reg, mask, shift, value): "
299 "0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n",
300 info->desc.name, info->voltage_bank,
301 info->voltage_reg, info->voltage_mask,
302 info->voltage_shift, regval);
09aefa12 303
09aefa12 304 val = regval & info->voltage_mask;
a0a7014c 305 return val >> info->voltage_shift;
c789ca20
SI		 306}
307
ae713d39
AL		 308static int ab8500_regulator_set_voltage_sel(struct regulator_dev *rdev,
309 unsigned selector)
c789ca20 310{
fc24b426 311 int ret;
c789ca20 312 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
09aefa12 313 u8 regval;
c789ca20 314
fc24b426
BJ		 315 if (info == NULL) {
316 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 317 return -EINVAL;
fc24b426 318 }
c789ca20 319
c789ca20 320 /* set the registers for the request */
a0a7014c 321 regval = (u8)selector << info->voltage_shift;
47c16975 322 ret = abx500_mask_and_set_register_interruptible(info->dev,
09aefa12
BJ		 323 info->voltage_bank, info->voltage_reg,
324 info->voltage_mask, regval);
c789ca20
SI		 325 if (ret < 0)
326 dev_err(rdev_get_dev(rdev),
327 "couldn't set voltage reg for regulator\n");
328
09aefa12
BJ		 329 dev_vdbg(rdev_get_dev(rdev),
330 "%s-set_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
331 " 0x%x\n",
332 info->desc.name, info->voltage_bank, info->voltage_reg,
333 info->voltage_mask, regval);
334
c789ca20
SI		 335 return ret;
336}
337
7ce4669c
BJ		 338static struct regulator_ops ab8500_regulator_volt_mode_ops = {
339 .enable = ab8500_regulator_enable,
340 .disable = ab8500_regulator_disable,
341 .is_enabled = ab8500_regulator_is_enabled,
342 .get_optimum_mode = ab8500_regulator_get_optimum_mode,
343 .set_mode = ab8500_regulator_set_mode,
344 .get_mode = ab8500_regulator_get_mode,
345 .get_voltage_sel = ab8500_regulator_get_voltage_sel,
346 .set_voltage_sel = ab8500_regulator_set_voltage_sel,
347 .list_voltage = regulator_list_voltage_table,
c789ca20
SI		 348};
349
7ce4669c
BJ		 350static struct regulator_ops ab8500_regulator_mode_ops = {
351 .enable = ab8500_regulator_enable,
352 .disable = ab8500_regulator_disable,
353 .is_enabled = ab8500_regulator_is_enabled,
354 .get_optimum_mode = ab8500_regulator_get_optimum_mode,
355 .set_mode = ab8500_regulator_set_mode,
356 .get_mode = ab8500_regulator_get_mode,
357 .get_voltage_sel = ab8500_regulator_get_voltage_sel,
5689e830 358 .list_voltage = regulator_list_voltage_linear,
7ce4669c
BJ		 359};
360
361static struct regulator_ops ab8500_regulator_ops = {
362 .enable = ab8500_regulator_enable,
363 .disable = ab8500_regulator_disable,
364 .is_enabled = ab8500_regulator_is_enabled,
365 .get_voltage_sel = ab8500_regulator_get_voltage_sel,
5689e830 366 .list_voltage = regulator_list_voltage_linear,
c789ca20
SI		 367};
368
6909b452
BJ		 369static struct ab8500_regulator_info
370 ab8500_regulator_info[AB8500_NUM_REGULATORS] = {
c789ca20 371 /*
e1159e6d
BJ		 372 * Variable Voltage Regulators
373 * name, min mV, max mV,
374 * update bank, reg, mask, enable val
ec1cc4d9 375 * volt bank, reg, mask
c789ca20 376 */
6909b452
BJ		 377 [AB8500_LDO_AUX1] = {
378 .desc = {
379 .name = "LDO-AUX1",
7ce4669c 380 .ops = &ab8500_regulator_volt_mode_ops,
6909b452
BJ		 381 .type = REGULATOR_VOLTAGE,
382 .id = AB8500_LDO_AUX1,
383 .owner = THIS_MODULE,
384 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
ec1cc4d9 385 .volt_table = ldo_vauxn_voltages,
530158b6 386 .enable_time = 200,
6909b452 387 },
7ce4669c 388 .load_lp_uA = 5000,
6909b452
BJ		 389 .update_bank = 0x04,
390 .update_reg = 0x09,
391 .update_mask = 0x03,
bd28a157
EV		 392 .update_val = 0x01,
393 .update_val_idle = 0x03,
394 .update_val_normal = 0x01,
6909b452
BJ		 395 .voltage_bank = 0x04,
396 .voltage_reg = 0x1f,
397 .voltage_mask = 0x0f,
6909b452
BJ		 398 },
399 [AB8500_LDO_AUX2] = {
400 .desc = {
401 .name = "LDO-AUX2",
7ce4669c 402 .ops = &ab8500_regulator_volt_mode_ops,
6909b452
BJ		 403 .type = REGULATOR_VOLTAGE,
404 .id = AB8500_LDO_AUX2,
405 .owner = THIS_MODULE,
406 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
ec1cc4d9 407 .volt_table = ldo_vauxn_voltages,
530158b6 408 .enable_time = 200,
6909b452 409 },
7ce4669c 410 .load_lp_uA = 5000,
6909b452
BJ		 411 .update_bank = 0x04,
412 .update_reg = 0x09,
413 .update_mask = 0x0c,
bd28a157
EV		 414 .update_val = 0x04,
415 .update_val_idle = 0x0c,
416 .update_val_normal = 0x04,
6909b452
BJ		 417 .voltage_bank = 0x04,
418 .voltage_reg = 0x20,
419 .voltage_mask = 0x0f,
6909b452
BJ		 420 },
421 [AB8500_LDO_AUX3] = {
422 .desc = {
423 .name = "LDO-AUX3",
7ce4669c 424 .ops = &ab8500_regulator_volt_mode_ops,
6909b452
BJ		 425 .type = REGULATOR_VOLTAGE,
426 .id = AB8500_LDO_AUX3,
427 .owner = THIS_MODULE,
428 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
ec1cc4d9 429 .volt_table = ldo_vaux3_voltages,
530158b6 430 .enable_time = 450,
6909b452 431 },
7ce4669c 432 .load_lp_uA = 5000,
6909b452
BJ		 433 .update_bank = 0x04,
434 .update_reg = 0x0a,
435 .update_mask = 0x03,
bd28a157
EV		 436 .update_val = 0x01,
437 .update_val_idle = 0x03,
438 .update_val_normal = 0x01,
6909b452
BJ		 439 .voltage_bank = 0x04,
440 .voltage_reg = 0x21,
441 .voltage_mask = 0x07,
6909b452
BJ		 442 },
443 [AB8500_LDO_INTCORE] = {
444 .desc = {
445 .name = "LDO-INTCORE",
7ce4669c 446 .ops = &ab8500_regulator_volt_mode_ops,
6909b452
BJ		 447 .type = REGULATOR_VOLTAGE,
448 .id = AB8500_LDO_INTCORE,
449 .owner = THIS_MODULE,
450 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
ec1cc4d9 451 .volt_table = ldo_vintcore_voltages,
530158b6 452 .enable_time = 750,
6909b452 453 },
7ce4669c 454 .load_lp_uA = 5000,
6909b452
BJ		 455 .update_bank = 0x03,
456 .update_reg = 0x80,
457 .update_mask = 0x44,
cc40dc29 458 .update_val = 0x44,
bd28a157
EV		 459 .update_val_idle = 0x44,
460 .update_val_normal = 0x04,
6909b452
BJ		 461 .voltage_bank = 0x03,
462 .voltage_reg = 0x80,
463 .voltage_mask = 0x38,
a0a7014c 464 .voltage_shift = 3,
6909b452 465 },
c789ca20
SI		 466
467 /*
e1159e6d
BJ		 468 * Fixed Voltage Regulators
469 * name, fixed mV,
470 * update bank, reg, mask, enable val
c789ca20 471 */
6909b452
BJ		 472 [AB8500_LDO_TVOUT] = {
473 .desc = {
474 .name = "LDO-TVOUT",
7ce4669c 475 .ops = &ab8500_regulator_mode_ops,
6909b452
BJ		 476 .type = REGULATOR_VOLTAGE,
477 .id = AB8500_LDO_TVOUT,
478 .owner = THIS_MODULE,
479 .n_voltages = 1,
7142e213 480 .min_uV = 2000000,
7fee2afb 481 .enable_time = 10000,
6909b452 482 },
7ce4669c 483 .load_lp_uA = 1000,
6909b452
BJ		 484 .update_bank = 0x03,
485 .update_reg = 0x80,
486 .update_mask = 0x82,
bd28a157 487 .update_val = 0x02,
7ce4669c
BJ		 488 .update_val_idle = 0x82,
489 .update_val_normal = 0x02,
6909b452 490 },
328a5369
AL		 491
492 /*
493 * Regulators with fixed voltage and normal mode
494 */
ea05ef31
BJ		 495 [AB8500_LDO_USB] = {
496 .desc = {
497 .name = "LDO-USB",
328a5369 498 .ops = &ab8500_regulator_ops,
ea05ef31
BJ		 499 .type = REGULATOR_VOLTAGE,
500 .id = AB8500_LDO_USB,
501 .owner = THIS_MODULE,
502 .n_voltages = 1,
7142e213 503 .min_uV = 3300000,
530158b6 504 .enable_time = 150,
ea05ef31 505 },
ea05ef31
BJ		 506 .update_bank = 0x03,
507 .update_reg = 0x82,
508 .update_mask = 0x03,
ea05ef31 509 },
6909b452
BJ		 510 [AB8500_LDO_AUDIO] = {
511 .desc = {
512 .name = "LDO-AUDIO",
7ce4669c 513 .ops = &ab8500_regulator_ops,
6909b452
BJ		 514 .type = REGULATOR_VOLTAGE,
515 .id = AB8500_LDO_AUDIO,
516 .owner = THIS_MODULE,
517 .n_voltages = 1,
7142e213 518 .min_uV = 2000000,
530158b6 519 .enable_time = 140,
6909b452 520 },
6909b452
BJ		 521 .update_bank = 0x03,
522 .update_reg = 0x83,
523 .update_mask = 0x02,
bd28a157 524 .update_val = 0x02,
6909b452
BJ		 525 },
526 [AB8500_LDO_ANAMIC1] = {
527 .desc = {
528 .name = "LDO-ANAMIC1",
7ce4669c 529 .ops = &ab8500_regulator_ops,
6909b452
BJ		 530 .type = REGULATOR_VOLTAGE,
531 .id = AB8500_LDO_ANAMIC1,
532 .owner = THIS_MODULE,
533 .n_voltages = 1,
7142e213 534 .min_uV = 2050000,
530158b6 535 .enable_time = 500,
6909b452 536 },
6909b452
BJ		 537 .update_bank = 0x03,
538 .update_reg = 0x83,
539 .update_mask = 0x08,
bd28a157 540 .update_val = 0x08,
6909b452
BJ		 541 },
542 [AB8500_LDO_ANAMIC2] = {
543 .desc = {
544 .name = "LDO-ANAMIC2",
7ce4669c 545 .ops = &ab8500_regulator_ops,
6909b452
BJ		 546 .type = REGULATOR_VOLTAGE,
547 .id = AB8500_LDO_ANAMIC2,
548 .owner = THIS_MODULE,
549 .n_voltages = 1,
7142e213 550 .min_uV = 2050000,
530158b6 551 .enable_time = 500,
6909b452 552 },
6909b452
BJ		 553 .update_bank = 0x03,
554 .update_reg = 0x83,
555 .update_mask = 0x10,
bd28a157 556 .update_val = 0x10,
6909b452
BJ		 557 },
558 [AB8500_LDO_DMIC] = {
559 .desc = {
560 .name = "LDO-DMIC",
7ce4669c 561 .ops = &ab8500_regulator_ops,
6909b452
BJ		 562 .type = REGULATOR_VOLTAGE,
563 .id = AB8500_LDO_DMIC,
564 .owner = THIS_MODULE,
565 .n_voltages = 1,
7142e213 566 .min_uV = 1800000,
530158b6 567 .enable_time = 420,
6909b452 568 },
6909b452
BJ		 569 .update_bank = 0x03,
570 .update_reg = 0x83,
571 .update_mask = 0x04,
bd28a157 572 .update_val = 0x04,
6909b452 573 },
7ce4669c
BJ		 574
575 /*
576 * Regulators with fixed voltage and normal/idle modes
577 */
6909b452
BJ		 578 [AB8500_LDO_ANA] = {
579 .desc = {
580 .name = "LDO-ANA",
7ce4669c 581 .ops = &ab8500_regulator_mode_ops,
6909b452
BJ		 582 .type = REGULATOR_VOLTAGE,
583 .id = AB8500_LDO_ANA,
584 .owner = THIS_MODULE,
585 .n_voltages = 1,
7142e213 586 .min_uV = 1200000,
530158b6 587 .enable_time = 140,
6909b452 588 },
7ce4669c 589 .load_lp_uA = 1000,
6909b452
BJ		 590 .update_bank = 0x04,
591 .update_reg = 0x06,
592 .update_mask = 0x0c,
bd28a157 593 .update_val = 0x04,
7ce4669c
BJ		 594 .update_val_idle = 0x0c,
595 .update_val_normal = 0x04,
6909b452
BJ		 596 },
597
598
c789ca20
SI		 599};
600
79568b94
BJ		 601struct ab8500_reg_init {
602 u8 bank;
603 u8 addr;
604 u8 mask;
605};
606
607#define REG_INIT(_id, _bank, _addr, _mask) \
608 [_id] = { \
609 .bank = _bank, \
610 .addr = _addr, \
611 .mask = _mask, \
612 }
613
614static struct ab8500_reg_init ab8500_reg_init[] = {
615 /*
33bc8f46 616 * 0x30, VanaRequestCtrl
79568b94
BJ		 617 * 0xc0, VextSupply1RequestCtrl
618 */
43a5911b 619 REG_INIT(AB8500_REGUREQUESTCTRL2, 0x03, 0x04, 0xf0),
79568b94
BJ		 620 /*
621 * 0x03, VextSupply2RequestCtrl
622 * 0x0c, VextSupply3RequestCtrl
623 * 0x30, Vaux1RequestCtrl
624 * 0xc0, Vaux2RequestCtrl
625 */
626 REG_INIT(AB8500_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
627 /*
628 * 0x03, Vaux3RequestCtrl
629 * 0x04, SwHPReq
630 */
631 REG_INIT(AB8500_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
632 /*
633 * 0x08, VanaSysClkReq1HPValid
634 * 0x20, Vaux1SysClkReq1HPValid
635 * 0x40, Vaux2SysClkReq1HPValid
636 * 0x80, Vaux3SysClkReq1HPValid
637 */
43a5911b 638 REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xe8),
79568b94
BJ		 639 /*
640 * 0x10, VextSupply1SysClkReq1HPValid
641 * 0x20, VextSupply2SysClkReq1HPValid
642 * 0x40, VextSupply3SysClkReq1HPValid
643 */
43a5911b 644 REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x70),
79568b94
BJ		 645 /*
646 * 0x08, VanaHwHPReq1Valid
647 * 0x20, Vaux1HwHPReq1Valid
648 * 0x40, Vaux2HwHPReq1Valid
649 * 0x80, Vaux3HwHPReq1Valid
650 */
43a5911b 651 REG_INIT(AB8500_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xe8),
79568b94
BJ		 652 /*
653 * 0x01, VextSupply1HwHPReq1Valid
654 * 0x02, VextSupply2HwHPReq1Valid
655 * 0x04, VextSupply3HwHPReq1Valid
656 */
43a5911b 657 REG_INIT(AB8500_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x07),
79568b94
BJ		 658 /*
659 * 0x08, VanaHwHPReq2Valid
660 * 0x20, Vaux1HwHPReq2Valid
661 * 0x40, Vaux2HwHPReq2Valid
662 * 0x80, Vaux3HwHPReq2Valid
663 */
43a5911b 664 REG_INIT(AB8500_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xe8),
79568b94
BJ		 665 /*
666 * 0x01, VextSupply1HwHPReq2Valid
667 * 0x02, VextSupply2HwHPReq2Valid
668 * 0x04, VextSupply3HwHPReq2Valid
669 */
43a5911b 670 REG_INIT(AB8500_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x07),
79568b94
BJ		 671 /*
672 * 0x20, VanaSwHPReqValid
673 * 0x80, Vaux1SwHPReqValid
674 */
43a5911b 675 REG_INIT(AB8500_REGUSWHPREQVALID1, 0x03, 0x0d, 0xa0),
79568b94
BJ		 676 /*
677 * 0x01, Vaux2SwHPReqValid
678 * 0x02, Vaux3SwHPReqValid
679 * 0x04, VextSupply1SwHPReqValid
680 * 0x08, VextSupply2SwHPReqValid
681 * 0x10, VextSupply3SwHPReqValid
682 */
43a5911b 683 REG_INIT(AB8500_REGUSWHPREQVALID2, 0x03, 0x0e, 0x1f),
79568b94
BJ		 684 /*
685 * 0x02, SysClkReq2Valid1
43a5911b
LJ		 686 * 0x04, SysClkReq3Valid1
687 * 0x08, SysClkReq4Valid1
688 * 0x10, SysClkReq5Valid1
689 * 0x20, SysClkReq6Valid1
690 * 0x40, SysClkReq7Valid1
79568b94
BJ		 691 * 0x80, SysClkReq8Valid1
692 */
693 REG_INIT(AB8500_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xfe),
694 /*
695 * 0x02, SysClkReq2Valid2
43a5911b
LJ		 696 * 0x04, SysClkReq3Valid2
697 * 0x08, SysClkReq4Valid2
698 * 0x10, SysClkReq5Valid2
699 * 0x20, SysClkReq6Valid2
700 * 0x40, SysClkReq7Valid2
79568b94
BJ		 701 * 0x80, SysClkReq8Valid2
702 */
703 REG_INIT(AB8500_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xfe),
704 /*
705 * 0x02, VTVoutEna
706 * 0x04, Vintcore12Ena
707 * 0x38, Vintcore12Sel
708 * 0x40, Vintcore12LP
709 * 0x80, VTVoutLP
710 */
711 REG_INIT(AB8500_REGUMISC1, 0x03, 0x80, 0xfe),
712 /*
713 * 0x02, VaudioEna
714 * 0x04, VdmicEna
715 * 0x08, Vamic1Ena
716 * 0x10, Vamic2Ena
717 */
718 REG_INIT(AB8500_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
719 /*
720 * 0x01, Vamic1_dzout
721 * 0x02, Vamic2_dzout
722 */
723 REG_INIT(AB8500_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
d79df329 724 /*
43a5911b 725 * 0x03, VpllRegu (NOTE! PRCMU register bits)
33bc8f46 726 * 0x0c, VanaRegu
79568b94
BJ		 727 */
728 REG_INIT(AB8500_VPLLVANAREGU, 0x04, 0x06, 0x0f),
729 /*
730 * 0x01, VrefDDREna
731 * 0x02, VrefDDRSleepMode
732 */
733 REG_INIT(AB8500_VREFDDR, 0x04, 0x07, 0x03),
734 /*
735 * 0x03, VextSupply1Regu
736 * 0x0c, VextSupply2Regu
737 * 0x30, VextSupply3Regu
738 * 0x40, ExtSupply2Bypass
739 * 0x80, ExtSupply3Bypass
740 */
741 REG_INIT(AB8500_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
742 /*
743 * 0x03, Vaux1Regu
744 * 0x0c, Vaux2Regu
745 */
746 REG_INIT(AB8500_VAUX12REGU, 0x04, 0x09, 0x0f),
747 /*
748 * 0x03, Vaux3Regu
749 */
43a5911b 750 REG_INIT(AB8500_VRF1VAUX3REGU, 0x04, 0x0a, 0x03),
79568b94
BJ		 751 /*
752 * 0x0f, Vaux1Sel
753 */
754 REG_INIT(AB8500_VAUX1SEL, 0x04, 0x1f, 0x0f),
755 /*
756 * 0x0f, Vaux2Sel
757 */
758 REG_INIT(AB8500_VAUX2SEL, 0x04, 0x20, 0x0f),
759 /*
760 * 0x07, Vaux3Sel
761 */
43a5911b 762 REG_INIT(AB8500_VRF1VAUX3SEL, 0x04, 0x21, 0x07),
79568b94
BJ		 763 /*
764 * 0x01, VextSupply12LP
765 */
766 REG_INIT(AB8500_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
767 /*
768 * 0x04, Vaux1Disch
769 * 0x08, Vaux2Disch
770 * 0x10, Vaux3Disch
771 * 0x20, Vintcore12Disch
772 * 0x40, VTVoutDisch
773 * 0x80, VaudioDisch
774 */
43a5911b 775 REG_INIT(AB8500_REGUCTRLDISCH, 0x04, 0x43, 0xfc),
79568b94
BJ		 776 /*
777 * 0x02, VanaDisch
778 * 0x04, VdmicPullDownEna
779 * 0x10, VdmicDisch
780 */
43a5911b 781 REG_INIT(AB8500_REGUCTRLDISCH2, 0x04, 0x44, 0x16),
79568b94
BJ		 782};
783
3c1b8438
LJ		 784static int ab8500_regulator_init_registers(struct platform_device *pdev,
785 int id, int mask, int value)
a7ac1d9e
LJ		 786{
787 int err;
788
3c1b8438
LJ		 789 BUG_ON(value & ~mask);
790 BUG_ON(mask & ~ab8500_reg_init[id].mask);
a7ac1d9e 791
3c1b8438 792 /* initialize register */
a7ac1d9e
LJ		 793 err = abx500_mask_and_set_register_interruptible(
794 &pdev->dev,
795 ab8500_reg_init[id].bank,
796 ab8500_reg_init[id].addr,
3c1b8438 797 mask, value);
a7ac1d9e
LJ		 798 if (err < 0) {
799 dev_err(&pdev->dev,
800 "Failed to initialize 0x%02x, 0x%02x.\n",
801 ab8500_reg_init[id].bank,
802 ab8500_reg_init[id].addr);
803 return err;
804 }
a7ac1d9e 805 dev_vdbg(&pdev->dev,
3c1b8438
LJ		 806 " init: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n",
807 ab8500_reg_init[id].bank,
808 ab8500_reg_init[id].addr,
809 mask, value);
a7ac1d9e
LJ		 810
811 return 0;
812}
813
a5023574 814static int ab8500_regulator_register(struct platform_device *pdev,
a7ac1d9e
LJ		 815 struct regulator_init_data *init_data,
816 int id,
817 struct device_node *np)
818{
819 struct ab8500_regulator_info *info = NULL;
820 struct regulator_config config = { };
821 int err;
822
823 /* assign per-regulator data */
824 info = &ab8500_regulator_info[id];
825 info->dev = &pdev->dev;
826
827 config.dev = &pdev->dev;
828 config.init_data = init_data;
829 config.driver_data = info;
830 config.of_node = np;
831
832 /* fix for hardware before ab8500v2.0 */
833 if (abx500_get_chip_id(info->dev) < 0x20) {
834 if (info->desc.id == AB8500_LDO_AUX3) {
835 info->desc.n_voltages =
836 ARRAY_SIZE(ldo_vauxn_voltages);
ec1cc4d9 837 info->desc.volt_table = ldo_vauxn_voltages;
a7ac1d9e
LJ		 838 info->voltage_mask = 0xf;
839 }
840 }
841
842 /* register regulator with framework */
843 info->regulator = regulator_register(&info->desc, &config);
844 if (IS_ERR(info->regulator)) {
845 err = PTR_ERR(info->regulator);
846 dev_err(&pdev->dev, "failed to register regulator %s\n",
847 info->desc.name);
848 /* when we fail, un-register all earlier regulators */
849 while (--id >= 0) {
850 info = &ab8500_regulator_info[id];
851 regulator_unregister(info->regulator);
852 }
853 return err;
854 }
855
856 return 0;
857}
858
3a8334b9 859static struct of_regulator_match ab8500_regulator_matches[] = {
7e715b95
LJ		 860 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8500_LDO_AUX1, },
861 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8500_LDO_AUX2, },
862 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8500_LDO_AUX3, },
863 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8500_LDO_INTCORE, },
864 { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB8500_LDO_TVOUT, },
865 { .name = "ab8500_ldo_usb", .driver_data = (void *) AB8500_LDO_USB, },
866 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8500_LDO_AUDIO, },
867 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8500_LDO_ANAMIC1, },
868 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8500_LDO_ANAMIC2, },
869 { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB8500_LDO_DMIC, },
870 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8500_LDO_ANA, },
3a8334b9
LJ		 871};
872
a5023574 873static int
3a8334b9
LJ		 874ab8500_regulator_of_probe(struct platform_device *pdev, struct device_node *np)
875{
876 int err, i;
877
878 for (i = 0; i < ARRAY_SIZE(ab8500_regulator_info); i++) {
879 err = ab8500_regulator_register(
880 pdev, ab8500_regulator_matches[i].init_data,
881 i, ab8500_regulator_matches[i].of_node);
882 if (err)
883 return err;
884 }
885
886 return 0;
887}
888
a5023574 889static int ab8500_regulator_probe(struct platform_device *pdev)
c789ca20
SI		 890{
891 struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
3a8334b9 892 struct device_node *np = pdev->dev.of_node;
732805a5
BJ		 893 struct ab8500_platform_data *ppdata;
894 struct ab8500_regulator_platform_data *pdata;
c789ca20
SI		 895 int i, err;
896
3a8334b9
LJ		 897 if (np) {
898 err = of_regulator_match(&pdev->dev, np,
899 ab8500_regulator_matches,
900 ARRAY_SIZE(ab8500_regulator_matches));
901 if (err < 0) {
902 dev_err(&pdev->dev,
903 "Error parsing regulator init data: %d\n", err);
904 return err;
905 }
906
907 err = ab8500_regulator_of_probe(pdev, np);
908 return err;
909 }
910
c789ca20
SI		 911 if (!ab8500) {
912 dev_err(&pdev->dev, "null mfd parent\n");
913 return -EINVAL;
914 }
732805a5
BJ		 915
916 ppdata = dev_get_platdata(ab8500->dev);
917 if (!ppdata) {
918 dev_err(&pdev->dev, "null parent pdata\n");
919 return -EINVAL;
920 }
921
922 pdata = ppdata->regulator;
fc24b426
BJ		 923 if (!pdata) {
924 dev_err(&pdev->dev, "null pdata\n");
925 return -EINVAL;
926 }
c789ca20 927
cb189b07
BJ		 928 /* make sure the platform data has the correct size */
929 if (pdata->num_regulator != ARRAY_SIZE(ab8500_regulator_info)) {
79568b94 930 dev_err(&pdev->dev, "Configuration error: size mismatch.\n");
cb189b07
BJ		 931 return -EINVAL;
932 }
933
79568b94 934 /* initialize registers */
732805a5 935 for (i = 0; i < pdata->num_reg_init; i++) {
3c1b8438 936 int id, mask, value;
79568b94 937
732805a5
BJ		 938 id = pdata->reg_init[i].id;
939 mask = pdata->reg_init[i].mask;
940 value = pdata->reg_init[i].value;
79568b94
BJ		 941
942 /* check for configuration errors */
3c1b8438 943 BUG_ON(id >= AB8500_NUM_REGULATOR_REGISTERS);
79568b94 944
3c1b8438 945 err = ab8500_regulator_init_registers(pdev, id, mask, value);
a7ac1d9e 946 if (err < 0)
79568b94 947 return err;
79568b94
BJ		 948 }
949
c789ca20
SI		 950 /* register all regulators */
951 for (i = 0; i < ARRAY_SIZE(ab8500_regulator_info); i++) {
a7ac1d9e
LJ		 952 err = ab8500_regulator_register(pdev, &pdata->regulator[i], i, NULL);
953 if (err < 0)
c789ca20 954 return err;
c789ca20
SI		 955 }
956
957 return 0;
958}
959
8dc995f5 960static int ab8500_regulator_remove(struct platform_device *pdev)
c789ca20
SI		 961{
962 int i;
963
964 for (i = 0; i < ARRAY_SIZE(ab8500_regulator_info); i++) {
965 struct ab8500_regulator_info *info = NULL;
966 info = &ab8500_regulator_info[i];
09aefa12
BJ		 967
968 dev_vdbg(rdev_get_dev(info->regulator),
969 "%s-remove\n", info->desc.name);
970
c789ca20
SI		 971 regulator_unregister(info->regulator);
972 }
973
974 return 0;
975}
976
977static struct platform_driver ab8500_regulator_driver = {
978 .probe = ab8500_regulator_probe,
5eb9f2b9 979 .remove = ab8500_regulator_remove,
c789ca20
SI		 980 .driver = {
981 .name = "ab8500-regulator",
982 .owner = THIS_MODULE,
983 },
984};
985
986static int __init ab8500_regulator_init(void)
987{
988 int ret;
989
990 ret = platform_driver_register(&ab8500_regulator_driver);
991 if (ret != 0)
992 pr_err("Failed to register ab8500 regulator: %d\n", ret);
993
994 return ret;
995}
996subsys_initcall(ab8500_regulator_init);
997
998static void __exit ab8500_regulator_exit(void)
999{
1000 platform_driver_unregister(&ab8500_regulator_driver);
1001}
1002module_exit(ab8500_regulator_exit);
1003
1004MODULE_LICENSE("GPL v2");
1005MODULE_AUTHOR("Sundar Iyer <sundar.iyer@stericsson.com>");
732805a5 1006MODULE_AUTHOR("Bengt Jonsson <bengt.g.jonsson@stericsson.com>");
c789ca20
SI		 1007MODULE_DESCRIPTION("Regulator Driver for ST-Ericsson AB8500 Mixed-Sig PMIC");
1008MODULE_ALIAS("platform:ab8500-regulator");
kernel source for telekom puls (alcatel/mediatek)