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a3725c45 AB |
1 | /* |
2 | * IDT CPS Gen.2 Serial RapidIO switch family support | |
3 | * | |
4 | * Copyright 2010 Integrated Device Technology, Inc. | |
5 | * Alexandre Bounine <alexandre.bounine@idt.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the | |
9 | * Free Software Foundation; either version 2 of the License, or (at your | |
10 | * option) any later version. | |
11 | */ | |
12 | ||
13 | #include <linux/rio.h> | |
14 | #include <linux/rio_drv.h> | |
15 | #include <linux/rio_ids.h> | |
16 | #include <linux/delay.h> | |
17 | #include "../rio.h" | |
18 | ||
19 | #define LOCAL_RTE_CONF_DESTID_SEL 0x010070 | |
20 | #define LOCAL_RTE_CONF_DESTID_SEL_PSEL 0x0000001f | |
21 | ||
22 | #define IDT_LT_ERR_REPORT_EN 0x03100c | |
23 | ||
24 | #define IDT_PORT_ERR_REPORT_EN(n) (0x031044 + (n)*0x40) | |
25 | #define IDT_PORT_ERR_REPORT_EN_BC 0x03ff04 | |
26 | ||
27 | #define IDT_PORT_ISERR_REPORT_EN(n) (0x03104C + (n)*0x40) | |
28 | #define IDT_PORT_ISERR_REPORT_EN_BC 0x03ff0c | |
29 | #define IDT_PORT_INIT_TX_ACQUIRED 0x00000020 | |
30 | ||
31 | #define IDT_LANE_ERR_REPORT_EN(n) (0x038010 + (n)*0x100) | |
32 | #define IDT_LANE_ERR_REPORT_EN_BC 0x03ff10 | |
33 | ||
34 | #define IDT_DEV_CTRL_1 0xf2000c | |
35 | #define IDT_DEV_CTRL_1_GENPW 0x02000000 | |
36 | #define IDT_DEV_CTRL_1_PRSTBEH 0x00000001 | |
37 | ||
38 | #define IDT_CFGBLK_ERR_CAPTURE_EN 0x020008 | |
39 | #define IDT_CFGBLK_ERR_REPORT 0xf20014 | |
40 | #define IDT_CFGBLK_ERR_REPORT_GENPW 0x00000002 | |
41 | ||
42 | #define IDT_AUX_PORT_ERR_CAP_EN 0x020000 | |
43 | #define IDT_AUX_ERR_REPORT_EN 0xf20018 | |
44 | #define IDT_AUX_PORT_ERR_LOG_I2C 0x00000002 | |
45 | #define IDT_AUX_PORT_ERR_LOG_JTAG 0x00000001 | |
46 | ||
47 | #define IDT_ISLTL_ADDRESS_CAP 0x021014 | |
48 | ||
49 | #define IDT_RIO_DOMAIN 0xf20020 | |
50 | #define IDT_RIO_DOMAIN_MASK 0x000000ff | |
51 | ||
52 | #define IDT_PW_INFO_CSR 0xf20024 | |
53 | ||
54 | #define IDT_SOFT_RESET 0xf20040 | |
55 | #define IDT_SOFT_RESET_REQ 0x00030097 | |
56 | ||
57 | #define IDT_I2C_MCTRL 0xf20050 | |
58 | #define IDT_I2C_MCTRL_GENPW 0x04000000 | |
59 | ||
60 | #define IDT_JTAG_CTRL 0xf2005c | |
61 | #define IDT_JTAG_CTRL_GENPW 0x00000002 | |
62 | ||
63 | #define IDT_LANE_CTRL(n) (0xff8000 + (n)*0x100) | |
64 | #define IDT_LANE_CTRL_BC 0xffff00 | |
65 | #define IDT_LANE_CTRL_GENPW 0x00200000 | |
66 | #define IDT_LANE_DFE_1_BC 0xffff18 | |
67 | #define IDT_LANE_DFE_2_BC 0xffff1c | |
68 | ||
69 | #define IDT_PORT_OPS(n) (0xf40004 + (n)*0x100) | |
70 | #define IDT_PORT_OPS_GENPW 0x08000000 | |
71 | #define IDT_PORT_OPS_PL_ELOG 0x00000040 | |
72 | #define IDT_PORT_OPS_LL_ELOG 0x00000020 | |
73 | #define IDT_PORT_OPS_LT_ELOG 0x00000010 | |
74 | #define IDT_PORT_OPS_BC 0xf4ff04 | |
75 | ||
76 | #define IDT_PORT_ISERR_DET(n) (0xf40008 + (n)*0x100) | |
77 | ||
78 | #define IDT_ERR_CAP 0xfd0000 | |
79 | #define IDT_ERR_CAP_LOG_OVERWR 0x00000004 | |
80 | ||
81 | #define IDT_ERR_RD 0xfd0004 | |
82 | ||
83 | #define IDT_DEFAULT_ROUTE 0xde | |
84 | #define IDT_NO_ROUTE 0xdf | |
85 | ||
86 | static int | |
87 | idtg2_route_add_entry(struct rio_mport *mport, u16 destid, u8 hopcount, | |
88 | u16 table, u16 route_destid, u8 route_port) | |
89 | { | |
90 | /* | |
91 | * Select routing table to update | |
92 | */ | |
93 | if (table == RIO_GLOBAL_TABLE) | |
94 | table = 0; | |
95 | else | |
96 | table++; | |
97 | ||
98 | rio_mport_write_config_32(mport, destid, hopcount, | |
99 | LOCAL_RTE_CONF_DESTID_SEL, table); | |
100 | ||
101 | /* | |
102 | * Program destination port for the specified destID | |
103 | */ | |
104 | rio_mport_write_config_32(mport, destid, hopcount, | |
105 | RIO_STD_RTE_CONF_DESTID_SEL_CSR, | |
106 | (u32)route_destid); | |
107 | ||
108 | rio_mport_write_config_32(mport, destid, hopcount, | |
109 | RIO_STD_RTE_CONF_PORT_SEL_CSR, | |
110 | (u32)route_port); | |
111 | udelay(10); | |
112 | ||
113 | return 0; | |
114 | } | |
115 | ||
116 | static int | |
117 | idtg2_route_get_entry(struct rio_mport *mport, u16 destid, u8 hopcount, | |
118 | u16 table, u16 route_destid, u8 *route_port) | |
119 | { | |
120 | u32 result; | |
121 | ||
122 | /* | |
123 | * Select routing table to read | |
124 | */ | |
125 | if (table == RIO_GLOBAL_TABLE) | |
126 | table = 0; | |
127 | else | |
128 | table++; | |
129 | ||
130 | rio_mport_write_config_32(mport, destid, hopcount, | |
131 | LOCAL_RTE_CONF_DESTID_SEL, table); | |
132 | ||
133 | rio_mport_write_config_32(mport, destid, hopcount, | |
134 | RIO_STD_RTE_CONF_DESTID_SEL_CSR, | |
135 | route_destid); | |
136 | ||
137 | rio_mport_read_config_32(mport, destid, hopcount, | |
138 | RIO_STD_RTE_CONF_PORT_SEL_CSR, &result); | |
139 | ||
140 | if (IDT_DEFAULT_ROUTE == (u8)result || IDT_NO_ROUTE == (u8)result) | |
141 | *route_port = RIO_INVALID_ROUTE; | |
142 | else | |
143 | *route_port = (u8)result; | |
144 | ||
145 | return 0; | |
146 | } | |
147 | ||
148 | static int | |
149 | idtg2_route_clr_table(struct rio_mport *mport, u16 destid, u8 hopcount, | |
150 | u16 table) | |
151 | { | |
152 | u32 i; | |
153 | ||
154 | /* | |
155 | * Select routing table to read | |
156 | */ | |
157 | if (table == RIO_GLOBAL_TABLE) | |
158 | table = 0; | |
159 | else | |
160 | table++; | |
161 | ||
162 | rio_mport_write_config_32(mport, destid, hopcount, | |
163 | LOCAL_RTE_CONF_DESTID_SEL, table); | |
164 | ||
165 | for (i = RIO_STD_RTE_CONF_EXTCFGEN; | |
166 | i <= (RIO_STD_RTE_CONF_EXTCFGEN | 0xff);) { | |
167 | rio_mport_write_config_32(mport, destid, hopcount, | |
168 | RIO_STD_RTE_CONF_DESTID_SEL_CSR, i); | |
169 | rio_mport_write_config_32(mport, destid, hopcount, | |
170 | RIO_STD_RTE_CONF_PORT_SEL_CSR, | |
171 | (IDT_DEFAULT_ROUTE << 24) | (IDT_DEFAULT_ROUTE << 16) | | |
172 | (IDT_DEFAULT_ROUTE << 8) | IDT_DEFAULT_ROUTE); | |
173 | i += 4; | |
174 | } | |
175 | ||
176 | return 0; | |
177 | } | |
178 | ||
179 | ||
180 | static int | |
181 | idtg2_set_domain(struct rio_mport *mport, u16 destid, u8 hopcount, | |
182 | u8 sw_domain) | |
183 | { | |
184 | /* | |
185 | * Switch domain configuration operates only at global level | |
186 | */ | |
187 | rio_mport_write_config_32(mport, destid, hopcount, | |
188 | IDT_RIO_DOMAIN, (u32)sw_domain); | |
189 | return 0; | |
190 | } | |
191 | ||
192 | static int | |
193 | idtg2_get_domain(struct rio_mport *mport, u16 destid, u8 hopcount, | |
194 | u8 *sw_domain) | |
195 | { | |
196 | u32 regval; | |
197 | ||
198 | /* | |
199 | * Switch domain configuration operates only at global level | |
200 | */ | |
201 | rio_mport_read_config_32(mport, destid, hopcount, | |
202 | IDT_RIO_DOMAIN, ®val); | |
203 | ||
204 | *sw_domain = (u8)(regval & 0xff); | |
205 | ||
206 | return 0; | |
207 | } | |
208 | ||
209 | static int | |
210 | idtg2_em_init(struct rio_dev *rdev) | |
211 | { | |
a3725c45 AB |
212 | u32 regval; |
213 | int i, tmp; | |
214 | ||
215 | /* | |
216 | * This routine performs device-specific initialization only. | |
217 | * All standard EM configuration should be performed at upper level. | |
218 | */ | |
219 | ||
a93192a5 | 220 | pr_debug("RIO: %s [%d:%d]\n", __func__, rdev->destid, rdev->hopcount); |
a3725c45 AB |
221 | |
222 | /* Set Port-Write info CSR: PRIO=3 and CRF=1 */ | |
a93192a5 | 223 | rio_write_config_32(rdev, IDT_PW_INFO_CSR, 0x0000e000); |
a3725c45 AB |
224 | |
225 | /* | |
226 | * Configure LT LAYER error reporting. | |
227 | */ | |
228 | ||
229 | /* Enable standard (RIO.p8) error reporting */ | |
a93192a5 | 230 | rio_write_config_32(rdev, IDT_LT_ERR_REPORT_EN, |
a3725c45 AB |
231 | REM_LTL_ERR_ILLTRAN | REM_LTL_ERR_UNSOLR | |
232 | REM_LTL_ERR_UNSUPTR); | |
233 | ||
234 | /* Use Port-Writes for LT layer error reporting. | |
235 | * Enable per-port reset | |
236 | */ | |
a93192a5 AB |
237 | rio_read_config_32(rdev, IDT_DEV_CTRL_1, ®val); |
238 | rio_write_config_32(rdev, IDT_DEV_CTRL_1, | |
a3725c45 AB |
239 | regval | IDT_DEV_CTRL_1_GENPW | IDT_DEV_CTRL_1_PRSTBEH); |
240 | ||
241 | /* | |
242 | * Configure PORT error reporting. | |
243 | */ | |
244 | ||
245 | /* Report all RIO.p8 errors supported by device */ | |
a93192a5 | 246 | rio_write_config_32(rdev, IDT_PORT_ERR_REPORT_EN_BC, 0x807e8037); |
a3725c45 AB |
247 | |
248 | /* Configure reporting of implementation specific errors/events */ | |
a93192a5 AB |
249 | rio_write_config_32(rdev, IDT_PORT_ISERR_REPORT_EN_BC, |
250 | IDT_PORT_INIT_TX_ACQUIRED); | |
a3725c45 AB |
251 | |
252 | /* Use Port-Writes for port error reporting and enable error logging */ | |
253 | tmp = RIO_GET_TOTAL_PORTS(rdev->swpinfo); | |
254 | for (i = 0; i < tmp; i++) { | |
a93192a5 AB |
255 | rio_read_config_32(rdev, IDT_PORT_OPS(i), ®val); |
256 | rio_write_config_32(rdev, | |
a3725c45 AB |
257 | IDT_PORT_OPS(i), regval | IDT_PORT_OPS_GENPW | |
258 | IDT_PORT_OPS_PL_ELOG | | |
259 | IDT_PORT_OPS_LL_ELOG | | |
260 | IDT_PORT_OPS_LT_ELOG); | |
261 | } | |
262 | /* Overwrite error log if full */ | |
a93192a5 | 263 | rio_write_config_32(rdev, IDT_ERR_CAP, IDT_ERR_CAP_LOG_OVERWR); |
a3725c45 AB |
264 | |
265 | /* | |
266 | * Configure LANE error reporting. | |
267 | */ | |
268 | ||
269 | /* Disable line error reporting */ | |
a93192a5 | 270 | rio_write_config_32(rdev, IDT_LANE_ERR_REPORT_EN_BC, 0); |
a3725c45 AB |
271 | |
272 | /* Use Port-Writes for lane error reporting (when enabled) | |
273 | * (do per-lane update because lanes may have different configuration) | |
274 | */ | |
275 | tmp = (rdev->did == RIO_DID_IDTCPS1848) ? 48 : 16; | |
276 | for (i = 0; i < tmp; i++) { | |
a93192a5 AB |
277 | rio_read_config_32(rdev, IDT_LANE_CTRL(i), ®val); |
278 | rio_write_config_32(rdev, IDT_LANE_CTRL(i), | |
279 | regval | IDT_LANE_CTRL_GENPW); | |
a3725c45 AB |
280 | } |
281 | ||
282 | /* | |
283 | * Configure AUX error reporting. | |
284 | */ | |
285 | ||
286 | /* Disable JTAG and I2C Error capture */ | |
a93192a5 | 287 | rio_write_config_32(rdev, IDT_AUX_PORT_ERR_CAP_EN, 0); |
a3725c45 AB |
288 | |
289 | /* Disable JTAG and I2C Error reporting/logging */ | |
a93192a5 | 290 | rio_write_config_32(rdev, IDT_AUX_ERR_REPORT_EN, 0); |
a3725c45 AB |
291 | |
292 | /* Disable Port-Write notification from JTAG */ | |
a93192a5 | 293 | rio_write_config_32(rdev, IDT_JTAG_CTRL, 0); |
a3725c45 AB |
294 | |
295 | /* Disable Port-Write notification from I2C */ | |
a93192a5 AB |
296 | rio_read_config_32(rdev, IDT_I2C_MCTRL, ®val); |
297 | rio_write_config_32(rdev, IDT_I2C_MCTRL, regval & ~IDT_I2C_MCTRL_GENPW); | |
a3725c45 AB |
298 | |
299 | /* | |
300 | * Configure CFG_BLK error reporting. | |
301 | */ | |
302 | ||
303 | /* Disable Configuration Block error capture */ | |
a93192a5 | 304 | rio_write_config_32(rdev, IDT_CFGBLK_ERR_CAPTURE_EN, 0); |
a3725c45 AB |
305 | |
306 | /* Disable Port-Writes for Configuration Block error reporting */ | |
a93192a5 AB |
307 | rio_read_config_32(rdev, IDT_CFGBLK_ERR_REPORT, ®val); |
308 | rio_write_config_32(rdev, IDT_CFGBLK_ERR_REPORT, | |
309 | regval & ~IDT_CFGBLK_ERR_REPORT_GENPW); | |
a3725c45 AB |
310 | |
311 | /* set TVAL = ~50us */ | |
a93192a5 | 312 | rio_write_config_32(rdev, |
a3725c45 AB |
313 | rdev->phys_efptr + RIO_PORT_LINKTO_CTL_CSR, 0x8e << 8); |
314 | ||
315 | return 0; | |
316 | } | |
317 | ||
318 | static int | |
319 | idtg2_em_handler(struct rio_dev *rdev, u8 portnum) | |
320 | { | |
a3725c45 AB |
321 | u32 regval, em_perrdet, em_ltlerrdet; |
322 | ||
a93192a5 | 323 | rio_read_config_32(rdev, |
a3725c45 AB |
324 | rdev->em_efptr + RIO_EM_LTL_ERR_DETECT, &em_ltlerrdet); |
325 | if (em_ltlerrdet) { | |
326 | /* Service Logical/Transport Layer Error(s) */ | |
327 | if (em_ltlerrdet & REM_LTL_ERR_IMPSPEC) { | |
328 | /* Implementation specific error reported */ | |
a93192a5 | 329 | rio_read_config_32(rdev, |
a3725c45 AB |
330 | IDT_ISLTL_ADDRESS_CAP, ®val); |
331 | ||
332 | pr_debug("RIO: %s Implementation Specific LTL errors" \ | |
333 | " 0x%x @(0x%x)\n", | |
334 | rio_name(rdev), em_ltlerrdet, regval); | |
335 | ||
336 | /* Clear implementation specific address capture CSR */ | |
a93192a5 | 337 | rio_write_config_32(rdev, IDT_ISLTL_ADDRESS_CAP, 0); |
a3725c45 AB |
338 | |
339 | } | |
340 | } | |
341 | ||
a93192a5 | 342 | rio_read_config_32(rdev, |
a3725c45 AB |
343 | rdev->em_efptr + RIO_EM_PN_ERR_DETECT(portnum), &em_perrdet); |
344 | if (em_perrdet) { | |
345 | /* Service Port-Level Error(s) */ | |
346 | if (em_perrdet & REM_PED_IMPL_SPEC) { | |
347 | /* Implementation Specific port error reported */ | |
348 | ||
349 | /* Get IS errors reported */ | |
a93192a5 | 350 | rio_read_config_32(rdev, |
a3725c45 AB |
351 | IDT_PORT_ISERR_DET(portnum), ®val); |
352 | ||
353 | pr_debug("RIO: %s Implementation Specific Port" \ | |
354 | " errors 0x%x\n", rio_name(rdev), regval); | |
355 | ||
356 | /* Clear all implementation specific events */ | |
a93192a5 | 357 | rio_write_config_32(rdev, |
a3725c45 AB |
358 | IDT_PORT_ISERR_DET(portnum), 0); |
359 | } | |
360 | } | |
361 | ||
362 | return 0; | |
363 | } | |
364 | ||
365 | static ssize_t | |
366 | idtg2_show_errlog(struct device *dev, struct device_attribute *attr, char *buf) | |
367 | { | |
368 | struct rio_dev *rdev = to_rio_dev(dev); | |
a3725c45 AB |
369 | ssize_t len = 0; |
370 | u32 regval; | |
371 | ||
a93192a5 | 372 | while (!rio_read_config_32(rdev, IDT_ERR_RD, ®val)) { |
a3725c45 AB |
373 | if (!regval) /* 0 = end of log */ |
374 | break; | |
375 | len += snprintf(buf + len, PAGE_SIZE - len, | |
376 | "%08x\n", regval); | |
377 | if (len >= (PAGE_SIZE - 10)) | |
378 | break; | |
379 | } | |
380 | ||
381 | return len; | |
382 | } | |
383 | ||
384 | static DEVICE_ATTR(errlog, S_IRUGO, idtg2_show_errlog, NULL); | |
385 | ||
386 | static int idtg2_sysfs(struct rio_dev *rdev, int create) | |
387 | { | |
388 | struct device *dev = &rdev->dev; | |
389 | int err = 0; | |
390 | ||
391 | if (create == RIO_SW_SYSFS_CREATE) { | |
392 | /* Initialize sysfs entries */ | |
393 | err = device_create_file(dev, &dev_attr_errlog); | |
394 | if (err) | |
395 | dev_err(dev, "Unable create sysfs errlog file\n"); | |
396 | } else | |
397 | device_remove_file(dev, &dev_attr_errlog); | |
398 | ||
399 | return err; | |
400 | } | |
401 | ||
402 | static int idtg2_switch_init(struct rio_dev *rdev, int do_enum) | |
403 | { | |
404 | pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev)); | |
405 | rdev->rswitch->add_entry = idtg2_route_add_entry; | |
406 | rdev->rswitch->get_entry = idtg2_route_get_entry; | |
407 | rdev->rswitch->clr_table = idtg2_route_clr_table; | |
408 | rdev->rswitch->set_domain = idtg2_set_domain; | |
409 | rdev->rswitch->get_domain = idtg2_get_domain; | |
410 | rdev->rswitch->em_init = idtg2_em_init; | |
411 | rdev->rswitch->em_handle = idtg2_em_handler; | |
412 | rdev->rswitch->sw_sysfs = idtg2_sysfs; | |
413 | ||
414 | return 0; | |
415 | } | |
416 | ||
417 | DECLARE_RIO_SWITCH_INIT(RIO_VID_IDT, RIO_DID_IDTCPS1848, idtg2_switch_init); | |
418 | DECLARE_RIO_SWITCH_INIT(RIO_VID_IDT, RIO_DID_IDTCPS1616, idtg2_switch_init); | |
2e9d4d84 AB |
419 | DECLARE_RIO_SWITCH_INIT(RIO_VID_IDT, RIO_DID_IDTVPS1616, idtg2_switch_init); |
420 | DECLARE_RIO_SWITCH_INIT(RIO_VID_IDT, RIO_DID_IDTSPS1616, idtg2_switch_init); |