[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / pwm / pwm-tiecap.c

/*
 * ECAP PWM driver
 *
 * Copyright (C) 2012 Texas Instruments, Inc. - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/pm_runtime.h>
#include <linux/pwm.h>
#include <linux/of_device.h>

#include "pwm-tipwmss.h"

/* ECAP registers and bits definitions */
#define CAP1			0x08
#define CAP2			0x0C
#define CAP3			0x10
#define CAP4			0x14
#define ECCTL2			0x2A
#define ECCTL2_APWM_POL_LOW	BIT(10)
#define ECCTL2_APWM_MODE	BIT(9)
#define ECCTL2_SYNC_SEL_DISA	(BIT(7) | BIT(6))
#define ECCTL2_TSCTR_FREERUN	BIT(4)

struct ecap_pwm_chip {
	struct pwm_chip	chip;
	unsigned int	clk_rate;
	void __iomem	*mmio_base;
};

static inline struct ecap_pwm_chip *to_ecap_pwm_chip(struct pwm_chip *chip)
{
	return container_of(chip, struct ecap_pwm_chip, chip);
}

/*
 * period_ns = 10^9 * period_cycles / PWM_CLK_RATE
 * duty_ns   = 10^9 * duty_cycles / PWM_CLK_RATE
 */
static int ecap_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
		int duty_ns, int period_ns)
{
	struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
	unsigned long long c;
	unsigned long period_cycles, duty_cycles;
	unsigned int reg_val;

	if (period_ns > NSEC_PER_SEC)
		return -ERANGE;

	c = pc->clk_rate;
	c = c * period_ns;
	do_div(c, NSEC_PER_SEC);
	period_cycles = (unsigned long)c;

	if (period_cycles < 1) {
		period_cycles = 1;
		duty_cycles = 1;
	} else {
		c = pc->clk_rate;
		c = c * duty_ns;
		do_div(c, NSEC_PER_SEC);
		duty_cycles = (unsigned long)c;
	}

	pm_runtime_get_sync(pc->chip.dev);

	reg_val = readw(pc->mmio_base + ECCTL2);

	/* Configure APWM mode & disable sync option */
	reg_val |= ECCTL2_APWM_MODE | ECCTL2_SYNC_SEL_DISA;

	writew(reg_val, pc->mmio_base + ECCTL2);

	if (!test_bit(PWMF_ENABLED, &pwm->flags)) {
		/* Update active registers if not running */
		writel(duty_cycles, pc->mmio_base + CAP2);
		writel(period_cycles, pc->mmio_base + CAP1);
	} else {
		/*
		 * Update shadow registers to configure period and
		 * compare values. This helps current PWM period to
		 * complete on reconfiguring
		 */
		writel(duty_cycles, pc->mmio_base + CAP4);
		writel(period_cycles, pc->mmio_base + CAP3);
	}

	if (!test_bit(PWMF_ENABLED, &pwm->flags)) {
		reg_val = readw(pc->mmio_base + ECCTL2);
		/* Disable APWM mode to put APWM output Low */
		reg_val &= ~ECCTL2_APWM_MODE;
		writew(reg_val, pc->mmio_base + ECCTL2);
	}

	pm_runtime_put_sync(pc->chip.dev);
	return 0;
}

static int ecap_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
		enum pwm_polarity polarity)
{
	struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
	unsigned short reg_val;

	pm_runtime_get_sync(pc->chip.dev);
	reg_val = readw(pc->mmio_base + ECCTL2);
	if (polarity == PWM_POLARITY_INVERSED)
		/* Duty cycle defines LOW period of PWM */
		reg_val |= ECCTL2_APWM_POL_LOW;
	else
		/* Duty cycle defines HIGH period of PWM */
		reg_val &= ~ECCTL2_APWM_POL_LOW;

	writew(reg_val, pc->mmio_base + ECCTL2);
	pm_runtime_put_sync(pc->chip.dev);
	return 0;
}

static int ecap_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
	unsigned int reg_val;

	/* Leave clock enabled on enabling PWM */
	pm_runtime_get_sync(pc->chip.dev);

	/*
	 * Enable 'Free run Time stamp counter mode' to start counter
	 * and  'APWM mode' to enable APWM output
	 */
	reg_val = readw(pc->mmio_base + ECCTL2);
	reg_val |= ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE;
	writew(reg_val, pc->mmio_base + ECCTL2);
	return 0;
}

static void ecap_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
	unsigned int reg_val;

	/*
	 * Disable 'Free run Time stamp counter mode' to stop counter
	 * and 'APWM mode' to put APWM output to low
	 */
	reg_val = readw(pc->mmio_base + ECCTL2);
	reg_val &= ~(ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE);
	writew(reg_val, pc->mmio_base + ECCTL2);

	/* Disable clock on PWM disable */
	pm_runtime_put_sync(pc->chip.dev);
}

static void ecap_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
{
	if (test_bit(PWMF_ENABLED, &pwm->flags)) {
		dev_warn(chip->dev, "Removing PWM device without disabling\n");
		pm_runtime_put_sync(chip->dev);
	}
}

static const struct pwm_ops ecap_pwm_ops = {
	.free		= ecap_pwm_free,
	.config		= ecap_pwm_config,
	.set_polarity	= ecap_pwm_set_polarity,
	.enable		= ecap_pwm_enable,
	.disable	= ecap_pwm_disable,
	.owner		= THIS_MODULE,
};

static const struct of_device_id ecap_of_match[] = {
	{ .compatible	= "ti,am33xx-ecap" },
	{},
};
MODULE_DEVICE_TABLE(of, ecap_of_match);

static int __devinit ecap_pwm_probe(struct platform_device *pdev)
{
	int ret;
	struct resource *r;
	struct clk *clk;
	struct ecap_pwm_chip *pc;
	u16 status;

	pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
	if (!pc) {
		dev_err(&pdev->dev, "failed to allocate memory\n");
		return -ENOMEM;
	}

	clk = devm_clk_get(&pdev->dev, "fck");
	if (IS_ERR(clk)) {
		dev_err(&pdev->dev, "failed to get clock\n");
		return PTR_ERR(clk);
	}

	pc->clk_rate = clk_get_rate(clk);
	if (!pc->clk_rate) {
		dev_err(&pdev->dev, "failed to get clock rate\n");
		return -EINVAL;
	}

	pc->chip.dev = &pdev->dev;
	pc->chip.ops = &ecap_pwm_ops;
	pc->chip.of_xlate = of_pwm_xlate_with_flags;
	pc->chip.of_pwm_n_cells = 3;
	pc->chip.base = -1;
	pc->chip.npwm = 1;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!r) {
		dev_err(&pdev->dev, "no memory resource defined\n");
		return -ENODEV;
	}

	pc->mmio_base = devm_request_and_ioremap(&pdev->dev, r);
	if (!pc->mmio_base)
		return -EADDRNOTAVAIL;

	ret = pwmchip_add(&pc->chip);
	if (ret < 0) {
		dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
		return ret;
	}

	pm_runtime_enable(&pdev->dev);
	pm_runtime_get_sync(&pdev->dev);

	status = pwmss_submodule_state_change(pdev->dev.parent,
			PWMSS_ECAPCLK_EN);
	if (!(status & PWMSS_ECAPCLK_EN_ACK)) {
		dev_err(&pdev->dev, "PWMSS config space clock enable failed\n");
		ret = -EINVAL;
		goto pwmss_clk_failure;
	}

	pm_runtime_put_sync(&pdev->dev);

	platform_set_drvdata(pdev, pc);
	return 0;

pwmss_clk_failure:
	pm_runtime_put_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);
	pwmchip_remove(&pc->chip);
	return ret;
}

static int __devexit ecap_pwm_remove(struct platform_device *pdev)
{
	struct ecap_pwm_chip *pc = platform_get_drvdata(pdev);

	pm_runtime_get_sync(&pdev->dev);
	/*
	 * Due to hardware misbehaviour, acknowledge of the stop_req
	 * is missing. Hence checking of the status bit skipped.
	 */
	pwmss_submodule_state_change(pdev->dev.parent, PWMSS_ECAPCLK_STOP_REQ);
	pm_runtime_put_sync(&pdev->dev);

	pm_runtime_put_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);
	return pwmchip_remove(&pc->chip);
}

static struct platform_driver ecap_pwm_driver = {
	.driver = {
		.name	= "ecap",
		.owner	= THIS_MODULE,
		.of_match_table = ecap_of_match,
	},
	.probe = ecap_pwm_probe,
	.remove = __devexit_p(ecap_pwm_remove),
};

module_platform_driver(ecap_pwm_driver);

MODULE_DESCRIPTION("ECAP PWM driver");
MODULE_AUTHOR("Texas Instruments");
MODULE_LICENSE("GPL");
Commit	Line	Data
8e0cb05b PA	1	/*
	2	* ECAP PWM driver
	3	*
	4	* Copyright (C) 2012 Texas Instruments, Inc. - http://www.ti.com/
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	19	*/
	20
	21	#include <linux/module.h>
	22	#include <linux/platform_device.h>
	23	#include <linux/io.h>
	24	#include <linux/err.h>
	25	#include <linux/clk.h>
	26	#include <linux/pm_runtime.h>
	27	#include <linux/pwm.h>
333b08ee PA	28	#include <linux/of_device.h>
	29
	30	#include "pwm-tipwmss.h"
8e0cb05b PA	31
	32	/* ECAP registers and bits definitions */
	33	#define CAP1 0x08
	34	#define CAP2 0x0C
	35	#define CAP3 0x10
	36	#define CAP4 0x14
	37	#define ECCTL2 0x2A
454870a4	38	#define ECCTL2_APWM_POL_LOW BIT(10)
8e0cb05b PA	39	#define ECCTL2_APWM_MODE BIT(9)
	40	#define ECCTL2_SYNC_SEL_DISA (BIT(7) \| BIT(6))
	41	#define ECCTL2_TSCTR_FREERUN BIT(4)
	42
	43	struct ecap_pwm_chip {
	44	struct pwm_chip chip;
	45	unsigned int clk_rate;
	46	void __iomem *mmio_base;
	47	};
	48
	49	static inline struct ecap_pwm_chip to_ecap_pwm_chip(struct pwm_chip chip)
	50	{
	51	return container_of(chip, struct ecap_pwm_chip, chip);
	52	}
	53
	54	/*
	55	* period_ns = 10^9 * period_cycles / PWM_CLK_RATE
	56	* duty_ns = 10^9 * duty_cycles / PWM_CLK_RATE
	57	*/
	58	static int ecap_pwm_config(struct pwm_chip chip, struct pwm_device pwm,
	59	int duty_ns, int period_ns)
	60	{
	61	struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
	62	unsigned long long c;
	63	unsigned long period_cycles, duty_cycles;
	64	unsigned int reg_val;
	65
c2d476a9	66	if (period_ns > NSEC_PER_SEC)
8e0cb05b PA	67	return -ERANGE;
	68
	69	c = pc->clk_rate;
	70	c = c * period_ns;
	71	do_div(c, NSEC_PER_SEC);
	72	period_cycles = (unsigned long)c;
	73
	74	if (period_cycles < 1) {
	75	period_cycles = 1;
	76	duty_cycles = 1;
	77	} else {
	78	c = pc->clk_rate;
	79	c = c * duty_ns;
	80	do_div(c, NSEC_PER_SEC);
	81	duty_cycles = (unsigned long)c;
	82	}
	83
	84	pm_runtime_get_sync(pc->chip.dev);
	85
	86	reg_val = readw(pc->mmio_base + ECCTL2);
	87
	88	/* Configure APWM mode & disable sync option */
	89	reg_val \|= ECCTL2_APWM_MODE \| ECCTL2_SYNC_SEL_DISA;
	90
	91	writew(reg_val, pc->mmio_base + ECCTL2);
	92
	93	if (!test_bit(PWMF_ENABLED, &pwm->flags)) {
	94	/* Update active registers if not running */
	95	writel(duty_cycles, pc->mmio_base + CAP2);
	96	writel(period_cycles, pc->mmio_base + CAP1);
	97	} else {
	98	/*
	99	* Update shadow registers to configure period and
	100	* compare values. This helps current PWM period to
	101	* complete on reconfiguring
	102	*/
	103	writel(duty_cycles, pc->mmio_base + CAP4);
	104	writel(period_cycles, pc->mmio_base + CAP3);
	105	}
	106
c06fad9d PA	107	if (!test_bit(PWMF_ENABLED, &pwm->flags)) {
	108	reg_val = readw(pc->mmio_base + ECCTL2);
	109	/* Disable APWM mode to put APWM output Low */
	110	reg_val &= ~ECCTL2_APWM_MODE;
	111	writew(reg_val, pc->mmio_base + ECCTL2);
	112	}
	113
8e0cb05b PA	114	pm_runtime_put_sync(pc->chip.dev);
	115	return 0;
	116	}
	117
454870a4 PA	118	static int ecap_pwm_set_polarity(struct pwm_chip chip, struct pwm_device pwm,
	119	enum pwm_polarity polarity)
	120	{
	121	struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
	122	unsigned short reg_val;
	123
	124	pm_runtime_get_sync(pc->chip.dev);
	125	reg_val = readw(pc->mmio_base + ECCTL2);
	126	if (polarity == PWM_POLARITY_INVERSED)
	127	/* Duty cycle defines LOW period of PWM */
	128	reg_val \|= ECCTL2_APWM_POL_LOW;
	129	else
	130	/* Duty cycle defines HIGH period of PWM */
	131	reg_val &= ~ECCTL2_APWM_POL_LOW;
	132
	133	writew(reg_val, pc->mmio_base + ECCTL2);
	134	pm_runtime_put_sync(pc->chip.dev);
	135	return 0;
	136	}
	137
8e0cb05b PA	138	static int ecap_pwm_enable(struct pwm_chip chip, struct pwm_device pwm)
	139	{
	140	struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
	141	unsigned int reg_val;
	142
	143	/* Leave clock enabled on enabling PWM */
	144	pm_runtime_get_sync(pc->chip.dev);
	145
	146	/*
	147	* Enable 'Free run Time stamp counter mode' to start counter
	148	* and 'APWM mode' to enable APWM output
	149	*/
	150	reg_val = readw(pc->mmio_base + ECCTL2);
	151	reg_val \|= ECCTL2_TSCTR_FREERUN \| ECCTL2_APWM_MODE;
	152	writew(reg_val, pc->mmio_base + ECCTL2);
	153	return 0;
	154	}
	155
	156	static void ecap_pwm_disable(struct pwm_chip chip, struct pwm_device pwm)
	157	{
	158	struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
	159	unsigned int reg_val;
	160
	161	/*
	162	* Disable 'Free run Time stamp counter mode' to stop counter
	163	* and 'APWM mode' to put APWM output to low
	164	*/
	165	reg_val = readw(pc->mmio_base + ECCTL2);
	166	reg_val &= ~(ECCTL2_TSCTR_FREERUN \| ECCTL2_APWM_MODE);
	167	writew(reg_val, pc->mmio_base + ECCTL2);
	168
	169	/* Disable clock on PWM disable */
	170	pm_runtime_put_sync(pc->chip.dev);
	171	}
	172
	173	static void ecap_pwm_free(struct pwm_chip chip, struct pwm_device pwm)
	174	{
	175	if (test_bit(PWMF_ENABLED, &pwm->flags)) {
	176	dev_warn(chip->dev, "Removing PWM device without disabling\n");
	177	pm_runtime_put_sync(chip->dev);
	178	}
	179	}
	180
	181	static const struct pwm_ops ecap_pwm_ops = {
	182	.free = ecap_pwm_free,
	183	.config = ecap_pwm_config,
454870a4	184	.set_polarity = ecap_pwm_set_polarity,
8e0cb05b PA	185	.enable = ecap_pwm_enable,
	186	.disable = ecap_pwm_disable,
	187	.owner = THIS_MODULE,
	188	};
	189
333b08ee PA	190	static const struct of_device_id ecap_of_match[] = {
	191	{ .compatible = "ti,am33xx-ecap" },
	192	{},
	193	};
	194	MODULE_DEVICE_TABLE(of, ecap_of_match);
	195
8e0cb05b PA	196	static int __devinit ecap_pwm_probe(struct platform_device *pdev)
	197	{
	198	int ret;
	199	struct resource *r;
	200	struct clk *clk;
	201	struct ecap_pwm_chip *pc;
333b08ee	202	u16 status;
8e0cb05b PA	203
	204	pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
	205	if (!pc) {
	206	dev_err(&pdev->dev, "failed to allocate memory\n");
	207	return -ENOMEM;
	208	}
	209
	210	clk = devm_clk_get(&pdev->dev, "fck");
	211	if (IS_ERR(clk)) {
	212	dev_err(&pdev->dev, "failed to get clock\n");
	213	return PTR_ERR(clk);
	214	}
	215
	216	pc->clk_rate = clk_get_rate(clk);
	217	if (!pc->clk_rate) {
	218	dev_err(&pdev->dev, "failed to get clock rate\n");
	219	return -EINVAL;
	220	}
	221
	222	pc->chip.dev = &pdev->dev;
	223	pc->chip.ops = &ecap_pwm_ops;
333b08ee PA	224	pc->chip.of_xlate = of_pwm_xlate_with_flags;
333b08ee PA	225	pc->chip.of_pwm_n_cells = 3;
8e0cb05b PA	226	pc->chip.base = -1;
	227	pc->chip.npwm = 1;
	228
	229	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	230	if (!r) {
	231	dev_err(&pdev->dev, "no memory resource defined\n");
	232	return -ENODEV;
	233	}
	234
	235	pc->mmio_base = devm_request_and_ioremap(&pdev->dev, r);
2ffdc9a6	236	if (!pc->mmio_base)
8e0cb05b	237	return -EADDRNOTAVAIL;
8e0cb05b PA	238
	239	ret = pwmchip_add(&pc->chip);
	240	if (ret < 0) {
	241	dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
	242	return ret;
	243	}
	244
	245	pm_runtime_enable(&pdev->dev);
333b08ee PA	246	pm_runtime_get_sync(&pdev->dev);
	247
	248	status = pwmss_submodule_state_change(pdev->dev.parent,
	249	PWMSS_ECAPCLK_EN);
	250	if (!(status & PWMSS_ECAPCLK_EN_ACK)) {
	251	dev_err(&pdev->dev, "PWMSS config space clock enable failed\n");
	252	ret = -EINVAL;
	253	goto pwmss_clk_failure;
	254	}
	255
	256	pm_runtime_put_sync(&pdev->dev);
	257
8e0cb05b PA	258	platform_set_drvdata(pdev, pc);
8e0cb05b PA	259	return 0;
333b08ee PA	260
	261	pwmss_clk_failure:
	262	pm_runtime_put_sync(&pdev->dev);
	263	pm_runtime_disable(&pdev->dev);
	264	pwmchip_remove(&pc->chip);
	265	return ret;
8e0cb05b PA	266	}
	267
	268	static int __devexit ecap_pwm_remove(struct platform_device *pdev)
	269	{
	270	struct ecap_pwm_chip *pc = platform_get_drvdata(pdev);
	271
333b08ee PA	272	pm_runtime_get_sync(&pdev->dev);
	273	/*
	274	* Due to hardware misbehaviour, acknowledge of the stop_req
	275	* is missing. Hence checking of the status bit skipped.
	276	*/
	277	pwmss_submodule_state_change(pdev->dev.parent, PWMSS_ECAPCLK_STOP_REQ);
	278	pm_runtime_put_sync(&pdev->dev);
	279
8e0cb05b PA	280	pm_runtime_put_sync(&pdev->dev);
	281	pm_runtime_disable(&pdev->dev);
	282	return pwmchip_remove(&pc->chip);
	283	}
	284
	285	static struct platform_driver ecap_pwm_driver = {
	286	.driver = {
333b08ee PA	287	.name = "ecap",
	288	.owner = THIS_MODULE,
	289	.of_match_table = ecap_of_match,
8e0cb05b PA	290	},
	291	.probe = ecap_pwm_probe,
	292	.remove = __devexit_p(ecap_pwm_remove),
	293	};
	294
	295	module_platform_driver(ecap_pwm_driver);
	296
	297	MODULE_DESCRIPTION("ECAP PWM driver");
	298	MODULE_AUTHOR("Texas Instruments");
	299	MODULE_LICENSE("GPL");