Commit | Line | Data |
---|---|---|
2744e8af LW |
1 | /* |
2 | * Core driver for the pin muxing portions of the pin control subsystem | |
3 | * | |
e93bcee0 | 4 | * Copyright (C) 2011-2012 ST-Ericsson SA |
2744e8af LW |
5 | * Written on behalf of Linaro for ST-Ericsson |
6 | * Based on bits of regulator core, gpio core and clk core | |
7 | * | |
8 | * Author: Linus Walleij <linus.walleij@linaro.org> | |
9 | * | |
7ecdb16f SW |
10 | * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. |
11 | * | |
2744e8af LW |
12 | * License terms: GNU General Public License (GPL) version 2 |
13 | */ | |
14 | #define pr_fmt(fmt) "pinmux core: " fmt | |
15 | ||
16 | #include <linux/kernel.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/device.h> | |
20 | #include <linux/slab.h> | |
21 | #include <linux/radix-tree.h> | |
22 | #include <linux/err.h> | |
23 | #include <linux/list.h> | |
97607d15 | 24 | #include <linux/string.h> |
2744e8af LW |
25 | #include <linux/sysfs.h> |
26 | #include <linux/debugfs.h> | |
27 | #include <linux/seq_file.h> | |
28 | #include <linux/pinctrl/machine.h> | |
29 | #include <linux/pinctrl/pinmux.h> | |
30 | #include "core.h" | |
befe5bdf | 31 | #include "pinmux.h" |
2744e8af | 32 | |
03665e0f SW |
33 | int pinmux_check_ops(struct pinctrl_dev *pctldev) |
34 | { | |
35 | const struct pinmux_ops *ops = pctldev->desc->pmxops; | |
a1d31f71 | 36 | unsigned nfuncs; |
03665e0f SW |
37 | unsigned selector = 0; |
38 | ||
39 | /* Check that we implement required operations */ | |
a1d31f71 DA |
40 | if (!ops || |
41 | !ops->get_functions_count || | |
03665e0f SW |
42 | !ops->get_function_name || |
43 | !ops->get_function_groups || | |
02b50ce4 | 44 | !ops->enable) { |
ad6e1107 | 45 | dev_err(pctldev->dev, "pinmux ops lacks necessary functions\n"); |
03665e0f | 46 | return -EINVAL; |
ad6e1107 | 47 | } |
03665e0f | 48 | /* Check that all functions registered have names */ |
a1d31f71 | 49 | nfuncs = ops->get_functions_count(pctldev); |
d1e90e9e | 50 | while (selector < nfuncs) { |
03665e0f SW |
51 | const char *fname = ops->get_function_name(pctldev, |
52 | selector); | |
53 | if (!fname) { | |
a1d31f71 | 54 | dev_err(pctldev->dev, "pinmux ops has no name for function%u\n", |
03665e0f SW |
55 | selector); |
56 | return -EINVAL; | |
57 | } | |
58 | selector++; | |
59 | } | |
60 | ||
61 | return 0; | |
62 | } | |
63 | ||
1e2082b5 SW |
64 | int pinmux_validate_map(struct pinctrl_map const *map, int i) |
65 | { | |
66 | if (!map->data.mux.function) { | |
67 | pr_err("failed to register map %s (%d): no function given\n", | |
68 | map->name, i); | |
69 | return -EINVAL; | |
70 | } | |
71 | ||
72 | return 0; | |
73 | } | |
74 | ||
2744e8af LW |
75 | /** |
76 | * pin_request() - request a single pin to be muxed in, typically for GPIO | |
77 | * @pin: the pin number in the global pin space | |
3cc70ed3 SW |
78 | * @owner: a representation of the owner of this pin; typically the device |
79 | * name that controls its mux function, or the requested GPIO name | |
2744e8af LW |
80 | * @gpio_range: the range matching the GPIO pin if this is a request for a |
81 | * single GPIO pin | |
82 | */ | |
83 | static int pin_request(struct pinctrl_dev *pctldev, | |
3cc70ed3 | 84 | int pin, const char *owner, |
2744e8af LW |
85 | struct pinctrl_gpio_range *gpio_range) |
86 | { | |
87 | struct pin_desc *desc; | |
88 | const struct pinmux_ops *ops = pctldev->desc->pmxops; | |
89 | int status = -EINVAL; | |
90 | ||
2744e8af LW |
91 | desc = pin_desc_get(pctldev, pin); |
92 | if (desc == NULL) { | |
51cd24ee | 93 | dev_err(pctldev->dev, |
d4705316 SW |
94 | "pin %d is not registered so it cannot be requested\n", |
95 | pin); | |
2744e8af LW |
96 | goto out; |
97 | } | |
98 | ||
d0bd8df5 DA |
99 | dev_dbg(pctldev->dev, "request pin %d (%s) for %s\n", |
100 | pin, desc->name, owner); | |
101 | ||
652162d4 SW |
102 | if (gpio_range) { |
103 | /* There's no need to support multiple GPIO requests */ | |
104 | if (desc->gpio_owner) { | |
105 | dev_err(pctldev->dev, | |
d4705316 SW |
106 | "pin %s already requested by %s; cannot claim for %s\n", |
107 | desc->name, desc->gpio_owner, owner); | |
652162d4 SW |
108 | goto out; |
109 | } | |
0e3db173 | 110 | |
652162d4 SW |
111 | desc->gpio_owner = owner; |
112 | } else { | |
113 | if (desc->mux_usecount && strcmp(desc->mux_owner, owner)) { | |
114 | dev_err(pctldev->dev, | |
d4705316 SW |
115 | "pin %s already requested by %s; cannot claim for %s\n", |
116 | desc->name, desc->mux_owner, owner); | |
652162d4 SW |
117 | goto out; |
118 | } | |
0e3db173 | 119 | |
652162d4 SW |
120 | desc->mux_usecount++; |
121 | if (desc->mux_usecount > 1) | |
122 | return 0; | |
123 | ||
124 | desc->mux_owner = owner; | |
125 | } | |
2744e8af LW |
126 | |
127 | /* Let each pin increase references to this module */ | |
128 | if (!try_module_get(pctldev->owner)) { | |
51cd24ee | 129 | dev_err(pctldev->dev, |
2744e8af LW |
130 | "could not increase module refcount for pin %d\n", |
131 | pin); | |
132 | status = -EINVAL; | |
133 | goto out_free_pin; | |
134 | } | |
135 | ||
136 | /* | |
137 | * If there is no kind of request function for the pin we just assume | |
138 | * we got it by default and proceed. | |
139 | */ | |
3712a3c4 | 140 | if (gpio_range && ops->gpio_request_enable) |
2744e8af LW |
141 | /* This requests and enables a single GPIO pin */ |
142 | status = ops->gpio_request_enable(pctldev, gpio_range, pin); | |
143 | else if (ops->request) | |
144 | status = ops->request(pctldev, pin); | |
145 | else | |
146 | status = 0; | |
147 | ||
0e3db173 | 148 | if (status) { |
d4705316 | 149 | dev_err(pctldev->dev, "request() failed for pin %d\n", pin); |
0e3db173 SW |
150 | module_put(pctldev->owner); |
151 | } | |
152 | ||
2744e8af | 153 | out_free_pin: |
0e3db173 | 154 | if (status) { |
652162d4 SW |
155 | if (gpio_range) { |
156 | desc->gpio_owner = NULL; | |
157 | } else { | |
158 | desc->mux_usecount--; | |
159 | if (!desc->mux_usecount) | |
160 | desc->mux_owner = NULL; | |
161 | } | |
0e3db173 | 162 | } |
2744e8af LW |
163 | out: |
164 | if (status) | |
51cd24ee | 165 | dev_err(pctldev->dev, "pin-%d (%s) status %d\n", |
d4705316 | 166 | pin, owner, status); |
2744e8af LW |
167 | |
168 | return status; | |
169 | } | |
170 | ||
171 | /** | |
172 | * pin_free() - release a single muxed in pin so something else can be muxed | |
173 | * @pctldev: pin controller device handling this pin | |
174 | * @pin: the pin to free | |
3712a3c4 SW |
175 | * @gpio_range: the range matching the GPIO pin if this is a request for a |
176 | * single GPIO pin | |
336cdba0 | 177 | * |
3cc70ed3 SW |
178 | * This function returns a pointer to the previous owner. This is used |
179 | * for callers that dynamically allocate an owner name so it can be freed | |
336cdba0 | 180 | * once the pin is free. This is done for GPIO request functions. |
2744e8af | 181 | */ |
3712a3c4 SW |
182 | static const char *pin_free(struct pinctrl_dev *pctldev, int pin, |
183 | struct pinctrl_gpio_range *gpio_range) | |
2744e8af LW |
184 | { |
185 | const struct pinmux_ops *ops = pctldev->desc->pmxops; | |
186 | struct pin_desc *desc; | |
3cc70ed3 | 187 | const char *owner; |
2744e8af LW |
188 | |
189 | desc = pin_desc_get(pctldev, pin); | |
190 | if (desc == NULL) { | |
51cd24ee | 191 | dev_err(pctldev->dev, |
2744e8af | 192 | "pin is not registered so it cannot be freed\n"); |
3712a3c4 | 193 | return NULL; |
2744e8af LW |
194 | } |
195 | ||
652162d4 | 196 | if (!gpio_range) { |
740924a2 RG |
197 | /* |
198 | * A pin should not be freed more times than allocated. | |
199 | */ | |
200 | if (WARN_ON(!desc->mux_usecount)) | |
201 | return NULL; | |
652162d4 SW |
202 | desc->mux_usecount--; |
203 | if (desc->mux_usecount) | |
204 | return NULL; | |
205 | } | |
0e3db173 | 206 | |
3712a3c4 SW |
207 | /* |
208 | * If there is no kind of request function for the pin we just assume | |
209 | * we got it by default and proceed. | |
210 | */ | |
211 | if (gpio_range && ops->gpio_disable_free) | |
212 | ops->gpio_disable_free(pctldev, gpio_range, pin); | |
213 | else if (ops->free) | |
2744e8af LW |
214 | ops->free(pctldev, pin); |
215 | ||
652162d4 SW |
216 | if (gpio_range) { |
217 | owner = desc->gpio_owner; | |
218 | desc->gpio_owner = NULL; | |
219 | } else { | |
220 | owner = desc->mux_owner; | |
221 | desc->mux_owner = NULL; | |
222 | desc->mux_setting = NULL; | |
223 | } | |
224 | ||
2744e8af | 225 | module_put(pctldev->owner); |
3712a3c4 | 226 | |
3cc70ed3 | 227 | return owner; |
2744e8af LW |
228 | } |
229 | ||
230 | /** | |
befe5bdf LW |
231 | * pinmux_request_gpio() - request pinmuxing for a GPIO pin |
232 | * @pctldev: pin controller device affected | |
233 | * @pin: the pin to mux in for GPIO | |
234 | * @range: the applicable GPIO range | |
2744e8af | 235 | */ |
befe5bdf LW |
236 | int pinmux_request_gpio(struct pinctrl_dev *pctldev, |
237 | struct pinctrl_gpio_range *range, | |
238 | unsigned pin, unsigned gpio) | |
2744e8af | 239 | { |
3cc70ed3 | 240 | const char *owner; |
2744e8af | 241 | int ret; |
2744e8af LW |
242 | |
243 | /* Conjure some name stating what chip and pin this is taken by */ | |
23a895ae | 244 | owner = kasprintf(GFP_KERNEL, "%s:%d", range->name, gpio); |
3cc70ed3 | 245 | if (!owner) |
5d2eaf80 SW |
246 | return -EINVAL; |
247 | ||
3cc70ed3 | 248 | ret = pin_request(pctldev, pin, owner, range); |
5d2eaf80 | 249 | if (ret < 0) |
3cc70ed3 | 250 | kfree(owner); |
5d2eaf80 SW |
251 | |
252 | return ret; | |
2744e8af | 253 | } |
2744e8af LW |
254 | |
255 | /** | |
befe5bdf LW |
256 | * pinmux_free_gpio() - release a pin from GPIO muxing |
257 | * @pctldev: the pin controller device for the pin | |
258 | * @pin: the affected currently GPIO-muxed in pin | |
259 | * @range: applicable GPIO range | |
2744e8af | 260 | */ |
befe5bdf LW |
261 | void pinmux_free_gpio(struct pinctrl_dev *pctldev, unsigned pin, |
262 | struct pinctrl_gpio_range *range) | |
2744e8af | 263 | { |
3cc70ed3 | 264 | const char *owner; |
2744e8af | 265 | |
3cc70ed3 SW |
266 | owner = pin_free(pctldev, pin, range); |
267 | kfree(owner); | |
2744e8af | 268 | } |
2744e8af | 269 | |
befe5bdf LW |
270 | /** |
271 | * pinmux_gpio_direction() - set the direction of a single muxed-in GPIO pin | |
272 | * @pctldev: the pin controller handling this pin | |
273 | * @range: applicable GPIO range | |
274 | * @pin: the affected GPIO pin in this controller | |
275 | * @input: true if we set the pin as input, false for output | |
276 | */ | |
277 | int pinmux_gpio_direction(struct pinctrl_dev *pctldev, | |
278 | struct pinctrl_gpio_range *range, | |
279 | unsigned pin, bool input) | |
542e704f | 280 | { |
542e704f LW |
281 | const struct pinmux_ops *ops; |
282 | int ret; | |
542e704f LW |
283 | |
284 | ops = pctldev->desc->pmxops; | |
285 | ||
542e704f LW |
286 | if (ops->gpio_set_direction) |
287 | ret = ops->gpio_set_direction(pctldev, range, pin, input); | |
288 | else | |
289 | ret = 0; | |
290 | ||
291 | return ret; | |
292 | } | |
293 | ||
7ecdb16f SW |
294 | static int pinmux_func_name_to_selector(struct pinctrl_dev *pctldev, |
295 | const char *function) | |
2744e8af LW |
296 | { |
297 | const struct pinmux_ops *ops = pctldev->desc->pmxops; | |
d1e90e9e | 298 | unsigned nfuncs = ops->get_functions_count(pctldev); |
2744e8af LW |
299 | unsigned selector = 0; |
300 | ||
301 | /* See if this pctldev has this function */ | |
d1e90e9e | 302 | while (selector < nfuncs) { |
2744e8af LW |
303 | const char *fname = ops->get_function_name(pctldev, |
304 | selector); | |
2744e8af | 305 | |
7ecdb16f SW |
306 | if (!strcmp(function, fname)) |
307 | return selector; | |
2744e8af | 308 | |
2744e8af LW |
309 | selector++; |
310 | } | |
311 | ||
312 | pr_err("%s does not support function %s\n", | |
7ecdb16f | 313 | pinctrl_dev_get_name(pctldev), function); |
2744e8af LW |
314 | return -EINVAL; |
315 | } | |
316 | ||
7ecdb16f SW |
317 | int pinmux_map_to_setting(struct pinctrl_map const *map, |
318 | struct pinctrl_setting *setting) | |
2744e8af | 319 | { |
7ecdb16f SW |
320 | struct pinctrl_dev *pctldev = setting->pctldev; |
321 | const struct pinmux_ops *pmxops = pctldev->desc->pmxops; | |
7ecdb16f SW |
322 | char const * const *groups; |
323 | unsigned num_groups; | |
2744e8af | 324 | int ret; |
7ecdb16f SW |
325 | const char *group; |
326 | int i; | |
2744e8af | 327 | |
ad8bb720 DA |
328 | if (!pmxops) { |
329 | dev_err(pctldev->dev, "does not support mux function\n"); | |
330 | return -EINVAL; | |
331 | } | |
332 | ||
15f70e1b | 333 | ret = pinmux_func_name_to_selector(pctldev, map->data.mux.function); |
ad6e1107 JC |
334 | if (ret < 0) { |
335 | dev_err(pctldev->dev, "invalid function %s in map table\n", | |
336 | map->data.mux.function); | |
15f70e1b | 337 | return ret; |
ad6e1107 | 338 | } |
15f70e1b | 339 | setting->data.mux.func = ret; |
2744e8af | 340 | |
1e2082b5 | 341 | ret = pmxops->get_function_groups(pctldev, setting->data.mux.func, |
7ecdb16f | 342 | &groups, &num_groups); |
ad6e1107 JC |
343 | if (ret < 0) { |
344 | dev_err(pctldev->dev, "can't query groups for function %s\n", | |
345 | map->data.mux.function); | |
7ecdb16f | 346 | return ret; |
ad6e1107 JC |
347 | } |
348 | if (!num_groups) { | |
349 | dev_err(pctldev->dev, | |
350 | "function %s can't be selected on any group\n", | |
351 | map->data.mux.function); | |
2744e8af | 352 | return -EINVAL; |
ad6e1107 | 353 | } |
1e2082b5 | 354 | if (map->data.mux.group) { |
7ecdb16f | 355 | bool found = false; |
1e2082b5 | 356 | group = map->data.mux.group; |
7ecdb16f SW |
357 | for (i = 0; i < num_groups; i++) { |
358 | if (!strcmp(group, groups[i])) { | |
359 | found = true; | |
360 | break; | |
361 | } | |
362 | } | |
ad6e1107 JC |
363 | if (!found) { |
364 | dev_err(pctldev->dev, | |
365 | "invalid group \"%s\" for function \"%s\"\n", | |
366 | group, map->data.mux.function); | |
7ecdb16f | 367 | return -EINVAL; |
ad6e1107 | 368 | } |
7ecdb16f SW |
369 | } else { |
370 | group = groups[0]; | |
2744e8af | 371 | } |
2744e8af | 372 | |
15f70e1b | 373 | ret = pinctrl_get_group_selector(pctldev, group); |
ad6e1107 JC |
374 | if (ret < 0) { |
375 | dev_err(pctldev->dev, "invalid group %s in map table\n", | |
376 | map->data.mux.group); | |
15f70e1b | 377 | return ret; |
ad6e1107 | 378 | } |
15f70e1b | 379 | setting->data.mux.group = ret; |
2744e8af | 380 | |
2744e8af LW |
381 | return 0; |
382 | } | |
383 | ||
7ecdb16f | 384 | void pinmux_free_setting(struct pinctrl_setting const *setting) |
2744e8af | 385 | { |
1a78958d | 386 | /* This function is currently unused */ |
2744e8af | 387 | } |
2744e8af | 388 | |
7ecdb16f | 389 | int pinmux_enable_setting(struct pinctrl_setting const *setting) |
2744e8af | 390 | { |
7ecdb16f | 391 | struct pinctrl_dev *pctldev = setting->pctldev; |
ba110d90 | 392 | const struct pinctrl_ops *pctlops = pctldev->desc->pctlops; |
befe5bdf | 393 | const struct pinmux_ops *ops = pctldev->desc->pmxops; |
ba110d90 SW |
394 | int ret; |
395 | const unsigned *pins; | |
396 | unsigned num_pins; | |
397 | int i; | |
398 | struct pin_desc *desc; | |
399 | ||
400 | ret = pctlops->get_group_pins(pctldev, setting->data.mux.group, | |
401 | &pins, &num_pins); | |
402 | if (ret) { | |
403 | /* errors only affect debug data, so just warn */ | |
404 | dev_warn(pctldev->dev, | |
405 | "could not get pins for group selector %d\n", | |
406 | setting->data.mux.group); | |
407 | num_pins = 0; | |
408 | } | |
409 | ||
1a78958d LW |
410 | /* Try to allocate all pins in this group, one by one */ |
411 | for (i = 0; i < num_pins; i++) { | |
412 | ret = pin_request(pctldev, pins[i], setting->dev_name, NULL); | |
413 | if (ret) { | |
414 | dev_err(pctldev->dev, | |
415 | "could not request pin %d on device %s\n", | |
416 | pins[i], pinctrl_dev_get_name(pctldev)); | |
e38d457d | 417 | goto err_pin_request; |
1a78958d LW |
418 | } |
419 | } | |
420 | ||
421 | /* Now that we have acquired the pins, encode the mux setting */ | |
ba110d90 SW |
422 | for (i = 0; i < num_pins; i++) { |
423 | desc = pin_desc_get(pctldev, pins[i]); | |
424 | if (desc == NULL) { | |
425 | dev_warn(pctldev->dev, | |
426 | "could not get pin desc for pin %d\n", | |
427 | pins[i]); | |
428 | continue; | |
429 | } | |
430 | desc->mux_setting = &(setting->data.mux); | |
431 | } | |
2744e8af | 432 | |
e38d457d AL |
433 | ret = ops->enable(pctldev, setting->data.mux.func, |
434 | setting->data.mux.group); | |
435 | ||
436 | if (ret) | |
437 | goto err_enable; | |
438 | ||
439 | return 0; | |
440 | ||
441 | err_enable: | |
442 | for (i = 0; i < num_pins; i++) { | |
443 | desc = pin_desc_get(pctldev, pins[i]); | |
444 | if (desc) | |
445 | desc->mux_setting = NULL; | |
446 | } | |
447 | err_pin_request: | |
448 | /* On error release all taken pins */ | |
449 | while (--i >= 0) | |
450 | pin_free(pctldev, pins[i], NULL); | |
451 | ||
452 | return ret; | |
2744e8af | 453 | } |
2744e8af | 454 | |
7ecdb16f | 455 | void pinmux_disable_setting(struct pinctrl_setting const *setting) |
2744e8af | 456 | { |
7ecdb16f | 457 | struct pinctrl_dev *pctldev = setting->pctldev; |
ba110d90 | 458 | const struct pinctrl_ops *pctlops = pctldev->desc->pctlops; |
befe5bdf | 459 | const struct pinmux_ops *ops = pctldev->desc->pmxops; |
ba110d90 SW |
460 | int ret; |
461 | const unsigned *pins; | |
462 | unsigned num_pins; | |
463 | int i; | |
464 | struct pin_desc *desc; | |
465 | ||
466 | ret = pctlops->get_group_pins(pctldev, setting->data.mux.group, | |
467 | &pins, &num_pins); | |
468 | if (ret) { | |
469 | /* errors only affect debug data, so just warn */ | |
470 | dev_warn(pctldev->dev, | |
471 | "could not get pins for group selector %d\n", | |
472 | setting->data.mux.group); | |
473 | num_pins = 0; | |
474 | } | |
475 | ||
1a78958d | 476 | /* Flag the descs that no setting is active */ |
ba110d90 SW |
477 | for (i = 0; i < num_pins; i++) { |
478 | desc = pin_desc_get(pctldev, pins[i]); | |
479 | if (desc == NULL) { | |
480 | dev_warn(pctldev->dev, | |
481 | "could not get pin desc for pin %d\n", | |
482 | pins[i]); | |
483 | continue; | |
484 | } | |
485 | desc->mux_setting = NULL; | |
486 | } | |
2744e8af | 487 | |
1a78958d LW |
488 | /* And release the pins */ |
489 | for (i = 0; i < num_pins; i++) | |
490 | pin_free(pctldev, pins[i], NULL); | |
491 | ||
02b50ce4 DA |
492 | if (ops->disable) |
493 | ops->disable(pctldev, setting->data.mux.func, setting->data.mux.group); | |
2744e8af | 494 | } |
2744e8af | 495 | |
2744e8af LW |
496 | #ifdef CONFIG_DEBUG_FS |
497 | ||
498 | /* Called from pincontrol core */ | |
499 | static int pinmux_functions_show(struct seq_file *s, void *what) | |
500 | { | |
501 | struct pinctrl_dev *pctldev = s->private; | |
502 | const struct pinmux_ops *pmxops = pctldev->desc->pmxops; | |
ad8bb720 | 503 | unsigned nfuncs; |
2744e8af LW |
504 | unsigned func_selector = 0; |
505 | ||
ad8bb720 DA |
506 | if (!pmxops) |
507 | return 0; | |
57b676f9 | 508 | |
42fed7ba | 509 | mutex_lock(&pctldev->mutex); |
ad8bb720 | 510 | nfuncs = pmxops->get_functions_count(pctldev); |
d1e90e9e | 511 | while (func_selector < nfuncs) { |
2744e8af LW |
512 | const char *func = pmxops->get_function_name(pctldev, |
513 | func_selector); | |
514 | const char * const *groups; | |
515 | unsigned num_groups; | |
516 | int ret; | |
517 | int i; | |
518 | ||
519 | ret = pmxops->get_function_groups(pctldev, func_selector, | |
520 | &groups, &num_groups); | |
521 | if (ret) | |
522 | seq_printf(s, "function %s: COULD NOT GET GROUPS\n", | |
523 | func); | |
524 | ||
525 | seq_printf(s, "function: %s, groups = [ ", func); | |
526 | for (i = 0; i < num_groups; i++) | |
527 | seq_printf(s, "%s ", groups[i]); | |
528 | seq_puts(s, "]\n"); | |
529 | ||
530 | func_selector++; | |
2744e8af LW |
531 | } |
532 | ||
42fed7ba | 533 | mutex_unlock(&pctldev->mutex); |
57b676f9 | 534 | |
2744e8af LW |
535 | return 0; |
536 | } | |
537 | ||
538 | static int pinmux_pins_show(struct seq_file *s, void *what) | |
539 | { | |
540 | struct pinctrl_dev *pctldev = s->private; | |
ba110d90 SW |
541 | const struct pinctrl_ops *pctlops = pctldev->desc->pctlops; |
542 | const struct pinmux_ops *pmxops = pctldev->desc->pmxops; | |
706e8520 | 543 | unsigned i, pin; |
2744e8af | 544 | |
ad8bb720 DA |
545 | if (!pmxops) |
546 | return 0; | |
547 | ||
2744e8af | 548 | seq_puts(s, "Pinmux settings per pin\n"); |
652162d4 | 549 | seq_puts(s, "Format: pin (name): mux_owner gpio_owner hog?\n"); |
2744e8af | 550 | |
42fed7ba | 551 | mutex_lock(&pctldev->mutex); |
57b676f9 | 552 | |
706e8520 CP |
553 | /* The pin number can be retrived from the pin controller descriptor */ |
554 | for (i = 0; i < pctldev->desc->npins; i++) { | |
2744e8af | 555 | struct pin_desc *desc; |
1cf94c45 | 556 | bool is_hog = false; |
2744e8af | 557 | |
706e8520 | 558 | pin = pctldev->desc->pins[i].number; |
2744e8af | 559 | desc = pin_desc_get(pctldev, pin); |
706e8520 | 560 | /* Skip if we cannot search the pin */ |
2744e8af LW |
561 | if (desc == NULL) |
562 | continue; | |
563 | ||
652162d4 SW |
564 | if (desc->mux_owner && |
565 | !strcmp(desc->mux_owner, pinctrl_dev_get_name(pctldev))) | |
1cf94c45 LW |
566 | is_hog = true; |
567 | ||
652162d4 | 568 | seq_printf(s, "pin %d (%s): %s %s%s", pin, |
2744e8af | 569 | desc->name ? desc->name : "unnamed", |
652162d4 SW |
570 | desc->mux_owner ? desc->mux_owner |
571 | : "(MUX UNCLAIMED)", | |
572 | desc->gpio_owner ? desc->gpio_owner | |
573 | : "(GPIO UNCLAIMED)", | |
1cf94c45 | 574 | is_hog ? " (HOG)" : ""); |
ba110d90 SW |
575 | |
576 | if (desc->mux_setting) | |
577 | seq_printf(s, " function %s group %s\n", | |
578 | pmxops->get_function_name(pctldev, | |
579 | desc->mux_setting->func), | |
580 | pctlops->get_group_name(pctldev, | |
581 | desc->mux_setting->group)); | |
582 | else | |
583 | seq_printf(s, "\n"); | |
2744e8af LW |
584 | } |
585 | ||
42fed7ba | 586 | mutex_unlock(&pctldev->mutex); |
57b676f9 | 587 | |
2744e8af LW |
588 | return 0; |
589 | } | |
590 | ||
1e2082b5 SW |
591 | void pinmux_show_map(struct seq_file *s, struct pinctrl_map const *map) |
592 | { | |
593 | seq_printf(s, "group %s\nfunction %s\n", | |
594 | map->data.mux.group ? map->data.mux.group : "(default)", | |
595 | map->data.mux.function); | |
596 | } | |
597 | ||
598 | void pinmux_show_setting(struct seq_file *s, | |
599 | struct pinctrl_setting const *setting) | |
2744e8af | 600 | { |
7ecdb16f SW |
601 | struct pinctrl_dev *pctldev = setting->pctldev; |
602 | const struct pinmux_ops *pmxops = pctldev->desc->pmxops; | |
603 | const struct pinctrl_ops *pctlops = pctldev->desc->pctlops; | |
604 | ||
1e2082b5 SW |
605 | seq_printf(s, "group: %s (%u) function: %s (%u)\n", |
606 | pctlops->get_group_name(pctldev, setting->data.mux.group), | |
607 | setting->data.mux.group, | |
608 | pmxops->get_function_name(pctldev, setting->data.mux.func), | |
609 | setting->data.mux.func); | |
2744e8af LW |
610 | } |
611 | ||
612 | static int pinmux_functions_open(struct inode *inode, struct file *file) | |
613 | { | |
614 | return single_open(file, pinmux_functions_show, inode->i_private); | |
615 | } | |
616 | ||
617 | static int pinmux_pins_open(struct inode *inode, struct file *file) | |
618 | { | |
619 | return single_open(file, pinmux_pins_show, inode->i_private); | |
620 | } | |
621 | ||
2744e8af LW |
622 | static const struct file_operations pinmux_functions_ops = { |
623 | .open = pinmux_functions_open, | |
624 | .read = seq_read, | |
625 | .llseek = seq_lseek, | |
626 | .release = single_release, | |
627 | }; | |
628 | ||
629 | static const struct file_operations pinmux_pins_ops = { | |
630 | .open = pinmux_pins_open, | |
631 | .read = seq_read, | |
632 | .llseek = seq_lseek, | |
633 | .release = single_release, | |
634 | }; | |
635 | ||
2744e8af LW |
636 | void pinmux_init_device_debugfs(struct dentry *devroot, |
637 | struct pinctrl_dev *pctldev) | |
638 | { | |
639 | debugfs_create_file("pinmux-functions", S_IFREG | S_IRUGO, | |
640 | devroot, pctldev, &pinmux_functions_ops); | |
641 | debugfs_create_file("pinmux-pins", S_IFREG | S_IRUGO, | |
642 | devroot, pctldev, &pinmux_pins_ops); | |
2744e8af LW |
643 | } |
644 | ||
645 | #endif /* CONFIG_DEBUG_FS */ |