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393daa81 RY |
1 | /* |
2 | * pinmux driver for CSR SiRFprimaII | |
3 | * | |
4 | * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. | |
5 | * | |
6 | * Licensed under GPLv2 or later. | |
7 | */ | |
8 | ||
9 | #include <linux/init.h> | |
10 | #include <linux/module.h> | |
51302162 | 11 | #include <linux/irq.h> |
393daa81 RY |
12 | #include <linux/platform_device.h> |
13 | #include <linux/io.h> | |
14 | #include <linux/slab.h> | |
15 | #include <linux/err.h> | |
51302162 | 16 | #include <linux/irqdomain.h> |
393daa81 RY |
17 | #include <linux/pinctrl/pinctrl.h> |
18 | #include <linux/pinctrl/pinmux.h> | |
51302162 | 19 | #include <linux/pinctrl/consumer.h> |
056876f6 | 20 | #include <linux/pinctrl/machine.h> |
393daa81 RY |
21 | #include <linux/of.h> |
22 | #include <linux/of_address.h> | |
23 | #include <linux/of_device.h> | |
24 | #include <linux/of_platform.h> | |
25 | #include <linux/bitops.h> | |
51302162 BS |
26 | #include <linux/gpio.h> |
27 | #include <linux/of_gpio.h> | |
6fd4011e | 28 | #include <asm/mach/irq.h> |
393daa81 RY |
29 | |
30 | #define DRIVER_NAME "pinmux-sirf" | |
31 | ||
32 | #define SIRFSOC_NUM_PADS 622 | |
393daa81 RY |
33 | #define SIRFSOC_RSC_PIN_MUX 0x4 |
34 | ||
51302162 BS |
35 | #define SIRFSOC_GPIO_PAD_EN(g) ((g)*0x100 + 0x84) |
36 | #define SIRFSOC_GPIO_CTRL(g, i) ((g)*0x100 + (i)*4) | |
37 | #define SIRFSOC_GPIO_DSP_EN0 (0x80) | |
38 | #define SIRFSOC_GPIO_PAD_EN(g) ((g)*0x100 + 0x84) | |
39 | #define SIRFSOC_GPIO_INT_STATUS(g) ((g)*0x100 + 0x8C) | |
40 | ||
41 | #define SIRFSOC_GPIO_CTL_INTR_LOW_MASK 0x1 | |
42 | #define SIRFSOC_GPIO_CTL_INTR_HIGH_MASK 0x2 | |
43 | #define SIRFSOC_GPIO_CTL_INTR_TYPE_MASK 0x4 | |
44 | #define SIRFSOC_GPIO_CTL_INTR_EN_MASK 0x8 | |
45 | #define SIRFSOC_GPIO_CTL_INTR_STS_MASK 0x10 | |
46 | #define SIRFSOC_GPIO_CTL_OUT_EN_MASK 0x20 | |
47 | #define SIRFSOC_GPIO_CTL_DATAOUT_MASK 0x40 | |
48 | #define SIRFSOC_GPIO_CTL_DATAIN_MASK 0x80 | |
49 | #define SIRFSOC_GPIO_CTL_PULL_MASK 0x100 | |
50 | #define SIRFSOC_GPIO_CTL_PULL_HIGH 0x200 | |
51 | #define SIRFSOC_GPIO_CTL_DSP_INT 0x400 | |
52 | ||
53 | #define SIRFSOC_GPIO_NO_OF_BANKS 5 | |
54 | #define SIRFSOC_GPIO_BANK_SIZE 32 | |
55 | #define SIRFSOC_GPIO_NUM(bank, index) (((bank)*(32)) + (index)) | |
56 | ||
57 | struct sirfsoc_gpio_bank { | |
58 | struct of_mm_gpio_chip chip; | |
59 | struct irq_domain *domain; | |
60 | int id; | |
61 | int parent_irq; | |
62 | spinlock_t lock; | |
63 | }; | |
64 | ||
65 | static struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS]; | |
66 | static DEFINE_SPINLOCK(sgpio_lock); | |
67 | ||
393daa81 RY |
68 | /* |
69 | * pad list for the pinmux subsystem | |
70 | * refer to CS-131858-DC-6A.xls | |
71 | */ | |
25aec320 | 72 | static const struct pinctrl_pin_desc sirfsoc_pads[] = { |
8dd9766f BS |
73 | PINCTRL_PIN(0, "gpio0-0"), |
74 | PINCTRL_PIN(1, "gpio0-1"), | |
75 | PINCTRL_PIN(2, "gpio0-2"), | |
76 | PINCTRL_PIN(3, "gpio0-3"), | |
393daa81 RY |
77 | PINCTRL_PIN(4, "pwm0"), |
78 | PINCTRL_PIN(5, "pwm1"), | |
79 | PINCTRL_PIN(6, "pwm2"), | |
80 | PINCTRL_PIN(7, "pwm3"), | |
81 | PINCTRL_PIN(8, "warm_rst_b"), | |
82 | PINCTRL_PIN(9, "odo_0"), | |
83 | PINCTRL_PIN(10, "odo_1"), | |
84 | PINCTRL_PIN(11, "dr_dir"), | |
8dd9766f | 85 | PINCTRL_PIN(12, "viprom_fa"), |
393daa81 | 86 | PINCTRL_PIN(13, "scl_1"), |
8dd9766f | 87 | PINCTRL_PIN(14, "ntrst"), |
393daa81 RY |
88 | PINCTRL_PIN(15, "sda_1"), |
89 | PINCTRL_PIN(16, "x_ldd[16]"), | |
90 | PINCTRL_PIN(17, "x_ldd[17]"), | |
91 | PINCTRL_PIN(18, "x_ldd[18]"), | |
92 | PINCTRL_PIN(19, "x_ldd[19]"), | |
93 | PINCTRL_PIN(20, "x_ldd[20]"), | |
94 | PINCTRL_PIN(21, "x_ldd[21]"), | |
95 | PINCTRL_PIN(22, "x_ldd[22]"), | |
96 | PINCTRL_PIN(23, "x_ldd[23], lcdrom_frdy"), | |
97 | PINCTRL_PIN(24, "gps_sgn"), | |
98 | PINCTRL_PIN(25, "gps_mag"), | |
99 | PINCTRL_PIN(26, "gps_clk"), | |
100 | PINCTRL_PIN(27, "sd_cd_b_1"), | |
101 | PINCTRL_PIN(28, "sd_vcc_on_1"), | |
102 | PINCTRL_PIN(29, "sd_wp_b_1"), | |
103 | PINCTRL_PIN(30, "sd_clk_3"), | |
104 | PINCTRL_PIN(31, "sd_cmd_3"), | |
105 | ||
106 | PINCTRL_PIN(32, "x_sd_dat_3[0]"), | |
107 | PINCTRL_PIN(33, "x_sd_dat_3[1]"), | |
108 | PINCTRL_PIN(34, "x_sd_dat_3[2]"), | |
109 | PINCTRL_PIN(35, "x_sd_dat_3[3]"), | |
110 | PINCTRL_PIN(36, "x_sd_clk_4"), | |
111 | PINCTRL_PIN(37, "x_sd_cmd_4"), | |
112 | PINCTRL_PIN(38, "x_sd_dat_4[0]"), | |
113 | PINCTRL_PIN(39, "x_sd_dat_4[1]"), | |
114 | PINCTRL_PIN(40, "x_sd_dat_4[2]"), | |
115 | PINCTRL_PIN(41, "x_sd_dat_4[3]"), | |
116 | PINCTRL_PIN(42, "x_cko_1"), | |
117 | PINCTRL_PIN(43, "x_ac97_bit_clk"), | |
118 | PINCTRL_PIN(44, "x_ac97_dout"), | |
119 | PINCTRL_PIN(45, "x_ac97_din"), | |
120 | PINCTRL_PIN(46, "x_ac97_sync"), | |
121 | PINCTRL_PIN(47, "x_txd_1"), | |
122 | PINCTRL_PIN(48, "x_txd_2"), | |
123 | PINCTRL_PIN(49, "x_rxd_1"), | |
124 | PINCTRL_PIN(50, "x_rxd_2"), | |
125 | PINCTRL_PIN(51, "x_usclk_0"), | |
126 | PINCTRL_PIN(52, "x_utxd_0"), | |
127 | PINCTRL_PIN(53, "x_urxd_0"), | |
128 | PINCTRL_PIN(54, "x_utfs_0"), | |
129 | PINCTRL_PIN(55, "x_urfs_0"), | |
130 | PINCTRL_PIN(56, "x_usclk_1"), | |
131 | PINCTRL_PIN(57, "x_utxd_1"), | |
132 | PINCTRL_PIN(58, "x_urxd_1"), | |
133 | PINCTRL_PIN(59, "x_utfs_1"), | |
134 | PINCTRL_PIN(60, "x_urfs_1"), | |
135 | PINCTRL_PIN(61, "x_usclk_2"), | |
136 | PINCTRL_PIN(62, "x_utxd_2"), | |
137 | PINCTRL_PIN(63, "x_urxd_2"), | |
138 | ||
139 | PINCTRL_PIN(64, "x_utfs_2"), | |
140 | PINCTRL_PIN(65, "x_urfs_2"), | |
141 | PINCTRL_PIN(66, "x_df_we_b"), | |
142 | PINCTRL_PIN(67, "x_df_re_b"), | |
143 | PINCTRL_PIN(68, "x_txd_0"), | |
144 | PINCTRL_PIN(69, "x_rxd_0"), | |
145 | PINCTRL_PIN(78, "x_cko_0"), | |
146 | PINCTRL_PIN(79, "x_vip_pxd[7]"), | |
147 | PINCTRL_PIN(80, "x_vip_pxd[6]"), | |
148 | PINCTRL_PIN(81, "x_vip_pxd[5]"), | |
149 | PINCTRL_PIN(82, "x_vip_pxd[4]"), | |
150 | PINCTRL_PIN(83, "x_vip_pxd[3]"), | |
151 | PINCTRL_PIN(84, "x_vip_pxd[2]"), | |
152 | PINCTRL_PIN(85, "x_vip_pxd[1]"), | |
153 | PINCTRL_PIN(86, "x_vip_pxd[0]"), | |
154 | PINCTRL_PIN(87, "x_vip_vsync"), | |
155 | PINCTRL_PIN(88, "x_vip_hsync"), | |
156 | PINCTRL_PIN(89, "x_vip_pxclk"), | |
157 | PINCTRL_PIN(90, "x_sda_0"), | |
158 | PINCTRL_PIN(91, "x_scl_0"), | |
159 | PINCTRL_PIN(92, "x_df_ry_by"), | |
160 | PINCTRL_PIN(93, "x_df_cs_b[1]"), | |
161 | PINCTRL_PIN(94, "x_df_cs_b[0]"), | |
162 | PINCTRL_PIN(95, "x_l_pclk"), | |
163 | ||
164 | PINCTRL_PIN(96, "x_l_lck"), | |
165 | PINCTRL_PIN(97, "x_l_fck"), | |
166 | PINCTRL_PIN(98, "x_l_de"), | |
167 | PINCTRL_PIN(99, "x_ldd[0]"), | |
168 | PINCTRL_PIN(100, "x_ldd[1]"), | |
169 | PINCTRL_PIN(101, "x_ldd[2]"), | |
170 | PINCTRL_PIN(102, "x_ldd[3]"), | |
171 | PINCTRL_PIN(103, "x_ldd[4]"), | |
172 | PINCTRL_PIN(104, "x_ldd[5]"), | |
173 | PINCTRL_PIN(105, "x_ldd[6]"), | |
174 | PINCTRL_PIN(106, "x_ldd[7]"), | |
175 | PINCTRL_PIN(107, "x_ldd[8]"), | |
176 | PINCTRL_PIN(108, "x_ldd[9]"), | |
177 | PINCTRL_PIN(109, "x_ldd[10]"), | |
178 | PINCTRL_PIN(110, "x_ldd[11]"), | |
179 | PINCTRL_PIN(111, "x_ldd[12]"), | |
180 | PINCTRL_PIN(112, "x_ldd[13]"), | |
181 | PINCTRL_PIN(113, "x_ldd[14]"), | |
182 | PINCTRL_PIN(114, "x_ldd[15]"), | |
183 | }; | |
184 | ||
185 | /** | |
186 | * @dev: a pointer back to containing device | |
187 | * @virtbase: the offset to the controller in virtual memory | |
188 | */ | |
189 | struct sirfsoc_pmx { | |
190 | struct device *dev; | |
191 | struct pinctrl_dev *pmx; | |
192 | void __iomem *gpio_virtbase; | |
193 | void __iomem *rsc_virtbase; | |
194 | }; | |
195 | ||
196 | /* SIRFSOC_GPIO_PAD_EN set */ | |
197 | struct sirfsoc_muxmask { | |
198 | unsigned long group; | |
199 | unsigned long mask; | |
200 | }; | |
201 | ||
202 | struct sirfsoc_padmux { | |
203 | unsigned long muxmask_counts; | |
204 | const struct sirfsoc_muxmask *muxmask; | |
205 | /* RSC_PIN_MUX set */ | |
206 | unsigned long funcmask; | |
207 | unsigned long funcval; | |
208 | }; | |
209 | ||
210 | /** | |
211 | * struct sirfsoc_pin_group - describes a SiRFprimaII pin group | |
212 | * @name: the name of this specific pin group | |
213 | * @pins: an array of discrete physical pins used in this group, taken | |
214 | * from the driver-local pin enumeration space | |
215 | * @num_pins: the number of pins in this group array, i.e. the number of | |
216 | * elements in .pins so we can iterate over that array | |
217 | */ | |
218 | struct sirfsoc_pin_group { | |
219 | const char *name; | |
220 | const unsigned int *pins; | |
221 | const unsigned num_pins; | |
222 | }; | |
223 | ||
224 | static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = { | |
225 | { | |
226 | .group = 3, | |
227 | .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | | |
228 | BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) | | |
229 | BIT(17) | BIT(18), | |
230 | }, { | |
231 | .group = 2, | |
232 | .mask = BIT(31), | |
233 | }, | |
234 | }; | |
235 | ||
236 | static const struct sirfsoc_padmux lcd_16bits_padmux = { | |
237 | .muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask), | |
238 | .muxmask = lcd_16bits_sirfsoc_muxmask, | |
239 | .funcmask = BIT(4), | |
240 | .funcval = 0, | |
241 | }; | |
242 | ||
243 | static const unsigned lcd_16bits_pins[] = { 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, | |
244 | 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 }; | |
245 | ||
246 | static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = { | |
247 | { | |
248 | .group = 3, | |
249 | .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | | |
250 | BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) | | |
251 | BIT(17) | BIT(18), | |
252 | }, { | |
253 | .group = 2, | |
254 | .mask = BIT(31), | |
255 | }, { | |
256 | .group = 0, | |
257 | .mask = BIT(16) | BIT(17), | |
258 | }, | |
259 | }; | |
260 | ||
261 | static const struct sirfsoc_padmux lcd_18bits_padmux = { | |
262 | .muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask), | |
263 | .muxmask = lcd_18bits_muxmask, | |
264 | .funcmask = BIT(4), | |
265 | .funcval = 0, | |
266 | }; | |
267 | ||
268 | static const unsigned lcd_18bits_pins[] = { 16, 17, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, | |
269 | 105, 106, 107, 108, 109, 110, 111, 112, 113, 114}; | |
270 | ||
271 | static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = { | |
272 | { | |
273 | .group = 3, | |
274 | .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | | |
275 | BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) | | |
276 | BIT(17) | BIT(18), | |
277 | }, { | |
278 | .group = 2, | |
279 | .mask = BIT(31), | |
280 | }, { | |
281 | .group = 0, | |
282 | .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23), | |
283 | }, | |
284 | }; | |
285 | ||
286 | static const struct sirfsoc_padmux lcd_24bits_padmux = { | |
287 | .muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask), | |
288 | .muxmask = lcd_24bits_muxmask, | |
289 | .funcmask = BIT(4), | |
290 | .funcval = 0, | |
291 | }; | |
292 | ||
293 | static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, | |
294 | 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 }; | |
295 | ||
296 | static const struct sirfsoc_muxmask lcdrom_muxmask[] = { | |
297 | { | |
298 | .group = 3, | |
299 | .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | | |
300 | BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) | | |
301 | BIT(17) | BIT(18), | |
302 | }, { | |
303 | .group = 2, | |
304 | .mask = BIT(31), | |
305 | }, { | |
306 | .group = 0, | |
307 | .mask = BIT(23), | |
308 | }, | |
309 | }; | |
310 | ||
311 | static const struct sirfsoc_padmux lcdrom_padmux = { | |
312 | .muxmask_counts = ARRAY_SIZE(lcdrom_muxmask), | |
313 | .muxmask = lcdrom_muxmask, | |
314 | .funcmask = BIT(4), | |
315 | .funcval = BIT(4), | |
316 | }; | |
317 | ||
318 | static const unsigned lcdrom_pins[] = { 23, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, | |
319 | 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 }; | |
320 | ||
321 | static const struct sirfsoc_muxmask uart0_muxmask[] = { | |
322 | { | |
323 | .group = 2, | |
324 | .mask = BIT(4) | BIT(5), | |
325 | }, { | |
326 | .group = 1, | |
327 | .mask = BIT(23) | BIT(28), | |
328 | }, | |
329 | }; | |
330 | ||
331 | static const struct sirfsoc_padmux uart0_padmux = { | |
332 | .muxmask_counts = ARRAY_SIZE(uart0_muxmask), | |
333 | .muxmask = uart0_muxmask, | |
334 | .funcmask = BIT(9), | |
335 | .funcval = BIT(9), | |
336 | }; | |
337 | ||
338 | static const unsigned uart0_pins[] = { 55, 60, 68, 69 }; | |
339 | ||
340 | static const struct sirfsoc_muxmask uart0_nostreamctrl_muxmask[] = { | |
341 | { | |
342 | .group = 2, | |
343 | .mask = BIT(4) | BIT(5), | |
344 | }, | |
345 | }; | |
346 | ||
347 | static const struct sirfsoc_padmux uart0_nostreamctrl_padmux = { | |
348 | .muxmask_counts = ARRAY_SIZE(uart0_nostreamctrl_muxmask), | |
349 | .muxmask = uart0_nostreamctrl_muxmask, | |
350 | }; | |
351 | ||
352 | static const unsigned uart0_nostreamctrl_pins[] = { 68, 39 }; | |
353 | ||
354 | static const struct sirfsoc_muxmask uart1_muxmask[] = { | |
355 | { | |
356 | .group = 1, | |
357 | .mask = BIT(15) | BIT(17), | |
358 | }, | |
359 | }; | |
360 | ||
361 | static const struct sirfsoc_padmux uart1_padmux = { | |
362 | .muxmask_counts = ARRAY_SIZE(uart1_muxmask), | |
363 | .muxmask = uart1_muxmask, | |
364 | }; | |
365 | ||
366 | static const unsigned uart1_pins[] = { 47, 49 }; | |
367 | ||
368 | static const struct sirfsoc_muxmask uart2_muxmask[] = { | |
369 | { | |
370 | .group = 1, | |
371 | .mask = BIT(16) | BIT(18) | BIT(24) | BIT(27), | |
372 | }, | |
373 | }; | |
374 | ||
375 | static const struct sirfsoc_padmux uart2_padmux = { | |
376 | .muxmask_counts = ARRAY_SIZE(uart2_muxmask), | |
377 | .muxmask = uart2_muxmask, | |
378 | .funcmask = BIT(10), | |
379 | .funcval = BIT(10), | |
380 | }; | |
381 | ||
382 | static const unsigned uart2_pins[] = { 48, 50, 56, 59 }; | |
383 | ||
384 | static const struct sirfsoc_muxmask uart2_nostreamctrl_muxmask[] = { | |
385 | { | |
386 | .group = 1, | |
387 | .mask = BIT(16) | BIT(18), | |
388 | }, | |
389 | }; | |
390 | ||
391 | static const struct sirfsoc_padmux uart2_nostreamctrl_padmux = { | |
392 | .muxmask_counts = ARRAY_SIZE(uart2_nostreamctrl_muxmask), | |
393 | .muxmask = uart2_nostreamctrl_muxmask, | |
394 | }; | |
395 | ||
396 | static const unsigned uart2_nostreamctrl_pins[] = { 48, 50 }; | |
397 | ||
398 | static const struct sirfsoc_muxmask sdmmc3_muxmask[] = { | |
399 | { | |
400 | .group = 0, | |
401 | .mask = BIT(30) | BIT(31), | |
402 | }, { | |
403 | .group = 1, | |
404 | .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3), | |
405 | }, | |
406 | }; | |
407 | ||
408 | static const struct sirfsoc_padmux sdmmc3_padmux = { | |
409 | .muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask), | |
410 | .muxmask = sdmmc3_muxmask, | |
411 | .funcmask = BIT(7), | |
412 | .funcval = 0, | |
413 | }; | |
414 | ||
415 | static const unsigned sdmmc3_pins[] = { 30, 31, 32, 33, 34, 35 }; | |
416 | ||
417 | static const struct sirfsoc_muxmask spi0_muxmask[] = { | |
418 | { | |
419 | .group = 1, | |
420 | .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3), | |
421 | }, | |
422 | }; | |
423 | ||
424 | static const struct sirfsoc_padmux spi0_padmux = { | |
425 | .muxmask_counts = ARRAY_SIZE(spi0_muxmask), | |
426 | .muxmask = spi0_muxmask, | |
427 | .funcmask = BIT(7), | |
428 | .funcval = BIT(7), | |
429 | }; | |
430 | ||
431 | static const unsigned spi0_pins[] = { 32, 33, 34, 35 }; | |
432 | ||
433 | static const struct sirfsoc_muxmask sdmmc4_muxmask[] = { | |
434 | { | |
435 | .group = 1, | |
436 | .mask = BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9), | |
437 | }, | |
438 | }; | |
439 | ||
440 | static const struct sirfsoc_padmux sdmmc4_padmux = { | |
441 | .muxmask_counts = ARRAY_SIZE(sdmmc4_muxmask), | |
442 | .muxmask = sdmmc4_muxmask, | |
443 | }; | |
444 | ||
445 | static const unsigned sdmmc4_pins[] = { 36, 37, 38, 39, 40, 41 }; | |
446 | ||
447 | static const struct sirfsoc_muxmask cko1_muxmask[] = { | |
448 | { | |
449 | .group = 1, | |
450 | .mask = BIT(10), | |
451 | }, | |
452 | }; | |
453 | ||
454 | static const struct sirfsoc_padmux cko1_padmux = { | |
455 | .muxmask_counts = ARRAY_SIZE(cko1_muxmask), | |
456 | .muxmask = cko1_muxmask, | |
457 | .funcmask = BIT(3), | |
458 | .funcval = 0, | |
459 | }; | |
460 | ||
461 | static const unsigned cko1_pins[] = { 42 }; | |
462 | ||
463 | static const struct sirfsoc_muxmask i2s_muxmask[] = { | |
464 | { | |
465 | .group = 1, | |
466 | .mask = | |
467 | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(19) | |
468 | | BIT(23) | BIT(28), | |
469 | }, | |
470 | }; | |
471 | ||
472 | static const struct sirfsoc_padmux i2s_padmux = { | |
473 | .muxmask_counts = ARRAY_SIZE(i2s_muxmask), | |
474 | .muxmask = i2s_muxmask, | |
475 | .funcmask = BIT(3) | BIT(9), | |
476 | .funcval = BIT(3), | |
477 | }; | |
478 | ||
479 | static const unsigned i2s_pins[] = { 42, 43, 44, 45, 46, 51, 55, 60 }; | |
480 | ||
481 | static const struct sirfsoc_muxmask ac97_muxmask[] = { | |
482 | { | |
483 | .group = 1, | |
484 | .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14), | |
485 | }, | |
486 | }; | |
487 | ||
488 | static const struct sirfsoc_padmux ac97_padmux = { | |
489 | .muxmask_counts = ARRAY_SIZE(ac97_muxmask), | |
490 | .muxmask = ac97_muxmask, | |
491 | .funcmask = BIT(8), | |
492 | .funcval = 0, | |
493 | }; | |
494 | ||
495 | static const unsigned ac97_pins[] = { 33, 34, 35, 36 }; | |
496 | ||
497 | static const struct sirfsoc_muxmask spi1_muxmask[] = { | |
498 | { | |
499 | .group = 1, | |
500 | .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14), | |
501 | }, | |
502 | }; | |
503 | ||
504 | static const struct sirfsoc_padmux spi1_padmux = { | |
505 | .muxmask_counts = ARRAY_SIZE(spi1_muxmask), | |
506 | .muxmask = spi1_muxmask, | |
507 | .funcmask = BIT(8), | |
508 | .funcval = BIT(8), | |
509 | }; | |
510 | ||
f59d28dc | 511 | static const unsigned spi1_pins[] = { 43, 44, 45, 46 }; |
393daa81 RY |
512 | |
513 | static const struct sirfsoc_muxmask sdmmc1_muxmask[] = { | |
514 | { | |
515 | .group = 0, | |
516 | .mask = BIT(27) | BIT(28) | BIT(29), | |
517 | }, | |
518 | }; | |
519 | ||
520 | static const struct sirfsoc_padmux sdmmc1_padmux = { | |
521 | .muxmask_counts = ARRAY_SIZE(sdmmc1_muxmask), | |
522 | .muxmask = sdmmc1_muxmask, | |
523 | }; | |
524 | ||
525 | static const unsigned sdmmc1_pins[] = { 27, 28, 29 }; | |
526 | ||
527 | static const struct sirfsoc_muxmask gps_muxmask[] = { | |
528 | { | |
529 | .group = 0, | |
530 | .mask = BIT(24) | BIT(25) | BIT(26), | |
531 | }, | |
532 | }; | |
533 | ||
534 | static const struct sirfsoc_padmux gps_padmux = { | |
535 | .muxmask_counts = ARRAY_SIZE(gps_muxmask), | |
536 | .muxmask = gps_muxmask, | |
537 | .funcmask = BIT(12) | BIT(13) | BIT(14), | |
538 | .funcval = BIT(12), | |
539 | }; | |
540 | ||
541 | static const unsigned gps_pins[] = { 24, 25, 26 }; | |
542 | ||
543 | static const struct sirfsoc_muxmask sdmmc5_muxmask[] = { | |
544 | { | |
545 | .group = 0, | |
546 | .mask = BIT(24) | BIT(25) | BIT(26), | |
547 | }, { | |
548 | .group = 1, | |
549 | .mask = BIT(29), | |
550 | }, { | |
551 | .group = 2, | |
552 | .mask = BIT(0) | BIT(1), | |
553 | }, | |
554 | }; | |
555 | ||
556 | static const struct sirfsoc_padmux sdmmc5_padmux = { | |
557 | .muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask), | |
558 | .muxmask = sdmmc5_muxmask, | |
559 | .funcmask = BIT(13) | BIT(14), | |
560 | .funcval = BIT(13) | BIT(14), | |
561 | }; | |
562 | ||
563 | static const unsigned sdmmc5_pins[] = { 24, 25, 26, 61, 64, 65 }; | |
564 | ||
565 | static const struct sirfsoc_muxmask usp0_muxmask[] = { | |
566 | { | |
567 | .group = 1, | |
568 | .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23), | |
569 | }, | |
570 | }; | |
571 | ||
572 | static const struct sirfsoc_padmux usp0_padmux = { | |
573 | .muxmask_counts = ARRAY_SIZE(usp0_muxmask), | |
574 | .muxmask = usp0_muxmask, | |
575 | .funcmask = BIT(1) | BIT(2) | BIT(6) | BIT(9), | |
576 | .funcval = 0, | |
577 | }; | |
578 | ||
579 | static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 }; | |
580 | ||
581 | static const struct sirfsoc_muxmask usp1_muxmask[] = { | |
582 | { | |
583 | .group = 1, | |
584 | .mask = BIT(24) | BIT(25) | BIT(26) | BIT(27) | BIT(28), | |
585 | }, | |
586 | }; | |
587 | ||
588 | static const struct sirfsoc_padmux usp1_padmux = { | |
589 | .muxmask_counts = ARRAY_SIZE(usp1_muxmask), | |
590 | .muxmask = usp1_muxmask, | |
591 | .funcmask = BIT(1) | BIT(9) | BIT(10) | BIT(11), | |
592 | .funcval = 0, | |
593 | }; | |
594 | ||
595 | static const unsigned usp1_pins[] = { 56, 57, 58, 59, 60 }; | |
596 | ||
597 | static const struct sirfsoc_muxmask usp2_muxmask[] = { | |
598 | { | |
599 | .group = 1, | |
600 | .mask = BIT(29) | BIT(30) | BIT(31), | |
601 | }, { | |
602 | .group = 2, | |
603 | .mask = BIT(0) | BIT(1), | |
604 | }, | |
605 | }; | |
606 | ||
607 | static const struct sirfsoc_padmux usp2_padmux = { | |
608 | .muxmask_counts = ARRAY_SIZE(usp2_muxmask), | |
609 | .muxmask = usp2_muxmask, | |
610 | .funcmask = BIT(13) | BIT(14), | |
611 | .funcval = 0, | |
612 | }; | |
613 | ||
614 | static const unsigned usp2_pins[] = { 61, 62, 63, 64, 65 }; | |
615 | ||
616 | static const struct sirfsoc_muxmask nand_muxmask[] = { | |
617 | { | |
618 | .group = 2, | |
619 | .mask = BIT(2) | BIT(3) | BIT(28) | BIT(29) | BIT(30), | |
620 | }, | |
621 | }; | |
622 | ||
623 | static const struct sirfsoc_padmux nand_padmux = { | |
624 | .muxmask_counts = ARRAY_SIZE(nand_muxmask), | |
625 | .muxmask = nand_muxmask, | |
626 | .funcmask = BIT(5), | |
627 | .funcval = 0, | |
628 | }; | |
629 | ||
630 | static const unsigned nand_pins[] = { 64, 65, 92, 93, 94 }; | |
631 | ||
632 | static const struct sirfsoc_padmux sdmmc0_padmux = { | |
633 | .muxmask_counts = 0, | |
634 | .funcmask = BIT(5), | |
635 | .funcval = 0, | |
636 | }; | |
637 | ||
638 | static const unsigned sdmmc0_pins[] = { }; | |
639 | ||
640 | static const struct sirfsoc_muxmask sdmmc2_muxmask[] = { | |
641 | { | |
642 | .group = 2, | |
643 | .mask = BIT(2) | BIT(3), | |
644 | }, | |
645 | }; | |
646 | ||
647 | static const struct sirfsoc_padmux sdmmc2_padmux = { | |
648 | .muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask), | |
649 | .muxmask = sdmmc2_muxmask, | |
650 | .funcmask = BIT(5), | |
651 | .funcval = BIT(5), | |
652 | }; | |
653 | ||
654 | static const unsigned sdmmc2_pins[] = { 66, 67 }; | |
655 | ||
656 | static const struct sirfsoc_muxmask cko0_muxmask[] = { | |
657 | { | |
658 | .group = 2, | |
659 | .mask = BIT(14), | |
660 | }, | |
661 | }; | |
662 | ||
663 | static const struct sirfsoc_padmux cko0_padmux = { | |
664 | .muxmask_counts = ARRAY_SIZE(cko0_muxmask), | |
665 | .muxmask = cko0_muxmask, | |
666 | }; | |
667 | ||
668 | static const unsigned cko0_pins[] = { 78 }; | |
669 | ||
670 | static const struct sirfsoc_muxmask vip_muxmask[] = { | |
671 | { | |
672 | .group = 2, | |
673 | .mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) | |
674 | | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) | | |
675 | BIT(25), | |
676 | }, | |
677 | }; | |
678 | ||
679 | static const struct sirfsoc_padmux vip_padmux = { | |
680 | .muxmask_counts = ARRAY_SIZE(vip_muxmask), | |
681 | .muxmask = vip_muxmask, | |
682 | .funcmask = BIT(0), | |
683 | .funcval = 0, | |
684 | }; | |
685 | ||
686 | static const unsigned vip_pins[] = { 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89 }; | |
687 | ||
688 | static const struct sirfsoc_muxmask i2c0_muxmask[] = { | |
689 | { | |
690 | .group = 2, | |
691 | .mask = BIT(26) | BIT(27), | |
692 | }, | |
693 | }; | |
694 | ||
695 | static const struct sirfsoc_padmux i2c0_padmux = { | |
696 | .muxmask_counts = ARRAY_SIZE(i2c0_muxmask), | |
697 | .muxmask = i2c0_muxmask, | |
698 | }; | |
699 | ||
700 | static const unsigned i2c0_pins[] = { 90, 91 }; | |
701 | ||
702 | static const struct sirfsoc_muxmask i2c1_muxmask[] = { | |
703 | { | |
704 | .group = 0, | |
705 | .mask = BIT(13) | BIT(15), | |
706 | }, | |
707 | }; | |
708 | ||
709 | static const struct sirfsoc_padmux i2c1_padmux = { | |
710 | .muxmask_counts = ARRAY_SIZE(i2c1_muxmask), | |
711 | .muxmask = i2c1_muxmask, | |
712 | }; | |
713 | ||
714 | static const unsigned i2c1_pins[] = { 13, 15 }; | |
715 | ||
716 | static const struct sirfsoc_muxmask viprom_muxmask[] = { | |
717 | { | |
718 | .group = 2, | |
719 | .mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) | |
720 | | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) | | |
721 | BIT(25), | |
722 | }, { | |
723 | .group = 0, | |
724 | .mask = BIT(12), | |
725 | }, | |
726 | }; | |
727 | ||
728 | static const struct sirfsoc_padmux viprom_padmux = { | |
729 | .muxmask_counts = ARRAY_SIZE(viprom_muxmask), | |
730 | .muxmask = viprom_muxmask, | |
731 | .funcmask = BIT(0), | |
732 | .funcval = BIT(0), | |
733 | }; | |
734 | ||
735 | static const unsigned viprom_pins[] = { 12, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89 }; | |
736 | ||
737 | static const struct sirfsoc_muxmask pwm0_muxmask[] = { | |
738 | { | |
739 | .group = 0, | |
740 | .mask = BIT(4), | |
741 | }, | |
742 | }; | |
743 | ||
744 | static const struct sirfsoc_padmux pwm0_padmux = { | |
745 | .muxmask_counts = ARRAY_SIZE(pwm0_muxmask), | |
746 | .muxmask = pwm0_muxmask, | |
747 | .funcmask = BIT(12), | |
748 | .funcval = 0, | |
749 | }; | |
750 | ||
751 | static const unsigned pwm0_pins[] = { 4 }; | |
752 | ||
753 | static const struct sirfsoc_muxmask pwm1_muxmask[] = { | |
754 | { | |
755 | .group = 0, | |
756 | .mask = BIT(5), | |
757 | }, | |
758 | }; | |
759 | ||
760 | static const struct sirfsoc_padmux pwm1_padmux = { | |
761 | .muxmask_counts = ARRAY_SIZE(pwm1_muxmask), | |
762 | .muxmask = pwm1_muxmask, | |
763 | }; | |
764 | ||
765 | static const unsigned pwm1_pins[] = { 5 }; | |
766 | ||
767 | static const struct sirfsoc_muxmask pwm2_muxmask[] = { | |
768 | { | |
769 | .group = 0, | |
770 | .mask = BIT(6), | |
771 | }, | |
772 | }; | |
773 | ||
774 | static const struct sirfsoc_padmux pwm2_padmux = { | |
775 | .muxmask_counts = ARRAY_SIZE(pwm2_muxmask), | |
776 | .muxmask = pwm2_muxmask, | |
777 | }; | |
778 | ||
779 | static const unsigned pwm2_pins[] = { 6 }; | |
780 | ||
781 | static const struct sirfsoc_muxmask pwm3_muxmask[] = { | |
782 | { | |
783 | .group = 0, | |
784 | .mask = BIT(7), | |
785 | }, | |
786 | }; | |
787 | ||
788 | static const struct sirfsoc_padmux pwm3_padmux = { | |
789 | .muxmask_counts = ARRAY_SIZE(pwm3_muxmask), | |
790 | .muxmask = pwm3_muxmask, | |
791 | }; | |
792 | ||
793 | static const unsigned pwm3_pins[] = { 7 }; | |
794 | ||
795 | static const struct sirfsoc_muxmask warm_rst_muxmask[] = { | |
796 | { | |
797 | .group = 0, | |
798 | .mask = BIT(8), | |
799 | }, | |
800 | }; | |
801 | ||
802 | static const struct sirfsoc_padmux warm_rst_padmux = { | |
803 | .muxmask_counts = ARRAY_SIZE(warm_rst_muxmask), | |
804 | .muxmask = warm_rst_muxmask, | |
805 | }; | |
806 | ||
807 | static const unsigned warm_rst_pins[] = { 8 }; | |
808 | ||
809 | static const struct sirfsoc_muxmask usb0_utmi_drvbus_muxmask[] = { | |
810 | { | |
811 | .group = 1, | |
812 | .mask = BIT(22), | |
813 | }, | |
814 | }; | |
815 | static const struct sirfsoc_padmux usb0_utmi_drvbus_padmux = { | |
816 | .muxmask_counts = ARRAY_SIZE(usb0_utmi_drvbus_muxmask), | |
817 | .muxmask = usb0_utmi_drvbus_muxmask, | |
818 | .funcmask = BIT(6), | |
819 | .funcval = BIT(6), /* refer to PAD_UTMI_DRVVBUS0_ENABLE */ | |
820 | }; | |
821 | ||
822 | static const unsigned usb0_utmi_drvbus_pins[] = { 54 }; | |
823 | ||
824 | static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = { | |
825 | { | |
826 | .group = 1, | |
827 | .mask = BIT(27), | |
828 | }, | |
829 | }; | |
830 | ||
831 | static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = { | |
832 | .muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask), | |
833 | .muxmask = usb1_utmi_drvbus_muxmask, | |
834 | .funcmask = BIT(11), | |
835 | .funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */ | |
836 | }; | |
837 | ||
838 | static const unsigned usb1_utmi_drvbus_pins[] = { 59 }; | |
839 | ||
840 | static const struct sirfsoc_muxmask pulse_count_muxmask[] = { | |
841 | { | |
842 | .group = 0, | |
843 | .mask = BIT(9) | BIT(10) | BIT(11), | |
844 | }, | |
845 | }; | |
846 | ||
847 | static const struct sirfsoc_padmux pulse_count_padmux = { | |
848 | .muxmask_counts = ARRAY_SIZE(pulse_count_muxmask), | |
849 | .muxmask = pulse_count_muxmask, | |
850 | }; | |
851 | ||
852 | static const unsigned pulse_count_pins[] = { 9, 10, 11 }; | |
853 | ||
854 | #define SIRFSOC_PIN_GROUP(n, p) \ | |
855 | { \ | |
856 | .name = n, \ | |
857 | .pins = p, \ | |
858 | .num_pins = ARRAY_SIZE(p), \ | |
859 | } | |
860 | ||
861 | static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = { | |
862 | SIRFSOC_PIN_GROUP("lcd_16bitsgrp", lcd_16bits_pins), | |
863 | SIRFSOC_PIN_GROUP("lcd_18bitsgrp", lcd_18bits_pins), | |
864 | SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins), | |
865 | SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins), | |
866 | SIRFSOC_PIN_GROUP("uart0grp", uart0_pins), | |
867 | SIRFSOC_PIN_GROUP("uart1grp", uart1_pins), | |
868 | SIRFSOC_PIN_GROUP("uart2grp", uart2_pins), | |
869 | SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins), | |
870 | SIRFSOC_PIN_GROUP("usp0grp", usp0_pins), | |
871 | SIRFSOC_PIN_GROUP("usp1grp", usp1_pins), | |
872 | SIRFSOC_PIN_GROUP("usp2grp", usp2_pins), | |
873 | SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins), | |
874 | SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins), | |
875 | SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins), | |
876 | SIRFSOC_PIN_GROUP("pwm1grp", pwm1_pins), | |
877 | SIRFSOC_PIN_GROUP("pwm2grp", pwm2_pins), | |
878 | SIRFSOC_PIN_GROUP("pwm3grp", pwm3_pins), | |
879 | SIRFSOC_PIN_GROUP("vipgrp", vip_pins), | |
880 | SIRFSOC_PIN_GROUP("vipromgrp", viprom_pins), | |
881 | SIRFSOC_PIN_GROUP("warm_rstgrp", warm_rst_pins), | |
882 | SIRFSOC_PIN_GROUP("cko0_rstgrp", cko0_pins), | |
883 | SIRFSOC_PIN_GROUP("cko1_rstgrp", cko1_pins), | |
884 | SIRFSOC_PIN_GROUP("sdmmc0grp", sdmmc0_pins), | |
885 | SIRFSOC_PIN_GROUP("sdmmc1grp", sdmmc1_pins), | |
886 | SIRFSOC_PIN_GROUP("sdmmc2grp", sdmmc2_pins), | |
887 | SIRFSOC_PIN_GROUP("sdmmc3grp", sdmmc3_pins), | |
888 | SIRFSOC_PIN_GROUP("sdmmc4grp", sdmmc4_pins), | |
889 | SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins), | |
890 | SIRFSOC_PIN_GROUP("usb0_utmi_drvbusgrp", usb0_utmi_drvbus_pins), | |
891 | SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins), | |
892 | SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins), | |
893 | SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins), | |
894 | SIRFSOC_PIN_GROUP("ac97grp", ac97_pins), | |
895 | SIRFSOC_PIN_GROUP("nandgrp", nand_pins), | |
896 | SIRFSOC_PIN_GROUP("spi0grp", spi0_pins), | |
897 | SIRFSOC_PIN_GROUP("spi1grp", spi1_pins), | |
898 | SIRFSOC_PIN_GROUP("gpsgrp", gps_pins), | |
899 | }; | |
900 | ||
d1e90e9e | 901 | static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev) |
393daa81 | 902 | { |
d1e90e9e | 903 | return ARRAY_SIZE(sirfsoc_pin_groups); |
393daa81 RY |
904 | } |
905 | ||
906 | static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev, | |
907 | unsigned selector) | |
908 | { | |
393daa81 RY |
909 | return sirfsoc_pin_groups[selector].name; |
910 | } | |
911 | ||
912 | static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, | |
a5818a8b | 913 | const unsigned **pins, |
ad7761ab | 914 | unsigned *num_pins) |
393daa81 | 915 | { |
a5818a8b | 916 | *pins = sirfsoc_pin_groups[selector].pins; |
393daa81 RY |
917 | *num_pins = sirfsoc_pin_groups[selector].num_pins; |
918 | return 0; | |
919 | } | |
920 | ||
921 | static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, | |
922 | unsigned offset) | |
923 | { | |
924 | seq_printf(s, " " DRIVER_NAME); | |
925 | } | |
926 | ||
056876f6 BS |
927 | static int sirfsoc_dt_node_to_map(struct pinctrl_dev *pctldev, |
928 | struct device_node *np_config, | |
929 | struct pinctrl_map **map, unsigned *num_maps) | |
930 | { | |
931 | struct sirfsoc_pmx *spmx = pinctrl_dev_get_drvdata(pctldev); | |
932 | struct device_node *np; | |
933 | struct property *prop; | |
934 | const char *function, *group; | |
935 | int ret, index = 0, count = 0; | |
936 | ||
937 | /* calculate number of maps required */ | |
938 | for_each_child_of_node(np_config, np) { | |
939 | ret = of_property_read_string(np, "sirf,function", &function); | |
940 | if (ret < 0) | |
941 | return ret; | |
942 | ||
943 | ret = of_property_count_strings(np, "sirf,pins"); | |
944 | if (ret < 0) | |
945 | return ret; | |
946 | ||
947 | count += ret; | |
948 | } | |
949 | ||
950 | if (!count) { | |
951 | dev_err(spmx->dev, "No child nodes passed via DT\n"); | |
952 | return -ENODEV; | |
953 | } | |
954 | ||
955 | *map = kzalloc(sizeof(**map) * count, GFP_KERNEL); | |
956 | if (!*map) | |
957 | return -ENOMEM; | |
958 | ||
959 | for_each_child_of_node(np_config, np) { | |
960 | of_property_read_string(np, "sirf,function", &function); | |
961 | of_property_for_each_string(np, "sirf,pins", prop, group) { | |
962 | (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP; | |
963 | (*map)[index].data.mux.group = group; | |
964 | (*map)[index].data.mux.function = function; | |
965 | index++; | |
966 | } | |
967 | } | |
968 | ||
969 | *num_maps = count; | |
970 | ||
971 | return 0; | |
972 | } | |
973 | ||
974 | static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev, | |
975 | struct pinctrl_map *map, unsigned num_maps) | |
976 | { | |
977 | kfree(map); | |
978 | } | |
979 | ||
393daa81 | 980 | static struct pinctrl_ops sirfsoc_pctrl_ops = { |
d1e90e9e | 981 | .get_groups_count = sirfsoc_get_groups_count, |
393daa81 RY |
982 | .get_group_name = sirfsoc_get_group_name, |
983 | .get_group_pins = sirfsoc_get_group_pins, | |
984 | .pin_dbg_show = sirfsoc_pin_dbg_show, | |
056876f6 BS |
985 | .dt_node_to_map = sirfsoc_dt_node_to_map, |
986 | .dt_free_map = sirfsoc_dt_free_map, | |
393daa81 RY |
987 | }; |
988 | ||
989 | struct sirfsoc_pmx_func { | |
990 | const char *name; | |
991 | const char * const *groups; | |
992 | const unsigned num_groups; | |
993 | const struct sirfsoc_padmux *padmux; | |
994 | }; | |
995 | ||
996 | static const char * const lcd_16bitsgrp[] = { "lcd_16bitsgrp" }; | |
997 | static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" }; | |
998 | static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" }; | |
999 | static const char * const lcdromgrp[] = { "lcdromgrp" }; | |
1000 | static const char * const uart0grp[] = { "uart0grp" }; | |
1001 | static const char * const uart1grp[] = { "uart1grp" }; | |
1002 | static const char * const uart2grp[] = { "uart2grp" }; | |
1003 | static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" }; | |
1004 | static const char * const usp0grp[] = { "usp0grp" }; | |
1005 | static const char * const usp1grp[] = { "usp1grp" }; | |
1006 | static const char * const usp2grp[] = { "usp2grp" }; | |
1007 | static const char * const i2c0grp[] = { "i2c0grp" }; | |
1008 | static const char * const i2c1grp[] = { "i2c1grp" }; | |
1009 | static const char * const pwm0grp[] = { "pwm0grp" }; | |
1010 | static const char * const pwm1grp[] = { "pwm1grp" }; | |
1011 | static const char * const pwm2grp[] = { "pwm2grp" }; | |
1012 | static const char * const pwm3grp[] = { "pwm3grp" }; | |
1013 | static const char * const vipgrp[] = { "vipgrp" }; | |
1014 | static const char * const vipromgrp[] = { "vipromgrp" }; | |
1015 | static const char * const warm_rstgrp[] = { "warm_rstgrp" }; | |
1016 | static const char * const cko0grp[] = { "cko0grp" }; | |
1017 | static const char * const cko1grp[] = { "cko1grp" }; | |
1018 | static const char * const sdmmc0grp[] = { "sdmmc0grp" }; | |
1019 | static const char * const sdmmc1grp[] = { "sdmmc1grp" }; | |
1020 | static const char * const sdmmc2grp[] = { "sdmmc2grp" }; | |
1021 | static const char * const sdmmc3grp[] = { "sdmmc3grp" }; | |
1022 | static const char * const sdmmc4grp[] = { "sdmmc4grp" }; | |
1023 | static const char * const sdmmc5grp[] = { "sdmmc5grp" }; | |
1024 | static const char * const usb0_utmi_drvbusgrp[] = { "usb0_utmi_drvbusgrp" }; | |
1025 | static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" }; | |
1026 | static const char * const pulse_countgrp[] = { "pulse_countgrp" }; | |
1027 | static const char * const i2sgrp[] = { "i2sgrp" }; | |
1028 | static const char * const ac97grp[] = { "ac97grp" }; | |
1029 | static const char * const nandgrp[] = { "nandgrp" }; | |
1030 | static const char * const spi0grp[] = { "spi0grp" }; | |
1031 | static const char * const spi1grp[] = { "spi1grp" }; | |
1032 | static const char * const gpsgrp[] = { "gpsgrp" }; | |
1033 | ||
1034 | #define SIRFSOC_PMX_FUNCTION(n, g, m) \ | |
1035 | { \ | |
1036 | .name = n, \ | |
1037 | .groups = g, \ | |
1038 | .num_groups = ARRAY_SIZE(g), \ | |
1039 | .padmux = &m, \ | |
1040 | } | |
1041 | ||
1042 | static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = { | |
1043 | SIRFSOC_PMX_FUNCTION("lcd_16bits", lcd_16bitsgrp, lcd_16bits_padmux), | |
1044 | SIRFSOC_PMX_FUNCTION("lcd_18bits", lcd_18bitsgrp, lcd_18bits_padmux), | |
1045 | SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux), | |
1046 | SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux), | |
1047 | SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux), | |
1048 | SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux), | |
1049 | SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux), | |
1050 | SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux), | |
1051 | SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux), | |
1052 | SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux), | |
1053 | SIRFSOC_PMX_FUNCTION("usp2", usp2grp, usp2_padmux), | |
1054 | SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux), | |
1055 | SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux), | |
1056 | SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux), | |
1057 | SIRFSOC_PMX_FUNCTION("pwm1", pwm1grp, pwm1_padmux), | |
1058 | SIRFSOC_PMX_FUNCTION("pwm2", pwm2grp, pwm2_padmux), | |
1059 | SIRFSOC_PMX_FUNCTION("pwm3", pwm3grp, pwm3_padmux), | |
1060 | SIRFSOC_PMX_FUNCTION("vip", vipgrp, vip_padmux), | |
1061 | SIRFSOC_PMX_FUNCTION("viprom", vipromgrp, viprom_padmux), | |
1062 | SIRFSOC_PMX_FUNCTION("warm_rst", warm_rstgrp, warm_rst_padmux), | |
1063 | SIRFSOC_PMX_FUNCTION("cko0", cko0grp, cko0_padmux), | |
1064 | SIRFSOC_PMX_FUNCTION("cko1", cko1grp, cko1_padmux), | |
1065 | SIRFSOC_PMX_FUNCTION("sdmmc0", sdmmc0grp, sdmmc0_padmux), | |
1066 | SIRFSOC_PMX_FUNCTION("sdmmc1", sdmmc1grp, sdmmc1_padmux), | |
1067 | SIRFSOC_PMX_FUNCTION("sdmmc2", sdmmc2grp, sdmmc2_padmux), | |
1068 | SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux), | |
1069 | SIRFSOC_PMX_FUNCTION("sdmmc4", sdmmc4grp, sdmmc4_padmux), | |
1070 | SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux), | |
1071 | SIRFSOC_PMX_FUNCTION("usb0_utmi_drvbus", usb0_utmi_drvbusgrp, usb0_utmi_drvbus_padmux), | |
1072 | SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux), | |
1073 | SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux), | |
1074 | SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux), | |
1075 | SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux), | |
1076 | SIRFSOC_PMX_FUNCTION("nand", nandgrp, nand_padmux), | |
1077 | SIRFSOC_PMX_FUNCTION("spi0", spi0grp, spi0_padmux), | |
1078 | SIRFSOC_PMX_FUNCTION("spi1", spi1grp, spi1_padmux), | |
1079 | SIRFSOC_PMX_FUNCTION("gps", gpsgrp, gps_padmux), | |
1080 | }; | |
1081 | ||
1082 | static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, unsigned selector, | |
1083 | bool enable) | |
1084 | { | |
1085 | int i; | |
1086 | const struct sirfsoc_padmux *mux = sirfsoc_pmx_functions[selector].padmux; | |
1087 | const struct sirfsoc_muxmask *mask = mux->muxmask; | |
1088 | ||
1089 | for (i = 0; i < mux->muxmask_counts; i++) { | |
1090 | u32 muxval; | |
1091 | muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group)); | |
1092 | if (enable) | |
1093 | muxval = muxval & ~mask[i].mask; | |
1094 | else | |
1095 | muxval = muxval | mask[i].mask; | |
1096 | writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group)); | |
1097 | } | |
1098 | ||
1099 | if (mux->funcmask && enable) { | |
1100 | u32 func_en_val; | |
1101 | func_en_val = | |
1102 | readl(spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX); | |
1103 | func_en_val = | |
1104 | (func_en_val & ~mux->funcmask) | (mux-> | |
1105 | funcval); | |
1106 | writel(func_en_val, spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX); | |
1107 | } | |
1108 | } | |
1109 | ||
1110 | static int sirfsoc_pinmux_enable(struct pinctrl_dev *pmxdev, unsigned selector, | |
1111 | unsigned group) | |
1112 | { | |
1113 | struct sirfsoc_pmx *spmx; | |
1114 | ||
1115 | spmx = pinctrl_dev_get_drvdata(pmxdev); | |
1116 | sirfsoc_pinmux_endisable(spmx, selector, true); | |
1117 | ||
1118 | return 0; | |
1119 | } | |
1120 | ||
1121 | static void sirfsoc_pinmux_disable(struct pinctrl_dev *pmxdev, unsigned selector, | |
1122 | unsigned group) | |
1123 | { | |
1124 | struct sirfsoc_pmx *spmx; | |
1125 | ||
1126 | spmx = pinctrl_dev_get_drvdata(pmxdev); | |
1127 | sirfsoc_pinmux_endisable(spmx, selector, false); | |
1128 | } | |
1129 | ||
d1e90e9e | 1130 | static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev) |
393daa81 | 1131 | { |
d1e90e9e | 1132 | return ARRAY_SIZE(sirfsoc_pmx_functions); |
393daa81 RY |
1133 | } |
1134 | ||
1135 | static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev, | |
1136 | unsigned selector) | |
1137 | { | |
1138 | return sirfsoc_pmx_functions[selector].name; | |
1139 | } | |
1140 | ||
1141 | static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned selector, | |
1142 | const char * const **groups, | |
1143 | unsigned * const num_groups) | |
1144 | { | |
1145 | *groups = sirfsoc_pmx_functions[selector].groups; | |
1146 | *num_groups = sirfsoc_pmx_functions[selector].num_groups; | |
1147 | return 0; | |
1148 | } | |
1149 | ||
1150 | static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev, | |
1151 | struct pinctrl_gpio_range *range, unsigned offset) | |
1152 | { | |
1153 | struct sirfsoc_pmx *spmx; | |
1154 | ||
1155 | int group = range->id; | |
1156 | ||
1157 | u32 muxval; | |
1158 | ||
1159 | spmx = pinctrl_dev_get_drvdata(pmxdev); | |
1160 | ||
1161 | muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group)); | |
3c739ad0 | 1162 | muxval = muxval | (1 << (offset - range->pin_base)); |
393daa81 RY |
1163 | writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group)); |
1164 | ||
1165 | return 0; | |
1166 | } | |
1167 | ||
1168 | static struct pinmux_ops sirfsoc_pinmux_ops = { | |
393daa81 RY |
1169 | .enable = sirfsoc_pinmux_enable, |
1170 | .disable = sirfsoc_pinmux_disable, | |
d1e90e9e | 1171 | .get_functions_count = sirfsoc_pinmux_get_funcs_count, |
393daa81 RY |
1172 | .get_function_name = sirfsoc_pinmux_get_func_name, |
1173 | .get_function_groups = sirfsoc_pinmux_get_groups, | |
1174 | .gpio_request_enable = sirfsoc_pinmux_request_gpio, | |
1175 | }; | |
1176 | ||
1177 | static struct pinctrl_desc sirfsoc_pinmux_desc = { | |
1178 | .name = DRIVER_NAME, | |
1179 | .pins = sirfsoc_pads, | |
1180 | .npins = ARRAY_SIZE(sirfsoc_pads), | |
393daa81 RY |
1181 | .pctlops = &sirfsoc_pctrl_ops, |
1182 | .pmxops = &sirfsoc_pinmux_ops, | |
1183 | .owner = THIS_MODULE, | |
1184 | }; | |
1185 | ||
1186 | /* | |
1187 | * Todo: bind irq_chip to every pinctrl_gpio_range | |
1188 | */ | |
1189 | static struct pinctrl_gpio_range sirfsoc_gpio_ranges[] = { | |
1190 | { | |
1191 | .name = "sirfsoc-gpio*", | |
1192 | .id = 0, | |
1193 | .base = 0, | |
3c739ad0 | 1194 | .pin_base = 0, |
393daa81 RY |
1195 | .npins = 32, |
1196 | }, { | |
1197 | .name = "sirfsoc-gpio*", | |
1198 | .id = 1, | |
1199 | .base = 32, | |
3c739ad0 | 1200 | .pin_base = 32, |
393daa81 RY |
1201 | .npins = 32, |
1202 | }, { | |
1203 | .name = "sirfsoc-gpio*", | |
1204 | .id = 2, | |
1205 | .base = 64, | |
3c739ad0 | 1206 | .pin_base = 64, |
393daa81 RY |
1207 | .npins = 32, |
1208 | }, { | |
1209 | .name = "sirfsoc-gpio*", | |
1210 | .id = 3, | |
1211 | .base = 96, | |
3c739ad0 | 1212 | .pin_base = 96, |
393daa81 RY |
1213 | .npins = 19, |
1214 | }, | |
1215 | }; | |
1216 | ||
1217 | static void __iomem *sirfsoc_rsc_of_iomap(void) | |
1218 | { | |
1219 | const struct of_device_id rsc_ids[] = { | |
1220 | { .compatible = "sirf,prima2-rsc" }, | |
1221 | {} | |
1222 | }; | |
1223 | struct device_node *np; | |
1224 | ||
1225 | np = of_find_matching_node(NULL, rsc_ids); | |
1226 | if (!np) | |
1227 | panic("unable to find compatible rsc node in dtb\n"); | |
1228 | ||
1229 | return of_iomap(np, 0); | |
1230 | } | |
1231 | ||
1232 | static int __devinit sirfsoc_pinmux_probe(struct platform_device *pdev) | |
1233 | { | |
1234 | int ret; | |
1235 | struct sirfsoc_pmx *spmx; | |
1236 | struct device_node *np = pdev->dev.of_node; | |
1237 | int i; | |
1238 | ||
1239 | /* Create state holders etc for this driver */ | |
1240 | spmx = devm_kzalloc(&pdev->dev, sizeof(*spmx), GFP_KERNEL); | |
1241 | if (!spmx) | |
1242 | return -ENOMEM; | |
1243 | ||
1244 | spmx->dev = &pdev->dev; | |
1245 | ||
1246 | platform_set_drvdata(pdev, spmx); | |
1247 | ||
1248 | spmx->gpio_virtbase = of_iomap(np, 0); | |
1249 | if (!spmx->gpio_virtbase) { | |
1250 | ret = -ENOMEM; | |
1251 | dev_err(&pdev->dev, "can't map gpio registers\n"); | |
1252 | goto out_no_gpio_remap; | |
1253 | } | |
1254 | ||
1255 | spmx->rsc_virtbase = sirfsoc_rsc_of_iomap(); | |
1256 | if (!spmx->rsc_virtbase) { | |
1257 | ret = -ENOMEM; | |
1258 | dev_err(&pdev->dev, "can't map rsc registers\n"); | |
1259 | goto out_no_rsc_remap; | |
1260 | } | |
1261 | ||
1262 | /* Now register the pin controller and all pins it handles */ | |
1263 | spmx->pmx = pinctrl_register(&sirfsoc_pinmux_desc, &pdev->dev, spmx); | |
1264 | if (!spmx->pmx) { | |
1265 | dev_err(&pdev->dev, "could not register SIRFSOC pinmux driver\n"); | |
1266 | ret = -EINVAL; | |
1267 | goto out_no_pmx; | |
1268 | } | |
1269 | ||
19830401 BS |
1270 | for (i = 0; i < ARRAY_SIZE(sirfsoc_gpio_ranges); i++) { |
1271 | sirfsoc_gpio_ranges[i].gc = &sgpio_bank[i].chip.gc; | |
393daa81 | 1272 | pinctrl_add_gpio_range(spmx->pmx, &sirfsoc_gpio_ranges[i]); |
19830401 | 1273 | } |
393daa81 RY |
1274 | |
1275 | dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n"); | |
1276 | ||
1277 | return 0; | |
1278 | ||
1279 | out_no_pmx: | |
1280 | iounmap(spmx->rsc_virtbase); | |
1281 | out_no_rsc_remap: | |
1282 | iounmap(spmx->gpio_virtbase); | |
1283 | out_no_gpio_remap: | |
1284 | platform_set_drvdata(pdev, NULL); | |
393daa81 RY |
1285 | return ret; |
1286 | } | |
1287 | ||
1253585d | 1288 | static const struct of_device_id pinmux_ids[] __devinitconst = { |
056876f6 | 1289 | { .compatible = "sirf,prima2-pinctrl" }, |
393daa81 RY |
1290 | {} |
1291 | }; | |
1292 | ||
1293 | static struct platform_driver sirfsoc_pinmux_driver = { | |
1294 | .driver = { | |
1295 | .name = DRIVER_NAME, | |
1296 | .owner = THIS_MODULE, | |
1297 | .of_match_table = pinmux_ids, | |
1298 | }, | |
1299 | .probe = sirfsoc_pinmux_probe, | |
1300 | }; | |
1301 | ||
1302 | static int __init sirfsoc_pinmux_init(void) | |
1303 | { | |
1304 | return platform_driver_register(&sirfsoc_pinmux_driver); | |
1305 | } | |
1306 | arch_initcall(sirfsoc_pinmux_init); | |
1307 | ||
51302162 BS |
1308 | static inline int sirfsoc_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
1309 | { | |
1310 | struct sirfsoc_gpio_bank *bank = container_of(to_of_mm_gpio_chip(chip), | |
1311 | struct sirfsoc_gpio_bank, chip); | |
1312 | ||
1313 | return irq_find_mapping(bank->domain, offset); | |
1314 | } | |
1315 | ||
1316 | static inline int sirfsoc_gpio_to_offset(unsigned int gpio) | |
1317 | { | |
1318 | return gpio % SIRFSOC_GPIO_BANK_SIZE; | |
1319 | } | |
1320 | ||
1321 | static inline struct sirfsoc_gpio_bank *sirfsoc_gpio_to_bank(unsigned int gpio) | |
1322 | { | |
1323 | return &sgpio_bank[gpio / SIRFSOC_GPIO_BANK_SIZE]; | |
1324 | } | |
1325 | ||
1326 | void sirfsoc_gpio_set_pull(unsigned gpio, unsigned mode) | |
1327 | { | |
1328 | struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(gpio); | |
1329 | int idx = sirfsoc_gpio_to_offset(gpio); | |
1330 | u32 val, offset; | |
1331 | unsigned long flags; | |
1332 | ||
1333 | offset = SIRFSOC_GPIO_CTRL(bank->id, idx); | |
1334 | ||
1335 | spin_lock_irqsave(&sgpio_lock, flags); | |
1336 | ||
1337 | val = readl(bank->chip.regs + offset); | |
1338 | ||
1339 | switch (mode) { | |
1340 | case SIRFSOC_GPIO_PULL_NONE: | |
1341 | val &= ~SIRFSOC_GPIO_CTL_PULL_MASK; | |
1342 | break; | |
1343 | case SIRFSOC_GPIO_PULL_UP: | |
1344 | val |= SIRFSOC_GPIO_CTL_PULL_MASK; | |
1345 | val |= SIRFSOC_GPIO_CTL_PULL_HIGH; | |
1346 | break; | |
1347 | case SIRFSOC_GPIO_PULL_DOWN: | |
1348 | val |= SIRFSOC_GPIO_CTL_PULL_MASK; | |
1349 | val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH; | |
1350 | break; | |
1351 | default: | |
1352 | break; | |
1353 | } | |
1354 | ||
1355 | writel(val, bank->chip.regs + offset); | |
1356 | ||
1357 | spin_unlock_irqrestore(&sgpio_lock, flags); | |
1358 | } | |
1359 | EXPORT_SYMBOL(sirfsoc_gpio_set_pull); | |
1360 | ||
1361 | static inline struct sirfsoc_gpio_bank *sirfsoc_irqchip_to_bank(struct gpio_chip *chip) | |
1362 | { | |
1363 | return container_of(to_of_mm_gpio_chip(chip), struct sirfsoc_gpio_bank, chip); | |
1364 | } | |
1365 | ||
1366 | static void sirfsoc_gpio_irq_ack(struct irq_data *d) | |
1367 | { | |
1368 | struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
1369 | int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE; | |
1370 | u32 val, offset; | |
1371 | unsigned long flags; | |
1372 | ||
1373 | offset = SIRFSOC_GPIO_CTRL(bank->id, idx); | |
1374 | ||
1375 | spin_lock_irqsave(&sgpio_lock, flags); | |
1376 | ||
1377 | val = readl(bank->chip.regs + offset); | |
1378 | ||
1379 | writel(val, bank->chip.regs + offset); | |
1380 | ||
1381 | spin_unlock_irqrestore(&sgpio_lock, flags); | |
1382 | } | |
1383 | ||
1384 | static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_bank *bank, int idx) | |
1385 | { | |
1386 | u32 val, offset; | |
1387 | unsigned long flags; | |
1388 | ||
1389 | offset = SIRFSOC_GPIO_CTRL(bank->id, idx); | |
1390 | ||
1391 | spin_lock_irqsave(&sgpio_lock, flags); | |
1392 | ||
1393 | val = readl(bank->chip.regs + offset); | |
1394 | val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK; | |
1395 | val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK; | |
1396 | writel(val, bank->chip.regs + offset); | |
1397 | ||
1398 | spin_unlock_irqrestore(&sgpio_lock, flags); | |
1399 | } | |
1400 | ||
1401 | static void sirfsoc_gpio_irq_mask(struct irq_data *d) | |
1402 | { | |
1403 | struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
1404 | ||
1405 | __sirfsoc_gpio_irq_mask(bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE); | |
1406 | } | |
1407 | ||
1408 | static void sirfsoc_gpio_irq_unmask(struct irq_data *d) | |
1409 | { | |
1410 | struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
1411 | int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE; | |
1412 | u32 val, offset; | |
1413 | unsigned long flags; | |
1414 | ||
1415 | offset = SIRFSOC_GPIO_CTRL(bank->id, idx); | |
1416 | ||
1417 | spin_lock_irqsave(&sgpio_lock, flags); | |
1418 | ||
1419 | val = readl(bank->chip.regs + offset); | |
1420 | val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK; | |
1421 | val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK; | |
1422 | writel(val, bank->chip.regs + offset); | |
1423 | ||
1424 | spin_unlock_irqrestore(&sgpio_lock, flags); | |
1425 | } | |
1426 | ||
1427 | static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type) | |
1428 | { | |
1429 | struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
1430 | int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE; | |
1431 | u32 val, offset; | |
1432 | unsigned long flags; | |
1433 | ||
1434 | offset = SIRFSOC_GPIO_CTRL(bank->id, idx); | |
1435 | ||
1436 | spin_lock_irqsave(&sgpio_lock, flags); | |
1437 | ||
1438 | val = readl(bank->chip.regs + offset); | |
1439 | val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK; | |
1440 | ||
1441 | switch (type) { | |
1442 | case IRQ_TYPE_NONE: | |
1443 | break; | |
1444 | case IRQ_TYPE_EDGE_RISING: | |
1445 | val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; | |
1446 | val &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK; | |
1447 | break; | |
1448 | case IRQ_TYPE_EDGE_FALLING: | |
1449 | val &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK; | |
1450 | val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; | |
1451 | break; | |
1452 | case IRQ_TYPE_EDGE_BOTH: | |
1453 | val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_LOW_MASK | | |
1454 | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; | |
1455 | break; | |
1456 | case IRQ_TYPE_LEVEL_LOW: | |
1457 | val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK); | |
1458 | val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK; | |
1459 | break; | |
1460 | case IRQ_TYPE_LEVEL_HIGH: | |
1461 | val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK; | |
1462 | val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK); | |
1463 | break; | |
1464 | } | |
1465 | ||
1466 | writel(val, bank->chip.regs + offset); | |
1467 | ||
1468 | spin_unlock_irqrestore(&sgpio_lock, flags); | |
1469 | ||
1470 | return 0; | |
1471 | } | |
1472 | ||
1473 | static struct irq_chip sirfsoc_irq_chip = { | |
1474 | .name = "sirf-gpio-irq", | |
1475 | .irq_ack = sirfsoc_gpio_irq_ack, | |
1476 | .irq_mask = sirfsoc_gpio_irq_mask, | |
1477 | .irq_unmask = sirfsoc_gpio_irq_unmask, | |
1478 | .irq_set_type = sirfsoc_gpio_irq_type, | |
1479 | }; | |
1480 | ||
1481 | static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc) | |
1482 | { | |
1483 | struct sirfsoc_gpio_bank *bank = irq_get_handler_data(irq); | |
1484 | u32 status, ctrl; | |
1485 | int idx = 0; | |
1486 | unsigned int first_irq; | |
6fd4011e BS |
1487 | struct irq_chip *chip = irq_get_chip(irq); |
1488 | ||
1489 | chained_irq_enter(chip, desc); | |
51302162 BS |
1490 | |
1491 | status = readl(bank->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id)); | |
1492 | if (!status) { | |
1493 | printk(KERN_WARNING | |
1494 | "%s: gpio id %d status %#x no interrupt is flaged\n", | |
1495 | __func__, bank->id, status); | |
1496 | handle_bad_irq(irq, desc); | |
1497 | return; | |
1498 | } | |
1499 | ||
1500 | first_irq = bank->domain->revmap_data.legacy.first_irq; | |
1501 | ||
1502 | while (status) { | |
1503 | ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx)); | |
1504 | ||
1505 | /* | |
1506 | * Here we must check whether the corresponding GPIO's interrupt | |
1507 | * has been enabled, otherwise just skip it | |
1508 | */ | |
1509 | if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) { | |
1510 | pr_debug("%s: gpio id %d idx %d happens\n", | |
1511 | __func__, bank->id, idx); | |
1512 | generic_handle_irq(first_irq + idx); | |
1513 | } | |
1514 | ||
1515 | idx++; | |
1516 | status = status >> 1; | |
1517 | } | |
6fd4011e BS |
1518 | |
1519 | chained_irq_exit(chip, desc); | |
51302162 BS |
1520 | } |
1521 | ||
1522 | static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_bank *bank, unsigned ctrl_offset) | |
1523 | { | |
1524 | u32 val; | |
51302162 BS |
1525 | |
1526 | val = readl(bank->chip.regs + ctrl_offset); | |
1527 | val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK; | |
1528 | writel(val, bank->chip.regs + ctrl_offset); | |
51302162 BS |
1529 | } |
1530 | ||
1531 | static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset) | |
1532 | { | |
1533 | struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip); | |
1534 | unsigned long flags; | |
1535 | ||
1536 | if (pinctrl_request_gpio(chip->base + offset)) | |
1537 | return -ENODEV; | |
1538 | ||
1539 | spin_lock_irqsave(&bank->lock, flags); | |
1540 | ||
1541 | /* | |
1542 | * default status: | |
1543 | * set direction as input and mask irq | |
1544 | */ | |
1545 | sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset)); | |
1546 | __sirfsoc_gpio_irq_mask(bank, offset); | |
1547 | ||
1548 | spin_unlock_irqrestore(&bank->lock, flags); | |
1549 | ||
1550 | return 0; | |
1551 | } | |
1552 | ||
1553 | static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset) | |
1554 | { | |
1555 | struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip); | |
1556 | unsigned long flags; | |
1557 | ||
1558 | spin_lock_irqsave(&bank->lock, flags); | |
1559 | ||
1560 | __sirfsoc_gpio_irq_mask(bank, offset); | |
1561 | sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset)); | |
1562 | ||
1563 | spin_unlock_irqrestore(&bank->lock, flags); | |
1564 | ||
1565 | pinctrl_free_gpio(chip->base + offset); | |
1566 | } | |
1567 | ||
1568 | static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) | |
1569 | { | |
1570 | struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip); | |
1571 | int idx = sirfsoc_gpio_to_offset(gpio); | |
1572 | unsigned long flags; | |
1573 | unsigned offset; | |
1574 | ||
1575 | offset = SIRFSOC_GPIO_CTRL(bank->id, idx); | |
1576 | ||
1577 | spin_lock_irqsave(&bank->lock, flags); | |
1578 | ||
1579 | sirfsoc_gpio_set_input(bank, offset); | |
1580 | ||
1581 | spin_unlock_irqrestore(&bank->lock, flags); | |
1582 | ||
1583 | return 0; | |
1584 | } | |
1585 | ||
1586 | static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_bank *bank, unsigned offset, | |
1587 | int value) | |
1588 | { | |
1589 | u32 out_ctrl; | |
1590 | unsigned long flags; | |
1591 | ||
1592 | spin_lock_irqsave(&bank->lock, flags); | |
1593 | ||
1594 | out_ctrl = readl(bank->chip.regs + offset); | |
1595 | if (value) | |
1596 | out_ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK; | |
1597 | else | |
1598 | out_ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK; | |
1599 | ||
1600 | out_ctrl &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK; | |
1601 | out_ctrl |= SIRFSOC_GPIO_CTL_OUT_EN_MASK; | |
1602 | writel(out_ctrl, bank->chip.regs + offset); | |
1603 | ||
1604 | spin_unlock_irqrestore(&bank->lock, flags); | |
1605 | } | |
1606 | ||
1607 | static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value) | |
1608 | { | |
1609 | struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip); | |
1610 | int idx = sirfsoc_gpio_to_offset(gpio); | |
1611 | u32 offset; | |
1612 | unsigned long flags; | |
1613 | ||
1614 | offset = SIRFSOC_GPIO_CTRL(bank->id, idx); | |
1615 | ||
1616 | spin_lock_irqsave(&sgpio_lock, flags); | |
1617 | ||
1618 | sirfsoc_gpio_set_output(bank, offset, value); | |
1619 | ||
1620 | spin_unlock_irqrestore(&sgpio_lock, flags); | |
1621 | ||
1622 | return 0; | |
1623 | } | |
1624 | ||
1625 | static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset) | |
1626 | { | |
1627 | struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip); | |
1628 | u32 val; | |
1629 | unsigned long flags; | |
1630 | ||
1631 | spin_lock_irqsave(&bank->lock, flags); | |
1632 | ||
1633 | val = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); | |
1634 | ||
1635 | spin_unlock_irqrestore(&bank->lock, flags); | |
1636 | ||
1637 | return !!(val & SIRFSOC_GPIO_CTL_DATAIN_MASK); | |
1638 | } | |
1639 | ||
1640 | static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset, | |
1641 | int value) | |
1642 | { | |
1643 | struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip); | |
1644 | u32 ctrl; | |
1645 | unsigned long flags; | |
1646 | ||
1647 | spin_lock_irqsave(&bank->lock, flags); | |
1648 | ||
1649 | ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); | |
1650 | if (value) | |
1651 | ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK; | |
1652 | else | |
1653 | ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK; | |
1654 | writel(ctrl, bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); | |
1655 | ||
1656 | spin_unlock_irqrestore(&bank->lock, flags); | |
1657 | } | |
1658 | ||
1659 | int sirfsoc_gpio_irq_map(struct irq_domain *d, unsigned int irq, | |
1660 | irq_hw_number_t hwirq) | |
1661 | { | |
1662 | struct sirfsoc_gpio_bank *bank = d->host_data; | |
1663 | ||
1664 | if (!bank) | |
1665 | return -EINVAL; | |
1666 | ||
1667 | irq_set_chip(irq, &sirfsoc_irq_chip); | |
1668 | irq_set_handler(irq, handle_level_irq); | |
1669 | irq_set_chip_data(irq, bank); | |
1670 | set_irq_flags(irq, IRQF_VALID); | |
1671 | ||
1672 | return 0; | |
1673 | } | |
1674 | ||
1675 | const struct irq_domain_ops sirfsoc_gpio_irq_simple_ops = { | |
1676 | .map = sirfsoc_gpio_irq_map, | |
1677 | .xlate = irq_domain_xlate_twocell, | |
1678 | }; | |
1679 | ||
1680 | static int __devinit sirfsoc_gpio_probe(struct device_node *np) | |
1681 | { | |
1682 | int i, err = 0; | |
1683 | struct sirfsoc_gpio_bank *bank; | |
1684 | void *regs; | |
1685 | struct platform_device *pdev; | |
1686 | ||
1687 | pdev = of_find_device_by_node(np); | |
1688 | if (!pdev) | |
1689 | return -ENODEV; | |
1690 | ||
1691 | regs = of_iomap(np, 0); | |
1692 | if (!regs) | |
1693 | return -ENOMEM; | |
1694 | ||
1695 | for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { | |
1696 | bank = &sgpio_bank[i]; | |
1697 | spin_lock_init(&bank->lock); | |
1698 | bank->chip.gc.request = sirfsoc_gpio_request; | |
1699 | bank->chip.gc.free = sirfsoc_gpio_free; | |
1700 | bank->chip.gc.direction_input = sirfsoc_gpio_direction_input; | |
1701 | bank->chip.gc.get = sirfsoc_gpio_get_value; | |
1702 | bank->chip.gc.direction_output = sirfsoc_gpio_direction_output; | |
1703 | bank->chip.gc.set = sirfsoc_gpio_set_value; | |
1704 | bank->chip.gc.to_irq = sirfsoc_gpio_to_irq; | |
1705 | bank->chip.gc.base = i * SIRFSOC_GPIO_BANK_SIZE; | |
1706 | bank->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE; | |
1707 | bank->chip.gc.label = kstrdup(np->full_name, GFP_KERNEL); | |
1708 | bank->chip.gc.of_node = np; | |
1709 | bank->chip.regs = regs; | |
1710 | bank->id = i; | |
1711 | bank->parent_irq = platform_get_irq(pdev, i); | |
1712 | if (bank->parent_irq < 0) { | |
1713 | err = bank->parent_irq; | |
1714 | goto out; | |
1715 | } | |
1716 | ||
1717 | err = gpiochip_add(&bank->chip.gc); | |
1718 | if (err) { | |
1719 | pr_err("%s: error in probe function with status %d\n", | |
1720 | np->full_name, err); | |
1721 | goto out; | |
1722 | } | |
1723 | ||
1724 | bank->domain = irq_domain_add_legacy(np, SIRFSOC_GPIO_BANK_SIZE, | |
1725 | SIRFSOC_GPIO_IRQ_START + i * SIRFSOC_GPIO_BANK_SIZE, 0, | |
1726 | &sirfsoc_gpio_irq_simple_ops, bank); | |
1727 | ||
1728 | if (!bank->domain) { | |
1729 | pr_err("%s: Failed to create irqdomain\n", np->full_name); | |
1730 | err = -ENOSYS; | |
1731 | goto out; | |
1732 | } | |
1733 | ||
1734 | irq_set_chained_handler(bank->parent_irq, sirfsoc_gpio_handle_irq); | |
1735 | irq_set_handler_data(bank->parent_irq, bank); | |
1736 | } | |
1737 | ||
ea536366 BS |
1738 | return 0; |
1739 | ||
51302162 BS |
1740 | out: |
1741 | iounmap(regs); | |
1742 | return err; | |
1743 | } | |
1744 | ||
1745 | static int __init sirfsoc_gpio_init(void) | |
1746 | { | |
1747 | ||
1748 | struct device_node *np; | |
1749 | ||
1750 | np = of_find_matching_node(NULL, pinmux_ids); | |
1751 | ||
1752 | if (!np) | |
1753 | return -ENODEV; | |
1754 | ||
1755 | return sirfsoc_gpio_probe(np); | |
1756 | } | |
1757 | subsys_initcall(sirfsoc_gpio_init); | |
1758 | ||
393daa81 | 1759 | MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>, " |
51302162 | 1760 | "Yuping Luo <yuping.luo@csr.com>, " |
393daa81 RY |
1761 | "Barry Song <baohua.song@csr.com>"); |
1762 | MODULE_DESCRIPTION("SIRFSOC pin control driver"); | |
1763 | MODULE_LICENSE("GPL"); |