projects / GitHub / LineageOS / android_kernel_motorola_exynos9610.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
pinctrl: stm32: Implement .pin_config_dbg_show()
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / pinctrl / pinctrl-rockchip.c
CommitLineData
d3e51161
HS		 1/*
2 * Pinctrl driver for Rockchip SoCs
3 *
4 * Copyright (c) 2013 MundoReader S.L.
5 * Author: Heiko Stuebner <heiko@sntech.de>
6 *
7 * With some ideas taken from pinctrl-samsung:
8 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
9 * http://www.samsung.com
10 * Copyright (c) 2012 Linaro Ltd
11 * http://www.linaro.org
12 *
13 * and pinctrl-at91:
14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as published
18 * by the Free Software Foundation.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 */
25
26#include <linux/module.h>
27#include <linux/platform_device.h>
28#include <linux/io.h>
29#include <linux/bitops.h>
30#include <linux/gpio.h>
31#include <linux/of_address.h>
32#include <linux/of_irq.h>
33#include <linux/pinctrl/machine.h>
34#include <linux/pinctrl/pinconf.h>
35#include <linux/pinctrl/pinctrl.h>
36#include <linux/pinctrl/pinmux.h>
37#include <linux/pinctrl/pinconf-generic.h>
38#include <linux/irqchip/chained_irq.h>
7e865abb 39#include <linux/clk.h>
751a99ab 40#include <linux/regmap.h>
14dee867 41#include <linux/mfd/syscon.h>
d3e51161
HS		 42#include <dt-bindings/pinctrl/rockchip.h>
43
44#include "core.h"
45#include "pinconf.h"
46
47/* GPIO control registers */
48#define GPIO_SWPORT_DR 0x00
49#define GPIO_SWPORT_DDR 0x04
50#define GPIO_INTEN 0x30
51#define GPIO_INTMASK 0x34
52#define GPIO_INTTYPE_LEVEL 0x38
53#define GPIO_INT_POLARITY 0x3c
54#define GPIO_INT_STATUS 0x40
55#define GPIO_INT_RAWSTATUS 0x44
56#define GPIO_DEBOUNCE 0x48
57#define GPIO_PORTS_EOI 0x4c
58#define GPIO_EXT_PORT 0x50
59#define GPIO_LS_SYNC 0x60
60
a282926d
HS		 61enum rockchip_pinctrl_type {
62 RK2928,
63 RK3066B,
64 RK3188,
66d750e1 65 RK3288,
daecdc66 66 RK3368,
b6c23275 67 RK3399,
a282926d
HS		 68};
69
fc72c923
HS		 70/**
71 * Encode variants of iomux registers into a type variable
72 */
73#define IOMUX_GPIO_ONLY BIT(0)
03716e1d 74#define IOMUX_WIDTH_4BIT BIT(1)
95ec8ae4 75#define IOMUX_SOURCE_PMU BIT(2)
62f49226 76#define IOMUX_UNROUTED BIT(3)
fc72c923
HS		 77
78/**
79 * @type: iomux variant using IOMUX_* constants
6bc0d121
HS		 80 * @offset: if initialized to -1 it will be autocalculated, by specifying
81 * an initial offset value the relevant source offset can be reset
82 * to a new value for autocalculating the following iomux registers.
fc72c923
HS		 83 */
84struct rockchip_iomux {
85 int type;
6bc0d121 86 int offset;
65fca613
HS		 87};
88
b6c23275
DW		 89/**
90 * enum type index corresponding to rockchip_perpin_drv_list arrays index.
91 */
92enum rockchip_pin_drv_type {
93 DRV_TYPE_IO_DEFAULT = 0,
94 DRV_TYPE_IO_1V8_OR_3V0,
95 DRV_TYPE_IO_1V8_ONLY,
96 DRV_TYPE_IO_1V8_3V0_AUTO,
97 DRV_TYPE_IO_3V3_ONLY,
98 DRV_TYPE_MAX
99};
100
101/**
102 * @drv_type: drive strength variant using rockchip_perpin_drv_type
103 * @offset: if initialized to -1 it will be autocalculated, by specifying
104 * an initial offset value the relevant source offset can be reset
105 * to a new value for autocalculating the following drive strength
106 * registers. if used chips own cal_drv func instead to calculate
107 * registers offset, the variant could be ignored.
108 */
109struct rockchip_drv {
110 enum rockchip_pin_drv_type drv_type;
111 int offset;
112};
113
d3e51161
HS		 114/**
115 * @reg_base: register base of the gpio bank
6ca5274d 116 * @reg_pull: optional separate register for additional pull settings
d3e51161
HS		 117 * @clk: clock of the gpio bank
118 * @irq: interrupt of the gpio bank
5ae0c7ad 119 * @saved_masks: Saved content of GPIO_INTEN at suspend time.
d3e51161
HS		 120 * @pin_base: first pin number
121 * @nr_pins: number of pins in this bank
122 * @name: name of the bank
123 * @bank_num: number of the bank, to account for holes
fc72c923 124 * @iomux: array describing the 4 iomux sources of the bank
b6c23275 125 * @drv: array describing the 4 drive strength sources of the bank
d3e51161
HS		 126 * @valid: are all necessary informations present
127 * @of_node: dt node of this bank
128 * @drvdata: common pinctrl basedata
129 * @domain: irqdomain of the gpio bank
130 * @gpio_chip: gpiolib chip
131 * @grange: gpio range
132 * @slock: spinlock for the gpio bank
133 */
134struct rockchip_pin_bank {
135 void __iomem *reg_base;
751a99ab 136 struct regmap *regmap_pull;
d3e51161
HS		 137 struct clk *clk;
138 int irq;
5ae0c7ad 139 u32 saved_masks;
d3e51161
HS		 140 u32 pin_base;
141 u8 nr_pins;
142 char *name;
143 u8 bank_num;
fc72c923 144 struct rockchip_iomux iomux[4];
b6c23275 145 struct rockchip_drv drv[4];
d3e51161
HS		 146 bool valid;
147 struct device_node *of_node;
148 struct rockchip_pinctrl *drvdata;
149 struct irq_domain *domain;
150 struct gpio_chip gpio_chip;
151 struct pinctrl_gpio_range grange;
152 spinlock_t slock;
5a927501 153 u32 toggle_edge_mode;
d3e51161
HS		 154};
155
156#define PIN_BANK(id, pins, label) \
157 { \
158 .bank_num = id, \
159 .nr_pins = pins, \
160 .name = label, \
6bc0d121
HS		 161 .iomux = { \
162 { .offset = -1 }, \
163 { .offset = -1 }, \
164 { .offset = -1 }, \
165 { .offset = -1 }, \
166 }, \
d3e51161
HS		 167 }
168
fc72c923
HS		 169#define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
170 { \
171 .bank_num = id, \
172 .nr_pins = pins, \
173 .name = label, \
174 .iomux = { \
6bc0d121
HS		 175 { .type = iom0, .offset = -1 }, \
176 { .type = iom1, .offset = -1 }, \
177 { .type = iom2, .offset = -1 }, \
178 { .type = iom3, .offset = -1 }, \
fc72c923
HS		 179 }, \
180 }
181
b6c23275
DW		 182#define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
183 { \
184 .bank_num = id, \
185 .nr_pins = pins, \
186 .name = label, \
187 .iomux = { \
188 { .offset = -1 }, \
189 { .offset = -1 }, \
190 { .offset = -1 }, \
191 { .offset = -1 }, \
192 }, \
193 .drv = { \
194 { .drv_type = type0, .offset = -1 }, \
195 { .drv_type = type1, .offset = -1 }, \
196 { .drv_type = type2, .offset = -1 }, \
197 { .drv_type = type3, .offset = -1 }, \
198 }, \
199 }
200
201#define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
202 iom2, iom3, drv0, drv1, drv2, \
203 drv3, offset0, offset1, \
204 offset2, offset3) \
205 { \
206 .bank_num = id, \
207 .nr_pins = pins, \
208 .name = label, \
209 .iomux = { \
210 { .type = iom0, .offset = -1 }, \
211 { .type = iom1, .offset = -1 }, \
212 { .type = iom2, .offset = -1 }, \
213 { .type = iom3, .offset = -1 }, \
214 }, \
215 .drv = { \
216 { .drv_type = drv0, .offset = offset0 }, \
217 { .drv_type = drv1, .offset = offset1 }, \
218 { .drv_type = drv2, .offset = offset2 }, \
219 { .drv_type = drv3, .offset = offset3 }, \
220 }, \
221 }
222
d3e51161 223/**
d3e51161
HS		 224 */
225struct rockchip_pin_ctrl {
226 struct rockchip_pin_bank *pin_banks;
227 u32 nr_banks;
228 u32 nr_pins;
229 char *label;
a282926d 230 enum rockchip_pinctrl_type type;
95ec8ae4
HS		 231 int grf_mux_offset;
232 int pmu_mux_offset;
b6c23275
DW		 233 int grf_drv_offset;
234 int pmu_drv_offset;
235
751a99ab
HS		 236 void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
237 int pin_num, struct regmap **regmap,
238 int *reg, u8 *bit);
ef17f69f
HS		 239 void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
240 int pin_num, struct regmap **regmap,
241 int *reg, u8 *bit);
d3e51161
HS		 242};
243
244struct rockchip_pin_config {
245 unsigned int func;
246 unsigned long *configs;
247 unsigned int nconfigs;
248};
249
250/**
251 * struct rockchip_pin_group: represent group of pins of a pinmux function.
252 * @name: name of the pin group, used to lookup the group.
253 * @pins: the pins included in this group.
254 * @npins: number of pins included in this group.
255 * @func: the mux function number to be programmed when selected.
256 * @configs: the config values to be set for each pin
257 * @nconfigs: number of configs for each pin
258 */
259struct rockchip_pin_group {
260 const char *name;
261 unsigned int npins;
262 unsigned int *pins;
263 struct rockchip_pin_config *data;
264};
265
266/**
267 * struct rockchip_pmx_func: represent a pin function.
268 * @name: name of the pin function, used to lookup the function.
269 * @groups: one or more names of pin groups that provide this function.
270 * @num_groups: number of groups included in @groups.
271 */
272struct rockchip_pmx_func {
273 const char *name;
274 const char **groups;
275 u8 ngroups;
276};
277
278struct rockchip_pinctrl {
751a99ab 279 struct regmap *regmap_base;
bfc7a42a 280 int reg_size;
751a99ab 281 struct regmap *regmap_pull;
14dee867 282 struct regmap *regmap_pmu;
d3e51161
HS		 283 struct device *dev;
284 struct rockchip_pin_ctrl *ctrl;
285 struct pinctrl_desc pctl;
286 struct pinctrl_dev *pctl_dev;
287 struct rockchip_pin_group *groups;
288 unsigned int ngroups;
289 struct rockchip_pmx_func *functions;
290 unsigned int nfunctions;
291};
292
751a99ab
HS		 293static struct regmap_config rockchip_regmap_config = {
294 .reg_bits = 32,
295 .val_bits = 32,
296 .reg_stride = 4,
297};
298
d3e51161
HS		 299static const inline struct rockchip_pin_group *pinctrl_name_to_group(
300 const struct rockchip_pinctrl *info,
301 const char *name)
302{
d3e51161
HS		 303 int i;
304
305 for (i = 0; i < info->ngroups; i++) {
1cb95395
AL		 306 if (!strcmp(info->groups[i].name, name))
307 return &info->groups[i];
d3e51161
HS		 308 }
309
1cb95395 310 return NULL;
d3e51161
HS		 311}
312
313/*
314 * given a pin number that is local to a pin controller, find out the pin bank
315 * and the register base of the pin bank.
316 */
317static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
318 unsigned pin)
319{
320 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
321
51578b9b 322 while (pin >= (b->pin_base + b->nr_pins))
d3e51161
HS		 323 b++;
324
325 return b;
326}
327
328static struct rockchip_pin_bank *bank_num_to_bank(
329 struct rockchip_pinctrl *info,
330 unsigned num)
331{
332 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
333 int i;
334
1cb95395 335 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
d3e51161 336 if (b->bank_num == num)
1cb95395 337 return b;
d3e51161
HS		 338 }
339
1cb95395 340 return ERR_PTR(-EINVAL);
d3e51161
HS		 341}
342
343/*
344 * Pinctrl_ops handling
345 */
346
347static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
348{
349 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
350
351 return info->ngroups;
352}
353
354static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
355 unsigned selector)
356{
357 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
358
359 return info->groups[selector].name;
360}
361
362static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
363 unsigned selector, const unsigned **pins,
364 unsigned *npins)
365{
366 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
367
368 if (selector >= info->ngroups)
369 return -EINVAL;
370
371 *pins = info->groups[selector].pins;
372 *npins = info->groups[selector].npins;
373
374 return 0;
375}
376
377static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
378 struct device_node *np,
379 struct pinctrl_map **map, unsigned *num_maps)
380{
381 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
382 const struct rockchip_pin_group *grp;
383 struct pinctrl_map *new_map;
384 struct device_node *parent;
385 int map_num = 1;
386 int i;
387
388 /*
389 * first find the group of this node and check if we need to create
390 * config maps for pins
391 */
392 grp = pinctrl_name_to_group(info, np->name);
393 if (!grp) {
394 dev_err(info->dev, "unable to find group for node %s\n",
395 np->name);
396 return -EINVAL;
397 }
398
399 map_num += grp->npins;
400 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
401 GFP_KERNEL);
402 if (!new_map)
403 return -ENOMEM;
404
405 *map = new_map;
406 *num_maps = map_num;
407
408 /* create mux map */
409 parent = of_get_parent(np);
410 if (!parent) {
411 devm_kfree(pctldev->dev, new_map);
412 return -EINVAL;
413 }
414 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
415 new_map[0].data.mux.function = parent->name;
416 new_map[0].data.mux.group = np->name;
417 of_node_put(parent);
418
419 /* create config map */
420 new_map++;
421 for (i = 0; i < grp->npins; i++) {
422 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
423 new_map[i].data.configs.group_or_pin =
424 pin_get_name(pctldev, grp->pins[i]);
425 new_map[i].data.configs.configs = grp->data[i].configs;
426 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
427 }
428
429 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
430 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
431
432 return 0;
433}
434
435static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
436 struct pinctrl_map *map, unsigned num_maps)
437{
438}
439
440static const struct pinctrl_ops rockchip_pctrl_ops = {
441 .get_groups_count = rockchip_get_groups_count,
442 .get_group_name = rockchip_get_group_name,
443 .get_group_pins = rockchip_get_group_pins,
444 .dt_node_to_map = rockchip_dt_node_to_map,
445 .dt_free_map = rockchip_dt_free_map,
446};
447
448/*
449 * Hardware access
450 */
451
a076e2ed
HS		 452static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
453{
454 struct rockchip_pinctrl *info = bank->drvdata;
fc72c923 455 int iomux_num = (pin / 8);
95ec8ae4 456 struct regmap *regmap;
751a99ab 457 unsigned int val;
03716e1d 458 int reg, ret, mask;
a076e2ed
HS		 459 u8 bit;
460
fc72c923
HS		 461 if (iomux_num > 3)
462 return -EINVAL;
463
62f49226
HS		 464 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
465 dev_err(info->dev, "pin %d is unrouted\n", pin);
466 return -EINVAL;
467 }
468
fc72c923 469 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
a076e2ed
HS		 470 return RK_FUNC_GPIO;
471
95ec8ae4
HS		 472 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
473 ? info->regmap_pmu : info->regmap_base;
474
a076e2ed 475 /* get basic quadrupel of mux registers and the correct reg inside */
03716e1d 476 mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
6bc0d121 477 reg = bank->iomux[iomux_num].offset;
03716e1d
HS		 478 if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
479 if ((pin % 8) >= 4)
480 reg += 0x4;
481 bit = (pin % 4) * 4;
482 } else {
483 bit = (pin % 8) * 2;
484 }
a076e2ed 485
95ec8ae4 486 ret = regmap_read(regmap, reg, &val);
751a99ab
HS		 487 if (ret)
488 return ret;
489
03716e1d 490 return ((val >> bit) & mask);
a076e2ed
HS		 491}
492
d3e51161
HS		 493/*
494 * Set a new mux function for a pin.
495 *
496 * The register is divided into the upper and lower 16 bit. When changing
497 * a value, the previous register value is not read and changed. Instead
498 * it seems the changed bits are marked in the upper 16 bit, while the
499 * changed value gets set in the same offset in the lower 16 bit.
500 * All pin settings seem to be 2 bit wide in both the upper and lower
501 * parts.
502 * @bank: pin bank to change
503 * @pin: pin to change
504 * @mux: new mux function to set
505 */
14797189 506static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
d3e51161
HS		 507{
508 struct rockchip_pinctrl *info = bank->drvdata;
fc72c923 509 int iomux_num = (pin / 8);
95ec8ae4 510 struct regmap *regmap;
03716e1d 511 int reg, ret, mask;
d3e51161
HS		 512 unsigned long flags;
513 u8 bit;
99e872d9 514 u32 data, rmask;
d3e51161 515
fc72c923
HS		 516 if (iomux_num > 3)
517 return -EINVAL;
518
62f49226
HS		 519 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
520 dev_err(info->dev, "pin %d is unrouted\n", pin);
521 return -EINVAL;
522 }
523
fc72c923 524 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
c4a532de
HS		 525 if (mux != RK_FUNC_GPIO) {
526 dev_err(info->dev,
527 "pin %d only supports a gpio mux\n", pin);
528 return -ENOTSUPP;
529 } else {
530 return 0;
531 }
532 }
533
d3e51161
HS		 534 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
535 bank->bank_num, pin, mux);
536
95ec8ae4
HS		 537 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
538 ? info->regmap_pmu : info->regmap_base;
539
d3e51161 540 /* get basic quadrupel of mux registers and the correct reg inside */
03716e1d 541 mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
6bc0d121 542 reg = bank->iomux[iomux_num].offset;
03716e1d
HS		 543 if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
544 if ((pin % 8) >= 4)
545 reg += 0x4;
546 bit = (pin % 4) * 4;
547 } else {
548 bit = (pin % 8) * 2;
549 }
d3e51161
HS		 550
551 spin_lock_irqsave(&bank->slock, flags);
552
03716e1d 553 data = (mask << (bit + 16));
99e872d9 554 rmask = data | (data >> 16);
03716e1d 555 data |= (mux & mask) << bit;
99e872d9 556 ret = regmap_update_bits(regmap, reg, rmask, data);
d3e51161
HS		 557
558 spin_unlock_irqrestore(&bank->slock, flags);
14797189 559
751a99ab 560 return ret;
d3e51161
HS		 561}
562
a282926d
HS		 563#define RK2928_PULL_OFFSET 0x118
564#define RK2928_PULL_PINS_PER_REG 16
565#define RK2928_PULL_BANK_STRIDE 8
566
567static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
751a99ab
HS		 568 int pin_num, struct regmap **regmap,
569 int *reg, u8 *bit)
a282926d
HS		 570{
571 struct rockchip_pinctrl *info = bank->drvdata;
572
751a99ab
HS		 573 *regmap = info->regmap_base;
574 *reg = RK2928_PULL_OFFSET;
a282926d
HS		 575 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
576 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
577
578 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
579};
580
bfc7a42a 581#define RK3188_PULL_OFFSET 0x164
6ca5274d
HS		 582#define RK3188_PULL_BITS_PER_PIN 2
583#define RK3188_PULL_PINS_PER_REG 8
584#define RK3188_PULL_BANK_STRIDE 16
14dee867 585#define RK3188_PULL_PMU_OFFSET 0x64
6ca5274d
HS		 586
587static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
751a99ab
HS		 588 int pin_num, struct regmap **regmap,
589 int *reg, u8 *bit)
6ca5274d
HS		 590{
591 struct rockchip_pinctrl *info = bank->drvdata;
592
593 /* The first 12 pins of the first bank are located elsewhere */
fc72c923 594 if (bank->bank_num == 0 && pin_num < 12) {
14dee867
HS		 595 *regmap = info->regmap_pmu ? info->regmap_pmu
596 : bank->regmap_pull;
597 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
751a99ab 598 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
6ca5274d
HS		 599 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
600 *bit *= RK3188_PULL_BITS_PER_PIN;
601 } else {
751a99ab
HS		 602 *regmap = info->regmap_pull ? info->regmap_pull
603 : info->regmap_base;
604 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
605
bfc7a42a
HS		 606 /* correct the offset, as it is the 2nd pull register */
607 *reg -= 4;
6ca5274d
HS		 608 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
609 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
610
611 /*
612 * The bits in these registers have an inverse ordering
613 * with the lowest pin being in bits 15:14 and the highest
614 * pin in bits 1:0
615 */
616 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
617 *bit *= RK3188_PULL_BITS_PER_PIN;
618 }
619}
620
304f077d
HS		 621#define RK3288_PULL_OFFSET 0x140
622static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
623 int pin_num, struct regmap **regmap,
624 int *reg, u8 *bit)
625{
626 struct rockchip_pinctrl *info = bank->drvdata;
627
628 /* The first 24 pins of the first bank are located in PMU */
629 if (bank->bank_num == 0) {
630 *regmap = info->regmap_pmu;
631 *reg = RK3188_PULL_PMU_OFFSET;
632
633 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
634 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
635 *bit *= RK3188_PULL_BITS_PER_PIN;
636 } else {
637 *regmap = info->regmap_base;
638 *reg = RK3288_PULL_OFFSET;
639
640 /* correct the offset, as we're starting with the 2nd bank */
641 *reg -= 0x10;
642 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
643 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
644
645 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
646 *bit *= RK3188_PULL_BITS_PER_PIN;
647 }
648}
649
b547c800
HS		 650#define RK3288_DRV_PMU_OFFSET 0x70
651#define RK3288_DRV_GRF_OFFSET 0x1c0
652#define RK3288_DRV_BITS_PER_PIN 2
653#define RK3288_DRV_PINS_PER_REG 8
654#define RK3288_DRV_BANK_STRIDE 16
b547c800
HS		 655
656static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
657 int pin_num, struct regmap **regmap,
658 int *reg, u8 *bit)
659{
660 struct rockchip_pinctrl *info = bank->drvdata;
661
662 /* The first 24 pins of the first bank are located in PMU */
663 if (bank->bank_num == 0) {
664 *regmap = info->regmap_pmu;
665 *reg = RK3288_DRV_PMU_OFFSET;
666
667 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
668 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
669 *bit *= RK3288_DRV_BITS_PER_PIN;
670 } else {
671 *regmap = info->regmap_base;
672 *reg = RK3288_DRV_GRF_OFFSET;
673
674 /* correct the offset, as we're starting with the 2nd bank */
675 *reg -= 0x10;
676 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
677 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
678
679 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
680 *bit *= RK3288_DRV_BITS_PER_PIN;
681 }
682}
683
fea0fe60
JC		 684#define RK3228_PULL_OFFSET 0x100
685
686static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
687 int pin_num, struct regmap **regmap,
688 int *reg, u8 *bit)
689{
690 struct rockchip_pinctrl *info = bank->drvdata;
691
692 *regmap = info->regmap_base;
693 *reg = RK3228_PULL_OFFSET;
694 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
695 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
696
697 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
698 *bit *= RK3188_PULL_BITS_PER_PIN;
699}
700
701#define RK3228_DRV_GRF_OFFSET 0x200
702
703static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
704 int pin_num, struct regmap **regmap,
705 int *reg, u8 *bit)
706{
707 struct rockchip_pinctrl *info = bank->drvdata;
708
709 *regmap = info->regmap_base;
710 *reg = RK3228_DRV_GRF_OFFSET;
711 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
712 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
713
714 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
715 *bit *= RK3288_DRV_BITS_PER_PIN;
716}
717
daecdc66
HS		 718#define RK3368_PULL_GRF_OFFSET 0x100
719#define RK3368_PULL_PMU_OFFSET 0x10
720
721static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
722 int pin_num, struct regmap **regmap,
723 int *reg, u8 *bit)
724{
725 struct rockchip_pinctrl *info = bank->drvdata;
726
727 /* The first 32 pins of the first bank are located in PMU */
728 if (bank->bank_num == 0) {
729 *regmap = info->regmap_pmu;
730 *reg = RK3368_PULL_PMU_OFFSET;
731
732 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
733 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
734 *bit *= RK3188_PULL_BITS_PER_PIN;
735 } else {
736 *regmap = info->regmap_base;
737 *reg = RK3368_PULL_GRF_OFFSET;
738
739 /* correct the offset, as we're starting with the 2nd bank */
740 *reg -= 0x10;
741 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
742 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
743
744 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
745 *bit *= RK3188_PULL_BITS_PER_PIN;
746 }
747}
748
749#define RK3368_DRV_PMU_OFFSET 0x20
750#define RK3368_DRV_GRF_OFFSET 0x200
751
752static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
753 int pin_num, struct regmap **regmap,
754 int *reg, u8 *bit)
755{
756 struct rockchip_pinctrl *info = bank->drvdata;
757
758 /* The first 32 pins of the first bank are located in PMU */
759 if (bank->bank_num == 0) {
760 *regmap = info->regmap_pmu;
761 *reg = RK3368_DRV_PMU_OFFSET;
762
763 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
764 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
765 *bit *= RK3288_DRV_BITS_PER_PIN;
766 } else {
767 *regmap = info->regmap_base;
768 *reg = RK3368_DRV_GRF_OFFSET;
769
770 /* correct the offset, as we're starting with the 2nd bank */
771 *reg -= 0x10;
772 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
773 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
774
775 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
776 *bit *= RK3288_DRV_BITS_PER_PIN;
777 }
778}
779
b6c23275
DW		 780#define RK3399_PULL_GRF_OFFSET 0xe040
781#define RK3399_PULL_PMU_OFFSET 0x40
782#define RK3399_DRV_3BITS_PER_PIN 3
783
784static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
785 int pin_num, struct regmap **regmap,
786 int *reg, u8 *bit)
787{
788 struct rockchip_pinctrl *info = bank->drvdata;
789
790 /* The bank0:16 and bank1:32 pins are located in PMU */
791 if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
792 *regmap = info->regmap_pmu;
793 *reg = RK3399_PULL_PMU_OFFSET;
794
795 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
796
797 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
798 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
799 *bit *= RK3188_PULL_BITS_PER_PIN;
800 } else {
801 *regmap = info->regmap_base;
802 *reg = RK3399_PULL_GRF_OFFSET;
803
804 /* correct the offset, as we're starting with the 3rd bank */
805 *reg -= 0x20;
806 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
807 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
808
809 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
810 *bit *= RK3188_PULL_BITS_PER_PIN;
811 }
812}
813
814static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
815 int pin_num, struct regmap **regmap,
816 int *reg, u8 *bit)
817{
818 struct rockchip_pinctrl *info = bank->drvdata;
819 int drv_num = (pin_num / 8);
820
821 /* The bank0:16 and bank1:32 pins are located in PMU */
822 if ((bank->bank_num == 0) || (bank->bank_num == 1))
823 *regmap = info->regmap_pmu;
824 else
825 *regmap = info->regmap_base;
826
827 *reg = bank->drv[drv_num].offset;
828 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
829 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
830 *bit = (pin_num % 8) * 3;
831 else
832 *bit = (pin_num % 8) * 2;
833}
834
835static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
836 { 2, 4, 8, 12, -1, -1, -1, -1 },
837 { 3, 6, 9, 12, -1, -1, -1, -1 },
838 { 5, 10, 15, 20, -1, -1, -1, -1 },
839 { 4, 6, 8, 10, 12, 14, 16, 18 },
840 { 4, 7, 10, 13, 16, 19, 22, 26 }
841};
ef17f69f
HS		 842
843static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
844 int pin_num)
b547c800 845{
ef17f69f
HS		 846 struct rockchip_pinctrl *info = bank->drvdata;
847 struct rockchip_pin_ctrl *ctrl = info->ctrl;
b547c800
HS		 848 struct regmap *regmap;
849 int reg, ret;
b6c23275 850 u32 data, temp, rmask_bits;
b547c800 851 u8 bit;
b6c23275 852 int drv_type = bank->drv[pin_num / 8].drv_type;
b547c800 853
ef17f69f 854 ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
b547c800 855
b6c23275
DW		 856 switch (drv_type) {
857 case DRV_TYPE_IO_1V8_3V0_AUTO:
858 case DRV_TYPE_IO_3V3_ONLY:
859 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
860 switch (bit) {
861 case 0 ... 12:
862 /* regular case, nothing to do */
863 break;
864 case 15:
865 /*
866 * drive-strength offset is special, as it is
867 * spread over 2 registers
868 */
869 ret = regmap_read(regmap, reg, &data);
870 if (ret)
871 return ret;
872
873 ret = regmap_read(regmap, reg + 0x4, &temp);
874 if (ret)
875 return ret;
876
877 /*
878 * the bit data[15] contains bit 0 of the value
879 * while temp[1:0] contains bits 2 and 1
880 */
881 data >>= 15;
882 temp &= 0x3;
883 temp <<= 1;
884 data |= temp;
885
886 return rockchip_perpin_drv_list[drv_type][data];
887 case 18 ... 21:
888 /* setting fully enclosed in the second register */
889 reg += 4;
890 bit -= 16;
891 break;
892 default:
893 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
894 bit, drv_type);
895 return -EINVAL;
896 }
897
898 break;
899 case DRV_TYPE_IO_DEFAULT:
900 case DRV_TYPE_IO_1V8_OR_3V0:
901 case DRV_TYPE_IO_1V8_ONLY:
902 rmask_bits = RK3288_DRV_BITS_PER_PIN;
903 break;
904 default:
905 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
906 drv_type);
907 return -EINVAL;
908 }
909
b547c800
HS		 910 ret = regmap_read(regmap, reg, &data);
911 if (ret)
912 return ret;
913
914 data >>= bit;
b6c23275 915 data &= (1 << rmask_bits) - 1;
b547c800 916
b6c23275 917 return rockchip_perpin_drv_list[drv_type][data];
b547c800
HS		 918}
919
ef17f69f
HS		 920static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
921 int pin_num, int strength)
b547c800
HS		 922{
923 struct rockchip_pinctrl *info = bank->drvdata;
ef17f69f 924 struct rockchip_pin_ctrl *ctrl = info->ctrl;
b547c800
HS		 925 struct regmap *regmap;
926 unsigned long flags;
927 int reg, ret, i;
b6c23275 928 u32 data, rmask, rmask_bits, temp;
b547c800 929 u8 bit;
b6c23275
DW		 930 int drv_type = bank->drv[pin_num / 8].drv_type;
931
932 dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n",
933 bank->bank_num, pin_num, strength);
b547c800 934
ef17f69f 935 ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
b547c800
HS		 936
937 ret = -EINVAL;
b6c23275
DW		 938 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
939 if (rockchip_perpin_drv_list[drv_type][i] == strength) {
b547c800
HS		 940 ret = i;
941 break;
b6c23275
DW		 942 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
943 ret = rockchip_perpin_drv_list[drv_type][i];
944 break;
b547c800
HS		 945 }
946 }
947
948 if (ret < 0) {
949 dev_err(info->dev, "unsupported driver strength %d\n",
950 strength);
951 return ret;
952 }
953
954 spin_lock_irqsave(&bank->slock, flags);
955
b6c23275
DW		 956 switch (drv_type) {
957 case DRV_TYPE_IO_1V8_3V0_AUTO:
958 case DRV_TYPE_IO_3V3_ONLY:
959 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
960 switch (bit) {
961 case 0 ... 12:
962 /* regular case, nothing to do */
963 break;
964 case 15:
965 /*
966 * drive-strength offset is special, as it is spread
967 * over 2 registers, the bit data[15] contains bit 0
968 * of the value while temp[1:0] contains bits 2 and 1
969 */
970 data = (ret & 0x1) << 15;
971 temp = (ret >> 0x1) & 0x3;
972
973 rmask = BIT(15) | BIT(31);
974 data |= BIT(31);
975 ret = regmap_update_bits(regmap, reg, rmask, data);
976 if (ret) {
977 spin_unlock_irqrestore(&bank->slock, flags);
978 return ret;
979 }
980
981 rmask = 0x3 | (0x3 << 16);
982 temp |= (0x3 << 16);
983 reg += 0x4;
984 ret = regmap_update_bits(regmap, reg, rmask, temp);
985
986 spin_unlock_irqrestore(&bank->slock, flags);
987 return ret;
988 case 18 ... 21:
989 /* setting fully enclosed in the second register */
990 reg += 4;
991 bit -= 16;
992 break;
993 default:
994 spin_unlock_irqrestore(&bank->slock, flags);
995 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
996 bit, drv_type);
997 return -EINVAL;
998 }
999 break;
1000 case DRV_TYPE_IO_DEFAULT:
1001 case DRV_TYPE_IO_1V8_OR_3V0:
1002 case DRV_TYPE_IO_1V8_ONLY:
1003 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1004 break;
1005 default:
1006 spin_unlock_irqrestore(&bank->slock, flags);
1007 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1008 drv_type);
1009 return -EINVAL;
1010 }
1011
b547c800 1012 /* enable the write to the equivalent lower bits */
b6c23275 1013 data = ((1 << rmask_bits) - 1) << (bit + 16);
99e872d9 1014 rmask = data | (data >> 16);
b547c800
HS		 1015 data |= (ret << bit);
1016
99e872d9 1017 ret = regmap_update_bits(regmap, reg, rmask, data);
b547c800
HS		 1018 spin_unlock_irqrestore(&bank->slock, flags);
1019
1020 return ret;
1021}
1022
d3e51161
HS		 1023static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
1024{
1025 struct rockchip_pinctrl *info = bank->drvdata;
1026 struct rockchip_pin_ctrl *ctrl = info->ctrl;
751a99ab
HS		 1027 struct regmap *regmap;
1028 int reg, ret;
d3e51161 1029 u8 bit;
6ca5274d 1030 u32 data;
d3e51161
HS		 1031
1032 /* rk3066b does support any pulls */
a282926d 1033 if (ctrl->type == RK3066B)
d3e51161
HS		 1034 return PIN_CONFIG_BIAS_DISABLE;
1035
751a99ab
HS		 1036 ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1037
1038 ret = regmap_read(regmap, reg, &data);
1039 if (ret)
1040 return ret;
6ca5274d 1041
a282926d
HS		 1042 switch (ctrl->type) {
1043 case RK2928:
751a99ab 1044 return !(data & BIT(bit))
d3e51161
HS		 1045 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
1046 : PIN_CONFIG_BIAS_DISABLE;
a282926d 1047 case RK3188:
66d750e1 1048 case RK3288:
daecdc66 1049 case RK3368:
b6c23275 1050 case RK3399:
751a99ab 1051 data >>= bit;
6ca5274d
HS		 1052 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
1053
1054 switch (data) {
1055 case 0:
1056 return PIN_CONFIG_BIAS_DISABLE;
1057 case 1:
1058 return PIN_CONFIG_BIAS_PULL_UP;
1059 case 2:
1060 return PIN_CONFIG_BIAS_PULL_DOWN;
1061 case 3:
1062 return PIN_CONFIG_BIAS_BUS_HOLD;
1063 }
1064
1065 dev_err(info->dev, "unknown pull setting\n");
d3e51161 1066 return -EIO;
a282926d
HS		 1067 default:
1068 dev_err(info->dev, "unsupported pinctrl type\n");
1069 return -EINVAL;
1070 };
d3e51161
HS		 1071}
1072
1073static int rockchip_set_pull(struct rockchip_pin_bank *bank,
1074 int pin_num, int pull)
1075{
1076 struct rockchip_pinctrl *info = bank->drvdata;
1077 struct rockchip_pin_ctrl *ctrl = info->ctrl;
751a99ab
HS		 1078 struct regmap *regmap;
1079 int reg, ret;
d3e51161
HS		 1080 unsigned long flags;
1081 u8 bit;
99e872d9 1082 u32 data, rmask;
d3e51161
HS		 1083
1084 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
1085 bank->bank_num, pin_num, pull);
1086
1087 /* rk3066b does support any pulls */
a282926d 1088 if (ctrl->type == RK3066B)
d3e51161
HS		 1089 return pull ? -EINVAL : 0;
1090
751a99ab 1091 ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
6ca5274d 1092
a282926d
HS		 1093 switch (ctrl->type) {
1094 case RK2928:
d3e51161
HS		 1095 spin_lock_irqsave(&bank->slock, flags);
1096
1097 data = BIT(bit + 16);
1098 if (pull == PIN_CONFIG_BIAS_DISABLE)
1099 data |= BIT(bit);
751a99ab 1100 ret = regmap_write(regmap, reg, data);
d3e51161
HS		 1101
1102 spin_unlock_irqrestore(&bank->slock, flags);
a282926d
HS		 1103 break;
1104 case RK3188:
66d750e1 1105 case RK3288:
daecdc66 1106 case RK3368:
b6c23275 1107 case RK3399:
6ca5274d
HS		 1108 spin_lock_irqsave(&bank->slock, flags);
1109
1110 /* enable the write to the equivalent lower bits */
1111 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
99e872d9 1112 rmask = data | (data >> 16);
6ca5274d
HS		 1113
1114 switch (pull) {
1115 case PIN_CONFIG_BIAS_DISABLE:
1116 break;
1117 case PIN_CONFIG_BIAS_PULL_UP:
1118 data |= (1 << bit);
1119 break;
1120 case PIN_CONFIG_BIAS_PULL_DOWN:
1121 data |= (2 << bit);
1122 break;
1123 case PIN_CONFIG_BIAS_BUS_HOLD:
1124 data |= (3 << bit);
1125 break;
1126 default:
d32c3e26 1127 spin_unlock_irqrestore(&bank->slock, flags);
6ca5274d
HS		 1128 dev_err(info->dev, "unsupported pull setting %d\n",
1129 pull);
1130 return -EINVAL;
1131 }
1132
99e872d9 1133 ret = regmap_update_bits(regmap, reg, rmask, data);
6ca5274d
HS		 1134
1135 spin_unlock_irqrestore(&bank->slock, flags);
1136 break;
a282926d
HS		 1137 default:
1138 dev_err(info->dev, "unsupported pinctrl type\n");
1139 return -EINVAL;
d3e51161
HS		 1140 }
1141
751a99ab 1142 return ret;
d3e51161
HS		 1143}
1144
1145/*
1146 * Pinmux_ops handling
1147 */
1148
1149static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
1150{
1151 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1152
1153 return info->nfunctions;
1154}
1155
1156static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
1157 unsigned selector)
1158{
1159 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1160
1161 return info->functions[selector].name;
1162}
1163
1164static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
1165 unsigned selector, const char * const **groups,
1166 unsigned * const num_groups)
1167{
1168 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1169
1170 *groups = info->functions[selector].groups;
1171 *num_groups = info->functions[selector].ngroups;
1172
1173 return 0;
1174}
1175
03e9f0ca
LW		 1176static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
1177 unsigned group)
d3e51161
HS		 1178{
1179 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1180 const unsigned int *pins = info->groups[group].pins;
1181 const struct rockchip_pin_config *data = info->groups[group].data;
1182 struct rockchip_pin_bank *bank;
14797189 1183 int cnt, ret = 0;
d3e51161
HS		 1184
1185 dev_dbg(info->dev, "enable function %s group %s\n",
1186 info->functions[selector].name, info->groups[group].name);
1187
1188 /*
1189 * for each pin in the pin group selected, program the correspoding pin
1190 * pin function number in the config register.
1191 */
1192 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
1193 bank = pin_to_bank(info, pins[cnt]);
14797189
HS		 1194 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
1195 data[cnt].func);
1196 if (ret)
1197 break;
1198 }
1199
1200 if (ret) {
1201 /* revert the already done pin settings */
1202 for (cnt--; cnt >= 0; cnt--)
1203 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
1204
1205 return ret;
d3e51161
HS		 1206 }
1207
1208 return 0;
1209}
1210
6ba20a00
CW		 1211static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1212{
1213 struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
1214 u32 data;
1215
1216 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1217
1218 return !(data & BIT(offset));
1219}
1220
d3e51161
HS		 1221/*
1222 * The calls to gpio_direction_output() and gpio_direction_input()
1223 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
1224 * function called from the gpiolib interface).
1225 */
e5c2c9db
DA		 1226static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
1227 int pin, bool input)
d3e51161 1228{
d3e51161 1229 struct rockchip_pin_bank *bank;
e5c2c9db 1230 int ret;
fab262f5 1231 unsigned long flags;
d3e51161
HS		 1232 u32 data;
1233
03bf81f1 1234 bank = gpiochip_get_data(chip);
d3e51161 1235
14797189
HS		 1236 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
1237 if (ret < 0)
1238 return ret;
d3e51161 1239
07a06ae9 1240 clk_enable(bank->clk);
fab262f5
DA		 1241 spin_lock_irqsave(&bank->slock, flags);
1242
d3e51161
HS		 1243 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1244 /* set bit to 1 for output, 0 for input */
1245 if (!input)
1246 data |= BIT(pin);
1247 else
1248 data &= ~BIT(pin);
1249 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1250
fab262f5 1251 spin_unlock_irqrestore(&bank->slock, flags);
07a06ae9 1252 clk_disable(bank->clk);
fab262f5 1253
d3e51161
HS		 1254 return 0;
1255}
1256
e5c2c9db
DA		 1257static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
1258 struct pinctrl_gpio_range *range,
1259 unsigned offset, bool input)
1260{
1261 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1262 struct gpio_chip *chip;
1263 int pin;
1264
1265 chip = range->gc;
1266 pin = offset - chip->base;
1267 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
1268 offset, range->name, pin, input ? "input" : "output");
1269
1270 return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
1271 input);
1272}
1273
d3e51161
HS		 1274static const struct pinmux_ops rockchip_pmx_ops = {
1275 .get_functions_count = rockchip_pmx_get_funcs_count,
1276 .get_function_name = rockchip_pmx_get_func_name,
1277 .get_function_groups = rockchip_pmx_get_groups,
03e9f0ca 1278 .set_mux = rockchip_pmx_set,
d3e51161
HS		 1279 .gpio_set_direction = rockchip_pmx_gpio_set_direction,
1280};
1281
1282/*
1283 * Pinconf_ops handling
1284 */
1285
44b6d930
HS		 1286static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
1287 enum pin_config_param pull)
1288{
a282926d
HS		 1289 switch (ctrl->type) {
1290 case RK2928:
1291 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
1292 pull == PIN_CONFIG_BIAS_DISABLE);
1293 case RK3066B:
44b6d930 1294 return pull ? false : true;
a282926d 1295 case RK3188:
66d750e1 1296 case RK3288:
daecdc66 1297 case RK3368:
b6c23275 1298 case RK3399:
a282926d 1299 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
44b6d930
HS		 1300 }
1301
a282926d 1302 return false;
44b6d930
HS		 1303}
1304
e5c2c9db 1305static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
a076e2ed
HS		 1306static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
1307
d3e51161
HS		 1308/* set the pin config settings for a specified pin */
1309static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
03b054e9 1310 unsigned long *configs, unsigned num_configs)
d3e51161
HS		 1311{
1312 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1313 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
03b054e9
SY		 1314 enum pin_config_param param;
1315 u16 arg;
1316 int i;
1317 int rc;
1318
1319 for (i = 0; i < num_configs; i++) {
1320 param = pinconf_to_config_param(configs[i]);
1321 arg = pinconf_to_config_argument(configs[i]);
1322
1323 switch (param) {
1324 case PIN_CONFIG_BIAS_DISABLE:
1325 rc = rockchip_set_pull(bank, pin - bank->pin_base,
1326 param);
1327 if (rc)
1328 return rc;
1329 break;
1330 case PIN_CONFIG_BIAS_PULL_UP:
1331 case PIN_CONFIG_BIAS_PULL_DOWN:
1332 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
6ca5274d 1333 case PIN_CONFIG_BIAS_BUS_HOLD:
03b054e9
SY		 1334 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1335 return -ENOTSUPP;
1336
1337 if (!arg)
1338 return -EINVAL;
1339
1340 rc = rockchip_set_pull(bank, pin - bank->pin_base,
1341 param);
1342 if (rc)
1343 return rc;
1344 break;
a076e2ed 1345 case PIN_CONFIG_OUTPUT:
e5c2c9db
DA		 1346 rockchip_gpio_set(&bank->gpio_chip,
1347 pin - bank->pin_base, arg);
1348 rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
1349 pin - bank->pin_base, false);
a076e2ed
HS		 1350 if (rc)
1351 return rc;
1352 break;
b547c800
HS		 1353 case PIN_CONFIG_DRIVE_STRENGTH:
1354 /* rk3288 is the first with per-pin drive-strength */
ef17f69f 1355 if (!info->ctrl->drv_calc_reg)
b547c800
HS		 1356 return -ENOTSUPP;
1357
ef17f69f
HS		 1358 rc = rockchip_set_drive_perpin(bank,
1359 pin - bank->pin_base, arg);
b547c800
HS		 1360 if (rc < 0)
1361 return rc;
1362 break;
03b054e9 1363 default:
44b6d930 1364 return -ENOTSUPP;
03b054e9
SY		 1365 break;
1366 }
1367 } /* for each config */
d3e51161
HS		 1368
1369 return 0;
1370}
1371
1372/* get the pin config settings for a specified pin */
1373static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
1374 unsigned long *config)
1375{
1376 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1377 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
1378 enum pin_config_param param = pinconf_to_config_param(*config);
dab3eba7 1379 u16 arg;
a076e2ed 1380 int rc;
d3e51161
HS		 1381
1382 switch (param) {
1383 case PIN_CONFIG_BIAS_DISABLE:
44b6d930
HS		 1384 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1385 return -EINVAL;
1386
dab3eba7 1387 arg = 0;
44b6d930 1388 break;
d3e51161
HS		 1389 case PIN_CONFIG_BIAS_PULL_UP:
1390 case PIN_CONFIG_BIAS_PULL_DOWN:
1391 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
6ca5274d 1392 case PIN_CONFIG_BIAS_BUS_HOLD:
44b6d930
HS		 1393 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1394 return -ENOTSUPP;
d3e51161 1395
44b6d930 1396 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
d3e51161
HS		 1397 return -EINVAL;
1398
dab3eba7 1399 arg = 1;
d3e51161 1400 break;
a076e2ed
HS		 1401 case PIN_CONFIG_OUTPUT:
1402 rc = rockchip_get_mux(bank, pin - bank->pin_base);
1403 if (rc != RK_FUNC_GPIO)
1404 return -EINVAL;
1405
1406 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
1407 if (rc < 0)
1408 return rc;
1409
1410 arg = rc ? 1 : 0;
1411 break;
b547c800
HS		 1412 case PIN_CONFIG_DRIVE_STRENGTH:
1413 /* rk3288 is the first with per-pin drive-strength */
ef17f69f 1414 if (!info->ctrl->drv_calc_reg)
b547c800
HS		 1415 return -ENOTSUPP;
1416
ef17f69f 1417 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
b547c800
HS		 1418 if (rc < 0)
1419 return rc;
1420
1421 arg = rc;
1422 break;
d3e51161
HS		 1423 default:
1424 return -ENOTSUPP;
1425 break;
1426 }
1427
dab3eba7
HS		 1428 *config = pinconf_to_config_packed(param, arg);
1429
d3e51161
HS		 1430 return 0;
1431}
1432
1433static const struct pinconf_ops rockchip_pinconf_ops = {
1434 .pin_config_get = rockchip_pinconf_get,
1435 .pin_config_set = rockchip_pinconf_set,
ed62f2f2 1436 .is_generic = true,
d3e51161
HS		 1437};
1438
65fca613
HS		 1439static const struct of_device_id rockchip_bank_match[] = {
1440 { .compatible = "rockchip,gpio-bank" },
6ca5274d 1441 { .compatible = "rockchip,rk3188-gpio-bank0" },
65fca613
HS		 1442 {},
1443};
d3e51161
HS		 1444
1445static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
1446 struct device_node *np)
1447{
1448 struct device_node *child;
1449
1450 for_each_child_of_node(np, child) {
65fca613 1451 if (of_match_node(rockchip_bank_match, child))
d3e51161
HS		 1452 continue;
1453
1454 info->nfunctions++;
1455 info->ngroups += of_get_child_count(child);
1456 }
1457}
1458
1459static int rockchip_pinctrl_parse_groups(struct device_node *np,
1460 struct rockchip_pin_group *grp,
1461 struct rockchip_pinctrl *info,
1462 u32 index)
1463{
1464 struct rockchip_pin_bank *bank;
1465 int size;
1466 const __be32 *list;
1467 int num;
1468 int i, j;
1469 int ret;
1470
1471 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
1472
1473 /* Initialise group */
1474 grp->name = np->name;
1475
1476 /*
1477 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
1478 * do sanity check and calculate pins number
1479 */
1480 list = of_get_property(np, "rockchip,pins", &size);
1481 /* we do not check return since it's safe node passed down */
1482 size /= sizeof(*list);
1483 if (!size || size % 4) {
1484 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
1485 return -EINVAL;
1486 }
1487
1488 grp->npins = size / 4;
1489
1490 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
1491 GFP_KERNEL);
1492 grp->data = devm_kzalloc(info->dev, grp->npins *
1493 sizeof(struct rockchip_pin_config),
1494 GFP_KERNEL);
1495 if (!grp->pins || !grp->data)
1496 return -ENOMEM;
1497
1498 for (i = 0, j = 0; i < size; i += 4, j++) {
1499 const __be32 *phandle;
1500 struct device_node *np_config;
1501
1502 num = be32_to_cpu(*list++);
1503 bank = bank_num_to_bank(info, num);
1504 if (IS_ERR(bank))
1505 return PTR_ERR(bank);
1506
1507 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
1508 grp->data[j].func = be32_to_cpu(*list++);
1509
1510 phandle = list++;
1511 if (!phandle)
1512 return -EINVAL;
1513
1514 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
dd4d01f7 1515 ret = pinconf_generic_parse_dt_config(np_config, NULL,
d3e51161
HS		 1516 &grp->data[j].configs, &grp->data[j].nconfigs);
1517 if (ret)
1518 return ret;
1519 }
1520
1521 return 0;
1522}
1523
1524static int rockchip_pinctrl_parse_functions(struct device_node *np,
1525 struct rockchip_pinctrl *info,
1526 u32 index)
1527{
1528 struct device_node *child;
1529 struct rockchip_pmx_func *func;
1530 struct rockchip_pin_group *grp;
1531 int ret;
1532 static u32 grp_index;
1533 u32 i = 0;
1534
1535 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
1536
1537 func = &info->functions[index];
1538
1539 /* Initialise function */
1540 func->name = np->name;
1541 func->ngroups = of_get_child_count(np);
1542 if (func->ngroups <= 0)
1543 return 0;
1544
1545 func->groups = devm_kzalloc(info->dev,
1546 func->ngroups * sizeof(char *), GFP_KERNEL);
1547 if (!func->groups)
1548 return -ENOMEM;
1549
1550 for_each_child_of_node(np, child) {
1551 func->groups[i] = child->name;
1552 grp = &info->groups[grp_index++];
1553 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
f7a81b7f
JL		 1554 if (ret) {
1555 of_node_put(child);
d3e51161 1556 return ret;
f7a81b7f 1557 }
d3e51161
HS		 1558 }
1559
1560 return 0;
1561}
1562
1563static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
1564 struct rockchip_pinctrl *info)
1565{
1566 struct device *dev = &pdev->dev;
1567 struct device_node *np = dev->of_node;
1568 struct device_node *child;
1569 int ret;
1570 int i;
1571
1572 rockchip_pinctrl_child_count(info, np);
1573
1574 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1575 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1576
1577 info->functions = devm_kzalloc(dev, info->nfunctions *
1578 sizeof(struct rockchip_pmx_func),
1579 GFP_KERNEL);
1580 if (!info->functions) {
1581 dev_err(dev, "failed to allocate memory for function list\n");
1582 return -EINVAL;
1583 }
1584
1585 info->groups = devm_kzalloc(dev, info->ngroups *
1586 sizeof(struct rockchip_pin_group),
1587 GFP_KERNEL);
1588 if (!info->groups) {
1589 dev_err(dev, "failed allocate memory for ping group list\n");
1590 return -EINVAL;
1591 }
1592
1593 i = 0;
1594
1595 for_each_child_of_node(np, child) {
65fca613 1596 if (of_match_node(rockchip_bank_match, child))
d3e51161 1597 continue;
65fca613 1598
d3e51161
HS		 1599 ret = rockchip_pinctrl_parse_functions(child, info, i++);
1600 if (ret) {
1601 dev_err(&pdev->dev, "failed to parse function\n");
f7a81b7f 1602 of_node_put(child);
d3e51161
HS		 1603 return ret;
1604 }
1605 }
1606
1607 return 0;
1608}
1609
1610static int rockchip_pinctrl_register(struct platform_device *pdev,
1611 struct rockchip_pinctrl *info)
1612{
1613 struct pinctrl_desc *ctrldesc = &info->pctl;
1614 struct pinctrl_pin_desc *pindesc, *pdesc;
1615 struct rockchip_pin_bank *pin_bank;
1616 int pin, bank, ret;
1617 int k;
1618
1619 ctrldesc->name = "rockchip-pinctrl";
1620 ctrldesc->owner = THIS_MODULE;
1621 ctrldesc->pctlops = &rockchip_pctrl_ops;
1622 ctrldesc->pmxops = &rockchip_pmx_ops;
1623 ctrldesc->confops = &rockchip_pinconf_ops;
1624
1625 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
1626 info->ctrl->nr_pins, GFP_KERNEL);
1627 if (!pindesc) {
1628 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
1629 return -ENOMEM;
1630 }
1631 ctrldesc->pins = pindesc;
1632 ctrldesc->npins = info->ctrl->nr_pins;
1633
1634 pdesc = pindesc;
1635 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
1636 pin_bank = &info->ctrl->pin_banks[bank];
1637 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
1638 pdesc->number = k;
1639 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
1640 pin_bank->name, pin);
1641 pdesc++;
1642 }
1643 }
1644
0fb7dcb1
DA		 1645 ret = rockchip_pinctrl_parse_dt(pdev, info);
1646 if (ret)
1647 return ret;
1648
0085a2b4 1649 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
323de9ef 1650 if (IS_ERR(info->pctl_dev)) {
d3e51161 1651 dev_err(&pdev->dev, "could not register pinctrl driver\n");
323de9ef 1652 return PTR_ERR(info->pctl_dev);
d3e51161
HS		 1653 }
1654
1655 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
1656 pin_bank = &info->ctrl->pin_banks[bank];
1657 pin_bank->grange.name = pin_bank->name;
1658 pin_bank->grange.id = bank;
1659 pin_bank->grange.pin_base = pin_bank->pin_base;
1660 pin_bank->grange.base = pin_bank->gpio_chip.base;
1661 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
1662 pin_bank->grange.gc = &pin_bank->gpio_chip;
1663 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
1664 }
1665
d3e51161
HS		 1666 return 0;
1667}
1668
1669/*
1670 * GPIO handling
1671 */
1672
1673static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
1674{
03bf81f1 1675 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
d3e51161
HS		 1676 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
1677 unsigned long flags;
1678 u32 data;
1679
07a06ae9 1680 clk_enable(bank->clk);
d3e51161
HS		 1681 spin_lock_irqsave(&bank->slock, flags);
1682
1683 data = readl(reg);
1684 data &= ~BIT(offset);
1685 if (value)
1686 data |= BIT(offset);
1687 writel(data, reg);
1688
1689 spin_unlock_irqrestore(&bank->slock, flags);
07a06ae9 1690 clk_disable(bank->clk);
d3e51161
HS		 1691}
1692
1693/*
1694 * Returns the level of the pin for input direction and setting of the DR
1695 * register for output gpios.
1696 */
1697static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
1698{
03bf81f1 1699 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
d3e51161
HS		 1700 u32 data;
1701
07a06ae9 1702 clk_enable(bank->clk);
d3e51161 1703 data = readl(bank->reg_base + GPIO_EXT_PORT);
07a06ae9 1704 clk_disable(bank->clk);
d3e51161
HS		 1705 data >>= offset;
1706 data &= 1;
1707 return data;
1708}
1709
1710/*
1711 * gpiolib gpio_direction_input callback function. The setting of the pin
1712 * mux function as 'gpio input' will be handled by the pinctrl susbsystem
1713 * interface.
1714 */
1715static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
1716{
1717 return pinctrl_gpio_direction_input(gc->base + offset);
1718}
1719
1720/*
1721 * gpiolib gpio_direction_output callback function. The setting of the pin
1722 * mux function as 'gpio output' will be handled by the pinctrl susbsystem
1723 * interface.
1724 */
1725static int rockchip_gpio_direction_output(struct gpio_chip *gc,
1726 unsigned offset, int value)
1727{
1728 rockchip_gpio_set(gc, offset, value);
1729 return pinctrl_gpio_direction_output(gc->base + offset);
1730}
1731
1732/*
1733 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
1734 * and a virtual IRQ, if not already present.
1735 */
1736static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
1737{
03bf81f1 1738 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
d3e51161
HS		 1739 unsigned int virq;
1740
1741 if (!bank->domain)
1742 return -ENXIO;
1743
1744 virq = irq_create_mapping(bank->domain, offset);
1745
1746 return (virq) ? : -ENXIO;
1747}
1748
1749static const struct gpio_chip rockchip_gpiolib_chip = {
98c85d58
JG		 1750 .request = gpiochip_generic_request,
1751 .free = gpiochip_generic_free,
d3e51161
HS		 1752 .set = rockchip_gpio_set,
1753 .get = rockchip_gpio_get,
6ba20a00 1754 .get_direction = rockchip_gpio_get_direction,
d3e51161
HS		 1755 .direction_input = rockchip_gpio_direction_input,
1756 .direction_output = rockchip_gpio_direction_output,
1757 .to_irq = rockchip_gpio_to_irq,
1758 .owner = THIS_MODULE,
1759};
1760
1761/*
1762 * Interrupt handling
1763 */
1764
bd0b9ac4 1765static void rockchip_irq_demux(struct irq_desc *desc)
d3e51161 1766{
5663bb27
JL		 1767 struct irq_chip *chip = irq_desc_get_chip(desc);
1768 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
d3e51161
HS		 1769 u32 pend;
1770
1771 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
1772
1773 chained_irq_enter(chip, desc);
1774
1775 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
1776
1777 while (pend) {
415f748c 1778 unsigned int irq, virq;
d3e51161
HS		 1779
1780 irq = __ffs(pend);
1781 pend &= ~BIT(irq);
1782 virq = irq_linear_revmap(bank->domain, irq);
1783
1784 if (!virq) {
1785 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
1786 continue;
1787 }
1788
1789 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
1790
5a927501
HS		 1791 /*
1792 * Triggering IRQ on both rising and falling edge
1793 * needs manual intervention.
1794 */
1795 if (bank->toggle_edge_mode & BIT(irq)) {
53b1bfc7
DA		 1796 u32 data, data_old, polarity;
1797 unsigned long flags;
1798
1799 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
1800 do {
1801 spin_lock_irqsave(&bank->slock, flags);
1802
1803 polarity = readl_relaxed(bank->reg_base +
1804 GPIO_INT_POLARITY);
1805 if (data & BIT(irq))
1806 polarity &= ~BIT(irq);
1807 else
1808 polarity |= BIT(irq);
1809 writel(polarity,
1810 bank->reg_base + GPIO_INT_POLARITY);
1811
1812 spin_unlock_irqrestore(&bank->slock, flags);
1813
1814 data_old = data;
1815 data = readl_relaxed(bank->reg_base +
1816 GPIO_EXT_PORT);
1817 } while ((data & BIT(irq)) != (data_old & BIT(irq)));
5a927501
HS		 1818 }
1819
d3e51161
HS		 1820 generic_handle_irq(virq);
1821 }
1822
1823 chained_irq_exit(chip, desc);
1824}
1825
1826static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
1827{
1828 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1829 struct rockchip_pin_bank *bank = gc->private;
1830 u32 mask = BIT(d->hwirq);
1831 u32 polarity;
1832 u32 level;
1833 u32 data;
fab262f5 1834 unsigned long flags;
14797189 1835 int ret;
d3e51161 1836
5a927501 1837 /* make sure the pin is configured as gpio input */
14797189
HS		 1838 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
1839 if (ret < 0)
1840 return ret;
1841
07a06ae9 1842 clk_enable(bank->clk);
fab262f5
DA		 1843 spin_lock_irqsave(&bank->slock, flags);
1844
5a927501
HS		 1845 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1846 data &= ~mask;
1847 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1848
fab262f5
DA		 1849 spin_unlock_irqrestore(&bank->slock, flags);
1850
d3e51161 1851 if (type & IRQ_TYPE_EDGE_BOTH)
2dbf1bc5 1852 irq_set_handler_locked(d, handle_edge_irq);
d3e51161 1853 else
2dbf1bc5 1854 irq_set_handler_locked(d, handle_level_irq);
d3e51161 1855
fab262f5 1856 spin_lock_irqsave(&bank->slock, flags);
d3e51161
HS		 1857 irq_gc_lock(gc);
1858
1859 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
1860 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
1861
1862 switch (type) {
5a927501
HS		 1863 case IRQ_TYPE_EDGE_BOTH:
1864 bank->toggle_edge_mode |= mask;
1865 level |= mask;
1866
1867 /*
1868 * Determine gpio state. If 1 next interrupt should be falling
1869 * otherwise rising.
1870 */
1871 data = readl(bank->reg_base + GPIO_EXT_PORT);
1872 if (data & mask)
1873 polarity &= ~mask;
1874 else
1875 polarity |= mask;
1876 break;
d3e51161 1877 case IRQ_TYPE_EDGE_RISING:
5a927501 1878 bank->toggle_edge_mode &= ~mask;
d3e51161
HS		 1879 level |= mask;
1880 polarity |= mask;
1881 break;
1882 case IRQ_TYPE_EDGE_FALLING:
5a927501 1883 bank->toggle_edge_mode &= ~mask;
d3e51161
HS		 1884 level |= mask;
1885 polarity &= ~mask;
1886 break;
1887 case IRQ_TYPE_LEVEL_HIGH:
5a927501 1888 bank->toggle_edge_mode &= ~mask;
d3e51161
HS		 1889 level &= ~mask;
1890 polarity |= mask;
1891 break;
1892 case IRQ_TYPE_LEVEL_LOW:
5a927501 1893 bank->toggle_edge_mode &= ~mask;
d3e51161
HS		 1894 level &= ~mask;
1895 polarity &= ~mask;
1896 break;
1897 default:
7cc5f970 1898 irq_gc_unlock(gc);
fab262f5 1899 spin_unlock_irqrestore(&bank->slock, flags);
07a06ae9 1900 clk_disable(bank->clk);
d3e51161
HS		 1901 return -EINVAL;
1902 }
1903
1904 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
1905 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
1906
1907 irq_gc_unlock(gc);
fab262f5 1908 spin_unlock_irqrestore(&bank->slock, flags);
07a06ae9 1909 clk_disable(bank->clk);
d3e51161 1910
d3e51161
HS		 1911 return 0;
1912}
1913
68bda47c
DA		 1914static void rockchip_irq_suspend(struct irq_data *d)
1915{
1916 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1917 struct rockchip_pin_bank *bank = gc->private;
1918
07a06ae9 1919 clk_enable(bank->clk);
5ae0c7ad
DA		 1920 bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
1921 irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
07a06ae9 1922 clk_disable(bank->clk);
68bda47c
DA		 1923}
1924
1925static void rockchip_irq_resume(struct irq_data *d)
1926{
1927 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1928 struct rockchip_pin_bank *bank = gc->private;
1929
07a06ae9 1930 clk_enable(bank->clk);
5ae0c7ad 1931 irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
07a06ae9
LH		 1932 clk_disable(bank->clk);
1933}
1934
1935static void rockchip_irq_gc_mask_clr_bit(struct irq_data *d)
1936{
1937 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1938 struct rockchip_pin_bank *bank = gc->private;
1939
1940 clk_enable(bank->clk);
1941 irq_gc_mask_clr_bit(d);
1942}
1943
1944void rockchip_irq_gc_mask_set_bit(struct irq_data *d)
1945{
1946 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1947 struct rockchip_pin_bank *bank = gc->private;
1948
1949 irq_gc_mask_set_bit(d);
1950 clk_disable(bank->clk);
f2dd028c
DA		 1951}
1952
d3e51161
HS		 1953static int rockchip_interrupts_register(struct platform_device *pdev,
1954 struct rockchip_pinctrl *info)
1955{
1956 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1957 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1958 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
1959 struct irq_chip_generic *gc;
1960 int ret;
07a06ae9 1961 int i, j;
d3e51161
HS		 1962
1963 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1964 if (!bank->valid) {
1965 dev_warn(&pdev->dev, "bank %s is not valid\n",
1966 bank->name);
1967 continue;
1968 }
1969
07a06ae9
LH		 1970 ret = clk_enable(bank->clk);
1971 if (ret) {
1972 dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
1973 bank->name);
1974 continue;
1975 }
1976
d3e51161
HS		 1977 bank->domain = irq_domain_add_linear(bank->of_node, 32,
1978 &irq_generic_chip_ops, NULL);
1979 if (!bank->domain) {
1980 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
1981 bank->name);
07a06ae9 1982 clk_disable(bank->clk);
d3e51161
HS		 1983 continue;
1984 }
1985
1986 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
1987 "rockchip_gpio_irq", handle_level_irq,
1988 clr, 0, IRQ_GC_INIT_MASK_CACHE);
1989 if (ret) {
1990 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
1991 bank->name);
1992 irq_domain_remove(bank->domain);
07a06ae9 1993 clk_disable(bank->clk);
d3e51161
HS		 1994 continue;
1995 }
1996
5ae0c7ad
DA		 1997 /*
1998 * Linux assumes that all interrupts start out disabled/masked.
1999 * Our driver only uses the concept of masked and always keeps
2000 * things enabled, so for us that's all masked and all enabled.
2001 */
2002 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
2003 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
2004
d3e51161
HS		 2005 gc = irq_get_domain_generic_chip(bank->domain, 0);
2006 gc->reg_base = bank->reg_base;
2007 gc->private = bank;
f2dd028c 2008 gc->chip_types[0].regs.mask = GPIO_INTMASK;
d3e51161
HS		 2009 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
2010 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
07a06ae9
LH		 2011 gc->chip_types[0].chip.irq_mask = rockchip_irq_gc_mask_set_bit;
2012 gc->chip_types[0].chip.irq_unmask =
2013 rockchip_irq_gc_mask_clr_bit;
d3e51161 2014 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
68bda47c
DA		 2015 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
2016 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
d3e51161 2017 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
876d716b 2018 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
d3e51161 2019
03051bc2
TG		 2020 irq_set_chained_handler_and_data(bank->irq,
2021 rockchip_irq_demux, bank);
07a06ae9
LH		 2022
2023 /* map the gpio irqs here, when the clock is still running */
2024 for (j = 0 ; j < 32 ; j++)
2025 irq_create_mapping(bank->domain, j);
2026
2027 clk_disable(bank->clk);
d3e51161
HS		 2028 }
2029
2030 return 0;
2031}
2032
2033static int rockchip_gpiolib_register(struct platform_device *pdev,
2034 struct rockchip_pinctrl *info)
2035{
2036 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2037 struct rockchip_pin_bank *bank = ctrl->pin_banks;
2038 struct gpio_chip *gc;
2039 int ret;
2040 int i;
2041
2042 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2043 if (!bank->valid) {
2044 dev_warn(&pdev->dev, "bank %s is not valid\n",
2045 bank->name);
2046 continue;
2047 }
2048
2049 bank->gpio_chip = rockchip_gpiolib_chip;
2050
2051 gc = &bank->gpio_chip;
2052 gc->base = bank->pin_base;
2053 gc->ngpio = bank->nr_pins;
58383c78 2054 gc->parent = &pdev->dev;
d3e51161
HS		 2055 gc->of_node = bank->of_node;
2056 gc->label = bank->name;
2057
03bf81f1 2058 ret = gpiochip_add_data(gc, bank);
d3e51161
HS		 2059 if (ret) {
2060 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
2061 gc->label, ret);
2062 goto fail;
2063 }
2064 }
2065
2066 rockchip_interrupts_register(pdev, info);
2067
2068 return 0;
2069
2070fail:
2071 for (--i, --bank; i >= 0; --i, --bank) {
2072 if (!bank->valid)
2073 continue;
b4e7c55d 2074 gpiochip_remove(&bank->gpio_chip);
d3e51161
HS		 2075 }
2076 return ret;
2077}
2078
2079static int rockchip_gpiolib_unregister(struct platform_device *pdev,
2080 struct rockchip_pinctrl *info)
2081{
2082 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2083 struct rockchip_pin_bank *bank = ctrl->pin_banks;
d3e51161
HS		 2084 int i;
2085
b4e7c55d 2086 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
d3e51161
HS		 2087 if (!bank->valid)
2088 continue;
b4e7c55d 2089 gpiochip_remove(&bank->gpio_chip);
d3e51161
HS		 2090 }
2091
b4e7c55d 2092 return 0;
d3e51161
HS		 2093}
2094
2095static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
622f3237 2096 struct rockchip_pinctrl *info)
d3e51161
HS		 2097{
2098 struct resource res;
751a99ab 2099 void __iomem *base;
d3e51161
HS		 2100
2101 if (of_address_to_resource(bank->of_node, 0, &res)) {
622f3237 2102 dev_err(info->dev, "cannot find IO resource for bank\n");
d3e51161
HS		 2103 return -ENOENT;
2104 }
2105
622f3237 2106 bank->reg_base = devm_ioremap_resource(info->dev, &res);
d3e51161
HS		 2107 if (IS_ERR(bank->reg_base))
2108 return PTR_ERR(bank->reg_base);
2109
6ca5274d
HS		 2110 /*
2111 * special case, where parts of the pull setting-registers are
2112 * part of the PMU register space
2113 */
2114 if (of_device_is_compatible(bank->of_node,
2115 "rockchip,rk3188-gpio-bank0")) {
a658efaa 2116 struct device_node *node;
bfc7a42a 2117
a658efaa
HS		 2118 node = of_parse_phandle(bank->of_node->parent,
2119 "rockchip,pmu", 0);
2120 if (!node) {
2121 if (of_address_to_resource(bank->of_node, 1, &res)) {
2122 dev_err(info->dev, "cannot find IO resource for bank\n");
2123 return -ENOENT;
2124 }
2125
2126 base = devm_ioremap_resource(info->dev, &res);
2127 if (IS_ERR(base))
2128 return PTR_ERR(base);
2129 rockchip_regmap_config.max_register =
2130 resource_size(&res) - 4;
2131 rockchip_regmap_config.name =
2132 "rockchip,rk3188-gpio-bank0-pull";
2133 bank->regmap_pull = devm_regmap_init_mmio(info->dev,
2134 base,
2135 &rockchip_regmap_config);
6ca5274d 2136 }
6ca5274d 2137 }
65fca613 2138
d3e51161
HS		 2139 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
2140
2141 bank->clk = of_clk_get(bank->of_node, 0);
2142 if (IS_ERR(bank->clk))
2143 return PTR_ERR(bank->clk);
2144
07a06ae9 2145 return clk_prepare(bank->clk);
d3e51161
HS		 2146}
2147
2148static const struct of_device_id rockchip_pinctrl_dt_match[];
2149
2150/* retrieve the soc specific data */
2151static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
2152 struct rockchip_pinctrl *d,
2153 struct platform_device *pdev)
2154{
2155 const struct of_device_id *match;
2156 struct device_node *node = pdev->dev.of_node;
2157 struct device_node *np;
2158 struct rockchip_pin_ctrl *ctrl;
2159 struct rockchip_pin_bank *bank;
b6c23275 2160 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
d3e51161
HS		 2161
2162 match = of_match_node(rockchip_pinctrl_dt_match, node);
2163 ctrl = (struct rockchip_pin_ctrl *)match->data;
2164
2165 for_each_child_of_node(node, np) {
2166 if (!of_find_property(np, "gpio-controller", NULL))
2167 continue;
2168
2169 bank = ctrl->pin_banks;
2170 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2171 if (!strcmp(bank->name, np->name)) {
2172 bank->of_node = np;
2173
622f3237 2174 if (!rockchip_get_bank_data(bank, d))
d3e51161
HS		 2175 bank->valid = true;
2176
2177 break;
2178 }
2179 }
2180 }
2181
95ec8ae4
HS		 2182 grf_offs = ctrl->grf_mux_offset;
2183 pmu_offs = ctrl->pmu_mux_offset;
b6c23275
DW		 2184 drv_pmu_offs = ctrl->pmu_drv_offset;
2185 drv_grf_offs = ctrl->grf_drv_offset;
d3e51161
HS		 2186 bank = ctrl->pin_banks;
2187 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
6bc0d121
HS		 2188 int bank_pins = 0;
2189
d3e51161
HS		 2190 spin_lock_init(&bank->slock);
2191 bank->drvdata = d;
2192 bank->pin_base = ctrl->nr_pins;
2193 ctrl->nr_pins += bank->nr_pins;
6bc0d121 2194
b6c23275 2195 /* calculate iomux and drv offsets */
6bc0d121
HS		 2196 for (j = 0; j < 4; j++) {
2197 struct rockchip_iomux *iom = &bank->iomux[j];
b6c23275 2198 struct rockchip_drv *drv = &bank->drv[j];
03716e1d 2199 int inc;
6bc0d121
HS		 2200
2201 if (bank_pins >= bank->nr_pins)
2202 break;
2203
b6c23275 2204 /* preset iomux offset value, set new start value */
6bc0d121 2205 if (iom->offset >= 0) {
95ec8ae4
HS		 2206 if (iom->type & IOMUX_SOURCE_PMU)
2207 pmu_offs = iom->offset;
2208 else
2209 grf_offs = iom->offset;
b6c23275 2210 } else { /* set current iomux offset */
95ec8ae4
HS		 2211 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
2212 pmu_offs : grf_offs;
6bc0d121
HS		 2213 }
2214
b6c23275
DW		 2215 /* preset drv offset value, set new start value */
2216 if (drv->offset >= 0) {
2217 if (iom->type & IOMUX_SOURCE_PMU)
2218 drv_pmu_offs = drv->offset;
2219 else
2220 drv_grf_offs = drv->offset;
2221 } else { /* set current drv offset */
2222 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
2223 drv_pmu_offs : drv_grf_offs;
2224 }
2225
2226 dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
2227 i, j, iom->offset, drv->offset);
6bc0d121
HS		 2228
2229 /*
2230 * Increase offset according to iomux width.
03716e1d 2231 * 4bit iomux'es are spread over two registers.
6bc0d121 2232 */
03716e1d 2233 inc = (iom->type & IOMUX_WIDTH_4BIT) ? 8 : 4;
95ec8ae4
HS		 2234 if (iom->type & IOMUX_SOURCE_PMU)
2235 pmu_offs += inc;
2236 else
2237 grf_offs += inc;
6bc0d121 2238
b6c23275
DW		 2239 /*
2240 * Increase offset according to drv width.
2241 * 3bit drive-strenth'es are spread over two registers.
2242 */
2243 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
2244 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
2245 inc = 8;
2246 else
2247 inc = 4;
2248
2249 if (iom->type & IOMUX_SOURCE_PMU)
2250 drv_pmu_offs += inc;
2251 else
2252 drv_grf_offs += inc;
2253
6bc0d121
HS		 2254 bank_pins += 8;
2255 }
d3e51161
HS		 2256 }
2257
2258 return ctrl;
2259}
2260
8dca9331
CZ		 2261#define RK3288_GRF_GPIO6C_IOMUX 0x64
2262#define GPIO6C6_SEL_WRITE_ENABLE BIT(28)
2263
2264static u32 rk3288_grf_gpio6c_iomux;
2265
9198f509
CZ		 2266static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
2267{
2268 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
8dca9331
CZ		 2269 int ret = pinctrl_force_sleep(info->pctl_dev);
2270
2271 if (ret)
2272 return ret;
2273
2274 /*
2275 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
2276 * the setting here, and restore it at resume.
2277 */
2278 if (info->ctrl->type == RK3288) {
2279 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
2280 &rk3288_grf_gpio6c_iomux);
2281 if (ret) {
2282 pinctrl_force_default(info->pctl_dev);
2283 return ret;
2284 }
2285 }
9198f509 2286
8dca9331 2287 return 0;
9198f509
CZ		 2288}
2289
2290static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
2291{
2292 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
8dca9331
CZ		 2293 int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
2294 rk3288_grf_gpio6c_iomux |
2295 GPIO6C6_SEL_WRITE_ENABLE);
2296
2297 if (ret)
2298 return ret;
9198f509
CZ		 2299
2300 return pinctrl_force_default(info->pctl_dev);
2301}
2302
2303static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
2304 rockchip_pinctrl_resume);
2305
d3e51161
HS		 2306static int rockchip_pinctrl_probe(struct platform_device *pdev)
2307{
2308 struct rockchip_pinctrl *info;
2309 struct device *dev = &pdev->dev;
2310 struct rockchip_pin_ctrl *ctrl;
14dee867 2311 struct device_node *np = pdev->dev.of_node, *node;
d3e51161 2312 struct resource *res;
751a99ab 2313 void __iomem *base;
d3e51161
HS		 2314 int ret;
2315
2316 if (!dev->of_node) {
2317 dev_err(dev, "device tree node not found\n");
2318 return -ENODEV;
2319 }
2320
2321 info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
2322 if (!info)
2323 return -ENOMEM;
2324
622f3237
HS		 2325 info->dev = dev;
2326
d3e51161
HS		 2327 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
2328 if (!ctrl) {
2329 dev_err(dev, "driver data not available\n");
2330 return -EINVAL;
2331 }
2332 info->ctrl = ctrl;
d3e51161 2333
1e747e59
HS		 2334 node = of_parse_phandle(np, "rockchip,grf", 0);
2335 if (node) {
2336 info->regmap_base = syscon_node_to_regmap(node);
2337 if (IS_ERR(info->regmap_base))
2338 return PTR_ERR(info->regmap_base);
2339 } else {
2340 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
751a99ab
HS		 2341 base = devm_ioremap_resource(&pdev->dev, res);
2342 if (IS_ERR(base))
2343 return PTR_ERR(base);
2344
2345 rockchip_regmap_config.max_register = resource_size(res) - 4;
1e747e59
HS		 2346 rockchip_regmap_config.name = "rockchip,pinctrl";
2347 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
2348 &rockchip_regmap_config);
2349
2350 /* to check for the old dt-bindings */
2351 info->reg_size = resource_size(res);
2352
2353 /* Honor the old binding, with pull registers as 2nd resource */
2354 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
2355 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2356 base = devm_ioremap_resource(&pdev->dev, res);
2357 if (IS_ERR(base))
2358 return PTR_ERR(base);
2359
2360 rockchip_regmap_config.max_register =
2361 resource_size(res) - 4;
2362 rockchip_regmap_config.name = "rockchip,pinctrl-pull";
2363 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
2364 base,
2365 &rockchip_regmap_config);
2366 }
6ca5274d
HS		 2367 }
2368
14dee867
HS		 2369 /* try to find the optional reference to the pmu syscon */
2370 node = of_parse_phandle(np, "rockchip,pmu", 0);
2371 if (node) {
2372 info->regmap_pmu = syscon_node_to_regmap(node);
2373 if (IS_ERR(info->regmap_pmu))
2374 return PTR_ERR(info->regmap_pmu);
2375 }
2376
d3e51161
HS		 2377 ret = rockchip_gpiolib_register(pdev, info);
2378 if (ret)
2379 return ret;
2380
2381 ret = rockchip_pinctrl_register(pdev, info);
2382 if (ret) {
2383 rockchip_gpiolib_unregister(pdev, info);
2384 return ret;
2385 }
2386
2387 platform_set_drvdata(pdev, info);
2388
2389 return 0;
2390}
2391
2392static struct rockchip_pin_bank rk2928_pin_banks[] = {
2393 PIN_BANK(0, 32, "gpio0"),
2394 PIN_BANK(1, 32, "gpio1"),
2395 PIN_BANK(2, 32, "gpio2"),
2396 PIN_BANK(3, 32, "gpio3"),
2397};
2398
2399static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
2400 .pin_banks = rk2928_pin_banks,
2401 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
2402 .label = "RK2928-GPIO",
a282926d 2403 .type = RK2928,
95ec8ae4 2404 .grf_mux_offset = 0xa8,
a282926d 2405 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
d3e51161
HS		 2406};
2407
c5ce7670
XZ		 2408static struct rockchip_pin_bank rk3036_pin_banks[] = {
2409 PIN_BANK(0, 32, "gpio0"),
2410 PIN_BANK(1, 32, "gpio1"),
2411 PIN_BANK(2, 32, "gpio2"),
2412};
2413
2414static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
2415 .pin_banks = rk3036_pin_banks,
2416 .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
2417 .label = "RK3036-GPIO",
2418 .type = RK2928,
2419 .grf_mux_offset = 0xa8,
2420 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
2421};
2422
d3e51161
HS		 2423static struct rockchip_pin_bank rk3066a_pin_banks[] = {
2424 PIN_BANK(0, 32, "gpio0"),
2425 PIN_BANK(1, 32, "gpio1"),
2426 PIN_BANK(2, 32, "gpio2"),
2427 PIN_BANK(3, 32, "gpio3"),
2428 PIN_BANK(4, 32, "gpio4"),
2429 PIN_BANK(6, 16, "gpio6"),
2430};
2431
2432static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
2433 .pin_banks = rk3066a_pin_banks,
2434 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
2435 .label = "RK3066a-GPIO",
a282926d 2436 .type = RK2928,
95ec8ae4 2437 .grf_mux_offset = 0xa8,
a282926d 2438 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
d3e51161
HS		 2439};
2440
2441static struct rockchip_pin_bank rk3066b_pin_banks[] = {
2442 PIN_BANK(0, 32, "gpio0"),
2443 PIN_BANK(1, 32, "gpio1"),
2444 PIN_BANK(2, 32, "gpio2"),
2445 PIN_BANK(3, 32, "gpio3"),
2446};
2447
2448static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
2449 .pin_banks = rk3066b_pin_banks,
2450 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
2451 .label = "RK3066b-GPIO",
a282926d 2452 .type = RK3066B,
95ec8ae4 2453 .grf_mux_offset = 0x60,
d3e51161
HS		 2454};
2455
2456static struct rockchip_pin_bank rk3188_pin_banks[] = {
fc72c923 2457 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
d3e51161
HS		 2458 PIN_BANK(1, 32, "gpio1"),
2459 PIN_BANK(2, 32, "gpio2"),
2460 PIN_BANK(3, 32, "gpio3"),
2461};
2462
2463static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
2464 .pin_banks = rk3188_pin_banks,
2465 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
2466 .label = "RK3188-GPIO",
a282926d 2467 .type = RK3188,
95ec8ae4 2468 .grf_mux_offset = 0x60,
6ca5274d 2469 .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
d3e51161
HS		 2470};
2471
fea0fe60
JC		 2472static struct rockchip_pin_bank rk3228_pin_banks[] = {
2473 PIN_BANK(0, 32, "gpio0"),
2474 PIN_BANK(1, 32, "gpio1"),
2475 PIN_BANK(2, 32, "gpio2"),
2476 PIN_BANK(3, 32, "gpio3"),
2477};
2478
2479static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
2480 .pin_banks = rk3228_pin_banks,
2481 .nr_banks = ARRAY_SIZE(rk3228_pin_banks),
2482 .label = "RK3228-GPIO",
2483 .type = RK3288,
2484 .grf_mux_offset = 0x0,
2485 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
2486 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
2487};
2488
304f077d
HS		 2489static struct rockchip_pin_bank rk3288_pin_banks[] = {
2490 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
2491 IOMUX_SOURCE_PMU,
2492 IOMUX_SOURCE_PMU,
2493 IOMUX_UNROUTED
2494 ),
2495 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
2496 IOMUX_UNROUTED,
2497 IOMUX_UNROUTED,
2498 0
2499 ),
2500 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
2501 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
2502 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
2503 IOMUX_WIDTH_4BIT,
2504 0,
2505 0
2506 ),
2507 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
2508 0,
2509 0,
2510 IOMUX_UNROUTED
2511 ),
2512 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
2513 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
2514 0,
2515 IOMUX_WIDTH_4BIT,
2516 IOMUX_UNROUTED
2517 ),
2518 PIN_BANK(8, 16, "gpio8"),
2519};
2520
2521static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
2522 .pin_banks = rk3288_pin_banks,
2523 .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
2524 .label = "RK3288-GPIO",
66d750e1 2525 .type = RK3288,
304f077d
HS		 2526 .grf_mux_offset = 0x0,
2527 .pmu_mux_offset = 0x84,
2528 .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
ef17f69f 2529 .drv_calc_reg = rk3288_calc_drv_reg_and_bit,
304f077d
HS		 2530};
2531
daecdc66
HS		 2532static struct rockchip_pin_bank rk3368_pin_banks[] = {
2533 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
2534 IOMUX_SOURCE_PMU,
2535 IOMUX_SOURCE_PMU,
2536 IOMUX_SOURCE_PMU
2537 ),
2538 PIN_BANK(1, 32, "gpio1"),
2539 PIN_BANK(2, 32, "gpio2"),
2540 PIN_BANK(3, 32, "gpio3"),
2541};
2542
2543static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
2544 .pin_banks = rk3368_pin_banks,
2545 .nr_banks = ARRAY_SIZE(rk3368_pin_banks),
2546 .label = "RK3368-GPIO",
2547 .type = RK3368,
2548 .grf_mux_offset = 0x0,
2549 .pmu_mux_offset = 0x0,
2550 .pull_calc_reg = rk3368_calc_pull_reg_and_bit,
2551 .drv_calc_reg = rk3368_calc_drv_reg_and_bit,
2552};
2553
b6c23275
DW		 2554static struct rockchip_pin_bank rk3399_pin_banks[] = {
2555 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(0, 32, "gpio0", IOMUX_SOURCE_PMU,
2556 IOMUX_SOURCE_PMU,
2557 IOMUX_SOURCE_PMU,
2558 IOMUX_SOURCE_PMU,
2559 DRV_TYPE_IO_1V8_ONLY,
2560 DRV_TYPE_IO_1V8_ONLY,
2561 DRV_TYPE_IO_DEFAULT,
2562 DRV_TYPE_IO_DEFAULT,
2563 0x0,
2564 0x8,
2565 -1,
2566 -1
2567 ),
2568 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
2569 IOMUX_SOURCE_PMU,
2570 IOMUX_SOURCE_PMU,
2571 IOMUX_SOURCE_PMU,
2572 DRV_TYPE_IO_1V8_OR_3V0,
2573 DRV_TYPE_IO_1V8_OR_3V0,
2574 DRV_TYPE_IO_1V8_OR_3V0,
2575 DRV_TYPE_IO_1V8_OR_3V0,
2576 0x20,
2577 0x28,
2578 0x30,
2579 0x38
2580 ),
2581 PIN_BANK_DRV_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
2582 DRV_TYPE_IO_1V8_OR_3V0,
2583 DRV_TYPE_IO_1V8_ONLY,
2584 DRV_TYPE_IO_1V8_ONLY
2585 ),
2586 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
2587 DRV_TYPE_IO_3V3_ONLY,
2588 DRV_TYPE_IO_3V3_ONLY,
2589 DRV_TYPE_IO_1V8_OR_3V0
2590 ),
2591 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
2592 DRV_TYPE_IO_1V8_3V0_AUTO,
2593 DRV_TYPE_IO_1V8_OR_3V0,
2594 DRV_TYPE_IO_1V8_OR_3V0
2595 ),
2596};
2597
2598static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
2599 .pin_banks = rk3399_pin_banks,
2600 .nr_banks = ARRAY_SIZE(rk3399_pin_banks),
2601 .label = "RK3399-GPIO",
2602 .type = RK3399,
2603 .grf_mux_offset = 0xe000,
2604 .pmu_mux_offset = 0x0,
2605 .grf_drv_offset = 0xe100,
2606 .pmu_drv_offset = 0x80,
2607 .pull_calc_reg = rk3399_calc_pull_reg_and_bit,
2608 .drv_calc_reg = rk3399_calc_drv_reg_and_bit,
2609};
daecdc66 2610
d3e51161
HS		 2611static const struct of_device_id rockchip_pinctrl_dt_match[] = {
2612 { .compatible = "rockchip,rk2928-pinctrl",
2613 .data = (void *)&rk2928_pin_ctrl },
c5ce7670
XZ		 2614 { .compatible = "rockchip,rk3036-pinctrl",
2615 .data = (void *)&rk3036_pin_ctrl },
d3e51161
HS		 2616 { .compatible = "rockchip,rk3066a-pinctrl",
2617 .data = (void *)&rk3066a_pin_ctrl },
2618 { .compatible = "rockchip,rk3066b-pinctrl",
2619 .data = (void *)&rk3066b_pin_ctrl },
2620 { .compatible = "rockchip,rk3188-pinctrl",
2621 .data = (void *)&rk3188_pin_ctrl },
fea0fe60
JC		 2622 { .compatible = "rockchip,rk3228-pinctrl",
2623 .data = (void *)&rk3228_pin_ctrl },
304f077d
HS		 2624 { .compatible = "rockchip,rk3288-pinctrl",
2625 .data = (void *)&rk3288_pin_ctrl },
daecdc66
HS		 2626 { .compatible = "rockchip,rk3368-pinctrl",
2627 .data = (void *)&rk3368_pin_ctrl },
b6c23275
DW		 2628 { .compatible = "rockchip,rk3399-pinctrl",
2629 .data = (void *)&rk3399_pin_ctrl },
d3e51161
HS		 2630 {},
2631};
2632MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
2633
2634static struct platform_driver rockchip_pinctrl_driver = {
2635 .probe = rockchip_pinctrl_probe,
2636 .driver = {
2637 .name = "rockchip-pinctrl",
9198f509 2638 .pm = &rockchip_pinctrl_dev_pm_ops,
0be9e70d 2639 .of_match_table = rockchip_pinctrl_dt_match,
d3e51161
HS		 2640 },
2641};
2642
2643static int __init rockchip_pinctrl_drv_register(void)
2644{
2645 return platform_driver_register(&rockchip_pinctrl_driver);
2646}
2647postcore_initcall(rockchip_pinctrl_drv_register);
2648
2649MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
2650MODULE_DESCRIPTION("Rockchip pinctrl driver");
2651MODULE_LICENSE("GPL v2");