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pinctrl/abx500: align GPIO cluster boundaries
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / pinctrl / pinctrl-abx500.c
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0493e649
PC		 1/*
2 * Copyright (C) ST-Ericsson SA 2013
3 *
4 * Author: Patrice Chotard <patrice.chotard@st.com>
5 * License terms: GNU General Public License (GPL) version 2
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/slab.h>
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/err.h>
17#include <linux/platform_device.h>
18#include <linux/gpio.h>
19#include <linux/irq.h>
20#include <linux/interrupt.h>
21#include <linux/bitops.h>
22#include <linux/mfd/abx500.h>
23#include <linux/mfd/abx500/ab8500.h>
24#include <linux/mfd/abx500/ab8500-gpio.h>
25#include <linux/pinctrl/pinctrl.h>
26#include <linux/pinctrl/consumer.h>
27#include <linux/pinctrl/pinmux.h>
28#include <linux/pinctrl/pinconf.h>
29#include <linux/pinctrl/pinconf-generic.h>
30
31#include "pinctrl-abx500.h"
32
33/*
34 * The AB9540 and AB8540 GPIO support are extended versions
35 * of the AB8500 GPIO support.
36 * The AB9540 supports an additional (7th) register so that
37 * more GPIO may be configured and used.
38 * The AB8540 supports 4 new gpios (GPIOx_VBAT) that have
39 * internal pull-up and pull-down capabilities.
40 */
41
42/*
43 * GPIO registers offset
44 * Bank: 0x10
45 */
46#define AB8500_GPIO_SEL1_REG 0x00
47#define AB8500_GPIO_SEL2_REG 0x01
48#define AB8500_GPIO_SEL3_REG 0x02
49#define AB8500_GPIO_SEL4_REG 0x03
50#define AB8500_GPIO_SEL5_REG 0x04
51#define AB8500_GPIO_SEL6_REG 0x05
52#define AB9540_GPIO_SEL7_REG 0x06
53
54#define AB8500_GPIO_DIR1_REG 0x10
55#define AB8500_GPIO_DIR2_REG 0x11
56#define AB8500_GPIO_DIR3_REG 0x12
57#define AB8500_GPIO_DIR4_REG 0x13
58#define AB8500_GPIO_DIR5_REG 0x14
59#define AB8500_GPIO_DIR6_REG 0x15
60#define AB9540_GPIO_DIR7_REG 0x16
61
62#define AB8500_GPIO_OUT1_REG 0x20
63#define AB8500_GPIO_OUT2_REG 0x21
64#define AB8500_GPIO_OUT3_REG 0x22
65#define AB8500_GPIO_OUT4_REG 0x23
66#define AB8500_GPIO_OUT5_REG 0x24
67#define AB8500_GPIO_OUT6_REG 0x25
68#define AB9540_GPIO_OUT7_REG 0x26
69
70#define AB8500_GPIO_PUD1_REG 0x30
71#define AB8500_GPIO_PUD2_REG 0x31
72#define AB8500_GPIO_PUD3_REG 0x32
73#define AB8500_GPIO_PUD4_REG 0x33
74#define AB8500_GPIO_PUD5_REG 0x34
75#define AB8500_GPIO_PUD6_REG 0x35
76#define AB9540_GPIO_PUD7_REG 0x36
77
78#define AB8500_GPIO_IN1_REG 0x40
79#define AB8500_GPIO_IN2_REG 0x41
80#define AB8500_GPIO_IN3_REG 0x42
81#define AB8500_GPIO_IN4_REG 0x43
82#define AB8500_GPIO_IN5_REG 0x44
83#define AB8500_GPIO_IN6_REG 0x45
84#define AB9540_GPIO_IN7_REG 0x46
85#define AB8540_GPIO_VINSEL_REG 0x47
86#define AB8540_GPIO_PULL_UPDOWN_REG 0x48
87#define AB8500_GPIO_ALTFUN_REG 0x50
88#define AB8500_NUM_VIR_GPIO_IRQ 16
89#define AB8540_GPIO_PULL_UPDOWN_MASK 0x03
90#define AB8540_GPIO_VINSEL_MASK 0x03
91#define AB8540_GPIOX_VBAT_START 51
92#define AB8540_GPIOX_VBAT_END 54
93
94enum abx500_gpio_action {
95 NONE,
96 STARTUP,
97 SHUTDOWN,
98 MASK,
99 UNMASK
100};
101
102struct abx500_pinctrl {
103 struct device *dev;
104 struct pinctrl_dev *pctldev;
105 struct abx500_pinctrl_soc_data *soc;
106 struct gpio_chip chip;
107 struct ab8500 *parent;
108 struct mutex lock;
109 u32 irq_base;
110 enum abx500_gpio_action irq_action;
111 u16 rising;
112 u16 falling;
113 struct abx500_gpio_irq_cluster *irq_cluster;
114 int irq_cluster_size;
115 int irq_gpio_rising_offset;
116 int irq_gpio_falling_offset;
117 int irq_gpio_factor;
118};
119
120/**
121 * to_abx500_pinctrl() - get the pointer to abx500_pinctrl
122 * @chip: Member of the structure abx500_pinctrl
123 */
124static inline struct abx500_pinctrl *to_abx500_pinctrl(struct gpio_chip *chip)
125{
126 return container_of(chip, struct abx500_pinctrl, chip);
127}
128
129static int abx500_gpio_get_bit(struct gpio_chip *chip, u8 reg,
83b423c8 130 unsigned offset, bool *bit)
0493e649
PC		 131{
132 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
133 u8 pos = offset % 8;
134 u8 val;
135 int ret;
136
137 reg += offset / 8;
138 ret = abx500_get_register_interruptible(pct->dev,
139 AB8500_MISC, reg, &val);
140
141 *bit = !!(val & BIT(pos));
142
143 if (ret < 0)
144 dev_err(pct->dev,
145 "%s read reg =%x, offset=%x failed\n",
146 __func__, reg, offset);
147
148 return ret;
149}
150
151static int abx500_gpio_set_bits(struct gpio_chip *chip, u8 reg,
83b423c8 152 unsigned offset, int val)
0493e649
PC		 153{
154 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
155 u8 pos = offset % 8;
156 int ret;
157
158 reg += offset / 8;
159 ret = abx500_mask_and_set_register_interruptible(pct->dev,
49dcf086 160 AB8500_MISC, reg, BIT(pos), val << pos);
0493e649
PC		 161 if (ret < 0)
162 dev_err(pct->dev, "%s write failed\n", __func__);
83b423c8 163
0493e649
PC		 164 return ret;
165}
83b423c8 166
0493e649
PC		 167/**
168 * abx500_gpio_get() - Get the particular GPIO value
83b423c8
LJ		 169 * @chip: Gpio device
170 * @offset: GPIO number to read
0493e649
PC		 171 */
172static int abx500_gpio_get(struct gpio_chip *chip, unsigned offset)
173{
174 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
175 bool bit;
176 int ret;
177
178 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_IN1_REG,
179 offset, &bit);
180 if (ret < 0) {
181 dev_err(pct->dev, "%s failed\n", __func__);
182 return ret;
183 }
83b423c8 184
0493e649
PC		 185 return bit;
186}
187
188static void abx500_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
189{
190 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
191 int ret;
192
193 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val);
194 if (ret < 0)
195 dev_err(pct->dev, "%s write failed\n", __func__);
196}
197
198static int abx500_config_pull_updown(struct abx500_pinctrl *pct,
83b423c8 199 int offset, enum abx500_gpio_pull_updown val)
0493e649
PC		 200{
201 u8 pos;
202 int ret;
203 struct pullud *pullud;
204
205 if (!pct->soc->pullud) {
206 dev_err(pct->dev, "%s AB chip doesn't support pull up/down feature",
207 __func__);
208 ret = -EPERM;
209 goto out;
210 }
211
212 pullud = pct->soc->pullud;
213
214 if ((offset < pullud->first_pin)
215 || (offset > pullud->last_pin)) {
216 ret = -EINVAL;
217 goto out;
218 }
219
220 pos = offset << 1;
221
222 ret = abx500_mask_and_set_register_interruptible(pct->dev,
223 AB8500_MISC, AB8540_GPIO_PULL_UPDOWN_REG,
224 AB8540_GPIO_PULL_UPDOWN_MASK << pos, val << pos);
225
226out:
227 if (ret < 0)
228 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
83b423c8 229
0493e649
PC		 230 return ret;
231}
232
233static int abx500_gpio_direction_output(struct gpio_chip *chip,
234 unsigned offset,
235 int val)
236{
237 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
238 struct pullud *pullud = pct->soc->pullud;
239 unsigned gpio;
240 int ret;
83b423c8 241
0493e649
PC		 242 /* set direction as output */
243 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_DIR1_REG, offset, 1);
244 if (ret < 0)
245 return ret;
246
247 /* disable pull down */
248 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG, offset, 1);
249 if (ret < 0)
250 return ret;
251
252 /* if supported, disable both pull down and pull up */
253 gpio = offset + 1;
254 if (pullud && gpio >= pullud->first_pin && gpio <= pullud->last_pin) {
255 ret = abx500_config_pull_updown(pct,
256 gpio,
257 ABX500_GPIO_PULL_NONE);
258 if (ret < 0)
259 return ret;
260 }
83b423c8 261
0493e649
PC		 262 /* set the output as 1 or 0 */
263 return abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val);
264}
265
266static int abx500_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
267{
268 /* set the register as input */
269 return abx500_gpio_set_bits(chip, AB8500_GPIO_DIR1_REG, offset, 0);
270}
271
272static int abx500_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
273{
274 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
b9fab6e4
LJ		 275 /* The AB8500 GPIO numbers are off by one */
276 int gpio = offset + 1;
0493e649
PC		 277 int base = pct->irq_base;
278 int i;
279
280 for (i = 0; i < pct->irq_cluster_size; i++) {
281 struct abx500_gpio_irq_cluster *cluster =
282 &pct->irq_cluster[i];
283
b9fab6e4
LJ		 284 if (gpio >= cluster->start && gpio <= cluster->end)
285 return base + gpio - cluster->start;
0493e649
PC		 286
287 /* Advance by the number of gpios in this cluster */
288 base += cluster->end + cluster->offset - cluster->start + 1;
289 }
290
291 return -EINVAL;
292}
293
294static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
83b423c8 295 unsigned gpio, int alt_setting)
0493e649
PC		 296{
297 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
298 struct alternate_functions af = pct->soc->alternate_functions[gpio];
299 int ret;
300 int val;
301 unsigned offset;
83b423c8 302
0493e649
PC		 303 const char *modes[] = {
304 [ABX500_DEFAULT] = "default",
305 [ABX500_ALT_A] = "altA",
306 [ABX500_ALT_B] = "altB",
307 [ABX500_ALT_C] = "altC",
308 };
309
310 /* sanity check */
311 if (((alt_setting == ABX500_ALT_A) && (af.gpiosel_bit == UNUSED)) ||
312 ((alt_setting == ABX500_ALT_B) && (af.alt_bit1 == UNUSED)) ||
313 ((alt_setting == ABX500_ALT_C) && (af.alt_bit2 == UNUSED))) {
314 dev_dbg(pct->dev, "pin %d doesn't support %s mode\n", gpio,
315 modes[alt_setting]);
316 return -EINVAL;
317 }
318
319 /* on ABx5xx, there is no GPIO0, so adjust the offset */
320 offset = gpio - 1;
83b423c8 321
0493e649
PC		 322 switch (alt_setting) {
323 case ABX500_DEFAULT:
324 /*
325 * for ABx5xx family, default mode is always selected by
326 * writing 0 to GPIOSELx register, except for pins which
327 * support at least ALT_B mode, default mode is selected
328 * by writing 1 to GPIOSELx register
329 */
330 val = 0;
331 if (af.alt_bit1 != UNUSED)
332 val++;
333
334 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
335 offset, val);
336 break;
83b423c8 337
0493e649
PC		 338 case ABX500_ALT_A:
339 /*
340 * for ABx5xx family, alt_a mode is always selected by
341 * writing 1 to GPIOSELx register, except for pins which
342 * support at least ALT_B mode, alt_a mode is selected
343 * by writing 0 to GPIOSELx register and 0 in ALTFUNC
344 * register
345 */
346 if (af.alt_bit1 != UNUSED) {
347 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
348 offset, 0);
349 ret = abx500_gpio_set_bits(chip,
350 AB8500_GPIO_ALTFUN_REG,
351 af.alt_bit1,
352 !!(af.alta_val && BIT(0)));
353 if (af.alt_bit2 != UNUSED)
354 ret = abx500_gpio_set_bits(chip,
355 AB8500_GPIO_ALTFUN_REG,
356 af.alt_bit2,
357 !!(af.alta_val && BIT(1)));
358 } else
359 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
360 offset, 1);
361 break;
83b423c8 362
0493e649
PC		 363 case ABX500_ALT_B:
364 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
365 offset, 0);
366 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
367 af.alt_bit1, !!(af.altb_val && BIT(0)));
368 if (af.alt_bit2 != UNUSED)
369 ret = abx500_gpio_set_bits(chip,
370 AB8500_GPIO_ALTFUN_REG,
371 af.alt_bit2,
372 !!(af.altb_val && BIT(1)));
373 break;
83b423c8 374
0493e649
PC		 375 case ABX500_ALT_C:
376 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
377 offset, 0);
378 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
379 af.alt_bit2, !!(af.altc_val && BIT(0)));
380 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
381 af.alt_bit2, !!(af.altc_val && BIT(1)));
382 break;
383
384 default:
385 dev_dbg(pct->dev, "unknow alt_setting %d\n", alt_setting);
83b423c8 386
0493e649
PC		 387 return -EINVAL;
388 }
83b423c8 389
0493e649
PC		 390 return ret;
391}
392
393static u8 abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
83b423c8 394 unsigned gpio)
0493e649
PC		 395{
396 u8 mode;
397 bool bit_mode;
398 bool alt_bit1;
399 bool alt_bit2;
400 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
401 struct alternate_functions af = pct->soc->alternate_functions[gpio];
402
403 /*
404 * if gpiosel_bit is set to unused,
405 * it means no GPIO or special case
406 */
407 if (af.gpiosel_bit == UNUSED)
408 return ABX500_DEFAULT;
409
410 /* read GpioSelx register */
411 abx500_gpio_get_bit(chip, AB8500_GPIO_SEL1_REG + (gpio / 8),
412 af.gpiosel_bit, &bit_mode);
413 mode = bit_mode;
414
415 /* sanity check */
416 if ((af.alt_bit1 < UNUSED) || (af.alt_bit1 > 7) ||
417 (af.alt_bit2 < UNUSED) || (af.alt_bit2 > 7)) {
418 dev_err(pct->dev,
419 "alt_bitX value not in correct range (-1 to 7)\n");
420 return -EINVAL;
421 }
83b423c8 422
0493e649
PC		 423 /* if alt_bit2 is used, alt_bit1 must be used too */
424 if ((af.alt_bit2 != UNUSED) && (af.alt_bit1 == UNUSED)) {
425 dev_err(pct->dev,
426 "if alt_bit2 is used, alt_bit1 can't be unused\n");
427 return -EINVAL;
428 }
429
430 /* check if pin use AlternateFunction register */
431 if ((af.alt_bit1 == UNUSED) && (af.alt_bit1 == UNUSED))
432 return mode;
433 /*
434 * if pin GPIOSEL bit is set and pin supports alternate function,
435 * it means DEFAULT mode
436 */
437 if (mode)
438 return ABX500_DEFAULT;
83b423c8 439
0493e649
PC		 440 /*
441 * pin use the AlternatFunction register
442 * read alt_bit1 value
443 */
444 abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG,
445 af.alt_bit1, &alt_bit1);
446
447 if (af.alt_bit2 != UNUSED)
448 /* read alt_bit2 value */
449 abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG, af.alt_bit2,
450 &alt_bit2);
451 else
452 alt_bit2 = 0;
453
454 mode = (alt_bit2 << 1) + alt_bit1;
455 if (mode == af.alta_val)
456 return ABX500_ALT_A;
457 else if (mode == af.altb_val)
458 return ABX500_ALT_B;
459 else
460 return ABX500_ALT_C;
461}
462
463#ifdef CONFIG_DEBUG_FS
464
465#include <linux/seq_file.h>
466
467static void abx500_gpio_dbg_show_one(struct seq_file *s,
83b423c8
LJ		 468 struct pinctrl_dev *pctldev,
469 struct gpio_chip *chip,
470 unsigned offset, unsigned gpio)
0493e649
PC		 471{
472 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
473 const char *label = gpiochip_is_requested(chip, offset - 1);
474 u8 gpio_offset = offset - 1;
475 int mode = -1;
476 bool is_out;
477 bool pull;
83b423c8 478
0493e649
PC		 479 const char *modes[] = {
480 [ABX500_DEFAULT] = "default",
481 [ABX500_ALT_A] = "altA",
482 [ABX500_ALT_B] = "altB",
483 [ABX500_ALT_C] = "altC",
484 };
485
486 abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG, gpio_offset, &is_out);
487 abx500_gpio_get_bit(chip, AB8500_GPIO_PUD1_REG, gpio_offset, &pull);
488
489 if (pctldev)
490 mode = abx500_get_mode(pctldev, chip, offset);
491
492 seq_printf(s, " gpio-%-3d (%-20.20s) %-3s %-9s %s",
493 gpio, label ?: "(none)",
494 is_out ? "out" : "in ",
495 is_out ?
496 (chip->get
497 ? (chip->get(chip, offset) ? "hi" : "lo")
498 : "? ")
499 : (pull ? "pull up" : "pull down"),
500 (mode < 0) ? "unknown" : modes[mode]);
501
502 if (label && !is_out) {
503 int irq = gpio_to_irq(gpio);
504 struct irq_desc *desc = irq_to_desc(irq);
505
506 if (irq >= 0 && desc->action) {
507 char *trigger;
508 int irq_offset = irq - pct->irq_base;
509
510 if (pct->rising & BIT(irq_offset))
511 trigger = "edge-rising";
512 else if (pct->falling & BIT(irq_offset))
513 trigger = "edge-falling";
514 else
515 trigger = "edge-undefined";
516
517 seq_printf(s, " irq-%d %s", irq, trigger);
518 }
519 }
520}
521
522static void abx500_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
523{
524 unsigned i;
525 unsigned gpio = chip->base;
526 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
527 struct pinctrl_dev *pctldev = pct->pctldev;
528
529 for (i = 0; i < chip->ngpio; i++, gpio++) {
530 /* On AB8500, there is no GPIO0, the first is the GPIO 1 */
531 abx500_gpio_dbg_show_one(s, pctldev, chip, i + 1, gpio);
532 seq_printf(s, "\n");
533 }
534}
535
536#else
537static inline void abx500_gpio_dbg_show_one(struct seq_file *s,
83b423c8
LJ		 538 struct pinctrl_dev *pctldev,
539 struct gpio_chip *chip,
540 unsigned offset, unsigned gpio)
0493e649
PC		 541{
542}
543#define abx500_gpio_dbg_show NULL
544#endif
545
546int abx500_gpio_request(struct gpio_chip *chip, unsigned offset)
547{
548 int gpio = chip->base + offset;
549
550 return pinctrl_request_gpio(gpio);
551}
552
553void abx500_gpio_free(struct gpio_chip *chip, unsigned offset)
554{
555 int gpio = chip->base + offset;
556
557 pinctrl_free_gpio(gpio);
558}
559
560static struct gpio_chip abx500gpio_chip = {
561 .label = "abx500-gpio",
562 .owner = THIS_MODULE,
563 .request = abx500_gpio_request,
564 .free = abx500_gpio_free,
565 .direction_input = abx500_gpio_direction_input,
566 .get = abx500_gpio_get,
567 .direction_output = abx500_gpio_direction_output,
568 .set = abx500_gpio_set,
569 .to_irq = abx500_gpio_to_irq,
570 .dbg_show = abx500_gpio_dbg_show,
571};
572
573static unsigned int irq_to_rising(unsigned int irq)
574{
575 struct abx500_pinctrl *pct = irq_get_chip_data(irq);
576 int offset = irq - pct->irq_base;
577 int new_irq;
578
579 new_irq = offset * pct->irq_gpio_factor
580 + pct->irq_gpio_rising_offset
581 + pct->parent->irq_base;
582
583 return new_irq;
584}
585
586static unsigned int irq_to_falling(unsigned int irq)
587{
588 struct abx500_pinctrl *pct = irq_get_chip_data(irq);
589 int offset = irq - pct->irq_base;
590 int new_irq;
591
592 new_irq = offset * pct->irq_gpio_factor
593 + pct->irq_gpio_falling_offset
594 + pct->parent->irq_base;
595 return new_irq;
596
597}
598
599static unsigned int rising_to_irq(unsigned int irq, void *dev)
600{
601 struct abx500_pinctrl *pct = dev;
602 int offset, new_irq;
603
604 offset = irq - pct->irq_gpio_rising_offset
605 - pct->parent->irq_base;
606 new_irq = (offset / pct->irq_gpio_factor)
607 + pct->irq_base;
608
609 return new_irq;
610}
611
612static unsigned int falling_to_irq(unsigned int irq, void *dev)
613{
614 struct abx500_pinctrl *pct = dev;
615 int offset, new_irq;
616
617 offset = irq - pct->irq_gpio_falling_offset
618 - pct->parent->irq_base;
619 new_irq = (offset / pct->irq_gpio_factor)
620 + pct->irq_base;
621
622 return new_irq;
623}
624
625/*
626 * IRQ handler
627 */
628
629static irqreturn_t handle_rising(int irq, void *dev)
630{
631
632 handle_nested_irq(rising_to_irq(irq , dev));
633 return IRQ_HANDLED;
634}
635
636static irqreturn_t handle_falling(int irq, void *dev)
637{
638
639 handle_nested_irq(falling_to_irq(irq, dev));
640 return IRQ_HANDLED;
641}
642
643static void abx500_gpio_irq_lock(struct irq_data *data)
644{
645 struct abx500_pinctrl *pct = irq_data_get_irq_chip_data(data);
646 mutex_lock(&pct->lock);
647}
648
649static void abx500_gpio_irq_sync_unlock(struct irq_data *data)
650{
651 struct abx500_pinctrl *pct = irq_data_get_irq_chip_data(data);
652 unsigned int irq = data->irq;
653 int offset = irq - pct->irq_base;
654 bool rising = pct->rising & BIT(offset);
655 bool falling = pct->falling & BIT(offset);
656 int ret;
657
658 switch (pct->irq_action) {
659 case STARTUP:
660 if (rising)
661 ret = request_threaded_irq(irq_to_rising(irq),
662 NULL, handle_rising,
663 IRQF_TRIGGER_RISING | IRQF_NO_SUSPEND,
664 "abx500-gpio-r", pct);
665 if (falling)
666 ret = request_threaded_irq(irq_to_falling(irq),
667 NULL, handle_falling,
668 IRQF_TRIGGER_FALLING | IRQF_NO_SUSPEND,
669 "abx500-gpio-f", pct);
670 break;
671 case SHUTDOWN:
672 if (rising)
673 free_irq(irq_to_rising(irq), pct);
674 if (falling)
675 free_irq(irq_to_falling(irq), pct);
676 break;
677 case MASK:
678 if (rising)
679 disable_irq(irq_to_rising(irq));
680 if (falling)
681 disable_irq(irq_to_falling(irq));
682 break;
683 case UNMASK:
684 if (rising)
685 enable_irq(irq_to_rising(irq));
686 if (falling)
687 enable_irq(irq_to_falling(irq));
688 break;
689 case NONE:
690 break;
691 }
692 pct->irq_action = NONE;
693 pct->rising &= ~(BIT(offset));
694 pct->falling &= ~(BIT(offset));
695 mutex_unlock(&pct->lock);
696}
697
698
699static void abx500_gpio_irq_mask(struct irq_data *data)
700{
701 struct abx500_pinctrl *pct = irq_data_get_irq_chip_data(data);
702 pct->irq_action = MASK;
703}
704
705static void abx500_gpio_irq_unmask(struct irq_data *data)
706{
707 struct abx500_pinctrl *pct = irq_data_get_irq_chip_data(data);
708 pct->irq_action = UNMASK;
709}
710
711static int abx500_gpio_irq_set_type(struct irq_data *data, unsigned int type)
712{
713 struct abx500_pinctrl *pct = irq_data_get_irq_chip_data(data);
714 unsigned int irq = data->irq;
715 int offset = irq - pct->irq_base;
716
717 if (type == IRQ_TYPE_EDGE_BOTH) {
718 pct->rising = BIT(offset);
719 pct->falling = BIT(offset);
720 } else if (type == IRQ_TYPE_EDGE_RISING) {
721 pct->rising = BIT(offset);
722 } else {
723 pct->falling = BIT(offset);
724 }
725 return 0;
726}
727
728static unsigned int abx500_gpio_irq_startup(struct irq_data *data)
729{
730 struct abx500_pinctrl *pct = irq_data_get_irq_chip_data(data);
731 pct->irq_action = STARTUP;
732 return 0;
733}
734
735static void abx500_gpio_irq_shutdown(struct irq_data *data)
736{
737 struct abx500_pinctrl *pct = irq_data_get_irq_chip_data(data);
738 pct->irq_action = SHUTDOWN;
739}
740
741static struct irq_chip abx500_gpio_irq_chip = {
742 .name = "abx500-gpio",
743 .irq_startup = abx500_gpio_irq_startup,
744 .irq_shutdown = abx500_gpio_irq_shutdown,
745 .irq_bus_lock = abx500_gpio_irq_lock,
746 .irq_bus_sync_unlock = abx500_gpio_irq_sync_unlock,
747 .irq_mask = abx500_gpio_irq_mask,
748 .irq_unmask = abx500_gpio_irq_unmask,
749 .irq_set_type = abx500_gpio_irq_set_type,
750};
751
752static int abx500_gpio_irq_init(struct abx500_pinctrl *pct)
753{
754 u32 base = pct->irq_base;
755 int irq;
756
757 for (irq = base; irq < base + AB8500_NUM_VIR_GPIO_IRQ ; irq++) {
758 irq_set_chip_data(irq, pct);
759 irq_set_chip_and_handler(irq, &abx500_gpio_irq_chip,
760 handle_simple_irq);
761 irq_set_nested_thread(irq, 1);
762#ifdef CONFIG_ARM
763 set_irq_flags(irq, IRQF_VALID);
764#else
765 irq_set_noprobe(irq);
766#endif
767 }
768
769 return 0;
770}
771
772static void abx500_gpio_irq_remove(struct abx500_pinctrl *pct)
773{
774 int base = pct->irq_base;
775 int irq;
776
777 for (irq = base; irq < base + AB8500_NUM_VIR_GPIO_IRQ; irq++) {
778#ifdef CONFIG_ARM
779 set_irq_flags(irq, 0);
780#endif
781 irq_set_chip_and_handler(irq, NULL, NULL);
782 irq_set_chip_data(irq, NULL);
783 }
784}
785
786static int abx500_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
787{
788 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
789
790 return pct->soc->nfunctions;
791}
792
793static const char *abx500_pmx_get_func_name(struct pinctrl_dev *pctldev,
794 unsigned function)
795{
796 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
797
798 return pct->soc->functions[function].name;
799}
800
801static int abx500_pmx_get_func_groups(struct pinctrl_dev *pctldev,
83b423c8
LJ		 802 unsigned function,
803 const char * const **groups,
804 unsigned * const num_groups)
0493e649
PC		 805{
806 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
807
808 *groups = pct->soc->functions[function].groups;
809 *num_groups = pct->soc->functions[function].ngroups;
810
811 return 0;
812}
813
814static void abx500_disable_lazy_irq(struct gpio_chip *chip, unsigned gpio)
815{
816 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
817 int irq;
818 int offset;
819 bool rising;
820 bool falling;
821
822 /*
823 * check if gpio has interrupt capability and convert
824 * gpio number to irq
825 * On ABx5xx, there is no GPIO0, GPIO1 is the
826 * first one, so adjust gpio number
827 */
828 gpio--;
829 irq = gpio_to_irq(gpio + chip->base);
830 if (irq < 0)
831 return;
832
833 offset = irq - pct->irq_base;
834 rising = pct->rising & BIT(offset);
835 falling = pct->falling & BIT(offset);
836
837 /* nothing to do ?*/
838 if (!rising && !falling)
839 return;
840
841 if (rising) {
842 disable_irq(irq_to_rising(irq));
843 free_irq(irq_to_rising(irq), pct);
844 }
845 if (falling) {
846 disable_irq(irq_to_falling(irq));
847 free_irq(irq_to_falling(irq), pct);
848 }
849}
850
851static int abx500_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
83b423c8 852 unsigned group)
0493e649
PC		 853{
854 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
855 struct gpio_chip *chip = &pct->chip;
856 const struct abx500_pingroup *g;
857 int i;
858 int ret = 0;
859
860 g = &pct->soc->groups[group];
861 if (g->altsetting < 0)
862 return -EINVAL;
863
864 dev_dbg(pct->dev, "enable group %s, %u pins\n", g->name, g->npins);
865
866 for (i = 0; i < g->npins; i++) {
867 dev_dbg(pct->dev, "setting pin %d to altsetting %d\n",
868 g->pins[i], g->altsetting);
869
870 abx500_disable_lazy_irq(chip, g->pins[i]);
871 ret = abx500_set_mode(pctldev, chip, g->pins[i], g->altsetting);
872 }
83b423c8 873
0493e649
PC		 874 return ret;
875}
876
877static void abx500_pmx_disable(struct pinctrl_dev *pctldev,
83b423c8 878 unsigned function, unsigned group)
0493e649
PC		 879{
880 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
881 const struct abx500_pingroup *g;
882
883 g = &pct->soc->groups[group];
884 if (g->altsetting < 0)
885 return;
886
887 /* FIXME: poke out the mux, set the pin to some default state? */
888 dev_dbg(pct->dev, "disable group %s, %u pins\n", g->name, g->npins);
889}
890
891int abx500_gpio_request_enable(struct pinctrl_dev *pctldev,
83b423c8
LJ		 892 struct pinctrl_gpio_range *range,
893 unsigned offset)
0493e649
PC		 894{
895 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
896 const struct abx500_pinrange *p;
897 int ret;
898 int i;
899
900 /*
901 * Different ranges have different ways to enable GPIO function on a
902 * pin, so refer back to our local range type, where we handily define
903 * what altfunc enables GPIO for a certain pin.
904 */
905 for (i = 0; i < pct->soc->gpio_num_ranges; i++) {
906 p = &pct->soc->gpio_ranges[i];
907 if ((offset >= p->offset) &&
908 (offset < (p->offset + p->npins)))
909 break;
910 }
911
912 if (i == pct->soc->gpio_num_ranges) {
913 dev_err(pct->dev, "%s failed to locate range\n", __func__);
914 return -ENODEV;
915 }
916
917 dev_dbg(pct->dev, "enable GPIO by altfunc %d at gpio %d\n",
918 p->altfunc, offset);
919
920 ret = abx500_set_mode(pct->pctldev, &pct->chip,
921 offset, p->altfunc);
922 if (ret < 0) {
923 dev_err(pct->dev, "%s setting altfunc failed\n", __func__);
924 return ret;
925 }
926
927 return ret;
928}
929
930static void abx500_gpio_disable_free(struct pinctrl_dev *pctldev,
83b423c8
LJ		 931 struct pinctrl_gpio_range *range,
932 unsigned offset)
0493e649
PC		 933{
934}
935
936static struct pinmux_ops abx500_pinmux_ops = {
937 .get_functions_count = abx500_pmx_get_funcs_cnt,
938 .get_function_name = abx500_pmx_get_func_name,
939 .get_function_groups = abx500_pmx_get_func_groups,
940 .enable = abx500_pmx_enable,
941 .disable = abx500_pmx_disable,
942 .gpio_request_enable = abx500_gpio_request_enable,
943 .gpio_disable_free = abx500_gpio_disable_free,
944};
945
946static int abx500_get_groups_cnt(struct pinctrl_dev *pctldev)
947{
948 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
949
950 return pct->soc->ngroups;
951}
952
953static const char *abx500_get_group_name(struct pinctrl_dev *pctldev,
83b423c8 954 unsigned selector)
0493e649
PC		 955{
956 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
957
958 return pct->soc->groups[selector].name;
959}
960
961static int abx500_get_group_pins(struct pinctrl_dev *pctldev,
83b423c8
LJ		 962 unsigned selector,
963 const unsigned **pins,
964 unsigned *num_pins)
0493e649
PC		 965{
966 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
967
968 *pins = pct->soc->groups[selector].pins;
969 *num_pins = pct->soc->groups[selector].npins;
83b423c8 970
0493e649
PC		 971 return 0;
972}
973
974static void abx500_pin_dbg_show(struct pinctrl_dev *pctldev,
83b423c8 975 struct seq_file *s, unsigned offset)
0493e649
PC		 976{
977 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
978 struct gpio_chip *chip = &pct->chip;
979
980 abx500_gpio_dbg_show_one(s, pctldev, chip, offset,
981 chip->base + offset - 1);
982}
983
984static struct pinctrl_ops abx500_pinctrl_ops = {
985 .get_groups_count = abx500_get_groups_cnt,
986 .get_group_name = abx500_get_group_name,
987 .get_group_pins = abx500_get_group_pins,
988 .pin_dbg_show = abx500_pin_dbg_show,
989};
990
991int abx500_pin_config_get(struct pinctrl_dev *pctldev,
83b423c8
LJ		 992 unsigned pin,
993 unsigned long *config)
0493e649 994{
1abeebea 995 return -ENOSYS;
0493e649
PC		 996}
997
998int abx500_pin_config_set(struct pinctrl_dev *pctldev,
83b423c8
LJ		 999 unsigned pin,
1000 unsigned long config)
0493e649
PC		 1001{
1002 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
1003 struct pullud *pullud = pct->soc->pullud;
1004 struct gpio_chip *chip = &pct->chip;
1005 unsigned offset;
1006 int ret;
1007 enum pin_config_param param = pinconf_to_config_param(config);
1008 enum pin_config_param argument = pinconf_to_config_argument(config);
1009
1010 dev_dbg(chip->dev, "pin %d [%#lx]: %s %s\n",
1011 pin, config, (param == PIN_CONFIG_OUTPUT) ? "output " : "input",
1012 (param == PIN_CONFIG_OUTPUT) ? (argument ? "high" : "low") :
1013 (argument ? "pull up" : "pull down"));
83b423c8 1014
0493e649
PC		 1015 /* on ABx500, there is no GPIO0, so adjust the offset */
1016 offset = pin - 1;
1017
1018 switch (param) {
1019 case PIN_CONFIG_BIAS_PULL_DOWN:
1020 /*
1021 * if argument = 1 set the pull down
1022 * else clear the pull down
1023 */
1024 ret = abx500_gpio_direction_input(chip, offset);
1025 /*
1026 * Some chips only support pull down, while some actually
1027 * support both pull up and pull down. Such chips have
1028 * a "pullud" range specified for the pins that support
1029 * both features. If the pin is not within that range, we
1030 * fall back to the old bit set that only support pull down.
1031 */
1032 if (pullud &&
1033 pin >= pullud->first_pin &&
1034 pin <= pullud->last_pin)
1035 ret = abx500_config_pull_updown(pct,
1036 pin,
1037 argument ? ABX500_GPIO_PULL_DOWN : ABX500_GPIO_PULL_NONE);
1038 else
1039 /* Chip only supports pull down */
1040 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG,
1041 offset, argument ? 0 : 1);
1042 break;
83b423c8 1043
0493e649
PC		 1044 case PIN_CONFIG_OUTPUT:
1045 ret = abx500_gpio_direction_output(chip, offset, argument);
83b423c8 1046
0493e649 1047 break;
83b423c8 1048
0493e649
PC		 1049 default:
1050 dev_err(chip->dev, "illegal configuration requested\n");
83b423c8 1051
0493e649
PC		 1052 return -EINVAL;
1053 }
83b423c8 1054
0493e649
PC		 1055 return ret;
1056}
1057
1058static struct pinconf_ops abx500_pinconf_ops = {
1059 .pin_config_get = abx500_pin_config_get,
1060 .pin_config_set = abx500_pin_config_set,
1061};
1062
1063static struct pinctrl_desc abx500_pinctrl_desc = {
1064 .name = "pinctrl-abx500",
1065 .pctlops = &abx500_pinctrl_ops,
1066 .pmxops = &abx500_pinmux_ops,
1067 .confops = &abx500_pinconf_ops,
1068 .owner = THIS_MODULE,
1069};
1070
1071static int abx500_get_gpio_num(struct abx500_pinctrl_soc_data *soc)
1072{
1073 unsigned int lowest = 0;
1074 unsigned int highest = 0;
1075 unsigned int npins = 0;
1076 int i;
1077
1078 /*
1079 * Compute number of GPIOs from the last SoC gpio range descriptors
1080 * These ranges may include "holes" but the GPIO number space shall
1081 * still be homogeneous, so we need to detect and account for any
1082 * such holes so that these are included in the number of GPIO pins.
1083 */
1084 for (i = 0; i < soc->gpio_num_ranges; i++) {
1085 unsigned gstart;
1086 unsigned gend;
1087 const struct abx500_pinrange *p;
1088
1089 p = &soc->gpio_ranges[i];
1090 gstart = p->offset;
1091 gend = p->offset + p->npins - 1;
1092
1093 if (i == 0) {
1094 /* First iteration, set start values */
1095 lowest = gstart;
1096 highest = gend;
1097 } else {
1098 if (gstart < lowest)
1099 lowest = gstart;
1100 if (gend > highest)
1101 highest = gend;
1102 }
1103 }
1104 /* this gives the absolute number of pins */
1105 npins = highest - lowest + 1;
1106 return npins;
1107}
1108
1109static int abx500_gpio_probe(struct platform_device *pdev)
1110{
1111 struct ab8500_platform_data *abx500_pdata =
1112 dev_get_platdata(pdev->dev.parent);
1113 struct abx500_gpio_platform_data *pdata;
1114 struct abx500_pinctrl *pct;
1115 const struct platform_device_id *platid = platform_get_device_id(pdev);
fa1ec996 1116 int ret, err;
0493e649
PC		 1117 int i;
1118
1119 pdata = abx500_pdata->gpio;
83b423c8 1120 if (!pdata) {
0493e649
PC		 1121 dev_err(&pdev->dev, "gpio platform data missing\n");
1122 return -ENODEV;
1123 }
1124
1125 pct = devm_kzalloc(&pdev->dev, sizeof(struct abx500_pinctrl),
1126 GFP_KERNEL);
1127 if (pct == NULL) {
1128 dev_err(&pdev->dev,
1129 "failed to allocate memory for pct\n");
1130 return -ENOMEM;
1131 }
1132
1133 pct->dev = &pdev->dev;
1134 pct->parent = dev_get_drvdata(pdev->dev.parent);
1135 pct->chip = abx500gpio_chip;
1136 pct->chip.dev = &pdev->dev;
1137 pct->chip.base = pdata->gpio_base;
1138 pct->irq_base = pdata->irq_base;
1139
1140 /* initialize the lock */
1141 mutex_init(&pct->lock);
1142
1143 /* Poke in other ASIC variants here */
1144 switch (platid->driver_data) {
3c937993
PC		 1145 case PINCTRL_AB8500:
1146 abx500_pinctrl_ab8500_init(&pct->soc);
1147 break;
a8f96e41
PC		 1148 case PINCTRL_AB8540:
1149 abx500_pinctrl_ab8540_init(&pct->soc);
1150 break;
09dbec3f
PC		 1151 case PINCTRL_AB9540:
1152 abx500_pinctrl_ab9540_init(&pct->soc);
1153 break;
1aa2d8d4
PC		 1154 case PINCTRL_AB8505:
1155 abx500_pinctrl_ab8505_init(&pct->soc);
1156 break;
0493e649
PC		 1157 default:
1158 dev_err(&pdev->dev, "Unsupported pinctrl sub driver (%d)\n",
1159 (int) platid->driver_data);
d41e35c3 1160 mutex_destroy(&pct->lock);
0493e649
PC		 1161 return -EINVAL;
1162 }
1163
1164 if (!pct->soc) {
1165 dev_err(&pdev->dev, "Invalid SOC data\n");
d41e35c3 1166 mutex_destroy(&pct->lock);
0493e649
PC		 1167 return -EINVAL;
1168 }
1169
1170 pct->chip.ngpio = abx500_get_gpio_num(pct->soc);
1171 pct->irq_cluster = pct->soc->gpio_irq_cluster;
1172 pct->irq_cluster_size = pct->soc->ngpio_irq_cluster;
1173 pct->irq_gpio_rising_offset = pct->soc->irq_gpio_rising_offset;
1174 pct->irq_gpio_falling_offset = pct->soc->irq_gpio_falling_offset;
1175 pct->irq_gpio_factor = pct->soc->irq_gpio_factor;
1176
1177 ret = abx500_gpio_irq_init(pct);
1178 if (ret)
1179 goto out_free;
1180 ret = gpiochip_add(&pct->chip);
1181 if (ret) {
83b423c8 1182 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
d41e35c3 1183 mutex_destroy(&pct->lock);
0493e649
PC		 1184 goto out_rem_irq;
1185 }
1186 dev_info(&pdev->dev, "added gpiochip\n");
1187
1188 abx500_pinctrl_desc.pins = pct->soc->pins;
1189 abx500_pinctrl_desc.npins = pct->soc->npins;
1190 pct->pctldev = pinctrl_register(&abx500_pinctrl_desc, &pdev->dev, pct);
1191 if (!pct->pctldev) {
1192 dev_err(&pdev->dev,
1193 "could not register abx500 pinctrl driver\n");
fa1ec996 1194 ret = -EINVAL;
0493e649
PC		 1195 goto out_rem_chip;
1196 }
1197 dev_info(&pdev->dev, "registered pin controller\n");
1198
1199 /* We will handle a range of GPIO pins */
1200 for (i = 0; i < pct->soc->gpio_num_ranges; i++) {
1201 const struct abx500_pinrange *p = &pct->soc->gpio_ranges[i];
1202
1203 ret = gpiochip_add_pin_range(&pct->chip,
1204 dev_name(&pdev->dev),
1205 p->offset - 1, p->offset, p->npins);
1206 if (ret < 0)
fa1ec996 1207 goto out_rem_chip;
0493e649
PC		 1208 }
1209
1210 platform_set_drvdata(pdev, pct);
1211 dev_info(&pdev->dev, "initialized abx500 pinctrl driver\n");
1212
1213 return 0;
1214
1215out_rem_chip:
fa1ec996
LJ		 1216 err = gpiochip_remove(&pct->chip);
1217 if (err)
0493e649
PC		 1218 dev_info(&pdev->dev, "failed to remove gpiochip\n");
1219out_rem_irq:
1220 abx500_gpio_irq_remove(pct);
1221out_free:
1222 mutex_destroy(&pct->lock);
1223 return ret;
1224}
1225
83b423c8 1226/**
0493e649 1227 * abx500_gpio_remove() - remove Ab8500-gpio driver
83b423c8 1228 * @pdev: Platform device registered
0493e649
PC		 1229 */
1230static int abx500_gpio_remove(struct platform_device *pdev)
1231{
1232 struct abx500_pinctrl *pct = platform_get_drvdata(pdev);
1233 int ret;
1234
1235 ret = gpiochip_remove(&pct->chip);
1236 if (ret < 0) {
1237 dev_err(pct->dev, "unable to remove gpiochip: %d\n",
1238 ret);
1239 return ret;
1240 }
1241
1242 mutex_destroy(&pct->lock);
1243
1244 return 0;
1245}
1246
1247static const struct platform_device_id abx500_pinctrl_id[] = {
1248 { "pinctrl-ab8500", PINCTRL_AB8500 },
1249 { "pinctrl-ab8540", PINCTRL_AB8540 },
1250 { "pinctrl-ab9540", PINCTRL_AB9540 },
1251 { "pinctrl-ab8505", PINCTRL_AB8505 },
1252 { },
1253};
1254
1255static struct platform_driver abx500_gpio_driver = {
1256 .driver = {
1257 .name = "abx500-gpio",
1258 .owner = THIS_MODULE,
1259 },
1260 .probe = abx500_gpio_probe,
1261 .remove = abx500_gpio_remove,
1262 .id_table = abx500_pinctrl_id,
1263};
1264
1265static int __init abx500_gpio_init(void)
1266{
1267 return platform_driver_register(&abx500_gpio_driver);
1268}
1269core_initcall(abx500_gpio_init);
1270
1271MODULE_AUTHOR("Patrice Chotard <patrice.chotard@st.com>");
1272MODULE_DESCRIPTION("Driver allows to use AxB5xx unused pins to be used as GPIO");
1273MODULE_ALIAS("platform:abx500-gpio");
1274MODULE_LICENSE("GPL v2");
kernel source for telekom puls (alcatel/mediatek)