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Merge tag 'mfd-3.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / pinctrl / mvebu / pinctrl-mvebu.c
CommitLineData
7e8d9415
SH		 1/*
2 * Marvell MVEBU pinctrl core driver
3 *
4 * Authors: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
5 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#include <linux/platform_device.h>
14#include <linux/module.h>
15#include <linux/slab.h>
16#include <linux/io.h>
17#include <linux/of.h>
18#include <linux/of_address.h>
19#include <linux/of_platform.h>
20#include <linux/err.h>
21#include <linux/gpio.h>
22#include <linux/pinctrl/machine.h>
23#include <linux/pinctrl/pinconf.h>
24#include <linux/pinctrl/pinctrl.h>
25#include <linux/pinctrl/pinmux.h>
26
7e8d9415
SH		 27#include "pinctrl-mvebu.h"
28
29#define MPPS_PER_REG 8
30#define MPP_BITS 4
31#define MPP_MASK 0xf
32
33struct mvebu_pinctrl_function {
34 const char *name;
35 const char **groups;
36 unsigned num_groups;
37};
38
39struct mvebu_pinctrl_group {
40 const char *name;
41 struct mvebu_mpp_ctrl *ctrl;
42 struct mvebu_mpp_ctrl_setting *settings;
43 unsigned num_settings;
44 unsigned gid;
45 unsigned *pins;
46 unsigned npins;
47};
48
49struct mvebu_pinctrl {
50 struct device *dev;
51 struct pinctrl_dev *pctldev;
52 struct pinctrl_desc desc;
53 void __iomem *base;
54 struct mvebu_pinctrl_group *groups;
55 unsigned num_groups;
56 struct mvebu_pinctrl_function *functions;
57 unsigned num_functions;
58 u8 variant;
59};
60
61static struct mvebu_pinctrl_group *mvebu_pinctrl_find_group_by_pid(
62 struct mvebu_pinctrl *pctl, unsigned pid)
63{
64 unsigned n;
65 for (n = 0; n < pctl->num_groups; n++) {
66 if (pid >= pctl->groups[n].pins[0] &&
67 pid < pctl->groups[n].pins[0] +
68 pctl->groups[n].npins)
69 return &pctl->groups[n];
70 }
71 return NULL;
72}
73
74static struct mvebu_pinctrl_group *mvebu_pinctrl_find_group_by_name(
75 struct mvebu_pinctrl *pctl, const char *name)
76{
77 unsigned n;
78 for (n = 0; n < pctl->num_groups; n++) {
79 if (strcmp(name, pctl->groups[n].name) == 0)
80 return &pctl->groups[n];
81 }
82 return NULL;
83}
84
85static struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_setting_by_val(
86 struct mvebu_pinctrl *pctl, struct mvebu_pinctrl_group *grp,
87 unsigned long config)
88{
89 unsigned n;
90 for (n = 0; n < grp->num_settings; n++) {
91 if (config == grp->settings[n].val) {
92 if (!pctl->variant || (pctl->variant &
93 grp->settings[n].variant))
94 return &grp->settings[n];
95 }
96 }
97 return NULL;
98}
99
100static struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_setting_by_name(
101 struct mvebu_pinctrl *pctl, struct mvebu_pinctrl_group *grp,
102 const char *name)
103{
104 unsigned n;
105 for (n = 0; n < grp->num_settings; n++) {
106 if (strcmp(name, grp->settings[n].name) == 0) {
107 if (!pctl->variant || (pctl->variant &
108 grp->settings[n].variant))
109 return &grp->settings[n];
110 }
111 }
112 return NULL;
113}
114
115static struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_gpio_setting(
116 struct mvebu_pinctrl *pctl, struct mvebu_pinctrl_group *grp)
117{
118 unsigned n;
119 for (n = 0; n < grp->num_settings; n++) {
120 if (grp->settings[n].flags &
121 (MVEBU_SETTING_GPO | MVEBU_SETTING_GPI)) {
122 if (!pctl->variant || (pctl->variant &
123 grp->settings[n].variant))
124 return &grp->settings[n];
125 }
126 }
127 return NULL;
128}
129
130static struct mvebu_pinctrl_function *mvebu_pinctrl_find_function_by_name(
131 struct mvebu_pinctrl *pctl, const char *name)
132{
133 unsigned n;
134 for (n = 0; n < pctl->num_functions; n++) {
135 if (strcmp(name, pctl->functions[n].name) == 0)
136 return &pctl->functions[n];
137 }
138 return NULL;
139}
140
141/*
142 * Common mpp pin configuration registers on MVEBU are
143 * registers of eight 4-bit values for each mpp setting.
144 * Register offset and bit mask are calculated accordingly below.
145 */
146static int mvebu_common_mpp_get(struct mvebu_pinctrl *pctl,
147 struct mvebu_pinctrl_group *grp,
148 unsigned long *config)
149{
150 unsigned pin = grp->gid;
151 unsigned off = (pin / MPPS_PER_REG) * MPP_BITS;
152 unsigned shift = (pin % MPPS_PER_REG) * MPP_BITS;
153
154 *config = readl(pctl->base + off);
155 *config >>= shift;
156 *config &= MPP_MASK;
157
158 return 0;
159}
160
161static int mvebu_common_mpp_set(struct mvebu_pinctrl *pctl,
162 struct mvebu_pinctrl_group *grp,
163 unsigned long config)
164{
165 unsigned pin = grp->gid;
166 unsigned off = (pin / MPPS_PER_REG) * MPP_BITS;
167 unsigned shift = (pin % MPPS_PER_REG) * MPP_BITS;
168 unsigned long reg;
169
170 reg = readl(pctl->base + off);
171 reg &= ~(MPP_MASK << shift);
172 reg |= (config << shift);
173 writel(reg, pctl->base + off);
174
175 return 0;
176}
177
178static int mvebu_pinconf_group_get(struct pinctrl_dev *pctldev,
179 unsigned gid, unsigned long *config)
180{
181 struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
182 struct mvebu_pinctrl_group *grp = &pctl->groups[gid];
183
184 if (!grp->ctrl)
185 return -EINVAL;
186
187 if (grp->ctrl->mpp_get)
188 return grp->ctrl->mpp_get(grp->ctrl, config);
189
190 return mvebu_common_mpp_get(pctl, grp, config);
191}
192
193static int mvebu_pinconf_group_set(struct pinctrl_dev *pctldev,
194 unsigned gid, unsigned long config)
195{
196 struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
197 struct mvebu_pinctrl_group *grp = &pctl->groups[gid];
198
199 if (!grp->ctrl)
200 return -EINVAL;
201
202 if (grp->ctrl->mpp_set)
203 return grp->ctrl->mpp_set(grp->ctrl, config);
204
205 return mvebu_common_mpp_set(pctl, grp, config);
206}
207
208static void mvebu_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
209 struct seq_file *s, unsigned gid)
210{
211 struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
212 struct mvebu_pinctrl_group *grp = &pctl->groups[gid];
213 struct mvebu_mpp_ctrl_setting *curr;
214 unsigned long config;
215 unsigned n;
216
217 if (mvebu_pinconf_group_get(pctldev, gid, &config))
218 return;
219
220 curr = mvebu_pinctrl_find_setting_by_val(pctl, grp, config);
221
222 if (curr) {
223 seq_printf(s, "current: %s", curr->name);
224 if (curr->subname)
225 seq_printf(s, "(%s)", curr->subname);
226 if (curr->flags & (MVEBU_SETTING_GPO | MVEBU_SETTING_GPI)) {
227 seq_printf(s, "(");
228 if (curr->flags & MVEBU_SETTING_GPI)
229 seq_printf(s, "i");
230 if (curr->flags & MVEBU_SETTING_GPO)
231 seq_printf(s, "o");
232 seq_printf(s, ")");
233 }
234 } else
235 seq_printf(s, "current: UNKNOWN");
236
237 if (grp->num_settings > 1) {
238 seq_printf(s, ", available = [");
239 for (n = 0; n < grp->num_settings; n++) {
240 if (curr == &grp->settings[n])
241 continue;
242
243 /* skip unsupported settings for this variant */
244 if (pctl->variant &&
245 !(pctl->variant & grp->settings[n].variant))
246 continue;
247
248 seq_printf(s, " %s", grp->settings[n].name);
249 if (grp->settings[n].subname)
250 seq_printf(s, "(%s)", grp->settings[n].subname);
251 if (grp->settings[n].flags &
252 (MVEBU_SETTING_GPO | MVEBU_SETTING_GPI)) {
253 seq_printf(s, "(");
254 if (grp->settings[n].flags & MVEBU_SETTING_GPI)
255 seq_printf(s, "i");
256 if (grp->settings[n].flags & MVEBU_SETTING_GPO)
257 seq_printf(s, "o");
258 seq_printf(s, ")");
259 }
260 }
261 seq_printf(s, " ]");
262 }
263 return;
264}
265
022ab148 266static const struct pinconf_ops mvebu_pinconf_ops = {
7e8d9415
SH		 267 .pin_config_group_get = mvebu_pinconf_group_get,
268 .pin_config_group_set = mvebu_pinconf_group_set,
269 .pin_config_group_dbg_show = mvebu_pinconf_group_dbg_show,
270};
271
272static int mvebu_pinmux_get_funcs_count(struct pinctrl_dev *pctldev)
273{
274 struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
275
276 return pctl->num_functions;
277}
278
279static const char *mvebu_pinmux_get_func_name(struct pinctrl_dev *pctldev,
280 unsigned fid)
281{
282 struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
283
284 return pctl->functions[fid].name;
285}
286
287static int mvebu_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned fid,
288 const char * const **groups,
289 unsigned * const num_groups)
290{
291 struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
292
293 *groups = pctl->functions[fid].groups;
294 *num_groups = pctl->functions[fid].num_groups;
295 return 0;
296}
297
298static int mvebu_pinmux_enable(struct pinctrl_dev *pctldev, unsigned fid,
299 unsigned gid)
300{
301 struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
302 struct mvebu_pinctrl_function *func = &pctl->functions[fid];
303 struct mvebu_pinctrl_group *grp = &pctl->groups[gid];
304 struct mvebu_mpp_ctrl_setting *setting;
305 int ret;
306
307 setting = mvebu_pinctrl_find_setting_by_name(pctl, grp,
308 func->name);
309 if (!setting) {
310 dev_err(pctl->dev,
311 "unable to find setting %s in group %s\n",
312 func->name, func->groups[gid]);
313 return -EINVAL;
314 }
315
316 ret = mvebu_pinconf_group_set(pctldev, grp->gid, setting->val);
317 if (ret) {
318 dev_err(pctl->dev, "cannot set group %s to %s\n",
319 func->groups[gid], func->name);
320 return ret;
321 }
322
323 return 0;
324}
325
326static int mvebu_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
327 struct pinctrl_gpio_range *range, unsigned offset)
328{
329 struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
330 struct mvebu_pinctrl_group *grp;
331 struct mvebu_mpp_ctrl_setting *setting;
332
333 grp = mvebu_pinctrl_find_group_by_pid(pctl, offset);
334 if (!grp)
335 return -EINVAL;
336
337 if (grp->ctrl->mpp_gpio_req)
338 return grp->ctrl->mpp_gpio_req(grp->ctrl, offset);
339
340 setting = mvebu_pinctrl_find_gpio_setting(pctl, grp);
341 if (!setting)
342 return -ENOTSUPP;
343
344 return mvebu_pinconf_group_set(pctldev, grp->gid, setting->val);
345}
346
347static int mvebu_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
348 struct pinctrl_gpio_range *range, unsigned offset, bool input)
349{
350 struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
351 struct mvebu_pinctrl_group *grp;
352 struct mvebu_mpp_ctrl_setting *setting;
353
354 grp = mvebu_pinctrl_find_group_by_pid(pctl, offset);
355 if (!grp)
356 return -EINVAL;
357
358 if (grp->ctrl->mpp_gpio_dir)
359 return grp->ctrl->mpp_gpio_dir(grp->ctrl, offset, input);
360
361 setting = mvebu_pinctrl_find_gpio_setting(pctl, grp);
362 if (!setting)
363 return -ENOTSUPP;
364
365 if ((input && (setting->flags & MVEBU_SETTING_GPI)) ||
366 (!input && (setting->flags & MVEBU_SETTING_GPO)))
367 return 0;
368
369 return -ENOTSUPP;
370}
371
022ab148 372static const struct pinmux_ops mvebu_pinmux_ops = {
7e8d9415
SH		 373 .get_functions_count = mvebu_pinmux_get_funcs_count,
374 .get_function_name = mvebu_pinmux_get_func_name,
375 .get_function_groups = mvebu_pinmux_get_groups,
376 .gpio_request_enable = mvebu_pinmux_gpio_request_enable,
377 .gpio_set_direction = mvebu_pinmux_gpio_set_direction,
378 .enable = mvebu_pinmux_enable,
379};
380
381static int mvebu_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
382{
383 struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
384 return pctl->num_groups;
385}
386
387static const char *mvebu_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
388 unsigned gid)
389{
390 struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
391 return pctl->groups[gid].name;
392}
393
394static int mvebu_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
395 unsigned gid, const unsigned **pins,
396 unsigned *num_pins)
397{
398 struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
399 *pins = pctl->groups[gid].pins;
400 *num_pins = pctl->groups[gid].npins;
401 return 0;
402}
403
404static int mvebu_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
405 struct device_node *np,
406 struct pinctrl_map **map,
407 unsigned *num_maps)
408{
409 struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
410 struct property *prop;
411 const char *function;
412 const char *group;
413 int ret, nmaps, n;
414
415 *map = NULL;
416 *num_maps = 0;
417
418 ret = of_property_read_string(np, "marvell,function", &function);
419 if (ret) {
420 dev_err(pctl->dev,
421 "missing marvell,function in node %s\n", np->name);
422 return 0;
423 }
424
425 nmaps = of_property_count_strings(np, "marvell,pins");
426 if (nmaps < 0) {
427 dev_err(pctl->dev,
428 "missing marvell,pins in node %s\n", np->name);
429 return 0;
430 }
431
432 *map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL);
433 if (map == NULL) {
434 dev_err(pctl->dev,
435 "cannot allocate pinctrl_map memory for %s\n",
436 np->name);
437 return -ENOMEM;
438 }
439
440 n = 0;
441 of_property_for_each_string(np, "marvell,pins", prop, group) {
442 struct mvebu_pinctrl_group *grp =
443 mvebu_pinctrl_find_group_by_name(pctl, group);
444
445 if (!grp) {
446 dev_err(pctl->dev, "unknown pin %s", group);
447 continue;
448 }
449
450 if (!mvebu_pinctrl_find_setting_by_name(pctl, grp, function)) {
451 dev_err(pctl->dev, "unsupported function %s on pin %s",
452 function, group);
453 continue;
454 }
455
456 (*map)[n].type = PIN_MAP_TYPE_MUX_GROUP;
457 (*map)[n].data.mux.group = group;
458 (*map)[n].data.mux.function = function;
459 n++;
460 }
461
462 *num_maps = nmaps;
463
464 return 0;
465}
466
467static void mvebu_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
468 struct pinctrl_map *map, unsigned num_maps)
469{
470 kfree(map);
471}
472
022ab148 473static const struct pinctrl_ops mvebu_pinctrl_ops = {
7e8d9415
SH		 474 .get_groups_count = mvebu_pinctrl_get_groups_count,
475 .get_group_name = mvebu_pinctrl_get_group_name,
476 .get_group_pins = mvebu_pinctrl_get_group_pins,
477 .dt_node_to_map = mvebu_pinctrl_dt_node_to_map,
478 .dt_free_map = mvebu_pinctrl_dt_free_map,
479};
480
aaed651f
DW		 481static int _add_function(struct mvebu_pinctrl_function *funcs, int *funcsize,
482 const char *name)
7e8d9415 483{
aaed651f
DW		 484 if (*funcsize <= 0)
485 return -EOVERFLOW;
486
7e8d9415
SH		 487 while (funcs->num_groups) {
488 /* function already there */
489 if (strcmp(funcs->name, name) == 0) {
490 funcs->num_groups++;
491 return -EEXIST;
492 }
493 funcs++;
494 }
aaed651f
DW		 495
496 /* append new unique function */
7e8d9415
SH		 497 funcs->name = name;
498 funcs->num_groups = 1;
aaed651f
DW		 499 (*funcsize)--;
500
7e8d9415
SH		 501 return 0;
502}
503
150632b0
GKH		 504static int mvebu_pinctrl_build_functions(struct platform_device *pdev,
505 struct mvebu_pinctrl *pctl)
7e8d9415
SH		 506{
507 struct mvebu_pinctrl_function *funcs;
aaed651f 508 int num = 0, funcsize = pctl->desc.npins;
7e8d9415
SH		 509 int n, s;
510
511 /* we allocate functions for number of pins and hope
aaed651f
DW		 512 * there are fewer unique functions than pins available */
513 funcs = devm_kzalloc(&pdev->dev, funcsize *
7e8d9415
SH		 514 sizeof(struct mvebu_pinctrl_function), GFP_KERNEL);
515 if (!funcs)
516 return -ENOMEM;
517
518 for (n = 0; n < pctl->num_groups; n++) {
519 struct mvebu_pinctrl_group *grp = &pctl->groups[n];
520 for (s = 0; s < grp->num_settings; s++) {
aaed651f
DW		 521 int ret;
522
7e8d9415
SH		 523 /* skip unsupported settings on this variant */
524 if (pctl->variant &&
525 !(pctl->variant & grp->settings[s].variant))
526 continue;
527
528 /* check for unique functions and count groups */
aaed651f
DW		 529 ret = _add_function(funcs, &funcsize,
530 grp->settings[s].name);
531 if (ret == -EOVERFLOW)
532 dev_err(&pdev->dev,
533 "More functions than pins(%d)\n",
534 pctl->desc.npins);
535 if (ret < 0)
7e8d9415
SH		 536 continue;
537
538 num++;
539 }
540 }
541
7e8d9415
SH		 542 pctl->num_functions = num;
543 pctl->functions = funcs;
544
545 for (n = 0; n < pctl->num_groups; n++) {
546 struct mvebu_pinctrl_group *grp = &pctl->groups[n];
547 for (s = 0; s < grp->num_settings; s++) {
548 struct mvebu_pinctrl_function *f;
549 const char **groups;
550
551 /* skip unsupported settings on this variant */
552 if (pctl->variant &&
553 !(pctl->variant & grp->settings[s].variant))
554 continue;
555
556 f = mvebu_pinctrl_find_function_by_name(pctl,
557 grp->settings[s].name);
558
559 /* allocate group name array if not done already */
560 if (!f->groups) {
561 f->groups = devm_kzalloc(&pdev->dev,
562 f->num_groups * sizeof(char *),
563 GFP_KERNEL);
564 if (!f->groups)
565 return -ENOMEM;
566 }
567
568 /* find next free group name and assign current name */
569 groups = f->groups;
570 while (*groups)
571 groups++;
572 *groups = grp->name;
573 }
574 }
575
576 return 0;
577}
578
150632b0 579int mvebu_pinctrl_probe(struct platform_device *pdev)
7e8d9415
SH		 580{
581 struct mvebu_pinctrl_soc_info *soc = dev_get_platdata(&pdev->dev);
582 struct device_node *np = pdev->dev.of_node;
583 struct mvebu_pinctrl *pctl;
584 void __iomem *base;
585 struct pinctrl_pin_desc *pdesc;
586 unsigned gid, n, k;
587 int ret;
588
589 if (!soc || !soc->controls || !soc->modes) {
590 dev_err(&pdev->dev, "wrong pinctrl soc info\n");
591 return -EINVAL;
592 }
593
594 base = of_iomap(np, 0);
595 if (!base) {
596 dev_err(&pdev->dev, "unable to get base address\n");
597 return -ENODEV;
598 }
599
600 pctl = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pinctrl),
601 GFP_KERNEL);
602 if (!pctl) {
603 dev_err(&pdev->dev, "unable to alloc driver\n");
604 return -ENOMEM;
605 }
606
607 pctl->desc.name = dev_name(&pdev->dev);
608 pctl->desc.owner = THIS_MODULE;
609 pctl->desc.pctlops = &mvebu_pinctrl_ops;
610 pctl->desc.pmxops = &mvebu_pinmux_ops;
611 pctl->desc.confops = &mvebu_pinconf_ops;
612 pctl->variant = soc->variant;
613 pctl->base = base;
614 pctl->dev = &pdev->dev;
615 platform_set_drvdata(pdev, pctl);
616
617 /* count controls and create names for mvebu generic
618 register controls; also does sanity checks */
619 pctl->num_groups = 0;
620 pctl->desc.npins = 0;
621 for (n = 0; n < soc->ncontrols; n++) {
622 struct mvebu_mpp_ctrl *ctrl = &soc->controls[n];
623 char *names;
624
625 pctl->desc.npins += ctrl->npins;
626 /* initial control pins */
627 for (k = 0; k < ctrl->npins; k++)
628 ctrl->pins[k] = ctrl->pid + k;
629
630 /* special soc specific control */
631 if (ctrl->mpp_get || ctrl->mpp_set) {
48a23fac 632 if (!ctrl->name || !ctrl->mpp_get || !ctrl->mpp_set) {
7e8d9415
SH		 633 dev_err(&pdev->dev, "wrong soc control info\n");
634 return -EINVAL;
635 }
636 pctl->num_groups += 1;
637 continue;
638 }
639
640 /* generic mvebu register control */
641 names = devm_kzalloc(&pdev->dev, ctrl->npins * 8, GFP_KERNEL);
642 if (!names) {
643 dev_err(&pdev->dev, "failed to alloc mpp names\n");
644 return -ENOMEM;
645 }
646 for (k = 0; k < ctrl->npins; k++)
647 sprintf(names + 8*k, "mpp%d", ctrl->pid+k);
648 ctrl->name = names;
649 pctl->num_groups += ctrl->npins;
650 }
651
652 pdesc = devm_kzalloc(&pdev->dev, pctl->desc.npins *
653 sizeof(struct pinctrl_pin_desc), GFP_KERNEL);
654 if (!pdesc) {
655 dev_err(&pdev->dev, "failed to alloc pinctrl pins\n");
656 return -ENOMEM;
657 }
658
659 for (n = 0; n < pctl->desc.npins; n++)
660 pdesc[n].number = n;
661 pctl->desc.pins = pdesc;
662
663 pctl->groups = devm_kzalloc(&pdev->dev, pctl->num_groups *
664 sizeof(struct mvebu_pinctrl_group), GFP_KERNEL);
665 if (!pctl->groups) {
666 dev_err(&pdev->dev, "failed to alloc pinctrl groups\n");
667 return -ENOMEM;
668 }
669
670 /* assign mpp controls to groups */
671 gid = 0;
672 for (n = 0; n < soc->ncontrols; n++) {
673 struct mvebu_mpp_ctrl *ctrl = &soc->controls[n];
674 pctl->groups[gid].gid = gid;
675 pctl->groups[gid].ctrl = ctrl;
676 pctl->groups[gid].name = ctrl->name;
677 pctl->groups[gid].pins = ctrl->pins;
678 pctl->groups[gid].npins = ctrl->npins;
679
680 /* generic mvebu register control maps to a number of groups */
681 if (!ctrl->mpp_get && !ctrl->mpp_set) {
682 pctl->groups[gid].npins = 1;
683
684 for (k = 1; k < ctrl->npins; k++) {
685 gid++;
686 pctl->groups[gid].gid = gid;
687 pctl->groups[gid].ctrl = ctrl;
688 pctl->groups[gid].name = &ctrl->name[8*k];
689 pctl->groups[gid].pins = &ctrl->pins[k];
690 pctl->groups[gid].npins = 1;
691 }
692 }
693 gid++;
694 }
695
696 /* assign mpp modes to groups */
697 for (n = 0; n < soc->nmodes; n++) {
698 struct mvebu_mpp_mode *mode = &soc->modes[n];
699 struct mvebu_pinctrl_group *grp =
700 mvebu_pinctrl_find_group_by_pid(pctl, mode->pid);
701 unsigned num_settings;
702
703 if (!grp) {
704 dev_warn(&pdev->dev, "unknown pinctrl group %d\n",
705 mode->pid);
706 continue;
707 }
708
709 for (num_settings = 0; ;) {
710 struct mvebu_mpp_ctrl_setting *set =
711 &mode->settings[num_settings];
712
713 if (!set->name)
714 break;
715 num_settings++;
716
717 /* skip unsupported settings for this variant */
718 if (pctl->variant && !(pctl->variant & set->variant))
719 continue;
720
721 /* find gpio/gpo/gpi settings */
722 if (strcmp(set->name, "gpio") == 0)
723 set->flags = MVEBU_SETTING_GPI |
724 MVEBU_SETTING_GPO;
725 else if (strcmp(set->name, "gpo") == 0)
726 set->flags = MVEBU_SETTING_GPO;
727 else if (strcmp(set->name, "gpi") == 0)
728 set->flags = MVEBU_SETTING_GPI;
729 }
730
731 grp->settings = mode->settings;
732 grp->num_settings = num_settings;
733 }
734
735 ret = mvebu_pinctrl_build_functions(pdev, pctl);
736 if (ret) {
737 dev_err(&pdev->dev, "unable to build functions\n");
738 return ret;
739 }
740
741 pctl->pctldev = pinctrl_register(&pctl->desc, &pdev->dev, pctl);
742 if (!pctl->pctldev) {
743 dev_err(&pdev->dev, "unable to register pinctrl driver\n");
744 return -EINVAL;
745 }
746
747 dev_info(&pdev->dev, "registered pinctrl driver\n");
748
749 /* register gpio ranges */
750 for (n = 0; n < soc->ngpioranges; n++)
751 pinctrl_add_gpio_range(pctl->pctldev, &soc->gpioranges[n]);
752
753 return 0;
754}
755
150632b0 756int mvebu_pinctrl_remove(struct platform_device *pdev)
7e8d9415
SH		 757{
758 struct mvebu_pinctrl *pctl = platform_get_drvdata(pdev);
759 pinctrl_unregister(pctl->pctldev);
760 return 0;
761}
kernel source for telekom puls (alcatel/mediatek)