[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / pcmcia / pxa2xx_base.c

/*======================================================================

  Device driver for the PCMCIA control functionality of PXA2xx
  microprocessors.

    The contents of this file may be used under the
    terms of the GNU Public License version 2 (the "GPL")

    (c) Ian Molton (spyro@f2s.com) 2003
    (c) Stefan Eletzhofer (stefan.eletzhofer@inquant.de) 2003,4

    derived from sa11xx_base.c

     Portions created by John G. Dorsey are
     Copyright (C) 1999 John G. Dorsey.

  ======================================================================*/

#include <linux/module.h>
#include <linux/init.h>
#include <linux/cpufreq.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>

#include <mach/hardware.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/system.h>
#include <mach/pxa2xx-regs.h>
#include <asm/mach-types.h>

#include <pcmcia/cs_types.h>
#include <pcmcia/ss.h>
#include <pcmcia/cistpl.h>

#include "soc_common.h"
#include "pxa2xx_base.h"

/*
 * Personal Computer Memory Card International Association (PCMCIA) sockets
 */

#define PCMCIAPrtSp	0x04000000	/* PCMCIA Partition Space [byte]   */
#define PCMCIASp	(4*PCMCIAPrtSp)	/* PCMCIA Space [byte]             */
#define PCMCIAIOSp	PCMCIAPrtSp	/* PCMCIA I/O Space [byte]         */
#define PCMCIAAttrSp	PCMCIAPrtSp	/* PCMCIA Attribute Space [byte]   */
#define PCMCIAMemSp	PCMCIAPrtSp	/* PCMCIA Memory Space [byte]      */

#define PCMCIA0Sp	PCMCIASp	/* PCMCIA 0 Space [byte]           */
#define PCMCIA0IOSp	PCMCIAIOSp	/* PCMCIA 0 I/O Space [byte]       */
#define PCMCIA0AttrSp	PCMCIAAttrSp	/* PCMCIA 0 Attribute Space [byte] */
#define PCMCIA0MemSp	PCMCIAMemSp	/* PCMCIA 0 Memory Space [byte]    */

#define PCMCIA1Sp	PCMCIASp	/* PCMCIA 1 Space [byte]           */
#define PCMCIA1IOSp	PCMCIAIOSp	/* PCMCIA 1 I/O Space [byte]       */
#define PCMCIA1AttrSp	PCMCIAAttrSp	/* PCMCIA 1 Attribute Space [byte] */
#define PCMCIA1MemSp	PCMCIAMemSp	/* PCMCIA 1 Memory Space [byte]    */

#define _PCMCIA(Nb)			/* PCMCIA [0..1]                   */ \
			(0x20000000 + (Nb) * PCMCIASp)
#define _PCMCIAIO(Nb)	_PCMCIA(Nb)	/* PCMCIA I/O [0..1]               */
#define _PCMCIAAttr(Nb)			/* PCMCIA Attribute [0..1]         */ \
			(_PCMCIA(Nb) + 2 * PCMCIAPrtSp)
#define _PCMCIAMem(Nb)			/* PCMCIA Memory [0..1]            */ \
			(_PCMCIA(Nb) + 3 * PCMCIAPrtSp)

#define _PCMCIA0	_PCMCIA(0)	/* PCMCIA 0                        */
#define _PCMCIA0IO	_PCMCIAIO(0)	/* PCMCIA 0 I/O                    */
#define _PCMCIA0Attr	_PCMCIAAttr(0)	/* PCMCIA 0 Attribute              */
#define _PCMCIA0Mem	_PCMCIAMem(0)	/* PCMCIA 0 Memory                 */

#define _PCMCIA1	_PCMCIA(1)	/* PCMCIA 1                        */
#define _PCMCIA1IO	_PCMCIAIO(1)	/* PCMCIA 1 I/O                    */
#define _PCMCIA1Attr	_PCMCIAAttr(1)	/* PCMCIA 1 Attribute              */
#define _PCMCIA1Mem	_PCMCIAMem(1)	/* PCMCIA 1 Memory                 */


#define MCXX_SETUP_MASK     (0x7f)
#define MCXX_ASST_MASK      (0x1f)
#define MCXX_HOLD_MASK      (0x3f)
#define MCXX_SETUP_SHIFT    (0)
#define MCXX_ASST_SHIFT     (7)
#define MCXX_HOLD_SHIFT     (14)

static inline u_int pxa2xx_mcxx_hold(u_int pcmcia_cycle_ns,
				     u_int mem_clk_10khz)
{
	u_int code = pcmcia_cycle_ns * mem_clk_10khz;
	return (code / 300000) + ((code % 300000) ? 1 : 0) - 1;
}

static inline u_int pxa2xx_mcxx_asst(u_int pcmcia_cycle_ns,
				     u_int mem_clk_10khz)
{
	u_int code = pcmcia_cycle_ns * mem_clk_10khz;
	return (code / 300000) + ((code % 300000) ? 1 : 0) + 1;
}

static inline u_int pxa2xx_mcxx_setup(u_int pcmcia_cycle_ns,
				      u_int mem_clk_10khz)
{
	u_int code = pcmcia_cycle_ns * mem_clk_10khz;
	return (code / 100000) + ((code % 100000) ? 1 : 0) - 1;
}

/* This function returns the (approximate) command assertion period, in
 * nanoseconds, for a given CPU clock frequency and MCXX_ASST value:
 */
static inline u_int pxa2xx_pcmcia_cmd_time(u_int mem_clk_10khz,
					   u_int pcmcia_mcxx_asst)
{
	return (300000 * (pcmcia_mcxx_asst + 1) / mem_clk_10khz);
}

static int pxa2xx_pcmcia_set_mcmem( int sock, int speed, int clock )
{
	MCMEM(sock) = ((pxa2xx_mcxx_setup(speed, clock)
		& MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
		| ((pxa2xx_mcxx_asst(speed, clock)
		& MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
		| ((pxa2xx_mcxx_hold(speed, clock)
		& MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);

	return 0;
}

static int pxa2xx_pcmcia_set_mcio( int sock, int speed, int clock )
{
	MCIO(sock) = ((pxa2xx_mcxx_setup(speed, clock)
		& MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
		| ((pxa2xx_mcxx_asst(speed, clock)
		& MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
		| ((pxa2xx_mcxx_hold(speed, clock)
		& MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);

	return 0;
}

static int pxa2xx_pcmcia_set_mcatt( int sock, int speed, int clock )
{
	MCATT(sock) = ((pxa2xx_mcxx_setup(speed, clock)
		& MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
		| ((pxa2xx_mcxx_asst(speed, clock)
		& MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
		| ((pxa2xx_mcxx_hold(speed, clock)
		& MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);

	return 0;
}

static int pxa2xx_pcmcia_set_mcxx(struct soc_pcmcia_socket *skt, unsigned int clk)
{
	struct soc_pcmcia_timing timing;
	int sock = skt->nr;

	soc_common_pcmcia_get_timing(skt, &timing);

	pxa2xx_pcmcia_set_mcmem(sock, timing.mem, clk);
	pxa2xx_pcmcia_set_mcatt(sock, timing.attr, clk);
	pxa2xx_pcmcia_set_mcio(sock, timing.io, clk);

	return 0;
}

static int pxa2xx_pcmcia_set_timing(struct soc_pcmcia_socket *skt)
{
	unsigned int clk = get_memclk_frequency_10khz();
	return pxa2xx_pcmcia_set_mcxx(skt, clk);
}

#ifdef CONFIG_CPU_FREQ

static int
pxa2xx_pcmcia_frequency_change(struct soc_pcmcia_socket *skt,
			       unsigned long val,
			       struct cpufreq_freqs *freqs)
{
#warning "it's not clear if this is right since the core CPU (N) clock has no effect on the memory (L) clock"
	switch (val) {
	case CPUFREQ_PRECHANGE:
		if (freqs->new > freqs->old) {
			debug(skt, 2, "new frequency %u.%uMHz > %u.%uMHz, "
			       "pre-updating\n",
			       freqs->new / 1000, (freqs->new / 100) % 10,
			       freqs->old / 1000, (freqs->old / 100) % 10);
			pxa2xx_pcmcia_set_mcxx(skt, freqs->new);
		}
		break;

	case CPUFREQ_POSTCHANGE:
		if (freqs->new < freqs->old) {
			debug(skt, 2, "new frequency %u.%uMHz < %u.%uMHz, "
			       "post-updating\n",
			       freqs->new / 1000, (freqs->new / 100) % 10,
			       freqs->old / 1000, (freqs->old / 100) % 10);
			pxa2xx_pcmcia_set_mcxx(skt, freqs->new);
		}
		break;
	}
	return 0;
}
#endif

static void pxa2xx_configure_sockets(struct device *dev)
{
	struct pcmcia_low_level *ops = dev->platform_data;

	/*
	 * We have at least one socket, so set MECR:CIT
	 * (Card Is There)
	 */
	MECR |= MECR_CIT;

	/* Set MECR:NOS (Number Of Sockets) */
	if ((ops->first + ops->nr) > 1 || machine_is_viper())
		MECR |= MECR_NOS;
	else
		MECR &= ~MECR_NOS;
}

static const char *skt_names[] = {
	"PCMCIA socket 0",
	"PCMCIA socket 1",
};

#define SKT_DEV_INFO_SIZE(n) \
	(sizeof(struct skt_dev_info) + (n)*sizeof(struct soc_pcmcia_socket))

int __pxa2xx_drv_pcmcia_probe(struct device *dev)
{
	int i, ret;
	struct pcmcia_low_level *ops;
	struct skt_dev_info *sinfo;
	struct soc_pcmcia_socket *skt;

	if (!dev || !dev->platform_data)
		return -ENODEV;

	ops = (struct pcmcia_low_level *)dev->platform_data;

	sinfo = kzalloc(SKT_DEV_INFO_SIZE(ops->nr), GFP_KERNEL);
	if (!sinfo)
		return -ENOMEM;

	sinfo->nskt = ops->nr;

	/* Initialize processor specific parameters */
	for (i = 0; i < ops->nr; i++) {
		skt = &sinfo->skt[i];

		skt->nr		= ops->first + i;
		skt->irq	= NO_IRQ;

		skt->res_skt.start	= _PCMCIA(skt->nr);
		skt->res_skt.end	= _PCMCIA(skt->nr) + PCMCIASp - 1;
		skt->res_skt.name	= skt_names[skt->nr];
		skt->res_skt.flags	= IORESOURCE_MEM;

		skt->res_io.start	= _PCMCIAIO(skt->nr);
		skt->res_io.end		= _PCMCIAIO(skt->nr) + PCMCIAIOSp - 1;
		skt->res_io.name	= "io";
		skt->res_io.flags	= IORESOURCE_MEM | IORESOURCE_BUSY;

		skt->res_mem.start	= _PCMCIAMem(skt->nr);
		skt->res_mem.end	= _PCMCIAMem(skt->nr) + PCMCIAMemSp - 1;
		skt->res_mem.name	= "memory";
		skt->res_mem.flags	= IORESOURCE_MEM;

		skt->res_attr.start	= _PCMCIAAttr(skt->nr);
		skt->res_attr.end	= _PCMCIAAttr(skt->nr) + PCMCIAAttrSp - 1;
		skt->res_attr.name	= "attribute";
		skt->res_attr.flags	= IORESOURCE_MEM;
	}

	/* Provide our PXA2xx specific timing routines. */
	ops->set_timing  = pxa2xx_pcmcia_set_timing;
#ifdef CONFIG_CPU_FREQ
	ops->frequency_change = pxa2xx_pcmcia_frequency_change;
#endif

	ret = soc_common_drv_pcmcia_probe(dev, ops, sinfo);

	if (!ret)
		pxa2xx_configure_sockets(dev);

	return ret;
}
EXPORT_SYMBOL(__pxa2xx_drv_pcmcia_probe);


static int pxa2xx_drv_pcmcia_probe(struct platform_device *dev)
{
	return __pxa2xx_drv_pcmcia_probe(&dev->dev);
}

static int pxa2xx_drv_pcmcia_remove(struct platform_device *dev)
{
	struct skt_dev_info *sinfo = platform_get_drvdata(dev);
	int i;

	platform_set_drvdata(dev, NULL);

	for (i = 0; i < sinfo->nskt; i++)
		soc_pcmcia_remove_one(&sinfo->skt[i]);

	kfree(sinfo);
	return 0;
}

static int pxa2xx_drv_pcmcia_suspend(struct device *dev)
{
	return pcmcia_socket_dev_suspend(dev);
}

static int pxa2xx_drv_pcmcia_resume(struct device *dev)
{
	pxa2xx_configure_sockets(dev);
	return pcmcia_socket_dev_resume(dev);
}

static struct dev_pm_ops  pxa2xx_drv_pcmcia_pm_ops = {
	.suspend	= pxa2xx_drv_pcmcia_suspend,
	.resume		= pxa2xx_drv_pcmcia_resume,
};

static struct platform_driver pxa2xx_pcmcia_driver = {
	.probe		= pxa2xx_drv_pcmcia_probe,
	.remove		= pxa2xx_drv_pcmcia_remove,
	.driver		= {
		.name	= "pxa2xx-pcmcia",
		.owner	= THIS_MODULE,
		.pm	= &pxa2xx_drv_pcmcia_pm_ops,
	},
};

static int __init pxa2xx_pcmcia_init(void)
{
	return platform_driver_register(&pxa2xx_pcmcia_driver);
}

static void __exit pxa2xx_pcmcia_exit(void)
{
	platform_driver_unregister(&pxa2xx_pcmcia_driver);
}

fs_initcall(pxa2xx_pcmcia_init);
module_exit(pxa2xx_pcmcia_exit);

MODULE_AUTHOR("Stefan Eletzhofer <stefan.eletzhofer@inquant.de> and Ian Molton <spyro@f2s.com>");
MODULE_DESCRIPTION("Linux PCMCIA Card Services: PXA2xx core socket driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:pxa2xx-pcmcia");
Commit	Line	Data
1da177e4 LT	1	/*======================================================================
	2
	3	Device driver for the PCMCIA control functionality of PXA2xx
	4	microprocessors.
	5
	6	The contents of this file may be used under the
	7	terms of the GNU Public License version 2 (the "GPL")
	8
	9	(c) Ian Molton (spyro@f2s.com) 2003
	10	(c) Stefan Eletzhofer (stefan.eletzhofer@inquant.de) 2003,4
	11
	12	derived from sa11xx_base.c
	13
	14	Portions created by John G. Dorsey are
	15	Copyright (C) 1999 John G. Dorsey.
	16
	17	======================================================================*/
	18
	19	#include <linux/module.h>
	20	#include <linux/init.h>
1da177e4 LT	21	#include <linux/cpufreq.h>
	22	#include <linux/ioport.h>
	23	#include <linux/kernel.h>
	24	#include <linux/spinlock.h>
d052d1be	25	#include <linux/platform_device.h>
1da177e4	26
a09e64fb	27	#include <mach/hardware.h>
1da177e4 LT	28	#include <asm/io.h>
	29	#include <asm/irq.h>
	30	#include <asm/system.h>
a09e64fb	31	#include <mach/pxa2xx-regs.h>
20f18ff3	32	#include <asm/mach-types.h>
1da177e4 LT	33
	34	#include <pcmcia/cs_types.h>
	35	#include <pcmcia/ss.h>
1da177e4 LT	36	#include <pcmcia/cistpl.h>
1da177e4 LT	37
1da177e4 LT	38	#include "soc_common.h"
	39	#include "pxa2xx_base.h"
	40
b393c696 EM	41	/*
	42	* Personal Computer Memory Card International Association (PCMCIA) sockets
	43	*/
	44
	45	#define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */
	46	#define PCMCIASp (4PCMCIAPrtSp) / PCMCIA Space [byte] */
	47	#define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */
	48	#define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */
	49	#define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */
	50
	51	#define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */
	52	#define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */
	53	#define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */
	54	#define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */
	55
	56	#define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */
	57	#define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */
	58	#define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */
	59	#define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */
	60
	61	#define _PCMCIA(Nb) /* PCMCIA [0..1] */ \
	62	(0x20000000 + (Nb) * PCMCIASp)
	63	#define _PCMCIAIO(Nb) _PCMCIA(Nb) /* PCMCIA I/O [0..1] */
	64	#define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \
	65	(_PCMCIA(Nb) + 2 * PCMCIAPrtSp)
	66	#define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
	67	(_PCMCIA(Nb) + 3 * PCMCIAPrtSp)
	68
	69	#define _PCMCIA0 _PCMCIA(0) /* PCMCIA 0 */
	70	#define _PCMCIA0IO _PCMCIAIO(0) /* PCMCIA 0 I/O */
	71	#define _PCMCIA0Attr _PCMCIAAttr(0) /* PCMCIA 0 Attribute */
	72	#define _PCMCIA0Mem _PCMCIAMem(0) /* PCMCIA 0 Memory */
	73
	74	#define _PCMCIA1 _PCMCIA(1) /* PCMCIA 1 */
	75	#define _PCMCIA1IO _PCMCIAIO(1) /* PCMCIA 1 I/O */
	76	#define _PCMCIA1Attr _PCMCIAAttr(1) /* PCMCIA 1 Attribute */
	77	#define _PCMCIA1Mem _PCMCIAMem(1) /* PCMCIA 1 Memory */
	78
1da177e4 LT	79
	80	#define MCXX_SETUP_MASK (0x7f)
	81	#define MCXX_ASST_MASK (0x1f)
	82	#define MCXX_HOLD_MASK (0x3f)
	83	#define MCXX_SETUP_SHIFT (0)
	84	#define MCXX_ASST_SHIFT (7)
	85	#define MCXX_HOLD_SHIFT (14)
	86
	87	static inline u_int pxa2xx_mcxx_hold(u_int pcmcia_cycle_ns,
	88	u_int mem_clk_10khz)
	89	{
	90	u_int code = pcmcia_cycle_ns * mem_clk_10khz;
	91	return (code / 300000) + ((code % 300000) ? 1 : 0) - 1;
	92	}
	93
	94	static inline u_int pxa2xx_mcxx_asst(u_int pcmcia_cycle_ns,
	95	u_int mem_clk_10khz)
	96	{
	97	u_int code = pcmcia_cycle_ns * mem_clk_10khz;
24d6572b	98	return (code / 300000) + ((code % 300000) ? 1 : 0) + 1;
1da177e4 LT	99	}
	100
	101	static inline u_int pxa2xx_mcxx_setup(u_int pcmcia_cycle_ns,
	102	u_int mem_clk_10khz)
	103	{
	104	u_int code = pcmcia_cycle_ns * mem_clk_10khz;
	105	return (code / 100000) + ((code % 100000) ? 1 : 0) - 1;
	106	}
	107
	108	/* This function returns the (approximate) command assertion period, in
	109	* nanoseconds, for a given CPU clock frequency and MCXX_ASST value:
	110	*/
	111	static inline u_int pxa2xx_pcmcia_cmd_time(u_int mem_clk_10khz,
	112	u_int pcmcia_mcxx_asst)
	113	{
	114	return (300000 * (pcmcia_mcxx_asst + 1) / mem_clk_10khz);
	115	}
	116
	117	static int pxa2xx_pcmcia_set_mcmem( int sock, int speed, int clock )
	118	{
	119	MCMEM(sock) = ((pxa2xx_mcxx_setup(speed, clock)
	120	& MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
	121	\| ((pxa2xx_mcxx_asst(speed, clock)
	122	& MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
	123	\| ((pxa2xx_mcxx_hold(speed, clock)
	124	& MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
	125
	126	return 0;
	127	}
	128
	129	static int pxa2xx_pcmcia_set_mcio( int sock, int speed, int clock )
	130	{
	131	MCIO(sock) = ((pxa2xx_mcxx_setup(speed, clock)
	132	& MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
	133	\| ((pxa2xx_mcxx_asst(speed, clock)
	134	& MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
	135	\| ((pxa2xx_mcxx_hold(speed, clock)
	136	& MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
	137
	138	return 0;
	139	}
	140
	141	static int pxa2xx_pcmcia_set_mcatt( int sock, int speed, int clock )
	142	{
	143	MCATT(sock) = ((pxa2xx_mcxx_setup(speed, clock)
	144	& MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
	145	\| ((pxa2xx_mcxx_asst(speed, clock)
	146	& MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
	147	\| ((pxa2xx_mcxx_hold(speed, clock)
	148	& MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
	149
	150	return 0;
	151	}
	152
	153	static int pxa2xx_pcmcia_set_mcxx(struct soc_pcmcia_socket *skt, unsigned int clk)
	154	{
	155	struct soc_pcmcia_timing timing;
	156	int sock = skt->nr;
	157
	158	soc_common_pcmcia_get_timing(skt, &timing);
	159
	160	pxa2xx_pcmcia_set_mcmem(sock, timing.mem, clk);
	161	pxa2xx_pcmcia_set_mcatt(sock, timing.attr, clk);
	162	pxa2xx_pcmcia_set_mcio(sock, timing.io, clk);
163
164	return 0;
165	}
166
167	static int pxa2xx_pcmcia_set_timing(struct soc_pcmcia_socket *skt)
168	{
169	unsigned int clk = get_memclk_frequency_10khz();
170	return pxa2xx_pcmcia_set_mcxx(skt, clk);
171	}
172
173	#ifdef CONFIG_CPU_FREQ
174
175	static int
176	pxa2xx_pcmcia_frequency_change(struct soc_pcmcia_socket *skt,
177	unsigned long val,
178	struct cpufreq_freqs *freqs)
179	{
180	#warning "it's not clear if this is right since the core CPU (N) clock has no effect on the memory (L) clock"
181	switch (val) {
182	case CPUFREQ_PRECHANGE:
183	if (freqs->new > freqs->old) {
184	debug(skt, 2, "new frequency %u.%uMHz > %u.%uMHz, "
185	"pre-updating\n",
186	freqs->new / 1000, (freqs->new / 100) % 10,
187	freqs->old / 1000, (freqs->old / 100) % 10);
188	pxa2xx_pcmcia_set_mcxx(skt, freqs->new);
189	}
190	break;
191
192	case CPUFREQ_POSTCHANGE:
193	if (freqs->new < freqs->old) {
194	debug(skt, 2, "new frequency %u.%uMHz < %u.%uMHz, "
195	"post-updating\n",
196	freqs->new / 1000, (freqs->new / 100) % 10,
197	freqs->old / 1000, (freqs->old / 100) % 10);
198	pxa2xx_pcmcia_set_mcxx(skt, freqs->new);
199	}
200	break;
201	}
202	return 0;
203	}
204	#endif
205
20f18ff3 MZ	206	static void pxa2xx_configure_sockets(struct device *dev)
	207	{
	208	struct pcmcia_low_level *ops = dev->platform_data;
	209
	210	/*
	211	* We have at least one socket, so set MECR:CIT
	212	* (Card Is There)
	213	*/
	214	MECR \|= MECR_CIT;
	215
	216	/* Set MECR:NOS (Number Of Sockets) */
d66ea8d4	217	if ((ops->first + ops->nr) > 1 \|\| machine_is_viper())
20f18ff3 MZ	218	MECR \|= MECR_NOS;
	219	else
	220	MECR &= ~MECR_NOS;
	221	}
	222
b393c696 EM	223	static const char *skt_names[] = {
	224	"PCMCIA socket 0",
	225	"PCMCIA socket 1",
	226	};
	227
	228	#define SKT_DEV_INFO_SIZE(n) \
	229	(sizeof(struct skt_dev_info) + (n)*sizeof(struct soc_pcmcia_socket))
	230
9468613b	231	int __pxa2xx_drv_pcmcia_probe(struct device *dev)
1da177e4	232	{
b393c696	233	int i, ret;
1da177e4	234	struct pcmcia_low_level *ops;
b393c696 EM	235	struct skt_dev_info *sinfo;
b393c696 EM	236	struct soc_pcmcia_socket *skt;
1da177e4 LT	237
	238	if (!dev \|\| !dev->platform_data)
	239	return -ENODEV;
	240
	241	ops = (struct pcmcia_low_level *)dev->platform_data;
1da177e4	242
b393c696 EM	243	sinfo = kzalloc(SKT_DEV_INFO_SIZE(ops->nr), GFP_KERNEL);
	244	if (!sinfo)
	245	return -ENOMEM;
	246
	247	sinfo->nskt = ops->nr;
	248
	249	/* Initialize processor specific parameters */
	250	for (i = 0; i < ops->nr; i++) {
	251	skt = &sinfo->skt[i];
	252
d66ea8d4	253	skt->nr = ops->first + i;
b393c696 EM	254	skt->irq = NO_IRQ;
	255
	256	skt->res_skt.start = _PCMCIA(skt->nr);
	257	skt->res_skt.end = _PCMCIA(skt->nr) + PCMCIASp - 1;
	258	skt->res_skt.name = skt_names[skt->nr];
	259	skt->res_skt.flags = IORESOURCE_MEM;
	260
	261	skt->res_io.start = _PCMCIAIO(skt->nr);
	262	skt->res_io.end = _PCMCIAIO(skt->nr) + PCMCIAIOSp - 1;
	263	skt->res_io.name = "io";
	264	skt->res_io.flags = IORESOURCE_MEM \| IORESOURCE_BUSY;
	265
	266	skt->res_mem.start = _PCMCIAMem(skt->nr);
	267	skt->res_mem.end = _PCMCIAMem(skt->nr) + PCMCIAMemSp - 1;
	268	skt->res_mem.name = "memory";
	269	skt->res_mem.flags = IORESOURCE_MEM;
	270
	271	skt->res_attr.start = _PCMCIAAttr(skt->nr);
	272	skt->res_attr.end = _PCMCIAAttr(skt->nr) + PCMCIAAttrSp - 1;
	273	skt->res_attr.name = "attribute";
	274	skt->res_attr.flags = IORESOURCE_MEM;
	275	}
	276
1da177e4 LT	277	/* Provide our PXA2xx specific timing routines. */
	278	ops->set_timing = pxa2xx_pcmcia_set_timing;
	279	#ifdef CONFIG_CPU_FREQ
	280	ops->frequency_change = pxa2xx_pcmcia_frequency_change;
	281	#endif
	282
b393c696	283	ret = soc_common_drv_pcmcia_probe(dev, ops, sinfo);
1da177e4	284
20f18ff3 MZ	285	if (!ret)
20f18ff3 MZ	286	pxa2xx_configure_sockets(dev);
1da177e4 LT	287
	288	return ret;
	289	}
9468613b	290	EXPORT_SYMBOL(__pxa2xx_drv_pcmcia_probe);
1da177e4	291
9468613b RK	292
	293	static int pxa2xx_drv_pcmcia_probe(struct platform_device *dev)
	294	{
	295	return __pxa2xx_drv_pcmcia_probe(&dev->dev);
	296	}
	297
	298	static int pxa2xx_drv_pcmcia_remove(struct platform_device *dev)
	299	{
be85458e RKAL	300	struct skt_dev_info *sinfo = platform_get_drvdata(dev);
	301	int i;
	302
	303	platform_set_drvdata(dev, NULL);
	304
	305	for (i = 0; i < sinfo->nskt; i++)
	306	soc_pcmcia_remove_one(&sinfo->skt[i]);
	307
	308	kfree(sinfo);
	309	return 0;
9468613b RK	310	}
9468613b RK	311
85c61021	312	static int pxa2xx_drv_pcmcia_suspend(struct device *dev)
9468613b	313	{
827b4649	314	return pcmcia_socket_dev_suspend(dev);
9468613b RK	315	}
9468613b RK	316
85c61021	317	static int pxa2xx_drv_pcmcia_resume(struct device *dev)
1da177e4	318	{
85c61021 MR	319	pxa2xx_configure_sockets(dev);
85c61021 MR	320	return pcmcia_socket_dev_resume(dev);
1da177e4 LT	321	}
1da177e4 LT	322
85c61021 MR	323	static struct dev_pm_ops pxa2xx_drv_pcmcia_pm_ops = {
	324	.suspend = pxa2xx_drv_pcmcia_suspend,
	325	.resume = pxa2xx_drv_pcmcia_resume,
	326	};
	327
9468613b	328	static struct platform_driver pxa2xx_pcmcia_driver = {
1da177e4	329	.probe = pxa2xx_drv_pcmcia_probe,
9468613b	330	.remove = pxa2xx_drv_pcmcia_remove,
9468613b RK	331	.driver = {
9468613b RK	332	.name = "pxa2xx-pcmcia",
12c2c019	333	.owner = THIS_MODULE,
85c61021	334	.pm = &pxa2xx_drv_pcmcia_pm_ops,
9468613b	335	},
1da177e4 LT	336	};
	337
	338	static int __init pxa2xx_pcmcia_init(void)
	339	{
9468613b	340	return platform_driver_register(&pxa2xx_pcmcia_driver);
1da177e4 LT	341	}
	342
	343	static void __exit pxa2xx_pcmcia_exit(void)
	344	{
9468613b	345	platform_driver_unregister(&pxa2xx_pcmcia_driver);
1da177e4 LT	346	}
1da177e4 LT	347
f36598ae	348	fs_initcall(pxa2xx_pcmcia_init);
1da177e4 LT	349	module_exit(pxa2xx_pcmcia_exit);
	350
	351	MODULE_AUTHOR("Stefan Eletzhofer <stefan.eletzhofer@inquant.de> and Ian Molton <spyro@f2s.com>");
	352	MODULE_DESCRIPTION("Linux PCMCIA Card Services: PXA2xx core socket driver");
	353	MODULE_LICENSE("GPL");
12c2c019	354	MODULE_ALIAS("platform:pxa2xx-pcmcia");