[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / pcmcia / pxa2xx_base.c

/*======================================================================

  Device driver for the PCMCIA control functionality of PXA2xx
  microprocessors.

    The contents of this file may be used under the
    terms of the GNU Public License version 2 (the "GPL")

    (c) Ian Molton (spyro@f2s.com) 2003
    (c) Stefan Eletzhofer (stefan.eletzhofer@inquant.de) 2003,4

    derived from sa11xx_base.c

     Portions created by John G. Dorsey are
     Copyright (C) 1999 John G. Dorsey.

  ======================================================================*/

#include <linux/module.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/cpufreq.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>

#include <mach/hardware.h>
#include <mach/smemc.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/system.h>
#include <mach/pxa2xx-regs.h>
#include <asm/mach-types.h>

#include <pcmcia/ss.h>
#include <pcmcia/cistpl.h>

#include "soc_common.h"
#include "pxa2xx_base.h"

/*
 * Personal Computer Memory Card International Association (PCMCIA) sockets
 */

#define PCMCIAPrtSp	0x04000000	/* PCMCIA Partition Space [byte]   */
#define PCMCIASp	(4*PCMCIAPrtSp)	/* PCMCIA Space [byte]             */
#define PCMCIAIOSp	PCMCIAPrtSp	/* PCMCIA I/O Space [byte]         */
#define PCMCIAAttrSp	PCMCIAPrtSp	/* PCMCIA Attribute Space [byte]   */
#define PCMCIAMemSp	PCMCIAPrtSp	/* PCMCIA Memory Space [byte]      */

#define PCMCIA0Sp	PCMCIASp	/* PCMCIA 0 Space [byte]           */
#define PCMCIA0IOSp	PCMCIAIOSp	/* PCMCIA 0 I/O Space [byte]       */
#define PCMCIA0AttrSp	PCMCIAAttrSp	/* PCMCIA 0 Attribute Space [byte] */
#define PCMCIA0MemSp	PCMCIAMemSp	/* PCMCIA 0 Memory Space [byte]    */

#define PCMCIA1Sp	PCMCIASp	/* PCMCIA 1 Space [byte]           */
#define PCMCIA1IOSp	PCMCIAIOSp	/* PCMCIA 1 I/O Space [byte]       */
#define PCMCIA1AttrSp	PCMCIAAttrSp	/* PCMCIA 1 Attribute Space [byte] */
#define PCMCIA1MemSp	PCMCIAMemSp	/* PCMCIA 1 Memory Space [byte]    */

#define _PCMCIA(Nb)			/* PCMCIA [0..1]                   */ \
			(0x20000000 + (Nb) * PCMCIASp)
#define _PCMCIAIO(Nb)	_PCMCIA(Nb)	/* PCMCIA I/O [0..1]               */
#define _PCMCIAAttr(Nb)			/* PCMCIA Attribute [0..1]         */ \
			(_PCMCIA(Nb) + 2 * PCMCIAPrtSp)
#define _PCMCIAMem(Nb)			/* PCMCIA Memory [0..1]            */ \
			(_PCMCIA(Nb) + 3 * PCMCIAPrtSp)

#define _PCMCIA0	_PCMCIA(0)	/* PCMCIA 0                        */
#define _PCMCIA0IO	_PCMCIAIO(0)	/* PCMCIA 0 I/O                    */
#define _PCMCIA0Attr	_PCMCIAAttr(0)	/* PCMCIA 0 Attribute              */
#define _PCMCIA0Mem	_PCMCIAMem(0)	/* PCMCIA 0 Memory                 */

#define _PCMCIA1	_PCMCIA(1)	/* PCMCIA 1                        */
#define _PCMCIA1IO	_PCMCIAIO(1)	/* PCMCIA 1 I/O                    */
#define _PCMCIA1Attr	_PCMCIAAttr(1)	/* PCMCIA 1 Attribute              */
#define _PCMCIA1Mem	_PCMCIAMem(1)	/* PCMCIA 1 Memory                 */


#define MCXX_SETUP_MASK     (0x7f)
#define MCXX_ASST_MASK      (0x1f)
#define MCXX_HOLD_MASK      (0x3f)
#define MCXX_SETUP_SHIFT    (0)
#define MCXX_ASST_SHIFT     (7)
#define MCXX_HOLD_SHIFT     (14)

static inline u_int pxa2xx_mcxx_hold(u_int pcmcia_cycle_ns,
				     u_int mem_clk_10khz)
{
	u_int code = pcmcia_cycle_ns * mem_clk_10khz;
	return (code / 300000) + ((code % 300000) ? 1 : 0) - 1;
}

static inline u_int pxa2xx_mcxx_asst(u_int pcmcia_cycle_ns,
				     u_int mem_clk_10khz)
{
	u_int code = pcmcia_cycle_ns * mem_clk_10khz;
	return (code / 300000) + ((code % 300000) ? 1 : 0) + 1;
}

static inline u_int pxa2xx_mcxx_setup(u_int pcmcia_cycle_ns,
				      u_int mem_clk_10khz)
{
	u_int code = pcmcia_cycle_ns * mem_clk_10khz;
	return (code / 100000) + ((code % 100000) ? 1 : 0) - 1;
}

/* This function returns the (approximate) command assertion period, in
 * nanoseconds, for a given CPU clock frequency and MCXX_ASST value:
 */
static inline u_int pxa2xx_pcmcia_cmd_time(u_int mem_clk_10khz,
					   u_int pcmcia_mcxx_asst)
{
	return (300000 * (pcmcia_mcxx_asst + 1) / mem_clk_10khz);
}

static int pxa2xx_pcmcia_set_mcmem( int sock, int speed, int clock )
{
	uint32_t val;

	val = ((pxa2xx_mcxx_setup(speed, clock)
		& MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
		| ((pxa2xx_mcxx_asst(speed, clock)
		& MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
		| ((pxa2xx_mcxx_hold(speed, clock)
		& MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);

	__raw_writel(val, MCMEM(sock));

	return 0;
}

static int pxa2xx_pcmcia_set_mcio( int sock, int speed, int clock )
{
	uint32_t val;

	val = ((pxa2xx_mcxx_setup(speed, clock)
		& MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
		| ((pxa2xx_mcxx_asst(speed, clock)
		& MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
		| ((pxa2xx_mcxx_hold(speed, clock)
		& MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);

	__raw_writel(val, MCIO(sock));

	return 0;
}

static int pxa2xx_pcmcia_set_mcatt( int sock, int speed, int clock )
{
	uint32_t val;

	val = ((pxa2xx_mcxx_setup(speed, clock)
		& MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
		| ((pxa2xx_mcxx_asst(speed, clock)
		& MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
		| ((pxa2xx_mcxx_hold(speed, clock)
		& MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);

	__raw_writel(val, MCATT(sock));

	return 0;
}

static int pxa2xx_pcmcia_set_mcxx(struct soc_pcmcia_socket *skt, unsigned int clk)
{
	struct soc_pcmcia_timing timing;
	int sock = skt->nr;

	soc_common_pcmcia_get_timing(skt, &timing);

	pxa2xx_pcmcia_set_mcmem(sock, timing.mem, clk);
	pxa2xx_pcmcia_set_mcatt(sock, timing.attr, clk);
	pxa2xx_pcmcia_set_mcio(sock, timing.io, clk);

	return 0;
}

static int pxa2xx_pcmcia_set_timing(struct soc_pcmcia_socket *skt)
{
	unsigned long clk = clk_get_rate(skt->clk);
	return pxa2xx_pcmcia_set_mcxx(skt, clk / 10000);
}

#ifdef CONFIG_CPU_FREQ

static int
pxa2xx_pcmcia_frequency_change(struct soc_pcmcia_socket *skt,
			       unsigned long val,
			       struct cpufreq_freqs *freqs)
{
	switch (val) {
	case CPUFREQ_PRECHANGE:
		if (freqs->new > freqs->old) {
			debug(skt, 2, "new frequency %u.%uMHz > %u.%uMHz, "
			       "pre-updating\n",
			       freqs->new / 1000, (freqs->new / 100) % 10,
			       freqs->old / 1000, (freqs->old / 100) % 10);
			pxa2xx_pcmcia_set_timing(skt);
		}
		break;

	case CPUFREQ_POSTCHANGE:
		if (freqs->new < freqs->old) {
			debug(skt, 2, "new frequency %u.%uMHz < %u.%uMHz, "
			       "post-updating\n",
			       freqs->new / 1000, (freqs->new / 100) % 10,
			       freqs->old / 1000, (freqs->old / 100) % 10);
			pxa2xx_pcmcia_set_timing(skt);
		}
		break;
	}
	return 0;
}
#endif

void pxa2xx_configure_sockets(struct device *dev)
{
	struct pcmcia_low_level *ops = dev->platform_data;
	/*
	 * We have at least one socket, so set MECR:CIT
	 * (Card Is There)
	 */
	uint32_t mecr = MECR_CIT;

	/* Set MECR:NOS (Number Of Sockets) */
	if ((ops->first + ops->nr) > 1 ||
	    machine_is_viper() || machine_is_arcom_zeus())
		mecr |= MECR_NOS;

	__raw_writel(mecr, MECR);
}
EXPORT_SYMBOL(pxa2xx_configure_sockets);

static const char *skt_names[] = {
	"PCMCIA socket 0",
	"PCMCIA socket 1",
};

#define SKT_DEV_INFO_SIZE(n) \
	(sizeof(struct skt_dev_info) + (n)*sizeof(struct soc_pcmcia_socket))

int pxa2xx_drv_pcmcia_add_one(struct soc_pcmcia_socket *skt)
{
	skt->res_skt.start = _PCMCIA(skt->nr);
	skt->res_skt.end = _PCMCIA(skt->nr) + PCMCIASp - 1;
	skt->res_skt.name = skt_names[skt->nr];
	skt->res_skt.flags = IORESOURCE_MEM;

	skt->res_io.start = _PCMCIAIO(skt->nr);
	skt->res_io.end = _PCMCIAIO(skt->nr) + PCMCIAIOSp - 1;
	skt->res_io.name = "io";
	skt->res_io.flags = IORESOURCE_MEM | IORESOURCE_BUSY;

	skt->res_mem.start = _PCMCIAMem(skt->nr);
	skt->res_mem.end = _PCMCIAMem(skt->nr) + PCMCIAMemSp - 1;
	skt->res_mem.name = "memory";
	skt->res_mem.flags = IORESOURCE_MEM;

	skt->res_attr.start = _PCMCIAAttr(skt->nr);
	skt->res_attr.end = _PCMCIAAttr(skt->nr) + PCMCIAAttrSp - 1;
	skt->res_attr.name = "attribute";
	skt->res_attr.flags = IORESOURCE_MEM;

	return soc_pcmcia_add_one(skt);
}
EXPORT_SYMBOL(pxa2xx_drv_pcmcia_add_one);

void pxa2xx_drv_pcmcia_ops(struct pcmcia_low_level *ops)
{
	/* Provide our PXA2xx specific timing routines. */
	ops->set_timing  = pxa2xx_pcmcia_set_timing;
#ifdef CONFIG_CPU_FREQ
	ops->frequency_change = pxa2xx_pcmcia_frequency_change;
#endif
}
EXPORT_SYMBOL(pxa2xx_drv_pcmcia_ops);

static int pxa2xx_drv_pcmcia_probe(struct platform_device *dev)
{
	int i, ret = 0;
	struct pcmcia_low_level *ops;
	struct skt_dev_info *sinfo;
	struct soc_pcmcia_socket *skt;
	struct clk *clk;

	ops = (struct pcmcia_low_level *)dev->dev.platform_data;
	if (!ops) {
		ret = -ENODEV;
		goto err0;
	}

	if (cpu_is_pxa320() && ops->nr > 1) {
		dev_err(&dev->dev, "pxa320 supports only one pcmcia slot");
		ret = -EINVAL;
		goto err0;
	}

	clk = clk_get(&dev->dev, NULL);
	if (!clk)
		return -ENODEV;

	pxa2xx_drv_pcmcia_ops(ops);

	sinfo = kzalloc(SKT_DEV_INFO_SIZE(ops->nr), GFP_KERNEL);
	if (!sinfo) {
		clk_put(clk);
		return -ENOMEM;
	}

	sinfo->nskt = ops->nr;
	sinfo->clk = clk;

	/* Initialize processor specific parameters */
	for (i = 0; i < ops->nr; i++) {
		skt = &sinfo->skt[i];

		skt->nr = ops->first + i;
		skt->clk = clk;
		skt->ops = ops;
		skt->socket.owner = ops->owner;
		skt->socket.dev.parent = &dev->dev;
		skt->socket.pci_irq = NO_IRQ;

		ret = pxa2xx_drv_pcmcia_add_one(skt);
		if (ret)
			goto err1;
	}

	if (ret) {
		while (--i >= 0)
			soc_pcmcia_remove_one(&sinfo->skt[i]);
		kfree(sinfo);
		clk_put(clk);
	} else {
		pxa2xx_configure_sockets(&dev->dev);
		dev_set_drvdata(&dev->dev, sinfo);
	}

	return 0;

err1:
	while (--i >= 0)
		soc_pcmcia_remove_one(&sinfo->skt[i]);
	kfree(sinfo);
err0:
	return ret;
}

static int pxa2xx_drv_pcmcia_remove(struct platform_device *dev)
{
	struct skt_dev_info *sinfo = platform_get_drvdata(dev);
	int i;

	platform_set_drvdata(dev, NULL);

	for (i = 0; i < sinfo->nskt; i++)
		soc_pcmcia_remove_one(&sinfo->skt[i]);

	clk_put(sinfo->clk);
	kfree(sinfo);
	return 0;
}

static int pxa2xx_drv_pcmcia_resume(struct device *dev)
{
	pxa2xx_configure_sockets(dev);
	return 0;
}

static const struct dev_pm_ops pxa2xx_drv_pcmcia_pm_ops = {
	.resume		= pxa2xx_drv_pcmcia_resume,
};

static struct platform_driver pxa2xx_pcmcia_driver = {
	.probe		= pxa2xx_drv_pcmcia_probe,
	.remove		= pxa2xx_drv_pcmcia_remove,
	.driver		= {
		.name	= "pxa2xx-pcmcia",
		.owner	= THIS_MODULE,
		.pm	= &pxa2xx_drv_pcmcia_pm_ops,
	},
};

static int __init pxa2xx_pcmcia_init(void)
{
	return platform_driver_register(&pxa2xx_pcmcia_driver);
}

static void __exit pxa2xx_pcmcia_exit(void)
{
	platform_driver_unregister(&pxa2xx_pcmcia_driver);
}

fs_initcall(pxa2xx_pcmcia_init);
module_exit(pxa2xx_pcmcia_exit);

MODULE_AUTHOR("Stefan Eletzhofer <stefan.eletzhofer@inquant.de> and Ian Molton <spyro@f2s.com>");
MODULE_DESCRIPTION("Linux PCMCIA Card Services: PXA2xx core socket driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:pxa2xx-pcmcia");
Commit	Line	Data
1da177e4 LT	1	/*======================================================================
	2
	3	Device driver for the PCMCIA control functionality of PXA2xx
	4	microprocessors.
	5
	6	The contents of this file may be used under the
	7	terms of the GNU Public License version 2 (the "GPL")
	8
	9	(c) Ian Molton (spyro@f2s.com) 2003
	10	(c) Stefan Eletzhofer (stefan.eletzhofer@inquant.de) 2003,4
	11
	12	derived from sa11xx_base.c
	13
	14	Portions created by John G. Dorsey are
	15	Copyright (C) 1999 John G. Dorsey.
	16
	17	======================================================================*/
	18
	19	#include <linux/module.h>
5a0e3ad6	20	#include <linux/slab.h>
1da177e4	21	#include <linux/init.h>
1da177e4 LT	22	#include <linux/cpufreq.h>
	23	#include <linux/ioport.h>
	24	#include <linux/kernel.h>
	25	#include <linux/spinlock.h>
d052d1be	26	#include <linux/platform_device.h>
1da177e4	27
a09e64fb	28	#include <mach/hardware.h>
ad68bb9f	29	#include <mach/smemc.h>
1da177e4 LT	30	#include <asm/io.h>
	31	#include <asm/irq.h>
	32	#include <asm/system.h>
a09e64fb	33	#include <mach/pxa2xx-regs.h>
20f18ff3	34	#include <asm/mach-types.h>
1da177e4	35
1da177e4	36	#include <pcmcia/ss.h>
1da177e4 LT	37	#include <pcmcia/cistpl.h>
1da177e4 LT	38
1da177e4 LT	39	#include "soc_common.h"
	40	#include "pxa2xx_base.h"
	41
b393c696 EM	42	/*
	43	* Personal Computer Memory Card International Association (PCMCIA) sockets
	44	*/
	45
	46	#define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */
	47	#define PCMCIASp (4PCMCIAPrtSp) / PCMCIA Space [byte] */
	48	#define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */
	49	#define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */
	50	#define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */
	51
	52	#define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */
	53	#define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */
	54	#define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */
	55	#define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */
	56
	57	#define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */
	58	#define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */
	59	#define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */
	60	#define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */
	61
	62	#define _PCMCIA(Nb) /* PCMCIA [0..1] */ \
	63	(0x20000000 + (Nb) * PCMCIASp)
	64	#define _PCMCIAIO(Nb) _PCMCIA(Nb) /* PCMCIA I/O [0..1] */
	65	#define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \
	66	(_PCMCIA(Nb) + 2 * PCMCIAPrtSp)
	67	#define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
	68	(_PCMCIA(Nb) + 3 * PCMCIAPrtSp)
	69
	70	#define _PCMCIA0 _PCMCIA(0) /* PCMCIA 0 */
	71	#define _PCMCIA0IO _PCMCIAIO(0) /* PCMCIA 0 I/O */
	72	#define _PCMCIA0Attr _PCMCIAAttr(0) /* PCMCIA 0 Attribute */
	73	#define _PCMCIA0Mem _PCMCIAMem(0) /* PCMCIA 0 Memory */
	74
	75	#define _PCMCIA1 _PCMCIA(1) /* PCMCIA 1 */
	76	#define _PCMCIA1IO _PCMCIAIO(1) /* PCMCIA 1 I/O */
	77	#define _PCMCIA1Attr _PCMCIAAttr(1) /* PCMCIA 1 Attribute */
	78	#define _PCMCIA1Mem _PCMCIAMem(1) /* PCMCIA 1 Memory */
	79
1da177e4 LT	80
	81	#define MCXX_SETUP_MASK (0x7f)
	82	#define MCXX_ASST_MASK (0x1f)
	83	#define MCXX_HOLD_MASK (0x3f)
	84	#define MCXX_SETUP_SHIFT (0)
	85	#define MCXX_ASST_SHIFT (7)
	86	#define MCXX_HOLD_SHIFT (14)
	87
	88	static inline u_int pxa2xx_mcxx_hold(u_int pcmcia_cycle_ns,
	89	u_int mem_clk_10khz)
	90	{
	91	u_int code = pcmcia_cycle_ns * mem_clk_10khz;
	92	return (code / 300000) + ((code % 300000) ? 1 : 0) - 1;
	93	}
	94
	95	static inline u_int pxa2xx_mcxx_asst(u_int pcmcia_cycle_ns,
	96	u_int mem_clk_10khz)
	97	{
	98	u_int code = pcmcia_cycle_ns * mem_clk_10khz;
24d6572b	99	return (code / 300000) + ((code % 300000) ? 1 : 0) + 1;
1da177e4 LT	100	}
	101
	102	static inline u_int pxa2xx_mcxx_setup(u_int pcmcia_cycle_ns,
	103	u_int mem_clk_10khz)
	104	{
	105	u_int code = pcmcia_cycle_ns * mem_clk_10khz;
	106	return (code / 100000) + ((code % 100000) ? 1 : 0) - 1;
	107	}
	108
	109	/* This function returns the (approximate) command assertion period, in
	110	* nanoseconds, for a given CPU clock frequency and MCXX_ASST value:
	111	*/
	112	static inline u_int pxa2xx_pcmcia_cmd_time(u_int mem_clk_10khz,
	113	u_int pcmcia_mcxx_asst)
	114	{
	115	return (300000 * (pcmcia_mcxx_asst + 1) / mem_clk_10khz);
	116	}
	117
	118	static int pxa2xx_pcmcia_set_mcmem( int sock, int speed, int clock )
	119	{
ad68bb9f MV	120	uint32_t val;
	121
	122	val = ((pxa2xx_mcxx_setup(speed, clock)
1da177e4 LT	123	& MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
	124	\| ((pxa2xx_mcxx_asst(speed, clock)
	125	& MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
	126	\| ((pxa2xx_mcxx_hold(speed, clock)
	127	& MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
	128
ad68bb9f MV	129	__raw_writel(val, MCMEM(sock));
ad68bb9f MV	130
1da177e4 LT	131	return 0;
	132	}
	133
	134	static int pxa2xx_pcmcia_set_mcio( int sock, int speed, int clock )
	135	{
ad68bb9f MV	136	uint32_t val;
	137
	138	val = ((pxa2xx_mcxx_setup(speed, clock)
1da177e4 LT	139	& MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
	140	\| ((pxa2xx_mcxx_asst(speed, clock)
	141	& MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
	142	\| ((pxa2xx_mcxx_hold(speed, clock)
	143	& MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
	144
ad68bb9f MV	145	__raw_writel(val, MCIO(sock));
ad68bb9f MV	146
1da177e4 LT	147	return 0;
	148	}
	149
	150	static int pxa2xx_pcmcia_set_mcatt( int sock, int speed, int clock )
	151	{
ad68bb9f MV	152	uint32_t val;
	153
	154	val = ((pxa2xx_mcxx_setup(speed, clock)
1da177e4 LT	155	& MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
	156	\| ((pxa2xx_mcxx_asst(speed, clock)
	157	& MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
	158	\| ((pxa2xx_mcxx_hold(speed, clock)
	159	& MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
	160
ad68bb9f MV	161	__raw_writel(val, MCATT(sock));
ad68bb9f MV	162
1da177e4 LT	163	return 0;
	164	}
	165
	166	static int pxa2xx_pcmcia_set_mcxx(struct soc_pcmcia_socket *skt, unsigned int clk)
	167	{
	168	struct soc_pcmcia_timing timing;
	169	int sock = skt->nr;
	170
	171	soc_common_pcmcia_get_timing(skt, &timing);
	172
	173	pxa2xx_pcmcia_set_mcmem(sock, timing.mem, clk);
	174	pxa2xx_pcmcia_set_mcatt(sock, timing.attr, clk);
	175	pxa2xx_pcmcia_set_mcio(sock, timing.io, clk);
	176
	177	return 0;
	178	}
	179
	180	static int pxa2xx_pcmcia_set_timing(struct soc_pcmcia_socket *skt)
	181	{
2a125dd5 EM	182	unsigned long clk = clk_get_rate(skt->clk);
2a125dd5 EM	183	return pxa2xx_pcmcia_set_mcxx(skt, clk / 10000);
1da177e4 LT	184	}
	185
	186	#ifdef CONFIG_CPU_FREQ
	187
	188	static int
	189	pxa2xx_pcmcia_frequency_change(struct soc_pcmcia_socket *skt,
	190	unsigned long val,
	191	struct cpufreq_freqs *freqs)
	192	{
1da177e4 LT	193	switch (val) {
	194	case CPUFREQ_PRECHANGE:
	195	if (freqs->new > freqs->old) {
	196	debug(skt, 2, "new frequency %u.%uMHz > %u.%uMHz, "
	197	"pre-updating\n",
	198	freqs->new / 1000, (freqs->new / 100) % 10,
	199	freqs->old / 1000, (freqs->old / 100) % 10);
d344a21a	200	pxa2xx_pcmcia_set_timing(skt);
1da177e4 LT	201	}
	202	break;
	203
	204	case CPUFREQ_POSTCHANGE:
	205	if (freqs->new < freqs->old) {
	206	debug(skt, 2, "new frequency %u.%uMHz < %u.%uMHz, "
	207	"post-updating\n",
	208	freqs->new / 1000, (freqs->new / 100) % 10,
	209	freqs->old / 1000, (freqs->old / 100) % 10);
d344a21a	210	pxa2xx_pcmcia_set_timing(skt);
1da177e4 LT	211	}
	212	break;
	213	}
	214	return 0;
	215	}
	216	#endif
	217
5b703683	218	void pxa2xx_configure_sockets(struct device *dev)
20f18ff3 MZ	219	{
20f18ff3 MZ	220	struct pcmcia_low_level *ops = dev->platform_data;
20f18ff3 MZ	221	/*
	222	* We have at least one socket, so set MECR:CIT
	223	* (Card Is There)
	224	*/
ad68bb9f	225	uint32_t mecr = MECR_CIT;
20f18ff3 MZ	226
20f18ff3 MZ	227	/* Set MECR:NOS (Number Of Sockets) */
c2de1c38 MZ	228	if ((ops->first + ops->nr) > 1 \|\|
c2de1c38 MZ	229	machine_is_viper() \|\| machine_is_arcom_zeus())
ad68bb9f MV	230	mecr \|= MECR_NOS;
	231
	232	__raw_writel(mecr, MECR);
20f18ff3	233	}
d5240dfd	234	EXPORT_SYMBOL(pxa2xx_configure_sockets);
20f18ff3	235
b393c696 EM	236	static const char *skt_names[] = {
	237	"PCMCIA socket 0",
	238	"PCMCIA socket 1",
	239	};
	240
	241	#define SKT_DEV_INFO_SIZE(n) \
	242	(sizeof(struct skt_dev_info) + (n)*sizeof(struct soc_pcmcia_socket))
	243
701a5dc0	244	int pxa2xx_drv_pcmcia_add_one(struct soc_pcmcia_socket *skt)
da4f0073 RKAL	245	{
	246	skt->res_skt.start = _PCMCIA(skt->nr);
	247	skt->res_skt.end = _PCMCIA(skt->nr) + PCMCIASp - 1;
	248	skt->res_skt.name = skt_names[skt->nr];
	249	skt->res_skt.flags = IORESOURCE_MEM;
	250
	251	skt->res_io.start = _PCMCIAIO(skt->nr);
	252	skt->res_io.end = _PCMCIAIO(skt->nr) + PCMCIAIOSp - 1;
	253	skt->res_io.name = "io";
	254	skt->res_io.flags = IORESOURCE_MEM \| IORESOURCE_BUSY;
	255
	256	skt->res_mem.start = _PCMCIAMem(skt->nr);
	257	skt->res_mem.end = _PCMCIAMem(skt->nr) + PCMCIAMemSp - 1;
	258	skt->res_mem.name = "memory";
	259	skt->res_mem.flags = IORESOURCE_MEM;
	260
	261	skt->res_attr.start = _PCMCIAAttr(skt->nr);
	262	skt->res_attr.end = _PCMCIAAttr(skt->nr) + PCMCIAAttrSp - 1;
	263	skt->res_attr.name = "attribute";
	264	skt->res_attr.flags = IORESOURCE_MEM;
	265
	266	return soc_pcmcia_add_one(skt);
	267	}
d0d26c33	268	EXPORT_SYMBOL(pxa2xx_drv_pcmcia_add_one);
da4f0073	269
701a5dc0 RKAL	270	void pxa2xx_drv_pcmcia_ops(struct pcmcia_low_level *ops)
	271	{
	272	/* Provide our PXA2xx specific timing routines. */
	273	ops->set_timing = pxa2xx_pcmcia_set_timing;
	274	#ifdef CONFIG_CPU_FREQ
	275	ops->frequency_change = pxa2xx_pcmcia_frequency_change;
	276	#endif
	277	}
d0d26c33	278	EXPORT_SYMBOL(pxa2xx_drv_pcmcia_ops);
701a5dc0	279
d0d26c33	280	static int pxa2xx_drv_pcmcia_probe(struct platform_device *dev)
1da177e4	281	{
701a5dc0	282	int i, ret = 0;
1da177e4	283	struct pcmcia_low_level *ops;
b393c696 EM	284	struct skt_dev_info *sinfo;
b393c696 EM	285	struct soc_pcmcia_socket *skt;
2a125dd5	286	struct clk *clk;
1da177e4	287
d0d26c33	288	ops = (struct pcmcia_low_level *)dev->dev.platform_data;
a4257af5 MV	289	if (!ops) {
	290	ret = -ENODEV;
	291	goto err0;
	292	}
	293
	294	if (cpu_is_pxa320() && ops->nr > 1) {
	295	dev_err(&dev->dev, "pxa320 supports only one pcmcia slot");
	296	ret = -EINVAL;
	297	goto err0;
	298	}
1da177e4	299
2a125dd5 EM	300	clk = clk_get(&dev->dev, NULL);
	301	if (!clk)
	302	return -ENODEV;
	303
701a5dc0	304	pxa2xx_drv_pcmcia_ops(ops);
da4f0073	305
b393c696	306	sinfo = kzalloc(SKT_DEV_INFO_SIZE(ops->nr), GFP_KERNEL);
2a125dd5 EM	307	if (!sinfo) {
2a125dd5 EM	308	clk_put(clk);
b393c696	309	return -ENOMEM;
2a125dd5	310	}
b393c696 EM	311
b393c696 EM	312	sinfo->nskt = ops->nr;
2a125dd5	313	sinfo->clk = clk;
b393c696 EM	314
	315	/* Initialize processor specific parameters */
	316	for (i = 0; i < ops->nr; i++) {
	317	skt = &sinfo->skt[i];
	318
da4f0073	319	skt->nr = ops->first + i;
2a125dd5	320	skt->clk = clk;
da4f0073 RKAL	321	skt->ops = ops;
da4f0073 RKAL	322	skt->socket.owner = ops->owner;
a7a5ac58	323	skt->socket.dev.parent = &dev->dev;
66024db5	324	skt->socket.pci_irq = NO_IRQ;
b393c696	325
da4f0073 RKAL	326	ret = pxa2xx_drv_pcmcia_add_one(skt);
da4f0073 RKAL	327	if (ret)
a4257af5	328	goto err1;
b393c696 EM	329	}
b393c696 EM	330
da4f0073 RKAL	331	if (ret) {
	332	while (--i >= 0)
	333	soc_pcmcia_remove_one(&sinfo->skt[i]);
	334	kfree(sinfo);
2a125dd5	335	clk_put(clk);
da4f0073	336	} else {
a7a5ac58 MZ	337	pxa2xx_configure_sockets(&dev->dev);
a7a5ac58 MZ	338	dev_set_drvdata(&dev->dev, sinfo);
da4f0073	339	}
1da177e4	340
a4257af5 MV	341	return 0;
	342
	343	err1:
	344	while (--i >= 0)
	345	soc_pcmcia_remove_one(&sinfo->skt[i]);
	346	kfree(sinfo);
	347	err0:
1da177e4 LT	348	return ret;
1da177e4 LT	349	}
9468613b RK	350
	351	static int pxa2xx_drv_pcmcia_remove(struct platform_device *dev)
	352	{
be85458e RKAL	353	struct skt_dev_info *sinfo = platform_get_drvdata(dev);
	354	int i;
	355
	356	platform_set_drvdata(dev, NULL);
	357
	358	for (i = 0; i < sinfo->nskt; i++)
	359	soc_pcmcia_remove_one(&sinfo->skt[i]);
	360
2a125dd5	361	clk_put(sinfo->clk);
be85458e RKAL	362	kfree(sinfo);
be85458e RKAL	363	return 0;
9468613b RK	364	}
9468613b RK	365
85c61021	366	static int pxa2xx_drv_pcmcia_resume(struct device *dev)
1da177e4	367	{
85c61021	368	pxa2xx_configure_sockets(dev);
d7646f76	369	return 0;
1da177e4 LT	370	}
1da177e4 LT	371
47145210	372	static const struct dev_pm_ops pxa2xx_drv_pcmcia_pm_ops = {
85c61021 MR	373	.resume = pxa2xx_drv_pcmcia_resume,
	374	};
	375
9468613b	376	static struct platform_driver pxa2xx_pcmcia_driver = {
1da177e4	377	.probe = pxa2xx_drv_pcmcia_probe,
9468613b	378	.remove = pxa2xx_drv_pcmcia_remove,
9468613b RK	379	.driver = {
9468613b RK	380	.name = "pxa2xx-pcmcia",
12c2c019	381	.owner = THIS_MODULE,
85c61021	382	.pm = &pxa2xx_drv_pcmcia_pm_ops,
9468613b	383	},
1da177e4 LT	384	};
	385
	386	static int __init pxa2xx_pcmcia_init(void)
	387	{
9468613b	388	return platform_driver_register(&pxa2xx_pcmcia_driver);
1da177e4 LT	389	}
	390
	391	static void __exit pxa2xx_pcmcia_exit(void)
	392	{
9468613b	393	platform_driver_unregister(&pxa2xx_pcmcia_driver);
1da177e4 LT	394	}
1da177e4 LT	395
f36598ae	396	fs_initcall(pxa2xx_pcmcia_init);
1da177e4 LT	397	module_exit(pxa2xx_pcmcia_exit);
	398
	399	MODULE_AUTHOR("Stefan Eletzhofer <stefan.eletzhofer@inquant.de> and Ian Molton <spyro@f2s.com>");
	400	MODULE_DESCRIPTION("Linux PCMCIA Card Services: PXA2xx core socket driver");
	401	MODULE_LICENSE("GPL");
12c2c019	402	MODULE_ALIAS("platform:pxa2xx-pcmcia");