Commit | Line | Data |
---|---|---|
de957c89 MT |
1 | /* |
2 | * m8xx_pcmcia.c - Linux PCMCIA socket driver for the mpc8xx series. | |
3 | * | |
cbba0de2 | 4 | * (C) 1999-2000 Magnus Damm <damm@opensource.se> |
de957c89 MT |
5 | * (C) 2001-2002 Montavista Software, Inc. |
6 | * <mlocke@mvista.com> | |
7 | * | |
8 | * Support for two slots by Cyclades Corporation | |
9 | * <oliver.kurth@cyclades.de> | |
10 | * Further fixes, v2.6 kernel port | |
11 | * <marcelo.tosatti@cyclades.com> | |
1371d3be | 12 | * |
80128ff7 | 13 | * Some fixes, additions (C) 2005-2007 Montavista Software, Inc. |
1371d3be | 14 | * <vbordug@ru.mvista.com> |
de957c89 MT |
15 | * |
16 | * "The ExCA standard specifies that socket controllers should provide | |
17 | * two IO and five memory windows per socket, which can be independently | |
18 | * configured and positioned in the host address space and mapped to | |
19 | * arbitrary segments of card address space. " - David A Hinds. 1999 | |
20 | * | |
21 | * This controller does _not_ meet the ExCA standard. | |
22 | * | |
23 | * m8xx pcmcia controller brief info: | |
24 | * + 8 windows (attrib, mem, i/o) | |
25 | * + up to two slots (SLOT_A and SLOT_B) | |
26 | * + inputpins, outputpins, event and mask registers. | |
27 | * - no offset register. sigh. | |
28 | * | |
29 | * Because of the lacking offset register we must map the whole card. | |
30 | * We assign each memory window PCMCIA_MEM_WIN_SIZE address space. | |
31 | * Make sure there is (PCMCIA_MEM_WIN_SIZE * PCMCIA_MEM_WIN_NO | |
32 | * * PCMCIA_SOCKETS_NO) bytes at PCMCIA_MEM_WIN_BASE. | |
33 | * The i/o windows are dynamically allocated at PCMCIA_IO_WIN_BASE. | |
34 | * They are maximum 64KByte each... | |
35 | */ | |
36 | ||
37 | #include <linux/module.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/types.h> | |
40 | #include <linux/fcntl.h> | |
41 | #include <linux/string.h> | |
42 | ||
de957c89 MT |
43 | #include <linux/kernel.h> |
44 | #include <linux/errno.h> | |
de957c89 MT |
45 | #include <linux/slab.h> |
46 | #include <linux/timer.h> | |
47 | #include <linux/ioport.h> | |
48 | #include <linux/delay.h> | |
49 | #include <linux/interrupt.h> | |
80128ff7 | 50 | #include <linux/fsl_devices.h> |
1977f032 | 51 | #include <linux/bitops.h> |
ad19dbdb SR |
52 | #include <linux/of_device.h> |
53 | #include <linux/of_platform.h> | |
de957c89 | 54 | |
80128ff7 | 55 | #include <asm/io.h> |
80128ff7 VB |
56 | #include <asm/system.h> |
57 | #include <asm/time.h> | |
de957c89 MT |
58 | #include <asm/mpc8xx.h> |
59 | #include <asm/8xx_immap.h> | |
60 | #include <asm/irq.h> | |
80128ff7 | 61 | #include <asm/fs_pd.h> |
de957c89 | 62 | |
de957c89 MT |
63 | #include <pcmcia/cs_types.h> |
64 | #include <pcmcia/cs.h> | |
65 | #include <pcmcia/ss.h> | |
66 | ||
7d16b658 DB |
67 | #ifdef CONFIG_PCMCIA_DEBUG |
68 | static int pc_debug; | |
de957c89 MT |
69 | module_param(pc_debug, int, 0); |
70 | #define dprintk(args...) printk(KERN_DEBUG "m8xx_pcmcia: " args); | |
71 | #else | |
72 | #define dprintk(args...) | |
73 | #endif | |
74 | ||
75 | #define pcmcia_info(args...) printk(KERN_INFO "m8xx_pcmcia: "args) | |
76 | #define pcmcia_error(args...) printk(KERN_ERR "m8xx_pcmcia: "args) | |
77 | ||
78 | static const char *version = "Version 0.06, Aug 2005"; | |
79 | MODULE_LICENSE("Dual MPL/GPL"); | |
80 | ||
81 | #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) | |
82 | ||
83 | /* The RPX series use SLOT_B */ | |
84 | #if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE) | |
85 | #define CONFIG_PCMCIA_SLOT_B | |
86 | #define CONFIG_BD_IS_MHZ | |
87 | #endif | |
88 | ||
89 | /* The ADS board use SLOT_A */ | |
90 | #ifdef CONFIG_ADS | |
91 | #define CONFIG_PCMCIA_SLOT_A | |
92 | #define CONFIG_BD_IS_MHZ | |
93 | #endif | |
94 | ||
95 | /* The FADS series are a mess */ | |
96 | #ifdef CONFIG_FADS | |
97 | #if defined(CONFIG_MPC860T) || defined(CONFIG_MPC860) || defined(CONFIG_MPC821) | |
98 | #define CONFIG_PCMCIA_SLOT_A | |
99 | #else | |
100 | #define CONFIG_PCMCIA_SLOT_B | |
101 | #endif | |
102 | #endif | |
103 | ||
1371d3be VB |
104 | #if defined(CONFIG_MPC885ADS) |
105 | #define CONFIG_PCMCIA_SLOT_A | |
106 | #define PCMCIA_GLITCHY_CD | |
107 | #endif | |
108 | ||
de957c89 MT |
109 | /* Cyclades ACS uses both slots */ |
110 | #ifdef CONFIG_PRxK | |
111 | #define CONFIG_PCMCIA_SLOT_A | |
112 | #define CONFIG_PCMCIA_SLOT_B | |
113 | #endif | |
114 | ||
99121c0d | 115 | #endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */ |
de957c89 MT |
116 | |
117 | #if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B) | |
118 | ||
119 | #define PCMCIA_SOCKETS_NO 2 | |
120 | /* We have only 8 windows, dualsocket support will be limited. */ | |
121 | #define PCMCIA_MEM_WIN_NO 2 | |
122 | #define PCMCIA_IO_WIN_NO 2 | |
123 | #define PCMCIA_SLOT_MSG "SLOT_A and SLOT_B" | |
124 | ||
125 | #elif defined(CONFIG_PCMCIA_SLOT_A) || defined(CONFIG_PCMCIA_SLOT_B) | |
126 | ||
127 | #define PCMCIA_SOCKETS_NO 1 | |
128 | /* full support for one slot */ | |
129 | #define PCMCIA_MEM_WIN_NO 5 | |
130 | #define PCMCIA_IO_WIN_NO 2 | |
131 | ||
132 | /* define _slot_ to be able to optimize macros */ | |
133 | ||
134 | #ifdef CONFIG_PCMCIA_SLOT_A | |
135 | #define _slot_ 0 | |
136 | #define PCMCIA_SLOT_MSG "SLOT_A" | |
137 | #else | |
138 | #define _slot_ 1 | |
139 | #define PCMCIA_SLOT_MSG "SLOT_B" | |
140 | #endif | |
141 | ||
142 | #else | |
143 | #error m8xx_pcmcia: Bad configuration! | |
144 | #endif | |
145 | ||
146 | /* ------------------------------------------------------------------------- */ | |
147 | ||
99121c0d VB |
148 | #define PCMCIA_MEM_WIN_BASE 0xe0000000 /* base address for memory window 0 */ |
149 | #define PCMCIA_MEM_WIN_SIZE 0x04000000 /* each memory window is 64 MByte */ | |
150 | #define PCMCIA_IO_WIN_BASE _IO_BASE /* base address for io window 0 */ | |
de957c89 MT |
151 | /* ------------------------------------------------------------------------- */ |
152 | ||
80128ff7 | 153 | static int pcmcia_schlvl; |
de957c89 | 154 | |
34af946a | 155 | static DEFINE_SPINLOCK(events_lock); |
de957c89 | 156 | |
de957c89 MT |
157 | #define PCMCIA_SOCKET_KEY_5V 1 |
158 | #define PCMCIA_SOCKET_KEY_LV 2 | |
159 | ||
160 | /* look up table for pgcrx registers */ | |
80128ff7 | 161 | static u32 *m8xx_pgcrx[2]; |
de957c89 MT |
162 | |
163 | /* | |
164 | * This structure is used to address each window in the PCMCIA controller. | |
165 | * | |
166 | * Keep in mind that we assume that pcmcia_win[n+1] is mapped directly | |
167 | * after pcmcia_win[n]... | |
168 | */ | |
169 | ||
170 | struct pcmcia_win { | |
99121c0d VB |
171 | u32 br; |
172 | u32 or; | |
de957c89 MT |
173 | }; |
174 | ||
175 | /* | |
176 | * For some reason the hardware guys decided to make both slots share | |
177 | * some registers. | |
178 | * | |
179 | * Could someone invent object oriented hardware ? | |
180 | * | |
181 | * The macros are used to get the right bit from the registers. | |
182 | * SLOT_A : slot = 0 | |
183 | * SLOT_B : slot = 1 | |
184 | */ | |
185 | ||
186 | #define M8XX_PCMCIA_VS1(slot) (0x80000000 >> (slot << 4)) | |
187 | #define M8XX_PCMCIA_VS2(slot) (0x40000000 >> (slot << 4)) | |
188 | #define M8XX_PCMCIA_VS_MASK(slot) (0xc0000000 >> (slot << 4)) | |
189 | #define M8XX_PCMCIA_VS_SHIFT(slot) (30 - (slot << 4)) | |
190 | ||
191 | #define M8XX_PCMCIA_WP(slot) (0x20000000 >> (slot << 4)) | |
192 | #define M8XX_PCMCIA_CD2(slot) (0x10000000 >> (slot << 4)) | |
193 | #define M8XX_PCMCIA_CD1(slot) (0x08000000 >> (slot << 4)) | |
194 | #define M8XX_PCMCIA_BVD2(slot) (0x04000000 >> (slot << 4)) | |
195 | #define M8XX_PCMCIA_BVD1(slot) (0x02000000 >> (slot << 4)) | |
196 | #define M8XX_PCMCIA_RDY(slot) (0x01000000 >> (slot << 4)) | |
197 | #define M8XX_PCMCIA_RDY_L(slot) (0x00800000 >> (slot << 4)) | |
198 | #define M8XX_PCMCIA_RDY_H(slot) (0x00400000 >> (slot << 4)) | |
199 | #define M8XX_PCMCIA_RDY_R(slot) (0x00200000 >> (slot << 4)) | |
200 | #define M8XX_PCMCIA_RDY_F(slot) (0x00100000 >> (slot << 4)) | |
201 | #define M8XX_PCMCIA_MASK(slot) (0xFFFF0000 >> (slot << 4)) | |
202 | ||
203 | #define M8XX_PCMCIA_POR_VALID 0x00000001 | |
204 | #define M8XX_PCMCIA_POR_WRPROT 0x00000002 | |
205 | #define M8XX_PCMCIA_POR_ATTRMEM 0x00000010 | |
206 | #define M8XX_PCMCIA_POR_IO 0x00000018 | |
207 | #define M8XX_PCMCIA_POR_16BIT 0x00000040 | |
208 | ||
209 | #define M8XX_PGCRX(slot) m8xx_pgcrx[slot] | |
210 | ||
211 | #define M8XX_PGCRX_CXOE 0x00000080 | |
212 | #define M8XX_PGCRX_CXRESET 0x00000040 | |
213 | ||
214 | /* we keep one lookup table per socket to check flags */ | |
215 | ||
99121c0d | 216 | #define PCMCIA_EVENTS_MAX 5 /* 4 max at a time + termination */ |
de957c89 MT |
217 | |
218 | struct event_table { | |
219 | u32 regbit; | |
220 | u32 eventbit; | |
221 | }; | |
222 | ||
80128ff7 VB |
223 | static const char driver_name[] = "m8xx-pcmcia"; |
224 | ||
de957c89 | 225 | struct socket_info { |
99121c0d VB |
226 | void (*handler) (void *info, u32 events); |
227 | void *info; | |
de957c89 MT |
228 | |
229 | u32 slot; | |
80128ff7 VB |
230 | pcmconf8xx_t *pcmcia; |
231 | u32 bus_freq; | |
232 | int hwirq; | |
de957c89 MT |
233 | |
234 | socket_state_t state; | |
235 | struct pccard_mem_map mem_win[PCMCIA_MEM_WIN_NO]; | |
99121c0d | 236 | struct pccard_io_map io_win[PCMCIA_IO_WIN_NO]; |
de957c89 MT |
237 | struct event_table events[PCMCIA_EVENTS_MAX]; |
238 | struct pcmcia_socket socket; | |
239 | }; | |
240 | ||
241 | static struct socket_info socket[PCMCIA_SOCKETS_NO]; | |
242 | ||
243 | /* | |
244 | * Search this table to see if the windowsize is | |
245 | * supported... | |
246 | */ | |
247 | ||
248 | #define M8XX_SIZES_NO 32 | |
249 | ||
99121c0d | 250 | static const u32 m8xx_size_to_gray[M8XX_SIZES_NO] = { |
de957c89 MT |
251 | 0x00000001, 0x00000002, 0x00000008, 0x00000004, |
252 | 0x00000080, 0x00000040, 0x00000010, 0x00000020, | |
253 | 0x00008000, 0x00004000, 0x00001000, 0x00002000, | |
254 | 0x00000100, 0x00000200, 0x00000800, 0x00000400, | |
255 | ||
256 | 0x0fffffff, 0xffffffff, 0xffffffff, 0xffffffff, | |
257 | 0x01000000, 0x02000000, 0xffffffff, 0x04000000, | |
258 | 0x00010000, 0x00020000, 0x00080000, 0x00040000, | |
259 | 0x00800000, 0x00400000, 0x00100000, 0x00200000 | |
260 | }; | |
261 | ||
262 | /* ------------------------------------------------------------------------- */ | |
263 | ||
7d12e780 | 264 | static irqreturn_t m8xx_interrupt(int irq, void *dev); |
de957c89 | 265 | |
99121c0d | 266 | #define PCMCIA_BMT_LIMIT (15*4) /* Bus Monitor Timeout value */ |
de957c89 MT |
267 | |
268 | /* ------------------------------------------------------------------------- */ | |
269 | /* board specific stuff: */ | |
270 | /* voltage_set(), hardware_enable() and hardware_disable() */ | |
271 | /* ------------------------------------------------------------------------- */ | |
272 | /* RPX Boards from Embedded Planet */ | |
273 | ||
274 | #if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE) | |
275 | ||
276 | /* The RPX boards seems to have it's bus monitor timeout set to 6*8 clocks. | |
277 | * SYPCR is write once only, therefore must the slowest memory be faster | |
278 | * than the bus monitor or we will get a machine check due to the bus timeout. | |
279 | */ | |
280 | ||
281 | #define PCMCIA_BOARD_MSG "RPX CLASSIC or RPX LITE" | |
282 | ||
283 | #undef PCMCIA_BMT_LIMIT | |
284 | #define PCMCIA_BMT_LIMIT (6*8) | |
285 | ||
286 | static int voltage_set(int slot, int vcc, int vpp) | |
287 | { | |
288 | u32 reg = 0; | |
289 | ||
99121c0d VB |
290 | switch (vcc) { |
291 | case 0: | |
292 | break; | |
de957c89 MT |
293 | case 33: |
294 | reg |= BCSR1_PCVCTL4; | |
295 | break; | |
296 | case 50: | |
297 | reg |= BCSR1_PCVCTL5; | |
298 | break; | |
299 | default: | |
300 | return 1; | |
301 | } | |
302 | ||
99121c0d VB |
303 | switch (vpp) { |
304 | case 0: | |
305 | break; | |
de957c89 MT |
306 | case 33: |
307 | case 50: | |
99121c0d | 308 | if (vcc == vpp) |
de957c89 MT |
309 | reg |= BCSR1_PCVCTL6; |
310 | else | |
311 | return 1; | |
312 | break; | |
313 | case 120: | |
314 | reg |= BCSR1_PCVCTL7; | |
315 | default: | |
316 | return 1; | |
317 | } | |
318 | ||
99121c0d | 319 | if (!((vcc == 50) || (vcc == 0))) |
de957c89 MT |
320 | return 1; |
321 | ||
322 | /* first, turn off all power */ | |
323 | ||
99121c0d VB |
324 | out_be32(((u32 *) RPX_CSR_ADDR), |
325 | in_be32(((u32 *) RPX_CSR_ADDR)) & ~(BCSR1_PCVCTL4 | | |
326 | BCSR1_PCVCTL5 | | |
327 | BCSR1_PCVCTL6 | | |
328 | BCSR1_PCVCTL7)); | |
de957c89 MT |
329 | |
330 | /* enable new powersettings */ | |
331 | ||
99121c0d | 332 | out_be32(((u32 *) RPX_CSR_ADDR), in_be32(((u32 *) RPX_CSR_ADDR)) | reg); |
de957c89 MT |
333 | |
334 | return 0; | |
335 | } | |
336 | ||
337 | #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V | |
99121c0d VB |
338 | #define hardware_enable(_slot_) /* No hardware to enable */ |
339 | #define hardware_disable(_slot_) /* No hardware to disable */ | |
de957c89 | 340 | |
99121c0d | 341 | #endif /* CONFIG_RPXCLASSIC */ |
de957c89 MT |
342 | |
343 | /* FADS Boards from Motorola */ | |
344 | ||
345 | #if defined(CONFIG_FADS) | |
346 | ||
347 | #define PCMCIA_BOARD_MSG "FADS" | |
348 | ||
349 | static int voltage_set(int slot, int vcc, int vpp) | |
350 | { | |
351 | u32 reg = 0; | |
352 | ||
99121c0d VB |
353 | switch (vcc) { |
354 | case 0: | |
355 | break; | |
356 | case 33: | |
357 | reg |= BCSR1_PCCVCC0; | |
358 | break; | |
359 | case 50: | |
360 | reg |= BCSR1_PCCVCC1; | |
361 | break; | |
362 | default: | |
363 | return 1; | |
de957c89 MT |
364 | } |
365 | ||
99121c0d VB |
366 | switch (vpp) { |
367 | case 0: | |
368 | break; | |
369 | case 33: | |
370 | case 50: | |
371 | if (vcc == vpp) | |
372 | reg |= BCSR1_PCCVPP1; | |
373 | else | |
de957c89 | 374 | return 1; |
99121c0d VB |
375 | break; |
376 | case 120: | |
377 | if ((vcc == 33) || (vcc == 50)) | |
378 | reg |= BCSR1_PCCVPP0; | |
379 | else | |
380 | return 1; | |
381 | default: | |
382 | return 1; | |
de957c89 MT |
383 | } |
384 | ||
385 | /* first, turn off all power */ | |
99121c0d VB |
386 | out_be32((u32 *) BCSR1, |
387 | in_be32((u32 *) BCSR1) & ~(BCSR1_PCCVCC_MASK | | |
388 | BCSR1_PCCVPP_MASK)); | |
1371d3be VB |
389 | |
390 | /* enable new powersettings */ | |
99121c0d | 391 | out_be32((u32 *) BCSR1, in_be32((u32 *) BCSR1) | reg); |
1371d3be VB |
392 | |
393 | return 0; | |
394 | } | |
395 | ||
396 | #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V | |
397 | ||
398 | static void hardware_enable(int slot) | |
399 | { | |
99121c0d | 400 | out_be32((u32 *) BCSR1, in_be32((u32 *) BCSR1) & ~BCSR1_PCCEN); |
1371d3be VB |
401 | } |
402 | ||
403 | static void hardware_disable(int slot) | |
404 | { | |
99121c0d | 405 | out_be32((u32 *) BCSR1, in_be32((u32 *) BCSR1) | BCSR1_PCCEN); |
1371d3be VB |
406 | } |
407 | ||
408 | #endif | |
409 | ||
410 | /* MPC885ADS Boards */ | |
411 | ||
412 | #if defined(CONFIG_MPC885ADS) | |
413 | ||
414 | #define PCMCIA_BOARD_MSG "MPC885ADS" | |
80128ff7 | 415 | #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V |
1371d3be | 416 | |
80128ff7 | 417 | static inline void hardware_enable(int slot) |
1371d3be | 418 | { |
99121c0d | 419 | m8xx_pcmcia_ops.hw_ctrl(slot, 1); |
de957c89 MT |
420 | } |
421 | ||
80128ff7 | 422 | static inline void hardware_disable(int slot) |
de957c89 | 423 | { |
80128ff7 | 424 | m8xx_pcmcia_ops.hw_ctrl(slot, 0); |
de957c89 MT |
425 | } |
426 | ||
80128ff7 | 427 | static inline int voltage_set(int slot, int vcc, int vpp) |
de957c89 | 428 | { |
80128ff7 | 429 | return m8xx_pcmcia_ops.voltage_set(slot, vcc, vpp); |
de957c89 MT |
430 | } |
431 | ||
432 | #endif | |
433 | ||
434 | /* ------------------------------------------------------------------------- */ | |
435 | /* Motorola MBX860 */ | |
436 | ||
437 | #if defined(CONFIG_MBX) | |
438 | ||
439 | #define PCMCIA_BOARD_MSG "MBX" | |
440 | ||
441 | static int voltage_set(int slot, int vcc, int vpp) | |
442 | { | |
443 | u8 reg = 0; | |
444 | ||
99121c0d VB |
445 | switch (vcc) { |
446 | case 0: | |
447 | break; | |
448 | case 33: | |
449 | reg |= CSR2_VCC_33; | |
450 | break; | |
451 | case 50: | |
452 | reg |= CSR2_VCC_50; | |
453 | break; | |
454 | default: | |
455 | return 1; | |
de957c89 MT |
456 | } |
457 | ||
99121c0d VB |
458 | switch (vpp) { |
459 | case 0: | |
460 | break; | |
461 | case 33: | |
462 | case 50: | |
463 | if (vcc == vpp) | |
464 | reg |= CSR2_VPP_VCC; | |
465 | else | |
466 | return 1; | |
467 | break; | |
468 | case 120: | |
469 | if ((vcc == 33) || (vcc == 50)) | |
470 | reg |= CSR2_VPP_12; | |
471 | else | |
de957c89 | 472 | return 1; |
99121c0d VB |
473 | default: |
474 | return 1; | |
de957c89 MT |
475 | } |
476 | ||
477 | /* first, turn off all power */ | |
99121c0d VB |
478 | out_8((u8 *) MBX_CSR2_ADDR, |
479 | in_8((u8 *) MBX_CSR2_ADDR) & ~(CSR2_VCC_MASK | CSR2_VPP_MASK)); | |
de957c89 MT |
480 | |
481 | /* enable new powersettings */ | |
99121c0d | 482 | out_8((u8 *) MBX_CSR2_ADDR, in_8((u8 *) MBX_CSR2_ADDR) | reg); |
de957c89 MT |
483 | |
484 | return 0; | |
485 | } | |
486 | ||
487 | #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V | |
99121c0d VB |
488 | #define hardware_enable(_slot_) /* No hardware to enable */ |
489 | #define hardware_disable(_slot_) /* No hardware to disable */ | |
de957c89 | 490 | |
99121c0d | 491 | #endif /* CONFIG_MBX */ |
de957c89 MT |
492 | |
493 | #if defined(CONFIG_PRxK) | |
494 | #include <asm/cpld.h> | |
495 | extern volatile fpga_pc_regs *fpga_pc; | |
496 | ||
497 | #define PCMCIA_BOARD_MSG "MPC855T" | |
498 | ||
499 | static int voltage_set(int slot, int vcc, int vpp) | |
500 | { | |
501 | u8 reg = 0; | |
502 | u8 regread; | |
503 | cpld_regs *ccpld = get_cpld(); | |
504 | ||
99121c0d VB |
505 | switch (vcc) { |
506 | case 0: | |
507 | break; | |
508 | case 33: | |
509 | reg |= PCMCIA_VCC_33; | |
510 | break; | |
511 | case 50: | |
512 | reg |= PCMCIA_VCC_50; | |
513 | break; | |
514 | default: | |
515 | return 1; | |
de957c89 MT |
516 | } |
517 | ||
99121c0d VB |
518 | switch (vpp) { |
519 | case 0: | |
520 | break; | |
521 | case 33: | |
522 | case 50: | |
523 | if (vcc == vpp) | |
524 | reg |= PCMCIA_VPP_VCC; | |
525 | else | |
de957c89 | 526 | return 1; |
99121c0d VB |
527 | break; |
528 | case 120: | |
529 | if ((vcc == 33) || (vcc == 50)) | |
530 | reg |= PCMCIA_VPP_12; | |
531 | else | |
532 | return 1; | |
533 | default: | |
534 | return 1; | |
de957c89 MT |
535 | } |
536 | ||
537 | reg = reg >> (slot << 2); | |
538 | regread = in_8(&ccpld->fpga_pc_ctl); | |
99121c0d VB |
539 | if (reg != |
540 | (regread & ((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >> (slot << 2)))) { | |
de957c89 | 541 | /* enable new powersettings */ |
99121c0d VB |
542 | regread = |
543 | regread & ~((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >> | |
544 | (slot << 2)); | |
de957c89 MT |
545 | out_8(&ccpld->fpga_pc_ctl, reg | regread); |
546 | msleep(100); | |
547 | } | |
548 | ||
549 | return 0; | |
550 | } | |
551 | ||
552 | #define socket_get(_slot_) PCMCIA_SOCKET_KEY_LV | |
99121c0d VB |
553 | #define hardware_enable(_slot_) /* No hardware to enable */ |
554 | #define hardware_disable(_slot_) /* No hardware to disable */ | |
de957c89 | 555 | |
99121c0d | 556 | #endif /* CONFIG_PRxK */ |
de957c89 | 557 | |
de957c89 | 558 | static u32 pending_events[PCMCIA_SOCKETS_NO]; |
34af946a | 559 | static DEFINE_SPINLOCK(pending_event_lock); |
de957c89 | 560 | |
7d12e780 | 561 | static irqreturn_t m8xx_interrupt(int irq, void *dev) |
de957c89 MT |
562 | { |
563 | struct socket_info *s; | |
564 | struct event_table *e; | |
565 | unsigned int i, events, pscr, pipr, per; | |
99121c0d | 566 | pcmconf8xx_t *pcmcia = socket[0].pcmcia; |
de957c89 MT |
567 | |
568 | dprintk("Interrupt!\n"); | |
569 | /* get interrupt sources */ | |
570 | ||
80128ff7 VB |
571 | pscr = in_be32(&pcmcia->pcmc_pscr); |
572 | pipr = in_be32(&pcmcia->pcmc_pipr); | |
573 | per = in_be32(&pcmcia->pcmc_per); | |
de957c89 | 574 | |
99121c0d | 575 | for (i = 0; i < PCMCIA_SOCKETS_NO; i++) { |
de957c89 MT |
576 | s = &socket[i]; |
577 | e = &s->events[0]; | |
578 | events = 0; | |
579 | ||
99121c0d VB |
580 | while (e->regbit) { |
581 | if (pscr & e->regbit) | |
de957c89 MT |
582 | events |= e->eventbit; |
583 | ||
99121c0d | 584 | e++; |
de957c89 MT |
585 | } |
586 | ||
587 | /* | |
588 | * report only if both card detect signals are the same | |
589 | * not too nice done, | |
590 | * we depend on that CD2 is the bit to the left of CD1... | |
591 | */ | |
99121c0d VB |
592 | if (events & SS_DETECT) |
593 | if (((pipr & M8XX_PCMCIA_CD2(i)) >> 1) ^ | |
594 | (pipr & M8XX_PCMCIA_CD1(i))) { | |
de957c89 MT |
595 | events &= ~SS_DETECT; |
596 | } | |
de957c89 MT |
597 | #ifdef PCMCIA_GLITCHY_CD |
598 | /* | |
599 | * I've experienced CD problems with my ADS board. | |
600 | * We make an extra check to see if there was a | |
601 | * real change of Card detection. | |
602 | */ | |
603 | ||
99121c0d VB |
604 | if ((events & SS_DETECT) && |
605 | ((pipr & | |
606 | (M8XX_PCMCIA_CD2(i) | M8XX_PCMCIA_CD1(i))) == 0) && | |
607 | (s->state.Vcc | s->state.Vpp)) { | |
de957c89 MT |
608 | events &= ~SS_DETECT; |
609 | /*printk( "CD glitch workaround - CD = 0x%08x!\n", | |
99121c0d VB |
610 | (pipr & (M8XX_PCMCIA_CD2(i) |
611 | | M8XX_PCMCIA_CD1(i)))); */ | |
de957c89 MT |
612 | } |
613 | #endif | |
614 | ||
615 | /* call the handler */ | |
616 | ||
617 | dprintk("slot %u: events = 0x%02x, pscr = 0x%08x, " | |
99121c0d | 618 | "pipr = 0x%08x\n", i, events, pscr, pipr); |
de957c89 | 619 | |
99121c0d | 620 | if (events) { |
de957c89 MT |
621 | spin_lock(&pending_event_lock); |
622 | pending_events[i] |= events; | |
623 | spin_unlock(&pending_event_lock); | |
624 | /* | |
625 | * Turn off RDY_L bits in the PER mask on | |
626 | * CD interrupt receival. | |
627 | * | |
628 | * They can generate bad interrupts on the | |
629 | * ACS4,8,16,32. - marcelo | |
630 | */ | |
631 | per &= ~M8XX_PCMCIA_RDY_L(0); | |
632 | per &= ~M8XX_PCMCIA_RDY_L(1); | |
633 | ||
80128ff7 | 634 | out_be32(&pcmcia->pcmc_per, per); |
de957c89 MT |
635 | |
636 | if (events) | |
637 | pcmcia_parse_events(&socket[i].socket, events); | |
638 | } | |
639 | } | |
640 | ||
641 | /* clear the interrupt sources */ | |
80128ff7 | 642 | out_be32(&pcmcia->pcmc_pscr, pscr); |
de957c89 MT |
643 | |
644 | dprintk("Interrupt done.\n"); | |
645 | ||
646 | return IRQ_HANDLED; | |
647 | } | |
648 | ||
649 | static u32 m8xx_get_graycode(u32 size) | |
650 | { | |
651 | u32 k; | |
652 | ||
99121c0d VB |
653 | for (k = 0; k < M8XX_SIZES_NO; k++) |
654 | if (m8xx_size_to_gray[k] == size) | |
de957c89 MT |
655 | break; |
656 | ||
99121c0d | 657 | if ((k == M8XX_SIZES_NO) || (m8xx_size_to_gray[k] == -1)) |
de957c89 MT |
658 | k = -1; |
659 | ||
660 | return k; | |
661 | } | |
662 | ||
80128ff7 | 663 | static u32 m8xx_get_speed(u32 ns, u32 is_io, u32 bus_freq) |
de957c89 MT |
664 | { |
665 | u32 reg, clocks, psst, psl, psht; | |
666 | ||
99121c0d | 667 | if (!ns) { |
de957c89 MT |
668 | |
669 | /* | |
670 | * We get called with IO maps setup to 0ns | |
671 | * if not specified by the user. | |
672 | * They should be 255ns. | |
673 | */ | |
674 | ||
99121c0d | 675 | if (is_io) |
de957c89 MT |
676 | ns = 255; |
677 | else | |
99121c0d | 678 | ns = 100; /* fast memory if 0 */ |
de957c89 MT |
679 | } |
680 | ||
681 | /* | |
682 | * In PSST, PSL, PSHT fields we tell the controller | |
683 | * timing parameters in CLKOUT clock cycles. | |
684 | * CLKOUT is the same as GCLK2_50. | |
685 | */ | |
686 | ||
687 | /* how we want to adjust the timing - in percent */ | |
688 | ||
99121c0d | 689 | #define ADJ 180 /* 80 % longer accesstime - to be sure */ |
de957c89 | 690 | |
80128ff7 | 691 | clocks = ((bus_freq / 1000) * ns) / 1000; |
99121c0d VB |
692 | clocks = (clocks * ADJ) / (100 * 1000); |
693 | if (clocks >= PCMCIA_BMT_LIMIT) { | |
694 | printk("Max access time limit reached\n"); | |
695 | clocks = PCMCIA_BMT_LIMIT - 1; | |
de957c89 MT |
696 | } |
697 | ||
99121c0d VB |
698 | psst = clocks / 7; /* setup time */ |
699 | psht = clocks / 7; /* hold time */ | |
700 | psl = (clocks * 5) / 7; /* strobe length */ | |
de957c89 MT |
701 | |
702 | psst += clocks - (psst + psht + psl); | |
703 | ||
99121c0d VB |
704 | reg = psst << 12; |
705 | reg |= psl << 7; | |
de957c89 MT |
706 | reg |= psht << 16; |
707 | ||
708 | return reg; | |
709 | } | |
710 | ||
711 | static int m8xx_get_status(struct pcmcia_socket *sock, unsigned int *value) | |
712 | { | |
713 | int lsock = container_of(sock, struct socket_info, socket)->slot; | |
714 | struct socket_info *s = &socket[lsock]; | |
715 | unsigned int pipr, reg; | |
80128ff7 | 716 | pcmconf8xx_t *pcmcia = s->pcmcia; |
de957c89 | 717 | |
80128ff7 | 718 | pipr = in_be32(&pcmcia->pcmc_pipr); |
de957c89 | 719 | |
99121c0d VB |
720 | *value = ((pipr & (M8XX_PCMCIA_CD1(lsock) |
721 | | M8XX_PCMCIA_CD2(lsock))) == 0) ? SS_DETECT : 0; | |
de957c89 MT |
722 | *value |= (pipr & M8XX_PCMCIA_WP(lsock)) ? SS_WRPROT : 0; |
723 | ||
724 | if (s->state.flags & SS_IOCARD) | |
725 | *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_STSCHG : 0; | |
726 | else { | |
727 | *value |= (pipr & M8XX_PCMCIA_RDY(lsock)) ? SS_READY : 0; | |
728 | *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_BATDEAD : 0; | |
729 | *value |= (pipr & M8XX_PCMCIA_BVD2(lsock)) ? SS_BATWARN : 0; | |
730 | } | |
731 | ||
732 | if (s->state.Vcc | s->state.Vpp) | |
733 | *value |= SS_POWERON; | |
734 | ||
735 | /* | |
736 | * Voltage detection: | |
737 | * This driver only supports 16-Bit pc-cards. | |
738 | * Cardbus is not handled here. | |
739 | * | |
740 | * To determine what voltage to use we must read the VS1 and VS2 pin. | |
741 | * Depending on what socket type is present, | |
742 | * different combinations mean different things. | |
743 | * | |
744 | * Card Key Socket Key VS1 VS2 Card Vcc for CIS parse | |
745 | * | |
746 | * 5V 5V, LV* NC NC 5V only 5V (if available) | |
747 | * | |
748 | * 5V 5V, LV* GND NC 5 or 3.3V as low as possible | |
749 | * | |
750 | * 5V 5V, LV* GND GND 5, 3.3, x.xV as low as possible | |
751 | * | |
752 | * LV* 5V - - shall not fit into socket | |
753 | * | |
754 | * LV* LV* GND NC 3.3V only 3.3V | |
755 | * | |
756 | * LV* LV* NC GND x.xV x.xV (if avail.) | |
757 | * | |
758 | * LV* LV* GND GND 3.3 or x.xV as low as possible | |
759 | * | |
760 | * *LV means Low Voltage | |
761 | * | |
762 | * | |
763 | * That gives us the following table: | |
764 | * | |
765 | * Socket VS1 VS2 Voltage | |
766 | * | |
767 | * 5V NC NC 5V | |
768 | * 5V NC GND none (should not be possible) | |
769 | * 5V GND NC >= 3.3V | |
770 | * 5V GND GND >= x.xV | |
771 | * | |
772 | * LV NC NC 5V (if available) | |
773 | * LV NC GND x.xV (if available) | |
774 | * LV GND NC 3.3V | |
775 | * LV GND GND >= x.xV | |
776 | * | |
777 | * So, how do I determine if I have a 5V or a LV | |
778 | * socket on my board? Look at the socket! | |
779 | * | |
780 | * | |
781 | * Socket with 5V key: | |
782 | * ++--------------------------------------------+ | |
783 | * || | | |
784 | * || || | |
785 | * || || | |
786 | * | | | |
787 | * +---------------------------------------------+ | |
788 | * | |
789 | * Socket with LV key: | |
790 | * ++--------------------------------------------+ | |
791 | * || | | |
792 | * | || | |
793 | * | || | |
794 | * | | | |
795 | * +---------------------------------------------+ | |
796 | * | |
797 | * | |
798 | * With other words - LV only cards does not fit | |
799 | * into the 5V socket! | |
800 | */ | |
801 | ||
802 | /* read out VS1 and VS2 */ | |
803 | ||
804 | reg = (pipr & M8XX_PCMCIA_VS_MASK(lsock)) | |
99121c0d | 805 | >> M8XX_PCMCIA_VS_SHIFT(lsock); |
de957c89 | 806 | |
99121c0d VB |
807 | if (socket_get(lsock) == PCMCIA_SOCKET_KEY_LV) { |
808 | switch (reg) { | |
de957c89 MT |
809 | case 1: |
810 | *value |= SS_3VCARD; | |
99121c0d | 811 | break; /* GND, NC - 3.3V only */ |
de957c89 MT |
812 | case 2: |
813 | *value |= SS_XVCARD; | |
99121c0d | 814 | break; /* NC. GND - x.xV only */ |
de957c89 MT |
815 | }; |
816 | } | |
817 | ||
818 | dprintk("GetStatus(%d) = %#2.2x\n", lsock, *value); | |
819 | return 0; | |
820 | } | |
821 | ||
99121c0d | 822 | static int m8xx_set_socket(struct pcmcia_socket *sock, socket_state_t * state) |
de957c89 MT |
823 | { |
824 | int lsock = container_of(sock, struct socket_info, socket)->slot; | |
825 | struct socket_info *s = &socket[lsock]; | |
826 | struct event_table *e; | |
827 | unsigned int reg; | |
828 | unsigned long flags; | |
80128ff7 | 829 | pcmconf8xx_t *pcmcia = socket[0].pcmcia; |
de957c89 | 830 | |
99121c0d VB |
831 | dprintk("SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, " |
832 | "io_irq %d, csc_mask %#2.2x)\n", lsock, state->flags, | |
833 | state->Vcc, state->Vpp, state->io_irq, state->csc_mask); | |
de957c89 MT |
834 | |
835 | /* First, set voltage - bail out if invalid */ | |
99121c0d | 836 | if (voltage_set(lsock, state->Vcc, state->Vpp)) |
de957c89 MT |
837 | return -EINVAL; |
838 | ||
839 | /* Take care of reset... */ | |
99121c0d VB |
840 | if (state->flags & SS_RESET) |
841 | out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXRESET); /* active high */ | |
de957c89 | 842 | else |
99121c0d VB |
843 | out_be32(M8XX_PGCRX(lsock), |
844 | in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXRESET); | |
de957c89 MT |
845 | |
846 | /* ... and output enable. */ | |
847 | ||
848 | /* The CxOE signal is connected to a 74541 on the ADS. | |
849 | I guess most other boards used the ADS as a reference. | |
850 | I tried to control the CxOE signal with SS_OUTPUT_ENA, | |
851 | but the reset signal seems connected via the 541. | |
852 | If the CxOE is left high are some signals tristated and | |
f26fc4e0 | 853 | no pullups are present -> the cards act weird. |
de957c89 MT |
854 | So right now the buffers are enabled if the power is on. */ |
855 | ||
99121c0d VB |
856 | if (state->Vcc || state->Vpp) |
857 | out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXOE); /* active low */ | |
de957c89 | 858 | else |
99121c0d VB |
859 | out_be32(M8XX_PGCRX(lsock), |
860 | in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXOE); | |
de957c89 MT |
861 | |
862 | /* | |
863 | * We'd better turn off interrupts before | |
864 | * we mess with the events-table.. | |
865 | */ | |
866 | ||
867 | spin_lock_irqsave(&events_lock, flags); | |
868 | ||
869 | /* | |
870 | * Play around with the interrupt mask to be able to | |
871 | * give the events the generic pcmcia driver wants us to. | |
872 | */ | |
873 | ||
874 | e = &s->events[0]; | |
875 | reg = 0; | |
876 | ||
99121c0d | 877 | if (state->csc_mask & SS_DETECT) { |
de957c89 MT |
878 | e->eventbit = SS_DETECT; |
879 | reg |= e->regbit = (M8XX_PCMCIA_CD2(lsock) | |
880 | | M8XX_PCMCIA_CD1(lsock)); | |
881 | e++; | |
882 | } | |
99121c0d | 883 | if (state->flags & SS_IOCARD) { |
de957c89 MT |
884 | /* |
885 | * I/O card | |
886 | */ | |
99121c0d | 887 | if (state->csc_mask & SS_STSCHG) { |
de957c89 MT |
888 | e->eventbit = SS_STSCHG; |
889 | reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock); | |
890 | e++; | |
891 | } | |
892 | /* | |
893 | * If io_irq is non-zero we should enable irq. | |
894 | */ | |
99121c0d | 895 | if (state->io_irq) { |
80128ff7 | 896 | out_be32(M8XX_PGCRX(lsock), |
99121c0d VB |
897 | in_be32(M8XX_PGCRX(lsock)) | |
898 | mk_int_int_mask(s->hwirq) << 24); | |
de957c89 MT |
899 | /* |
900 | * Strange thing here: | |
901 | * The manual does not tell us which interrupt | |
902 | * the sources generate. | |
903 | * Anyhow, I found out that RDY_L generates IREQLVL. | |
904 | * | |
905 | * We use level triggerd interrupts, and they don't | |
906 | * have to be cleared in PSCR in the interrupt handler. | |
907 | */ | |
908 | reg |= M8XX_PCMCIA_RDY_L(lsock); | |
99121c0d VB |
909 | } else |
910 | out_be32(M8XX_PGCRX(lsock), | |
911 | in_be32(M8XX_PGCRX(lsock)) & 0x00ffffff); | |
912 | } else { | |
de957c89 MT |
913 | /* |
914 | * Memory card | |
915 | */ | |
99121c0d | 916 | if (state->csc_mask & SS_BATDEAD) { |
de957c89 MT |
917 | e->eventbit = SS_BATDEAD; |
918 | reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock); | |
919 | e++; | |
920 | } | |
99121c0d | 921 | if (state->csc_mask & SS_BATWARN) { |
de957c89 MT |
922 | e->eventbit = SS_BATWARN; |
923 | reg |= e->regbit = M8XX_PCMCIA_BVD2(lsock); | |
924 | e++; | |
925 | } | |
926 | /* What should I trigger on - low/high,raise,fall? */ | |
99121c0d | 927 | if (state->csc_mask & SS_READY) { |
de957c89 | 928 | e->eventbit = SS_READY; |
99121c0d | 929 | reg |= e->regbit = 0; //?? |
de957c89 MT |
930 | e++; |
931 | } | |
932 | } | |
933 | ||
99121c0d | 934 | e->regbit = 0; /* terminate list */ |
de957c89 MT |
935 | |
936 | /* | |
937 | * Clear the status changed . | |
938 | * Port A and Port B share the same port. | |
939 | * Writing ones will clear the bits. | |
940 | */ | |
941 | ||
80128ff7 | 942 | out_be32(&pcmcia->pcmc_pscr, reg); |
de957c89 MT |
943 | |
944 | /* | |
945 | * Write the mask. | |
946 | * Port A and Port B share the same port. | |
947 | * Need for read-modify-write. | |
948 | * Ones will enable the interrupt. | |
949 | */ | |
950 | ||
99121c0d VB |
951 | reg |= |
952 | in_be32(&pcmcia-> | |
953 | pcmc_per) & (M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1)); | |
80128ff7 | 954 | out_be32(&pcmcia->pcmc_per, reg); |
de957c89 MT |
955 | |
956 | spin_unlock_irqrestore(&events_lock, flags); | |
957 | ||
958 | /* copy the struct and modify the copy */ | |
959 | ||
960 | s->state = *state; | |
961 | ||
962 | return 0; | |
963 | } | |
964 | ||
965 | static int m8xx_set_io_map(struct pcmcia_socket *sock, struct pccard_io_map *io) | |
966 | { | |
967 | int lsock = container_of(sock, struct socket_info, socket)->slot; | |
968 | ||
969 | struct socket_info *s = &socket[lsock]; | |
970 | struct pcmcia_win *w; | |
971 | unsigned int reg, winnr; | |
80128ff7 VB |
972 | pcmconf8xx_t *pcmcia = s->pcmcia; |
973 | ||
de957c89 MT |
974 | #define M8XX_SIZE (io->stop - io->start + 1) |
975 | #define M8XX_BASE (PCMCIA_IO_WIN_BASE + io->start) | |
976 | ||
99121c0d VB |
977 | dprintk("SetIOMap(%d, %d, %#2.2x, %d ns, " |
978 | "%#4.4x-%#4.4x)\n", lsock, io->map, io->flags, | |
979 | io->speed, io->start, io->stop); | |
de957c89 MT |
980 | |
981 | if ((io->map >= PCMCIA_IO_WIN_NO) || (io->start > 0xffff) | |
982 | || (io->stop > 0xffff) || (io->stop < io->start)) | |
983 | return -EINVAL; | |
984 | ||
99121c0d | 985 | if ((reg = m8xx_get_graycode(M8XX_SIZE)) == -1) |
de957c89 MT |
986 | return -EINVAL; |
987 | ||
99121c0d | 988 | if (io->flags & MAP_ACTIVE) { |
de957c89 | 989 | |
99121c0d | 990 | dprintk("io->flags & MAP_ACTIVE\n"); |
de957c89 MT |
991 | |
992 | winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO) | |
99121c0d | 993 | + (lsock * PCMCIA_IO_WIN_NO) + io->map; |
de957c89 MT |
994 | |
995 | /* setup registers */ | |
996 | ||
99121c0d | 997 | w = (void *)&pcmcia->pcmc_pbr0; |
de957c89 MT |
998 | w += winnr; |
999 | ||
99121c0d | 1000 | out_be32(&w->or, 0); /* turn off window first */ |
de957c89 MT |
1001 | out_be32(&w->br, M8XX_BASE); |
1002 | ||
1003 | reg <<= 27; | |
99121c0d | 1004 | reg |= M8XX_PCMCIA_POR_IO | (lsock << 2); |
de957c89 | 1005 | |
80128ff7 | 1006 | reg |= m8xx_get_speed(io->speed, 1, s->bus_freq); |
de957c89 | 1007 | |
99121c0d | 1008 | if (io->flags & MAP_WRPROT) |
de957c89 MT |
1009 | reg |= M8XX_PCMCIA_POR_WRPROT; |
1010 | ||
99121c0d VB |
1011 | /*if(io->flags & (MAP_16BIT | MAP_AUTOSZ)) */ |
1012 | if (io->flags & MAP_16BIT) | |
de957c89 MT |
1013 | reg |= M8XX_PCMCIA_POR_16BIT; |
1014 | ||
99121c0d | 1015 | if (io->flags & MAP_ACTIVE) |
de957c89 MT |
1016 | reg |= M8XX_PCMCIA_POR_VALID; |
1017 | ||
1018 | out_be32(&w->or, reg); | |
1019 | ||
1020 | dprintk("Socket %u: Mapped io window %u at %#8.8x, " | |
99121c0d | 1021 | "OR = %#8.8x.\n", lsock, io->map, w->br, w->or); |
de957c89 MT |
1022 | } else { |
1023 | /* shutdown IO window */ | |
1024 | winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO) | |
99121c0d | 1025 | + (lsock * PCMCIA_IO_WIN_NO) + io->map; |
de957c89 MT |
1026 | |
1027 | /* setup registers */ | |
1028 | ||
99121c0d | 1029 | w = (void *)&pcmcia->pcmc_pbr0; |
de957c89 MT |
1030 | w += winnr; |
1031 | ||
99121c0d VB |
1032 | out_be32(&w->or, 0); /* turn off window */ |
1033 | out_be32(&w->br, 0); /* turn off base address */ | |
de957c89 MT |
1034 | |
1035 | dprintk("Socket %u: Unmapped io window %u at %#8.8x, " | |
1036 | "OR = %#8.8x.\n", lsock, io->map, w->br, w->or); | |
1037 | } | |
1038 | ||
1039 | /* copy the struct and modify the copy */ | |
1040 | s->io_win[io->map] = *io; | |
99121c0d | 1041 | s->io_win[io->map].flags &= (MAP_WRPROT | MAP_16BIT | MAP_ACTIVE); |
de957c89 MT |
1042 | dprintk("SetIOMap exit\n"); |
1043 | ||
1044 | return 0; | |
1045 | } | |
1046 | ||
99121c0d VB |
1047 | static int m8xx_set_mem_map(struct pcmcia_socket *sock, |
1048 | struct pccard_mem_map *mem) | |
de957c89 MT |
1049 | { |
1050 | int lsock = container_of(sock, struct socket_info, socket)->slot; | |
1051 | struct socket_info *s = &socket[lsock]; | |
1052 | struct pcmcia_win *w; | |
1053 | struct pccard_mem_map *old; | |
1054 | unsigned int reg, winnr; | |
80128ff7 | 1055 | pcmconf8xx_t *pcmcia = s->pcmcia; |
de957c89 | 1056 | |
99121c0d VB |
1057 | dprintk("SetMemMap(%d, %d, %#2.2x, %d ns, " |
1058 | "%#5.5lx, %#5.5x)\n", lsock, mem->map, mem->flags, | |
1059 | mem->speed, mem->static_start, mem->card_start); | |
de957c89 MT |
1060 | |
1061 | if ((mem->map >= PCMCIA_MEM_WIN_NO) | |
99121c0d | 1062 | // || ((mem->s) >= PCMCIA_MEM_WIN_SIZE) |
de957c89 | 1063 | || (mem->card_start >= 0x04000000) |
99121c0d VB |
1064 | || (mem->static_start & 0xfff) /* 4KByte resolution */ |
1065 | ||(mem->card_start & 0xfff)) | |
de957c89 MT |
1066 | return -EINVAL; |
1067 | ||
99121c0d VB |
1068 | if ((reg = m8xx_get_graycode(PCMCIA_MEM_WIN_SIZE)) == -1) { |
1069 | printk("Cannot set size to 0x%08x.\n", PCMCIA_MEM_WIN_SIZE); | |
de957c89 MT |
1070 | return -EINVAL; |
1071 | } | |
1072 | reg <<= 27; | |
1073 | ||
1074 | winnr = (lsock * PCMCIA_MEM_WIN_NO) + mem->map; | |
1075 | ||
1076 | /* Setup the window in the pcmcia controller */ | |
1077 | ||
99121c0d | 1078 | w = (void *)&pcmcia->pcmc_pbr0; |
de957c89 MT |
1079 | w += winnr; |
1080 | ||
1081 | reg |= lsock << 2; | |
1082 | ||
80128ff7 | 1083 | reg |= m8xx_get_speed(mem->speed, 0, s->bus_freq); |
de957c89 | 1084 | |
99121c0d VB |
1085 | if (mem->flags & MAP_ATTRIB) |
1086 | reg |= M8XX_PCMCIA_POR_ATTRMEM; | |
de957c89 | 1087 | |
99121c0d | 1088 | if (mem->flags & MAP_WRPROT) |
de957c89 MT |
1089 | reg |= M8XX_PCMCIA_POR_WRPROT; |
1090 | ||
99121c0d | 1091 | if (mem->flags & MAP_16BIT) |
de957c89 MT |
1092 | reg |= M8XX_PCMCIA_POR_16BIT; |
1093 | ||
99121c0d | 1094 | if (mem->flags & MAP_ACTIVE) |
de957c89 MT |
1095 | reg |= M8XX_PCMCIA_POR_VALID; |
1096 | ||
1097 | out_be32(&w->or, reg); | |
1098 | ||
1099 | dprintk("Socket %u: Mapped memory window %u at %#8.8x, " | |
99121c0d | 1100 | "OR = %#8.8x.\n", lsock, mem->map, w->br, w->or); |
de957c89 | 1101 | |
99121c0d | 1102 | if (mem->flags & MAP_ACTIVE) { |
de957c89 MT |
1103 | /* get the new base address */ |
1104 | mem->static_start = PCMCIA_MEM_WIN_BASE + | |
99121c0d VB |
1105 | (PCMCIA_MEM_WIN_SIZE * winnr) |
1106 | + mem->card_start; | |
de957c89 MT |
1107 | } |
1108 | ||
1109 | dprintk("SetMemMap(%d, %d, %#2.2x, %d ns, " | |
99121c0d VB |
1110 | "%#5.5lx, %#5.5x)\n", lsock, mem->map, mem->flags, |
1111 | mem->speed, mem->static_start, mem->card_start); | |
de957c89 MT |
1112 | |
1113 | /* copy the struct and modify the copy */ | |
1114 | ||
1115 | old = &s->mem_win[mem->map]; | |
1116 | ||
1117 | *old = *mem; | |
99121c0d | 1118 | old->flags &= (MAP_ATTRIB | MAP_WRPROT | MAP_16BIT | MAP_ACTIVE); |
de957c89 MT |
1119 | |
1120 | return 0; | |
1121 | } | |
1122 | ||
1123 | static int m8xx_sock_init(struct pcmcia_socket *sock) | |
1124 | { | |
1125 | int i; | |
1126 | pccard_io_map io = { 0, 0, 0, 0, 1 }; | |
1127 | pccard_mem_map mem = { 0, 0, 0, 0, 0, 0 }; | |
1128 | ||
99121c0d | 1129 | dprintk("sock_init(%d)\n", s); |
de957c89 MT |
1130 | |
1131 | m8xx_set_socket(sock, &dead_socket); | |
1132 | for (i = 0; i < PCMCIA_IO_WIN_NO; i++) { | |
1133 | io.map = i; | |
1134 | m8xx_set_io_map(sock, &io); | |
1135 | } | |
1136 | for (i = 0; i < PCMCIA_MEM_WIN_NO; i++) { | |
1137 | mem.map = i; | |
1138 | m8xx_set_mem_map(sock, &mem); | |
1139 | } | |
1140 | ||
1141 | return 0; | |
1142 | ||
1143 | } | |
1144 | ||
80128ff7 | 1145 | static int m8xx_sock_suspend(struct pcmcia_socket *sock) |
de957c89 MT |
1146 | { |
1147 | return m8xx_set_socket(sock, &dead_socket); | |
1148 | } | |
1149 | ||
1150 | static struct pccard_operations m8xx_services = { | |
99121c0d | 1151 | .init = m8xx_sock_init, |
80128ff7 | 1152 | .suspend = m8xx_sock_suspend, |
de957c89 | 1153 | .get_status = m8xx_get_status, |
de957c89 MT |
1154 | .set_socket = m8xx_set_socket, |
1155 | .set_io_map = m8xx_set_io_map, | |
1156 | .set_mem_map = m8xx_set_mem_map, | |
1157 | }; | |
1158 | ||
99121c0d VB |
1159 | static int __init m8xx_probe(struct of_device *ofdev, |
1160 | const struct of_device_id *match) | |
de957c89 MT |
1161 | { |
1162 | struct pcmcia_win *w; | |
80128ff7 VB |
1163 | unsigned int i, m, hwirq; |
1164 | pcmconf8xx_t *pcmcia; | |
1165 | int status; | |
1166 | struct device_node *np = ofdev->node; | |
de957c89 MT |
1167 | |
1168 | pcmcia_info("%s\n", version); | |
1169 | ||
80128ff7 | 1170 | pcmcia = of_iomap(np, 0); |
99121c0d | 1171 | if (pcmcia == NULL) |
80128ff7 VB |
1172 | return -EINVAL; |
1173 | ||
1174 | pcmcia_schlvl = irq_of_parse_and_map(np, 0); | |
99121c0d | 1175 | hwirq = irq_map[pcmcia_schlvl].hwirq; |
5a1c3e1a JL |
1176 | if (pcmcia_schlvl < 0) { |
1177 | iounmap(pcmcia); | |
80128ff7 | 1178 | return -EINVAL; |
5a1c3e1a | 1179 | } |
80128ff7 VB |
1180 | |
1181 | m8xx_pgcrx[0] = &pcmcia->pcmc_pgcra; | |
1182 | m8xx_pgcrx[1] = &pcmcia->pcmc_pgcrb; | |
1183 | ||
de957c89 | 1184 | pcmcia_info(PCMCIA_BOARD_MSG " using " PCMCIA_SLOT_MSG |
80128ff7 | 1185 | " with IRQ %u (%d). \n", pcmcia_schlvl, hwirq); |
de957c89 MT |
1186 | |
1187 | /* Configure Status change interrupt */ | |
1188 | ||
99121c0d VB |
1189 | if (request_irq(pcmcia_schlvl, m8xx_interrupt, IRQF_SHARED, |
1190 | driver_name, socket)) { | |
de957c89 MT |
1191 | pcmcia_error("Cannot allocate IRQ %u for SCHLVL!\n", |
1192 | pcmcia_schlvl); | |
5a1c3e1a | 1193 | iounmap(pcmcia); |
de957c89 MT |
1194 | return -1; |
1195 | } | |
1196 | ||
99121c0d | 1197 | w = (void *)&pcmcia->pcmc_pbr0; |
de957c89 | 1198 | |
99121c0d | 1199 | out_be32(&pcmcia->pcmc_pscr, M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1)); |
80128ff7 | 1200 | clrbits32(&pcmcia->pcmc_per, M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1)); |
de957c89 | 1201 | |
80128ff7 | 1202 | /* connect interrupt and disable CxOE */ |
de957c89 | 1203 | |
99121c0d VB |
1204 | out_be32(M8XX_PGCRX(0), |
1205 | M8XX_PGCRX_CXOE | (mk_int_int_mask(hwirq) << 16)); | |
1206 | out_be32(M8XX_PGCRX(1), | |
1207 | M8XX_PGCRX_CXOE | (mk_int_int_mask(hwirq) << 16)); | |
de957c89 | 1208 | |
80128ff7 | 1209 | /* intialize the fixed memory windows */ |
de957c89 | 1210 | |
99121c0d | 1211 | for (i = 0; i < PCMCIA_SOCKETS_NO; i++) { |
80128ff7 | 1212 | for (m = 0; m < PCMCIA_MEM_WIN_NO; m++) { |
de957c89 | 1213 | out_be32(&w->br, PCMCIA_MEM_WIN_BASE + |
99121c0d VB |
1214 | (PCMCIA_MEM_WIN_SIZE |
1215 | * (m + i * PCMCIA_MEM_WIN_NO))); | |
de957c89 | 1216 | |
99121c0d | 1217 | out_be32(&w->or, 0); /* set to not valid */ |
de957c89 MT |
1218 | |
1219 | w++; | |
1220 | } | |
1221 | } | |
1222 | ||
80128ff7 | 1223 | /* turn off voltage */ |
de957c89 MT |
1224 | voltage_set(0, 0, 0); |
1225 | voltage_set(1, 0, 0); | |
1226 | ||
80128ff7 | 1227 | /* Enable external hardware */ |
de957c89 MT |
1228 | hardware_enable(0); |
1229 | hardware_enable(1); | |
1230 | ||
99121c0d | 1231 | for (i = 0; i < PCMCIA_SOCKETS_NO; i++) { |
de957c89 MT |
1232 | socket[i].slot = i; |
1233 | socket[i].socket.owner = THIS_MODULE; | |
99121c0d VB |
1234 | socket[i].socket.features = |
1235 | SS_CAP_PCCARD | SS_CAP_MEM_ALIGN | SS_CAP_STATIC_MAP; | |
de957c89 MT |
1236 | socket[i].socket.irq_mask = 0x000; |
1237 | socket[i].socket.map_size = 0x1000; | |
1238 | socket[i].socket.io_offset = 0; | |
80128ff7 | 1239 | socket[i].socket.pci_irq = pcmcia_schlvl; |
de957c89 | 1240 | socket[i].socket.ops = &m8xx_services; |
80128ff7 | 1241 | socket[i].socket.resource_ops = &pccard_nonstatic_ops; |
de957c89 | 1242 | socket[i].socket.cb_dev = NULL; |
80128ff7 VB |
1243 | socket[i].socket.dev.parent = &ofdev->dev; |
1244 | socket[i].pcmcia = pcmcia; | |
1245 | socket[i].bus_freq = ppc_proc_freq; | |
1246 | socket[i].hwirq = hwirq; | |
1247 | ||
de957c89 MT |
1248 | } |
1249 | ||
80128ff7 VB |
1250 | for (i = 0; i < PCMCIA_SOCKETS_NO; i++) { |
1251 | status = pcmcia_register_socket(&socket[i].socket); | |
1252 | if (status < 0) | |
1253 | pcmcia_error("Socket register failed\n"); | |
1254 | } | |
de957c89 MT |
1255 | |
1256 | return 0; | |
1257 | } | |
1258 | ||
99121c0d | 1259 | static int m8xx_remove(struct of_device *ofdev) |
de957c89 | 1260 | { |
80128ff7 VB |
1261 | u32 m, i; |
1262 | struct pcmcia_win *w; | |
1263 | pcmconf8xx_t *pcmcia = socket[0].pcmcia; | |
1264 | ||
1265 | for (i = 0; i < PCMCIA_SOCKETS_NO; i++) { | |
99121c0d | 1266 | w = (void *)&pcmcia->pcmc_pbr0; |
80128ff7 VB |
1267 | |
1268 | out_be32(&pcmcia->pcmc_pscr, M8XX_PCMCIA_MASK(i)); | |
1269 | out_be32(&pcmcia->pcmc_per, | |
99121c0d | 1270 | in_be32(&pcmcia->pcmc_per) & ~M8XX_PCMCIA_MASK(i)); |
de957c89 | 1271 | |
80128ff7 VB |
1272 | /* turn off interrupt and disable CxOE */ |
1273 | out_be32(M8XX_PGCRX(i), M8XX_PGCRX_CXOE); | |
1274 | ||
1275 | /* turn off memory windows */ | |
1276 | for (m = 0; m < PCMCIA_MEM_WIN_NO; m++) { | |
99121c0d | 1277 | out_be32(&w->or, 0); /* set to not valid */ |
80128ff7 VB |
1278 | w++; |
1279 | } | |
1280 | ||
1281 | /* turn off voltage */ | |
1282 | voltage_set(i, 0, 0); | |
1283 | ||
1284 | /* disable external hardware */ | |
1285 | hardware_disable(i); | |
1286 | } | |
de957c89 MT |
1287 | for (i = 0; i < PCMCIA_SOCKETS_NO; i++) |
1288 | pcmcia_unregister_socket(&socket[i].socket); | |
5a1c3e1a | 1289 | iounmap(pcmcia); |
de957c89 | 1290 | |
80128ff7 | 1291 | free_irq(pcmcia_schlvl, NULL); |
de957c89 | 1292 | |
80128ff7 VB |
1293 | return 0; |
1294 | } | |
1295 | ||
1296 | #ifdef CONFIG_PM | |
1297 | static int m8xx_suspend(struct platform_device *pdev, pm_message_t state) | |
1298 | { | |
827b4649 | 1299 | return pcmcia_socket_dev_suspend(&pdev->dev); |
80128ff7 VB |
1300 | } |
1301 | ||
1302 | static int m8xx_resume(struct platform_device *pdev) | |
1303 | { | |
1304 | return pcmcia_socket_dev_resume(&pdev->dev); | |
1305 | } | |
1306 | #else | |
1307 | #define m8xx_suspend NULL | |
1308 | #define m8xx_resume NULL | |
1309 | #endif | |
1310 | ||
1311 | static struct of_device_id m8xx_pcmcia_match[] = { | |
1312 | { | |
99121c0d VB |
1313 | .type = "pcmcia", |
1314 | .compatible = "fsl,pq-pcmcia", | |
1315 | }, | |
80128ff7 VB |
1316 | {}, |
1317 | }; | |
1318 | ||
1319 | MODULE_DEVICE_TABLE(of, m8xx_pcmcia_match); | |
1320 | ||
1321 | static struct of_platform_driver m8xx_pcmcia_driver = { | |
8bf8df71 | 1322 | .name = driver_name, |
99121c0d VB |
1323 | .match_table = m8xx_pcmcia_match, |
1324 | .probe = m8xx_probe, | |
1325 | .remove = m8xx_remove, | |
1326 | .suspend = m8xx_suspend, | |
1327 | .resume = m8xx_resume, | |
80128ff7 VB |
1328 | }; |
1329 | ||
1330 | static int __init m8xx_init(void) | |
1331 | { | |
1332 | return of_register_platform_driver(&m8xx_pcmcia_driver); | |
1333 | } | |
1334 | ||
1335 | static void __exit m8xx_exit(void) | |
1336 | { | |
1337 | of_unregister_platform_driver(&m8xx_pcmcia_driver); | |
de957c89 MT |
1338 | } |
1339 | ||
1340 | module_init(m8xx_init); | |
1341 | module_exit(m8xx_exit); |