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1da177e4 LT |
1 | /* |
2 | * Driver for Intel I82092AA PCI-PCMCIA bridge. | |
3 | * | |
4 | * (C) 2001 Red Hat, Inc. | |
5 | * | |
6 | * Author: Arjan Van De Ven <arjanv@redhat.com> | |
7 | * Loosly based on i82365.c from the pcmcia-cs package | |
1da177e4 LT |
8 | */ |
9 | ||
10 | #include <linux/kernel.h> | |
1da177e4 LT |
11 | #include <linux/module.h> |
12 | #include <linux/pci.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/workqueue.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/device.h> | |
17 | ||
1da177e4 | 18 | #include <pcmcia/ss.h> |
1da177e4 | 19 | |
1da177e4 LT |
20 | #include <asm/io.h> |
21 | ||
22 | #include "i82092aa.h" | |
23 | #include "i82365.h" | |
24 | ||
25 | MODULE_LICENSE("GPL"); | |
26 | ||
27 | /* PCI core routines */ | |
28 | static struct pci_device_id i82092aa_pci_ids[] = { | |
29 | { | |
30 | .vendor = PCI_VENDOR_ID_INTEL, | |
31 | .device = PCI_DEVICE_ID_INTEL_82092AA_0, | |
32 | .subvendor = PCI_ANY_ID, | |
33 | .subdevice = PCI_ANY_ID, | |
34 | }, | |
35 | {} | |
36 | }; | |
37 | MODULE_DEVICE_TABLE(pci, i82092aa_pci_ids); | |
38 | ||
ba66ddfa | 39 | static struct pci_driver i82092aa_pci_driver = { |
1da177e4 LT |
40 | .name = "i82092aa", |
41 | .id_table = i82092aa_pci_ids, | |
42 | .probe = i82092aa_pci_probe, | |
43 | .remove = __devexit_p(i82092aa_pci_remove), | |
1da177e4 LT |
44 | }; |
45 | ||
46 | ||
47 | /* the pccard structure and its functions */ | |
48 | static struct pccard_operations i82092aa_operations = { | |
49 | .init = i82092aa_init, | |
50 | .get_status = i82092aa_get_status, | |
1da177e4 LT |
51 | .set_socket = i82092aa_set_socket, |
52 | .set_io_map = i82092aa_set_io_map, | |
53 | .set_mem_map = i82092aa_set_mem_map, | |
54 | }; | |
55 | ||
25985edc | 56 | /* The card can do up to 4 sockets, allocate a structure for each of them */ |
1da177e4 LT |
57 | |
58 | struct socket_info { | |
59 | int number; | |
60 | int card_state; /* 0 = no socket, | |
61 | 1 = empty socket, | |
62 | 2 = card but not initialized, | |
63 | 3 = operational card */ | |
906da809 | 64 | unsigned int io_base; /* base io address of the socket */ |
1da177e4 LT |
65 | |
66 | struct pcmcia_socket socket; | |
67 | struct pci_dev *dev; /* The PCI device for the socket */ | |
68 | }; | |
69 | ||
70 | #define MAX_SOCKETS 4 | |
71 | static struct socket_info sockets[MAX_SOCKETS]; | |
72 | static int socket_count; /* shortcut */ | |
73 | ||
74 | ||
75 | static int __devinit i82092aa_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) | |
76 | { | |
77 | unsigned char configbyte; | |
78 | int i, ret; | |
79 | ||
80 | enter("i82092aa_pci_probe"); | |
81 | ||
82 | if ((ret = pci_enable_device(dev))) | |
83 | return ret; | |
84 | ||
85 | pci_read_config_byte(dev, 0x40, &configbyte); /* PCI Configuration Control */ | |
86 | switch(configbyte&6) { | |
87 | case 0: | |
88 | socket_count = 2; | |
89 | break; | |
90 | case 2: | |
91 | socket_count = 1; | |
92 | break; | |
93 | case 4: | |
94 | case 6: | |
95 | socket_count = 4; | |
96 | break; | |
97 | ||
98 | default: | |
99 | printk(KERN_ERR "i82092aa: Oops, you did something we didn't think of.\n"); | |
100 | ret = -EIO; | |
101 | goto err_out_disable; | |
102 | } | |
103 | printk(KERN_INFO "i82092aa: configured as a %d socket device.\n", socket_count); | |
104 | ||
105 | if (!request_region(pci_resource_start(dev, 0), 2, "i82092aa")) { | |
106 | ret = -EBUSY; | |
107 | goto err_out_disable; | |
108 | } | |
109 | ||
110 | for (i = 0;i<socket_count;i++) { | |
111 | sockets[i].card_state = 1; /* 1 = present but empty */ | |
112 | sockets[i].io_base = pci_resource_start(dev, 0); | |
113 | sockets[i].socket.features |= SS_CAP_PCCARD; | |
114 | sockets[i].socket.map_size = 0x1000; | |
115 | sockets[i].socket.irq_mask = 0; | |
116 | sockets[i].socket.pci_irq = dev->irq; | |
7a96e87d | 117 | sockets[i].socket.cb_dev = dev; |
1da177e4 LT |
118 | sockets[i].socket.owner = THIS_MODULE; |
119 | ||
120 | sockets[i].number = i; | |
121 | ||
122 | if (card_present(i)) { | |
123 | sockets[i].card_state = 3; | |
124 | dprintk(KERN_DEBUG "i82092aa: slot %i is occupied\n",i); | |
125 | } else { | |
126 | dprintk(KERN_DEBUG "i82092aa: slot %i is vacant\n",i); | |
127 | } | |
128 | } | |
129 | ||
130 | /* Now, specifiy that all interrupts are to be done as PCI interrupts */ | |
131 | configbyte = 0xFF; /* bitmask, one bit per event, 1 = PCI interrupt, 0 = ISA interrupt */ | |
132 | pci_write_config_byte(dev, 0x50, configbyte); /* PCI Interrupt Routing Register */ | |
133 | ||
134 | /* Register the interrupt handler */ | |
135 | dprintk(KERN_DEBUG "Requesting interrupt %i \n",dev->irq); | |
dace1453 | 136 | if ((ret = request_irq(dev->irq, i82092aa_interrupt, IRQF_SHARED, "i82092aa", i82092aa_interrupt))) { |
1da177e4 LT |
137 | printk(KERN_ERR "i82092aa: Failed to register IRQ %d, aborting\n", dev->irq); |
138 | goto err_out_free_res; | |
139 | } | |
140 | ||
141 | pci_set_drvdata(dev, &sockets[i].socket); | |
142 | ||
143 | for (i = 0; i<socket_count; i++) { | |
87373318 | 144 | sockets[i].socket.dev.parent = &dev->dev; |
1da177e4 LT |
145 | sockets[i].socket.ops = &i82092aa_operations; |
146 | sockets[i].socket.resource_ops = &pccard_nonstatic_ops; | |
147 | ret = pcmcia_register_socket(&sockets[i].socket); | |
148 | if (ret) { | |
149 | goto err_out_free_sockets; | |
150 | } | |
151 | } | |
152 | ||
153 | leave("i82092aa_pci_probe"); | |
154 | return 0; | |
155 | ||
156 | err_out_free_sockets: | |
157 | if (i) { | |
158 | for (i--;i>=0;i--) { | |
159 | pcmcia_unregister_socket(&sockets[i].socket); | |
160 | } | |
161 | } | |
162 | free_irq(dev->irq, i82092aa_interrupt); | |
163 | err_out_free_res: | |
164 | release_region(pci_resource_start(dev, 0), 2); | |
165 | err_out_disable: | |
166 | pci_disable_device(dev); | |
167 | return ret; | |
168 | } | |
169 | ||
170 | static void __devexit i82092aa_pci_remove(struct pci_dev *dev) | |
171 | { | |
172 | struct pcmcia_socket *socket = pci_get_drvdata(dev); | |
173 | ||
174 | enter("i82092aa_pci_remove"); | |
175 | ||
176 | free_irq(dev->irq, i82092aa_interrupt); | |
177 | ||
178 | if (socket) | |
179 | pcmcia_unregister_socket(socket); | |
180 | ||
181 | leave("i82092aa_pci_remove"); | |
182 | } | |
183 | ||
184 | static DEFINE_SPINLOCK(port_lock); | |
185 | ||
186 | /* basic value read/write functions */ | |
187 | ||
188 | static unsigned char indirect_read(int socket, unsigned short reg) | |
189 | { | |
190 | unsigned short int port; | |
191 | unsigned char val; | |
192 | unsigned long flags; | |
193 | spin_lock_irqsave(&port_lock,flags); | |
194 | reg += socket * 0x40; | |
195 | port = sockets[socket].io_base; | |
196 | outb(reg,port); | |
197 | val = inb(port+1); | |
198 | spin_unlock_irqrestore(&port_lock,flags); | |
199 | return val; | |
200 | } | |
201 | ||
202 | #if 0 | |
203 | static unsigned short indirect_read16(int socket, unsigned short reg) | |
204 | { | |
205 | unsigned short int port; | |
206 | unsigned short tmp; | |
207 | unsigned long flags; | |
208 | spin_lock_irqsave(&port_lock,flags); | |
209 | reg = reg + socket * 0x40; | |
210 | port = sockets[socket].io_base; | |
211 | outb(reg,port); | |
212 | tmp = inb(port+1); | |
213 | reg++; | |
214 | outb(reg,port); | |
215 | tmp = tmp | (inb(port+1)<<8); | |
216 | spin_unlock_irqrestore(&port_lock,flags); | |
217 | return tmp; | |
218 | } | |
219 | #endif | |
220 | ||
221 | static void indirect_write(int socket, unsigned short reg, unsigned char value) | |
222 | { | |
223 | unsigned short int port; | |
224 | unsigned long flags; | |
225 | spin_lock_irqsave(&port_lock,flags); | |
226 | reg = reg + socket * 0x40; | |
227 | port = sockets[socket].io_base; | |
228 | outb(reg,port); | |
229 | outb(value,port+1); | |
230 | spin_unlock_irqrestore(&port_lock,flags); | |
231 | } | |
232 | ||
233 | static void indirect_setbit(int socket, unsigned short reg, unsigned char mask) | |
234 | { | |
235 | unsigned short int port; | |
236 | unsigned char val; | |
237 | unsigned long flags; | |
238 | spin_lock_irqsave(&port_lock,flags); | |
239 | reg = reg + socket * 0x40; | |
240 | port = sockets[socket].io_base; | |
241 | outb(reg,port); | |
242 | val = inb(port+1); | |
243 | val |= mask; | |
244 | outb(reg,port); | |
245 | outb(val,port+1); | |
246 | spin_unlock_irqrestore(&port_lock,flags); | |
247 | } | |
248 | ||
249 | ||
250 | static void indirect_resetbit(int socket, unsigned short reg, unsigned char mask) | |
251 | { | |
252 | unsigned short int port; | |
253 | unsigned char val; | |
254 | unsigned long flags; | |
255 | spin_lock_irqsave(&port_lock,flags); | |
256 | reg = reg + socket * 0x40; | |
257 | port = sockets[socket].io_base; | |
258 | outb(reg,port); | |
259 | val = inb(port+1); | |
260 | val &= ~mask; | |
261 | outb(reg,port); | |
262 | outb(val,port+1); | |
263 | spin_unlock_irqrestore(&port_lock,flags); | |
264 | } | |
265 | ||
266 | static void indirect_write16(int socket, unsigned short reg, unsigned short value) | |
267 | { | |
268 | unsigned short int port; | |
269 | unsigned char val; | |
270 | unsigned long flags; | |
271 | spin_lock_irqsave(&port_lock,flags); | |
272 | reg = reg + socket * 0x40; | |
273 | port = sockets[socket].io_base; | |
274 | ||
275 | outb(reg,port); | |
276 | val = value & 255; | |
277 | outb(val,port+1); | |
278 | ||
279 | reg++; | |
280 | ||
281 | outb(reg,port); | |
282 | val = value>>8; | |
283 | outb(val,port+1); | |
284 | spin_unlock_irqrestore(&port_lock,flags); | |
285 | } | |
286 | ||
287 | /* simple helper functions */ | |
288 | /* External clock time, in nanoseconds. 120 ns = 8.33 MHz */ | |
289 | static int cycle_time = 120; | |
290 | ||
291 | static int to_cycles(int ns) | |
292 | { | |
293 | if (cycle_time!=0) | |
294 | return ns/cycle_time; | |
295 | else | |
296 | return 0; | |
297 | } | |
298 | ||
299 | ||
300 | /* Interrupt handler functionality */ | |
301 | ||
7d12e780 | 302 | static irqreturn_t i82092aa_interrupt(int irq, void *dev) |
1da177e4 LT |
303 | { |
304 | int i; | |
305 | int loopcount = 0; | |
306 | int handled = 0; | |
307 | ||
308 | unsigned int events, active=0; | |
309 | ||
310 | /* enter("i82092aa_interrupt");*/ | |
311 | ||
312 | while (1) { | |
313 | loopcount++; | |
314 | if (loopcount>20) { | |
315 | printk(KERN_ERR "i82092aa: infinite eventloop in interrupt \n"); | |
316 | break; | |
317 | } | |
318 | ||
319 | active = 0; | |
320 | ||
321 | for (i=0;i<socket_count;i++) { | |
322 | int csc; | |
323 | if (sockets[i].card_state==0) /* Inactive socket, should not happen */ | |
324 | continue; | |
325 | ||
326 | csc = indirect_read(i,I365_CSC); /* card status change register */ | |
327 | ||
328 | if (csc==0) /* no events on this socket */ | |
329 | continue; | |
330 | handled = 1; | |
331 | events = 0; | |
332 | ||
333 | if (csc & I365_CSC_DETECT) { | |
334 | events |= SS_DETECT; | |
335 | printk("Card detected in socket %i!\n",i); | |
336 | } | |
337 | ||
338 | if (indirect_read(i,I365_INTCTL) & I365_PC_IOCARD) { | |
339 | /* For IO/CARDS, bit 0 means "read the card" */ | |
340 | events |= (csc & I365_CSC_STSCHG) ? SS_STSCHG : 0; | |
341 | } else { | |
342 | /* Check for battery/ready events */ | |
343 | events |= (csc & I365_CSC_BVD1) ? SS_BATDEAD : 0; | |
344 | events |= (csc & I365_CSC_BVD2) ? SS_BATWARN : 0; | |
345 | events |= (csc & I365_CSC_READY) ? SS_READY : 0; | |
346 | } | |
347 | ||
348 | if (events) { | |
349 | pcmcia_parse_events(&sockets[i].socket, events); | |
350 | } | |
351 | active |= events; | |
352 | } | |
353 | ||
354 | if (active==0) /* no more events to handle */ | |
355 | break; | |
356 | ||
357 | } | |
358 | return IRQ_RETVAL(handled); | |
359 | /* leave("i82092aa_interrupt");*/ | |
360 | } | |
361 | ||
362 | ||
363 | ||
364 | /* socket functions */ | |
365 | ||
366 | static int card_present(int socketno) | |
367 | { | |
368 | unsigned int val; | |
369 | enter("card_present"); | |
370 | ||
371 | if ((socketno<0) || (socketno >= MAX_SOCKETS)) | |
372 | return 0; | |
373 | if (sockets[socketno].io_base == 0) | |
374 | return 0; | |
375 | ||
376 | ||
377 | val = indirect_read(socketno, 1); /* Interface status register */ | |
378 | if ((val&12)==12) { | |
379 | leave("card_present 1"); | |
380 | return 1; | |
381 | } | |
382 | ||
383 | leave("card_present 0"); | |
384 | return 0; | |
385 | } | |
386 | ||
387 | static void set_bridge_state(int sock) | |
388 | { | |
389 | enter("set_bridge_state"); | |
390 | indirect_write(sock, I365_GBLCTL,0x00); | |
391 | indirect_write(sock, I365_GENCTL,0x00); | |
392 | ||
393 | indirect_setbit(sock, I365_INTCTL,0x08); | |
394 | leave("set_bridge_state"); | |
395 | } | |
396 | ||
397 | ||
398 | ||
399 | ||
400 | ||
401 | ||
402 | static int i82092aa_init(struct pcmcia_socket *sock) | |
403 | { | |
404 | int i; | |
405 | struct resource res = { .start = 0, .end = 0x0fff }; | |
406 | pccard_io_map io = { 0, 0, 0, 0, 1 }; | |
407 | pccard_mem_map mem = { .res = &res, }; | |
408 | ||
409 | enter("i82092aa_init"); | |
410 | ||
411 | for (i = 0; i < 2; i++) { | |
412 | io.map = i; | |
413 | i82092aa_set_io_map(sock, &io); | |
414 | } | |
415 | for (i = 0; i < 5; i++) { | |
416 | mem.map = i; | |
417 | i82092aa_set_mem_map(sock, &mem); | |
418 | } | |
419 | ||
420 | leave("i82092aa_init"); | |
421 | return 0; | |
422 | } | |
423 | ||
424 | static int i82092aa_get_status(struct pcmcia_socket *socket, u_int *value) | |
425 | { | |
426 | unsigned int sock = container_of(socket, struct socket_info, socket)->number; | |
427 | unsigned int status; | |
428 | ||
429 | enter("i82092aa_get_status"); | |
430 | ||
431 | status = indirect_read(sock,I365_STATUS); /* Interface Status Register */ | |
432 | *value = 0; | |
433 | ||
434 | if ((status & I365_CS_DETECT) == I365_CS_DETECT) { | |
435 | *value |= SS_DETECT; | |
436 | } | |
437 | ||
438 | /* IO cards have a different meaning of bits 0,1 */ | |
439 | /* Also notice the inverse-logic on the bits */ | |
440 | if (indirect_read(sock, I365_INTCTL) & I365_PC_IOCARD) { | |
441 | /* IO card */ | |
442 | if (!(status & I365_CS_STSCHG)) | |
443 | *value |= SS_STSCHG; | |
444 | } else { /* non I/O card */ | |
445 | if (!(status & I365_CS_BVD1)) | |
446 | *value |= SS_BATDEAD; | |
447 | if (!(status & I365_CS_BVD2)) | |
448 | *value |= SS_BATWARN; | |
449 | ||
450 | } | |
451 | ||
452 | if (status & I365_CS_WRPROT) | |
453 | (*value) |= SS_WRPROT; /* card is write protected */ | |
454 | ||
455 | if (status & I365_CS_READY) | |
456 | (*value) |= SS_READY; /* card is not busy */ | |
457 | ||
458 | if (status & I365_CS_POWERON) | |
459 | (*value) |= SS_POWERON; /* power is applied to the card */ | |
460 | ||
461 | ||
462 | leave("i82092aa_get_status"); | |
463 | return 0; | |
464 | } | |
465 | ||
466 | ||
1da177e4 LT |
467 | static int i82092aa_set_socket(struct pcmcia_socket *socket, socket_state_t *state) |
468 | { | |
469 | unsigned int sock = container_of(socket, struct socket_info, socket)->number; | |
470 | unsigned char reg; | |
471 | ||
472 | enter("i82092aa_set_socket"); | |
473 | ||
474 | /* First, set the global controller options */ | |
475 | ||
476 | set_bridge_state(sock); | |
477 | ||
478 | /* Values for the IGENC register */ | |
479 | ||
480 | reg = 0; | |
481 | if (!(state->flags & SS_RESET)) /* The reset bit has "inverse" logic */ | |
482 | reg = reg | I365_PC_RESET; | |
483 | if (state->flags & SS_IOCARD) | |
484 | reg = reg | I365_PC_IOCARD; | |
485 | ||
486 | indirect_write(sock,I365_INTCTL,reg); /* IGENC, Interrupt and General Control Register */ | |
487 | ||
488 | /* Power registers */ | |
489 | ||
490 | reg = I365_PWR_NORESET; /* default: disable resetdrv on resume */ | |
491 | ||
492 | if (state->flags & SS_PWR_AUTO) { | |
493 | printk("Auto power\n"); | |
494 | reg |= I365_PWR_AUTO; /* automatic power mngmnt */ | |
495 | } | |
496 | if (state->flags & SS_OUTPUT_ENA) { | |
497 | printk("Power Enabled \n"); | |
498 | reg |= I365_PWR_OUT; /* enable power */ | |
499 | } | |
500 | ||
501 | switch (state->Vcc) { | |
502 | case 0: | |
503 | break; | |
504 | case 50: | |
505 | printk("setting voltage to Vcc to 5V on socket %i\n",sock); | |
506 | reg |= I365_VCC_5V; | |
507 | break; | |
508 | default: | |
509 | printk("i82092aa: i82092aa_set_socket called with invalid VCC power value: %i ", state->Vcc); | |
510 | leave("i82092aa_set_socket"); | |
511 | return -EINVAL; | |
512 | } | |
513 | ||
514 | ||
515 | switch (state->Vpp) { | |
516 | case 0: | |
517 | printk("not setting Vpp on socket %i\n",sock); | |
518 | break; | |
519 | case 50: | |
520 | printk("setting Vpp to 5.0 for socket %i\n",sock); | |
521 | reg |= I365_VPP1_5V | I365_VPP2_5V; | |
522 | break; | |
523 | case 120: | |
524 | printk("setting Vpp to 12.0\n"); | |
525 | reg |= I365_VPP1_12V | I365_VPP2_12V; | |
526 | break; | |
527 | default: | |
528 | printk("i82092aa: i82092aa_set_socket called with invalid VPP power value: %i ", state->Vcc); | |
529 | leave("i82092aa_set_socket"); | |
530 | return -EINVAL; | |
531 | } | |
532 | ||
533 | if (reg != indirect_read(sock,I365_POWER)) /* only write if changed */ | |
534 | indirect_write(sock,I365_POWER,reg); | |
535 | ||
536 | /* Enable specific interrupt events */ | |
537 | ||
538 | reg = 0x00; | |
539 | if (state->csc_mask & SS_DETECT) { | |
540 | reg |= I365_CSC_DETECT; | |
541 | } | |
542 | if (state->flags & SS_IOCARD) { | |
543 | if (state->csc_mask & SS_STSCHG) | |
544 | reg |= I365_CSC_STSCHG; | |
545 | } else { | |
546 | if (state->csc_mask & SS_BATDEAD) | |
547 | reg |= I365_CSC_BVD1; | |
548 | if (state->csc_mask & SS_BATWARN) | |
549 | reg |= I365_CSC_BVD2; | |
550 | if (state->csc_mask & SS_READY) | |
551 | reg |= I365_CSC_READY; | |
552 | ||
553 | } | |
554 | ||
555 | /* now write the value and clear the (probably bogus) pending stuff by doing a dummy read*/ | |
556 | ||
557 | indirect_write(sock,I365_CSCINT,reg); | |
558 | (void)indirect_read(sock,I365_CSC); | |
559 | ||
560 | leave("i82092aa_set_socket"); | |
561 | return 0; | |
562 | } | |
563 | ||
564 | static int i82092aa_set_io_map(struct pcmcia_socket *socket, struct pccard_io_map *io) | |
565 | { | |
566 | unsigned int sock = container_of(socket, struct socket_info, socket)->number; | |
567 | unsigned char map, ioctl; | |
568 | ||
569 | enter("i82092aa_set_io_map"); | |
570 | ||
571 | map = io->map; | |
572 | ||
573 | /* Check error conditions */ | |
574 | if (map > 1) { | |
575 | leave("i82092aa_set_io_map with invalid map"); | |
576 | return -EINVAL; | |
577 | } | |
578 | if ((io->start > 0xffff) || (io->stop > 0xffff) || (io->stop < io->start)){ | |
579 | leave("i82092aa_set_io_map with invalid io"); | |
580 | return -EINVAL; | |
581 | } | |
582 | ||
583 | /* Turn off the window before changing anything */ | |
584 | if (indirect_read(sock, I365_ADDRWIN) & I365_ENA_IO(map)) | |
585 | indirect_resetbit(sock, I365_ADDRWIN, I365_ENA_IO(map)); | |
586 | ||
587 | /* printk("set_io_map: Setting range to %x - %x \n",io->start,io->stop); */ | |
588 | ||
589 | /* write the new values */ | |
590 | indirect_write16(sock,I365_IO(map)+I365_W_START,io->start); | |
591 | indirect_write16(sock,I365_IO(map)+I365_W_STOP,io->stop); | |
592 | ||
593 | ioctl = indirect_read(sock,I365_IOCTL) & ~I365_IOCTL_MASK(map); | |
594 | ||
595 | if (io->flags & (MAP_16BIT|MAP_AUTOSZ)) | |
596 | ioctl |= I365_IOCTL_16BIT(map); | |
597 | ||
598 | indirect_write(sock,I365_IOCTL,ioctl); | |
599 | ||
600 | /* Turn the window back on if needed */ | |
601 | if (io->flags & MAP_ACTIVE) | |
602 | indirect_setbit(sock,I365_ADDRWIN,I365_ENA_IO(map)); | |
603 | ||
604 | leave("i82092aa_set_io_map"); | |
605 | return 0; | |
606 | } | |
607 | ||
608 | static int i82092aa_set_mem_map(struct pcmcia_socket *socket, struct pccard_mem_map *mem) | |
609 | { | |
610 | struct socket_info *sock_info = container_of(socket, struct socket_info, socket); | |
611 | unsigned int sock = sock_info->number; | |
612 | struct pci_bus_region region; | |
613 | unsigned short base, i; | |
614 | unsigned char map; | |
615 | ||
616 | enter("i82092aa_set_mem_map"); | |
617 | ||
618 | pcibios_resource_to_bus(sock_info->dev, ®ion, mem->res); | |
619 | ||
620 | map = mem->map; | |
621 | if (map > 4) { | |
622 | leave("i82092aa_set_mem_map: invalid map"); | |
623 | return -EINVAL; | |
624 | } | |
625 | ||
626 | ||
627 | if ( (mem->card_start > 0x3ffffff) || (region.start > region.end) || | |
628 | (mem->speed > 1000) ) { | |
629 | leave("i82092aa_set_mem_map: invalid address / speed"); | |
f96ee7a4 AM |
630 | printk("invalid mem map for socket %i: %llx to %llx with a " |
631 | "start of %x\n", | |
632 | sock, | |
633 | (unsigned long long)region.start, | |
634 | (unsigned long long)region.end, | |
635 | mem->card_start); | |
1da177e4 LT |
636 | return -EINVAL; |
637 | } | |
638 | ||
639 | /* Turn off the window before changing anything */ | |
640 | if (indirect_read(sock, I365_ADDRWIN) & I365_ENA_MEM(map)) | |
641 | indirect_resetbit(sock, I365_ADDRWIN, I365_ENA_MEM(map)); | |
642 | ||
643 | ||
644 | /* printk("set_mem_map: Setting map %i range to %x - %x on socket %i, speed is %i, active = %i \n",map, region.start,region.end,sock,mem->speed,mem->flags & MAP_ACTIVE); */ | |
645 | ||
646 | /* write the start address */ | |
647 | base = I365_MEM(map); | |
648 | i = (region.start >> 12) & 0x0fff; | |
649 | if (mem->flags & MAP_16BIT) | |
650 | i |= I365_MEM_16BIT; | |
651 | if (mem->flags & MAP_0WS) | |
652 | i |= I365_MEM_0WS; | |
653 | indirect_write16(sock,base+I365_W_START,i); | |
654 | ||
655 | /* write the stop address */ | |
656 | ||
657 | i= (region.end >> 12) & 0x0fff; | |
658 | switch (to_cycles(mem->speed)) { | |
659 | case 0: | |
660 | break; | |
661 | case 1: | |
662 | i |= I365_MEM_WS0; | |
663 | break; | |
664 | case 2: | |
665 | i |= I365_MEM_WS1; | |
666 | break; | |
667 | default: | |
668 | i |= I365_MEM_WS1 | I365_MEM_WS0; | |
669 | break; | |
670 | } | |
671 | ||
672 | indirect_write16(sock,base+I365_W_STOP,i); | |
673 | ||
674 | /* card start */ | |
675 | ||
676 | i = ((mem->card_start - region.start) >> 12) & 0x3fff; | |
677 | if (mem->flags & MAP_WRPROT) | |
678 | i |= I365_MEM_WRPROT; | |
679 | if (mem->flags & MAP_ATTRIB) { | |
680 | /* printk("requesting attribute memory for socket %i\n",sock);*/ | |
681 | i |= I365_MEM_REG; | |
682 | } else { | |
683 | /* printk("requesting normal memory for socket %i\n",sock);*/ | |
684 | } | |
685 | indirect_write16(sock,base+I365_W_OFF,i); | |
686 | ||
687 | /* Enable the window if necessary */ | |
688 | if (mem->flags & MAP_ACTIVE) | |
689 | indirect_setbit(sock, I365_ADDRWIN, I365_ENA_MEM(map)); | |
690 | ||
691 | leave("i82092aa_set_mem_map"); | |
692 | return 0; | |
693 | } | |
694 | ||
695 | static int i82092aa_module_init(void) | |
696 | { | |
ba66ddfa | 697 | return pci_register_driver(&i82092aa_pci_driver); |
1da177e4 LT |
698 | } |
699 | ||
700 | static void i82092aa_module_exit(void) | |
701 | { | |
702 | enter("i82092aa_module_exit"); | |
ba66ddfa | 703 | pci_unregister_driver(&i82092aa_pci_driver); |
1da177e4 LT |
704 | if (sockets[0].io_base>0) |
705 | release_region(sockets[0].io_base, 2); | |
706 | leave("i82092aa_module_exit"); | |
707 | } | |
708 | ||
709 | module_init(i82092aa_module_init); | |
710 | module_exit(i82092aa_module_exit); | |
711 |