[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / pci / setup-res.c

/*
 *	drivers/pci/setup-res.c
 *
 * Extruded from code written by
 *      Dave Rusling (david.rusling@reo.mts.dec.com)
 *      David Mosberger (davidm@cs.arizona.edu)
 *	David Miller (davem@redhat.com)
 *
 * Support routines for initializing a PCI subsystem.
 */

/* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */

/*
 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
 *	     Resource sorting
 */

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/cache.h>
#include <linux/slab.h>
#include "pci.h"


void pci_update_resource(struct pci_dev *dev, int resno)
{
	struct pci_bus_region region;
	u32 new, check, mask;
	int reg;
	enum pci_bar_type type;
	struct resource *res = dev->resource + resno;

	/*
	 * Ignore resources for unimplemented BARs and unused resource slots
	 * for 64 bit BARs.
	 */
	if (!res->flags)
		return;

	/*
	 * Ignore non-moveable resources.  This might be legacy resources for
	 * which no functional BAR register exists or another important
	 * system resource we shouldn't move around.
	 */
	if (res->flags & IORESOURCE_PCI_FIXED)
		return;

	pcibios_resource_to_bus(dev, &region, res);

	dev_dbg(&dev->dev, "BAR %d: got res %pR bus [%#llx-%#llx] "
		"flags %#lx\n", resno, res,
		 (unsigned long long)region.start,
		 (unsigned long long)region.end,
		 (unsigned long)res->flags);

	new = region.start | (res->flags & PCI_REGION_FLAG_MASK);
	if (res->flags & IORESOURCE_IO)
		mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
	else
		mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;

	reg = pci_resource_bar(dev, resno, &type);
	if (!reg)
		return;
	if (type != pci_bar_unknown) {
		if (!(res->flags & IORESOURCE_ROM_ENABLE))
			return;
		new |= PCI_ROM_ADDRESS_ENABLE;
	}

	pci_write_config_dword(dev, reg, new);
	pci_read_config_dword(dev, reg, &check);

	if ((new ^ check) & mask) {
		dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n",
			resno, new, check);
	}

	if ((new & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
	    (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64)) {
		new = region.start >> 16 >> 16;
		pci_write_config_dword(dev, reg + 4, new);
		pci_read_config_dword(dev, reg + 4, &check);
		if (check != new) {
			dev_err(&dev->dev, "BAR %d: error updating "
			       "(high %#08x != %#08x)\n", resno, new, check);
		}
	}
	res->flags &= ~IORESOURCE_UNSET;
	dev_dbg(&dev->dev, "BAR %d: moved to bus [%#llx-%#llx] flags %#lx\n",
		resno, (unsigned long long)region.start,
		(unsigned long long)region.end, res->flags);
}

int pci_claim_resource(struct pci_dev *dev, int resource)
{
	struct resource *res = &dev->resource[resource];
	struct resource *root = NULL;
	char *dtype = resource < PCI_BRIDGE_RESOURCES ? "device" : "bridge";
	int err;

	root = pcibios_select_root(dev, res);

	err = -EINVAL;
	if (root != NULL)
		err = insert_resource(root, res);

	if (err) {
		dev_err(&dev->dev, "BAR %d: %s of %s %pR\n",
			resource,
			root ? "address space collision on" :
				"no parent found for",
			dtype, res);
	}

	return err;
}

#ifdef CONFIG_PCI_QUIRKS
void pci_disable_bridge_window(struct pci_dev *dev)
{
	dev_dbg(&dev->dev, "Disabling bridge window.\n");

	/* MMIO Base/Limit */
	pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);

	/* Prefetchable MMIO Base/Limit */
	pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
	pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
	pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
}
#endif	/* CONFIG_PCI_QUIRKS */

int pci_assign_resource(struct pci_dev *dev, int resno)
{
	struct pci_bus *bus = dev->bus;
	struct resource *res = dev->resource + resno;
	resource_size_t size, min, align;
	int ret;

	size = resource_size(res);
	min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;

	align = resource_alignment(res);
	if (!align) {
		dev_info(&dev->dev, "BAR %d: can't allocate resource (bogus "
			"alignment) %pR flags %#lx\n",
			resno, res, res->flags);
		return -EINVAL;
	}

	/* First, try exact prefetching match.. */
	ret = pci_bus_alloc_resource(bus, res, size, align, min,
				     IORESOURCE_PREFETCH,
				     pcibios_align_resource, dev);

	if (ret < 0 && (res->flags & IORESOURCE_PREFETCH)) {
		/*
		 * That failed.
		 *
		 * But a prefetching area can handle a non-prefetching
		 * window (it will just not perform as well).
		 */
		ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
					     pcibios_align_resource, dev);
	}

	if (ret) {
		dev_info(&dev->dev, "BAR %d: can't allocate %s resource %pR\n",
			resno, res->flags & IORESOURCE_IO ? "I/O" : "mem", res);
	} else {
		res->flags &= ~IORESOURCE_STARTALIGN;
		if (resno < PCI_BRIDGE_RESOURCES)
			pci_update_resource(dev, resno);
	}

	return ret;
}

#if 0
int pci_assign_resource_fixed(struct pci_dev *dev, int resno)
{
	struct pci_bus *bus = dev->bus;
	struct resource *res = dev->resource + resno;
	unsigned int type_mask;
	int i, ret = -EBUSY;

	type_mask = IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH;

	for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
		struct resource *r = bus->resource[i];
		if (!r)
			continue;

		/* type_mask must match */
		if ((res->flags ^ r->flags) & type_mask)
			continue;

		ret = request_resource(r, res);

		if (ret == 0)
			break;
	}

	if (ret) {
		dev_err(&dev->dev, "BAR %d: can't allocate %s resource %pR\n",
			resno, res->flags & IORESOURCE_IO ? "I/O" : "mem", res);
	} else if (resno < PCI_BRIDGE_RESOURCES) {
		pci_update_resource(dev, resno);
	}

	return ret;
}
EXPORT_SYMBOL_GPL(pci_assign_resource_fixed);
#endif

/* Sort resources by alignment */
void pdev_sort_resources(struct pci_dev *dev, struct resource_list *head)
{
	int i;

	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
		struct resource *r;
		struct resource_list *list, *tmp;
		resource_size_t r_align;

		r = &dev->resource[i];

		if (r->flags & IORESOURCE_PCI_FIXED)
			continue;

		if (!(r->flags) || r->parent)
			continue;

		r_align = resource_alignment(r);
		if (!r_align) {
			dev_warn(&dev->dev, "BAR %d: bogus alignment "
				"%pR flags %#lx\n",
				i, r, r->flags);
			continue;
		}
		for (list = head; ; list = list->next) {
			resource_size_t align = 0;
			struct resource_list *ln = list->next;

			if (ln)
				align = resource_alignment(ln->res);

			if (r_align > align) {
				tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
				if (!tmp)
					panic("pdev_sort_resources(): "
					      "kmalloc() failed!\n");
				tmp->next = ln;
				tmp->res = r;
				tmp->dev = dev;
				list->next = tmp;
				break;
			}
		}
	}
}

int pci_enable_resources(struct pci_dev *dev, int mask)
{
	u16 cmd, old_cmd;
	int i;
	struct resource *r;

	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	old_cmd = cmd;

	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
		if (!(mask & (1 << i)))
			continue;

		r = &dev->resource[i];

		if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
			continue;
		if ((i == PCI_ROM_RESOURCE) &&
				(!(r->flags & IORESOURCE_ROM_ENABLE)))
			continue;

		if (!r->parent) {
			dev_err(&dev->dev, "device not available because of "
				"BAR %d %pR collisions\n", i, r);
			return -EINVAL;
		}

		if (r->flags & IORESOURCE_IO)
			cmd |= PCI_COMMAND_IO;
		if (r->flags & IORESOURCE_MEM)
			cmd |= PCI_COMMAND_MEMORY;
	}

	if (cmd != old_cmd) {
		dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
			 old_cmd, cmd);
		pci_write_config_word(dev, PCI_COMMAND, cmd);
	}
	return 0;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* drivers/pci/setup-res.c
	3	*
	4	* Extruded from code written by
	5	* Dave Rusling (david.rusling@reo.mts.dec.com)
	6	* David Mosberger (davidm@cs.arizona.edu)
	7	* David Miller (davem@redhat.com)
	8	*
	9	* Support routines for initializing a PCI subsystem.
	10	*/
	11
	12	/* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */
	13
	14	/*
	15	* Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
	16	* Resource sorting
	17	*/
	18
	19	#include <linux/init.h>
	20	#include <linux/kernel.h>
	21	#include <linux/pci.h>
	22	#include <linux/errno.h>
	23	#include <linux/ioport.h>
	24	#include <linux/cache.h>
	25	#include <linux/slab.h>
	26	#include "pci.h"
	27
	28
14add80b	29	void pci_update_resource(struct pci_dev *dev, int resno)
1da177e4 LT	30	{
	31	struct pci_bus_region region;
	32	u32 new, check, mask;
	33	int reg;
613e7ed6	34	enum pci_bar_type type;
14add80b	35	struct resource *res = dev->resource + resno;
1da177e4	36
fb0f2b40 RB	37	/*
	38	* Ignore resources for unimplemented BARs and unused resource slots
	39	* for 64 bit BARs.
	40	*/
cf7bee5a IK	41	if (!res->flags)
	42	return;
	43
fb0f2b40 RB	44	/*
	45	* Ignore non-moveable resources. This might be legacy resources for
	46	* which no functional BAR register exists or another important
80ccba11	47	* system resource we shouldn't move around.
fb0f2b40 RB	48	*/
	49	if (res->flags & IORESOURCE_PCI_FIXED)
	50	return;
	51
1da177e4 LT	52	pcibios_resource_to_bus(dev, &region, res);
1da177e4 LT	53
096e6f67 BH	54	dev_dbg(&dev->dev, "BAR %d: got res %pR bus [%#llx-%#llx] "
096e6f67 BH	55	"flags %#lx\n", resno, res,
6015fbef BH	56	(unsigned long long)region.start,
6015fbef BH	57	(unsigned long long)region.end,
80ccba11	58	(unsigned long)res->flags);
1da177e4 LT	59
	60	new = region.start \| (res->flags & PCI_REGION_FLAG_MASK);
	61	if (res->flags & IORESOURCE_IO)
	62	mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
	63	else
	64	mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
	65
613e7ed6 YZ	66	reg = pci_resource_bar(dev, resno, &type);
	67	if (!reg)
	68	return;
	69	if (type != pci_bar_unknown) {
755528c8 LT	70	if (!(res->flags & IORESOURCE_ROM_ENABLE))
	71	return;
	72	new \|= PCI_ROM_ADDRESS_ENABLE;
1da177e4 LT	73	}
	74
	75	pci_write_config_dword(dev, reg, new);
	76	pci_read_config_dword(dev, reg, &check);
	77
	78	if ((new ^ check) & mask) {
80ccba11 BH	79	dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n",
80ccba11 BH	80	resno, new, check);
1da177e4 LT	81	}
	82
	83	if ((new & (PCI_BASE_ADDRESS_SPACE\|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
	84	(PCI_BASE_ADDRESS_SPACE_MEMORY\|PCI_BASE_ADDRESS_MEM_TYPE_64)) {
cf7bee5a	85	new = region.start >> 16 >> 16;
1da177e4 LT	86	pci_write_config_dword(dev, reg + 4, new);
	87	pci_read_config_dword(dev, reg + 4, &check);
	88	if (check != new) {
80ccba11 BH	89	dev_err(&dev->dev, "BAR %d: error updating "
80ccba11 BH	90	"(high %#08x != %#08x)\n", resno, new, check);
1da177e4 LT	91	}
	92	}
	93	res->flags &= ~IORESOURCE_UNSET;
80ccba11 BH	94	dev_dbg(&dev->dev, "BAR %d: moved to bus [%#llx-%#llx] flags %#lx\n",
	95	resno, (unsigned long long)region.start,
	96	(unsigned long long)region.end, res->flags);
1da177e4 LT	97	}
1da177e4 LT	98
96bde06a	99	int pci_claim_resource(struct pci_dev *dev, int resource)
1da177e4 LT	100	{
	101	struct resource *res = &dev->resource[resource];
	102	struct resource *root = NULL;
	103	char *dtype = resource < PCI_BRIDGE_RESOURCES ? "device" : "bridge";
	104	int err;
	105
085ae41f	106	root = pcibios_select_root(dev, res);
1da177e4 LT	107
	108	err = -EINVAL;
	109	if (root != NULL)
	110	err = insert_resource(root, res);
	111
	112	if (err) {
096e6f67	113	dev_err(&dev->dev, "BAR %d: %s of %s %pR\n",
80ccba11 BH	114	resource,
	115	root ? "address space collision on" :
	116	"no parent found for",
096e6f67	117	dtype, res);
1da177e4 LT	118	}
	119
	120	return err;
	121	}
	122
32a9a682 YS	123	#ifdef CONFIG_PCI_QUIRKS
	124	void pci_disable_bridge_window(struct pci_dev *dev)
	125	{
	126	dev_dbg(&dev->dev, "Disabling bridge window.\n");
	127
	128	/* MMIO Base/Limit */
	129	pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
	130
	131	/* Prefetchable MMIO Base/Limit */
	132	pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
	133	pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
	134	pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
	135	}
	136	#endif /* CONFIG_PCI_QUIRKS */
	137
1da177e4 LT	138	int pci_assign_resource(struct pci_dev *dev, int resno)
	139	{
	140	struct pci_bus *bus = dev->bus;
	141	struct resource *res = dev->resource + resno;
e31dd6e4	142	resource_size_t size, min, align;
1da177e4 LT	143	int ret;
1da177e4 LT	144
022edd86	145	size = resource_size(res);
1da177e4	146	min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
88452565 IK	147
	148	align = resource_alignment(res);
	149	if (!align) {
104bafcf	150	dev_info(&dev->dev, "BAR %d: can't allocate resource (bogus "
096e6f67 BH	151	"alignment) %pR flags %#lx\n",
096e6f67 BH	152	resno, res, res->flags);
88452565 IK	153	return -EINVAL;
88452565 IK	154	}
1da177e4 LT	155
	156	/* First, try exact prefetching match.. */
	157	ret = pci_bus_alloc_resource(bus, res, size, align, min,
	158	IORESOURCE_PREFETCH,
	159	pcibios_align_resource, dev);
	160
	161	if (ret < 0 && (res->flags & IORESOURCE_PREFETCH)) {
	162	/*
	163	* That failed.
	164	*
	165	* But a prefetching area can handle a non-prefetching
	166	* window (it will just not perform as well).
	167	*/
	168	ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
	169	pcibios_align_resource, dev);
	170	}
	171
	172	if (ret) {
104bafcf	173	dev_info(&dev->dev, "BAR %d: can't allocate %s resource %pR\n",
096e6f67	174	resno, res->flags & IORESOURCE_IO ? "I/O" : "mem", res);
88452565 IK	175	} else {
	176	res->flags &= ~IORESOURCE_STARTALIGN;
	177	if (resno < PCI_BRIDGE_RESOURCES)
14add80b	178	pci_update_resource(dev, resno);
1da177e4 LT	179	}
	180
	181	return ret;
	182	}
	183
2baad5f9	184	#if 0
75acfeca KG	185	int pci_assign_resource_fixed(struct pci_dev *dev, int resno)
	186	{
	187	struct pci_bus *bus = dev->bus;
	188	struct resource *res = dev->resource + resno;
	189	unsigned int type_mask;
	190	int i, ret = -EBUSY;
	191
	192	type_mask = IORESOURCE_IO \| IORESOURCE_MEM \| IORESOURCE_PREFETCH;
	193
	194	for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
	195	struct resource *r = bus->resource[i];
	196	if (!r)
	197	continue;
	198
	199	/* type_mask must match */
	200	if ((res->flags ^ r->flags) & type_mask)
	201	continue;
	202
	203	ret = request_resource(r, res);
	204
	205	if (ret == 0)
	206	break;
	207	}
	208
	209	if (ret) {
096e6f67 BH	210	dev_err(&dev->dev, "BAR %d: can't allocate %s resource %pR\n",
096e6f67 BH	211	resno, res->flags & IORESOURCE_IO ? "I/O" : "mem", res);
75acfeca	212	} else if (resno < PCI_BRIDGE_RESOURCES) {
14add80b	213	pci_update_resource(dev, resno);
75acfeca KG	214	}
	215
	216	return ret;
	217	}
	218	EXPORT_SYMBOL_GPL(pci_assign_resource_fixed);
	219	#endif
	220
1da177e4	221	/* Sort resources by alignment */
96bde06a	222	void pdev_sort_resources(struct pci_dev dev, struct resource_list head)
1da177e4 LT	223	{
	224	int i;
	225
	226	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
	227	struct resource *r;
	228	struct resource_list list, tmp;
e31dd6e4	229	resource_size_t r_align;
1da177e4 LT	230
1da177e4 LT	231	r = &dev->resource[i];
fb0f2b40 RB	232
	233	if (r->flags & IORESOURCE_PCI_FIXED)
	234	continue;
	235
1da177e4 LT	236	if (!(r->flags) \|\| r->parent)
1da177e4 LT	237	continue;
88452565 IK	238
88452565 IK	239	r_align = resource_alignment(r);
1da177e4	240	if (!r_align) {
80ccba11	241	dev_warn(&dev->dev, "BAR %d: bogus alignment "
096e6f67 BH	242	"%pR flags %#lx\n",
096e6f67 BH	243	i, r, r->flags);
1da177e4 LT	244	continue;
1da177e4 LT	245	}
1da177e4	246	for (list = head; ; list = list->next) {
e31dd6e4	247	resource_size_t align = 0;
1da177e4	248	struct resource_list *ln = list->next;
88452565 IK	249
	250	if (ln)
	251	align = resource_alignment(ln->res);
	252
1da177e4 LT	253	if (r_align > align) {
	254	tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
	255	if (!tmp)
	256	panic("pdev_sort_resources(): "
	257	"kmalloc() failed!\n");
	258	tmp->next = ln;
	259	tmp->res = r;
	260	tmp->dev = dev;
	261	list->next = tmp;
	262	break;
	263	}
	264	}
	265	}
	266	}
842de40d BH	267
	268	int pci_enable_resources(struct pci_dev *dev, int mask)
	269	{
	270	u16 cmd, old_cmd;
	271	int i;
	272	struct resource *r;
	273
	274	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	275	old_cmd = cmd;
	276
	277	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
	278	if (!(mask & (1 << i)))
	279	continue;
	280
	281	r = &dev->resource[i];
	282
	283	if (!(r->flags & (IORESOURCE_IO \| IORESOURCE_MEM)))
	284	continue;
	285	if ((i == PCI_ROM_RESOURCE) &&
	286	(!(r->flags & IORESOURCE_ROM_ENABLE)))
	287	continue;
	288
	289	if (!r->parent) {
	290	dev_err(&dev->dev, "device not available because of "
096e6f67	291	"BAR %d %pR collisions\n", i, r);
842de40d BH	292	return -EINVAL;
	293	}
	294
	295	if (r->flags & IORESOURCE_IO)
	296	cmd \|= PCI_COMMAND_IO;
	297	if (r->flags & IORESOURCE_MEM)
	298	cmd \|= PCI_COMMAND_MEMORY;
	299	}
	300
	301	if (cmd != old_cmd) {
	302	dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
	303	old_cmd, cmd);
	304	pci_write_config_word(dev, PCI_COMMAND, cmd);
	305	}
	306	return 0;
	307	}