Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * drivers/pci/setup-bus.c | |
3 | * | |
4 | * Extruded from code written by | |
5 | * Dave Rusling (david.rusling@reo.mts.dec.com) | |
6 | * David Mosberger (davidm@cs.arizona.edu) | |
7 | * David Miller (davem@redhat.com) | |
8 | * | |
9 | * Support routines for initializing a PCI subsystem. | |
10 | */ | |
11 | ||
12 | /* | |
13 | * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
14 | * PCI-PCI bridges cleanup, sorted resource allocation. | |
15 | * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
16 | * Converted to allocation in 3 passes, which gives | |
17 | * tighter packing. Prefetchable range support. | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/pci.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/ioport.h> | |
26 | #include <linux/cache.h> | |
27 | #include <linux/slab.h> | |
6faf17f6 | 28 | #include "pci.h" |
1da177e4 | 29 | |
568ddef8 YL |
30 | struct resource_list_x { |
31 | struct resource_list_x *next; | |
32 | struct resource *res; | |
33 | struct pci_dev *dev; | |
34 | resource_size_t start; | |
35 | resource_size_t end; | |
c8adf9a3 | 36 | resource_size_t add_size; |
2bbc6942 | 37 | resource_size_t min_align; |
568ddef8 YL |
38 | unsigned long flags; |
39 | }; | |
40 | ||
094732a5 RP |
41 | #define free_list(type, head) do { \ |
42 | struct type *list, *tmp; \ | |
43 | for (list = (head)->next; list;) { \ | |
44 | tmp = list; \ | |
45 | list = list->next; \ | |
46 | kfree(tmp); \ | |
47 | } \ | |
48 | (head)->next = NULL; \ | |
49 | } while (0) | |
50 | ||
f483d392 RP |
51 | int pci_realloc_enable = 0; |
52 | #define pci_realloc_enabled() pci_realloc_enable | |
53 | void pci_realloc(void) | |
54 | { | |
55 | pci_realloc_enable = 1; | |
56 | } | |
57 | ||
c8adf9a3 RP |
58 | /** |
59 | * add_to_list() - add a new resource tracker to the list | |
60 | * @head: Head of the list | |
61 | * @dev: device corresponding to which the resource | |
62 | * belongs | |
63 | * @res: The resource to be tracked | |
64 | * @add_size: additional size to be optionally added | |
65 | * to the resource | |
66 | */ | |
ef62dfef | 67 | static int add_to_list(struct resource_list_x *head, |
c8adf9a3 | 68 | struct pci_dev *dev, struct resource *res, |
2bbc6942 | 69 | resource_size_t add_size, resource_size_t min_align) |
568ddef8 YL |
70 | { |
71 | struct resource_list_x *list = head; | |
72 | struct resource_list_x *ln = list->next; | |
73 | struct resource_list_x *tmp; | |
74 | ||
75 | tmp = kmalloc(sizeof(*tmp), GFP_KERNEL); | |
76 | if (!tmp) { | |
c8adf9a3 | 77 | pr_warning("add_to_list: kmalloc() failed!\n"); |
ef62dfef | 78 | return -ENOMEM; |
568ddef8 YL |
79 | } |
80 | ||
81 | tmp->next = ln; | |
82 | tmp->res = res; | |
83 | tmp->dev = dev; | |
84 | tmp->start = res->start; | |
85 | tmp->end = res->end; | |
86 | tmp->flags = res->flags; | |
c8adf9a3 | 87 | tmp->add_size = add_size; |
2bbc6942 | 88 | tmp->min_align = min_align; |
568ddef8 | 89 | list->next = tmp; |
ef62dfef YL |
90 | |
91 | return 0; | |
568ddef8 YL |
92 | } |
93 | ||
c8adf9a3 RP |
94 | static void add_to_failed_list(struct resource_list_x *head, |
95 | struct pci_dev *dev, struct resource *res) | |
96 | { | |
2bbc6942 RP |
97 | add_to_list(head, dev, res, |
98 | 0 /* dont care */, | |
99 | 0 /* dont care */); | |
c8adf9a3 RP |
100 | } |
101 | ||
3e6e0d80 YL |
102 | static void remove_from_list(struct resource_list_x *realloc_head, |
103 | struct resource *res) | |
104 | { | |
105 | struct resource_list_x *prev, *tmp, *list; | |
106 | ||
107 | prev = realloc_head; | |
108 | for (list = realloc_head->next; list;) { | |
109 | if (list->res != res) { | |
110 | prev = list; | |
111 | list = list->next; | |
112 | continue; | |
113 | } | |
114 | tmp = list; | |
115 | prev->next = list = list->next; | |
116 | kfree(tmp); | |
117 | } | |
118 | } | |
119 | ||
1c372353 YL |
120 | static resource_size_t get_res_add_size(struct resource_list_x *realloc_head, |
121 | struct resource *res) | |
122 | { | |
123 | struct resource_list_x *list; | |
124 | ||
125 | /* check if it is in realloc_head list */ | |
126 | for (list = realloc_head->next; list && list->res != res; | |
127 | list = list->next) | |
128 | ; | |
3e6e0d80 YL |
129 | |
130 | if (list) { | |
131 | dev_printk(KERN_DEBUG, &list->dev->dev, | |
132 | "%pR get_res_add_size add_size %llx\n", | |
133 | list->res, (unsigned long long)list->add_size); | |
1c372353 | 134 | return list->add_size; |
3e6e0d80 | 135 | } |
1c372353 YL |
136 | |
137 | return 0; | |
138 | } | |
139 | ||
78c3b329 YL |
140 | /* Sort resources by alignment */ |
141 | static void pdev_sort_resources(struct pci_dev *dev, struct resource_list *head) | |
142 | { | |
143 | int i; | |
144 | ||
145 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
146 | struct resource *r; | |
147 | struct resource_list *list, *tmp; | |
148 | resource_size_t r_align; | |
149 | ||
150 | r = &dev->resource[i]; | |
151 | ||
152 | if (r->flags & IORESOURCE_PCI_FIXED) | |
153 | continue; | |
154 | ||
155 | if (!(r->flags) || r->parent) | |
156 | continue; | |
157 | ||
158 | r_align = pci_resource_alignment(dev, r); | |
159 | if (!r_align) { | |
160 | dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n", | |
161 | i, r); | |
162 | continue; | |
163 | } | |
164 | for (list = head; ; list = list->next) { | |
165 | resource_size_t align = 0; | |
166 | struct resource_list *ln = list->next; | |
167 | ||
168 | if (ln) | |
169 | align = pci_resource_alignment(ln->dev, ln->res); | |
170 | ||
171 | if (r_align > align) { | |
172 | tmp = kmalloc(sizeof(*tmp), GFP_KERNEL); | |
173 | if (!tmp) | |
174 | panic("pdev_sort_resources(): " | |
175 | "kmalloc() failed!\n"); | |
176 | tmp->next = ln; | |
177 | tmp->res = r; | |
178 | tmp->dev = dev; | |
179 | list->next = tmp; | |
180 | break; | |
181 | } | |
182 | } | |
183 | } | |
184 | } | |
185 | ||
6841ec68 YL |
186 | static void __dev_sort_resources(struct pci_dev *dev, |
187 | struct resource_list *head) | |
1da177e4 | 188 | { |
6841ec68 | 189 | u16 class = dev->class >> 8; |
1da177e4 | 190 | |
6841ec68 YL |
191 | /* Don't touch classless devices or host bridges or ioapics. */ |
192 | if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST) | |
193 | return; | |
1da177e4 | 194 | |
6841ec68 YL |
195 | /* Don't touch ioapic devices already enabled by firmware */ |
196 | if (class == PCI_CLASS_SYSTEM_PIC) { | |
197 | u16 command; | |
198 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
199 | if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | |
200 | return; | |
201 | } | |
1da177e4 | 202 | |
6841ec68 YL |
203 | pdev_sort_resources(dev, head); |
204 | } | |
23186279 | 205 | |
fc075e1d RP |
206 | static inline void reset_resource(struct resource *res) |
207 | { | |
208 | res->start = 0; | |
209 | res->end = 0; | |
210 | res->flags = 0; | |
211 | } | |
212 | ||
c8adf9a3 | 213 | /** |
9e8bf93a | 214 | * reassign_resources_sorted() - satisfy any additional resource requests |
c8adf9a3 | 215 | * |
9e8bf93a | 216 | * @realloc_head : head of the list tracking requests requiring additional |
c8adf9a3 RP |
217 | * resources |
218 | * @head : head of the list tracking requests with allocated | |
219 | * resources | |
220 | * | |
9e8bf93a | 221 | * Walk through each element of the realloc_head and try to procure |
c8adf9a3 RP |
222 | * additional resources for the element, provided the element |
223 | * is in the head list. | |
224 | */ | |
9e8bf93a | 225 | static void reassign_resources_sorted(struct resource_list_x *realloc_head, |
c8adf9a3 | 226 | struct resource_list *head) |
6841ec68 YL |
227 | { |
228 | struct resource *res; | |
c8adf9a3 RP |
229 | struct resource_list_x *list, *tmp, *prev; |
230 | struct resource_list *hlist; | |
231 | resource_size_t add_size; | |
6841ec68 | 232 | int idx; |
1da177e4 | 233 | |
9e8bf93a RP |
234 | prev = realloc_head; |
235 | for (list = realloc_head->next; list;) { | |
1da177e4 | 236 | res = list->res; |
c8adf9a3 RP |
237 | /* skip resource that has been reset */ |
238 | if (!res->flags) | |
239 | goto out; | |
240 | ||
241 | /* skip this resource if not found in head list */ | |
242 | for (hlist = head->next; hlist && hlist->res != res; | |
243 | hlist = hlist->next); | |
244 | if (!hlist) { /* just skip */ | |
245 | prev = list; | |
246 | list = list->next; | |
247 | continue; | |
248 | } | |
249 | ||
1da177e4 | 250 | idx = res - &list->dev->resource[0]; |
c8adf9a3 | 251 | add_size=list->add_size; |
2bbc6942 | 252 | if (!resource_size(res)) { |
0a2daa1c | 253 | res->start = list->start; |
2bbc6942 RP |
254 | res->end = res->start + add_size - 1; |
255 | if(pci_assign_resource(list->dev, idx)) | |
c8adf9a3 | 256 | reset_resource(res); |
2bbc6942 RP |
257 | } else { |
258 | resource_size_t align = list->min_align; | |
259 | res->flags |= list->flags & (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN); | |
260 | if (pci_reassign_resource(list->dev, idx, add_size, align)) | |
261 | dev_printk(KERN_DEBUG, &list->dev->dev, "failed to add optional resources res=%pR\n", | |
262 | res); | |
c8adf9a3 RP |
263 | } |
264 | out: | |
265 | tmp = list; | |
266 | prev->next = list = list->next; | |
267 | kfree(tmp); | |
268 | } | |
269 | } | |
270 | ||
271 | /** | |
272 | * assign_requested_resources_sorted() - satisfy resource requests | |
273 | * | |
274 | * @head : head of the list tracking requests for resources | |
275 | * @failed_list : head of the list tracking requests that could | |
276 | * not be allocated | |
277 | * | |
278 | * Satisfy resource requests of each element in the list. Add | |
279 | * requests that could not satisfied to the failed_list. | |
280 | */ | |
281 | static void assign_requested_resources_sorted(struct resource_list *head, | |
282 | struct resource_list_x *fail_head) | |
283 | { | |
284 | struct resource *res; | |
285 | struct resource_list *list; | |
286 | int idx; | |
9a928660 | 287 | |
c8adf9a3 RP |
288 | for (list = head->next; list; list = list->next) { |
289 | res = list->res; | |
290 | idx = res - &list->dev->resource[0]; | |
291 | if (resource_size(res) && pci_assign_resource(list->dev, idx)) { | |
9a928660 YL |
292 | if (fail_head && !pci_is_root_bus(list->dev->bus)) { |
293 | /* | |
294 | * if the failed res is for ROM BAR, and it will | |
295 | * be enabled later, don't add it to the list | |
296 | */ | |
297 | if (!((idx == PCI_ROM_RESOURCE) && | |
298 | (!(res->flags & IORESOURCE_ROM_ENABLE)))) | |
299 | add_to_failed_list(fail_head, list->dev, res); | |
300 | } | |
fc075e1d | 301 | reset_resource(res); |
542df5de | 302 | } |
1da177e4 LT |
303 | } |
304 | } | |
305 | ||
c8adf9a3 | 306 | static void __assign_resources_sorted(struct resource_list *head, |
9e8bf93a | 307 | struct resource_list_x *realloc_head, |
c8adf9a3 RP |
308 | struct resource_list_x *fail_head) |
309 | { | |
3e6e0d80 YL |
310 | /* |
311 | * Should not assign requested resources at first. | |
312 | * they could be adjacent, so later reassign can not reallocate | |
313 | * them one by one in parent resource window. | |
314 | * Try to assign requested + add_size at begining | |
315 | * if could do that, could get out early. | |
316 | * if could not do that, we still try to assign requested at first, | |
317 | * then try to reassign add_size for some resources. | |
318 | */ | |
319 | struct resource_list_x save_head, local_fail_head, *list; | |
320 | struct resource_list *l; | |
321 | ||
322 | /* Check if optional add_size is there */ | |
323 | if (!realloc_head || !realloc_head->next) | |
324 | goto requested_and_reassign; | |
325 | ||
326 | /* Save original start, end, flags etc at first */ | |
327 | save_head.next = NULL; | |
328 | for (l = head->next; l; l = l->next) | |
329 | if (add_to_list(&save_head, l->dev, l->res, 0, 0)) { | |
330 | free_list(resource_list_x, &save_head); | |
331 | goto requested_and_reassign; | |
332 | } | |
333 | ||
334 | /* Update res in head list with add_size in realloc_head list */ | |
335 | for (l = head->next; l; l = l->next) | |
336 | l->res->end += get_res_add_size(realloc_head, l->res); | |
337 | ||
338 | /* Try updated head list with add_size added */ | |
339 | local_fail_head.next = NULL; | |
340 | assign_requested_resources_sorted(head, &local_fail_head); | |
341 | ||
342 | /* all assigned with add_size ? */ | |
343 | if (!local_fail_head.next) { | |
344 | /* Remove head list from realloc_head list */ | |
345 | for (l = head->next; l; l = l->next) | |
346 | remove_from_list(realloc_head, l->res); | |
347 | free_list(resource_list_x, &save_head); | |
348 | free_list(resource_list, head); | |
349 | return; | |
350 | } | |
351 | ||
352 | free_list(resource_list_x, &local_fail_head); | |
353 | /* Release assigned resource */ | |
354 | for (l = head->next; l; l = l->next) | |
355 | if (l->res->parent) | |
356 | release_resource(l->res); | |
357 | /* Restore start/end/flags from saved list */ | |
358 | for (list = save_head.next; list; list = list->next) { | |
359 | struct resource *res = list->res; | |
360 | ||
361 | res->start = list->start; | |
362 | res->end = list->end; | |
363 | res->flags = list->flags; | |
364 | } | |
365 | free_list(resource_list_x, &save_head); | |
366 | ||
367 | requested_and_reassign: | |
c8adf9a3 RP |
368 | /* Satisfy the must-have resource requests */ |
369 | assign_requested_resources_sorted(head, fail_head); | |
370 | ||
0a2daa1c | 371 | /* Try to satisfy any additional optional resource |
c8adf9a3 | 372 | requests */ |
9e8bf93a RP |
373 | if (realloc_head) |
374 | reassign_resources_sorted(realloc_head, head); | |
c8adf9a3 RP |
375 | free_list(resource_list, head); |
376 | } | |
377 | ||
6841ec68 | 378 | static void pdev_assign_resources_sorted(struct pci_dev *dev, |
8424d759 | 379 | struct resource_list_x *add_head, |
6841ec68 YL |
380 | struct resource_list_x *fail_head) |
381 | { | |
382 | struct resource_list head; | |
383 | ||
384 | head.next = NULL; | |
385 | __dev_sort_resources(dev, &head); | |
8424d759 | 386 | __assign_resources_sorted(&head, add_head, fail_head); |
6841ec68 YL |
387 | |
388 | } | |
389 | ||
390 | static void pbus_assign_resources_sorted(const struct pci_bus *bus, | |
9e8bf93a | 391 | struct resource_list_x *realloc_head, |
6841ec68 YL |
392 | struct resource_list_x *fail_head) |
393 | { | |
394 | struct pci_dev *dev; | |
395 | struct resource_list head; | |
396 | ||
397 | head.next = NULL; | |
398 | list_for_each_entry(dev, &bus->devices, bus_list) | |
399 | __dev_sort_resources(dev, &head); | |
400 | ||
9e8bf93a | 401 | __assign_resources_sorted(&head, realloc_head, fail_head); |
6841ec68 YL |
402 | } |
403 | ||
b3743fa4 | 404 | void pci_setup_cardbus(struct pci_bus *bus) |
1da177e4 LT |
405 | { |
406 | struct pci_dev *bridge = bus->self; | |
c7dabef8 | 407 | struct resource *res; |
1da177e4 LT |
408 | struct pci_bus_region region; |
409 | ||
865df576 BH |
410 | dev_info(&bridge->dev, "CardBus bridge to [bus %02x-%02x]\n", |
411 | bus->secondary, bus->subordinate); | |
1da177e4 | 412 | |
c7dabef8 BH |
413 | res = bus->resource[0]; |
414 | pcibios_resource_to_bus(bridge, ®ion, res); | |
415 | if (res->flags & IORESOURCE_IO) { | |
1da177e4 LT |
416 | /* |
417 | * The IO resource is allocated a range twice as large as it | |
418 | * would normally need. This allows us to set both IO regs. | |
419 | */ | |
c7dabef8 | 420 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
1da177e4 LT |
421 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, |
422 | region.start); | |
423 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, | |
424 | region.end); | |
425 | } | |
426 | ||
c7dabef8 BH |
427 | res = bus->resource[1]; |
428 | pcibios_resource_to_bus(bridge, ®ion, res); | |
429 | if (res->flags & IORESOURCE_IO) { | |
430 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
431 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, |
432 | region.start); | |
433 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, | |
434 | region.end); | |
435 | } | |
436 | ||
c7dabef8 BH |
437 | res = bus->resource[2]; |
438 | pcibios_resource_to_bus(bridge, ®ion, res); | |
439 | if (res->flags & IORESOURCE_MEM) { | |
440 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
441 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, |
442 | region.start); | |
443 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, | |
444 | region.end); | |
445 | } | |
446 | ||
c7dabef8 BH |
447 | res = bus->resource[3]; |
448 | pcibios_resource_to_bus(bridge, ®ion, res); | |
449 | if (res->flags & IORESOURCE_MEM) { | |
450 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
451 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, |
452 | region.start); | |
453 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, | |
454 | region.end); | |
455 | } | |
456 | } | |
b3743fa4 | 457 | EXPORT_SYMBOL(pci_setup_cardbus); |
1da177e4 LT |
458 | |
459 | /* Initialize bridges with base/limit values we have collected. | |
460 | PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998) | |
461 | requires that if there is no I/O ports or memory behind the | |
462 | bridge, corresponding range must be turned off by writing base | |
463 | value greater than limit to the bridge's base/limit registers. | |
464 | ||
465 | Note: care must be taken when updating I/O base/limit registers | |
466 | of bridges which support 32-bit I/O. This update requires two | |
467 | config space writes, so it's quite possible that an I/O window of | |
468 | the bridge will have some undesirable address (e.g. 0) after the | |
469 | first write. Ditto 64-bit prefetchable MMIO. */ | |
7cc5997d | 470 | static void pci_setup_bridge_io(struct pci_bus *bus) |
1da177e4 LT |
471 | { |
472 | struct pci_dev *bridge = bus->self; | |
c7dabef8 | 473 | struct resource *res; |
1da177e4 | 474 | struct pci_bus_region region; |
7cc5997d | 475 | u32 l, io_upper16; |
1da177e4 LT |
476 | |
477 | /* Set up the top and bottom of the PCI I/O segment for this bus. */ | |
c7dabef8 BH |
478 | res = bus->resource[0]; |
479 | pcibios_resource_to_bus(bridge, ®ion, res); | |
480 | if (res->flags & IORESOURCE_IO) { | |
1da177e4 LT |
481 | pci_read_config_dword(bridge, PCI_IO_BASE, &l); |
482 | l &= 0xffff0000; | |
483 | l |= (region.start >> 8) & 0x00f0; | |
484 | l |= region.end & 0xf000; | |
485 | /* Set up upper 16 bits of I/O base/limit. */ | |
486 | io_upper16 = (region.end & 0xffff0000) | (region.start >> 16); | |
c7dabef8 | 487 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 488 | } else { |
1da177e4 LT |
489 | /* Clear upper 16 bits of I/O base/limit. */ |
490 | io_upper16 = 0; | |
491 | l = 0x00f0; | |
1da177e4 LT |
492 | } |
493 | /* Temporarily disable the I/O range before updating PCI_IO_BASE. */ | |
494 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff); | |
495 | /* Update lower 16 bits of I/O base/limit. */ | |
496 | pci_write_config_dword(bridge, PCI_IO_BASE, l); | |
497 | /* Update upper 16 bits of I/O base/limit. */ | |
498 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16); | |
7cc5997d YL |
499 | } |
500 | ||
501 | static void pci_setup_bridge_mmio(struct pci_bus *bus) | |
502 | { | |
503 | struct pci_dev *bridge = bus->self; | |
504 | struct resource *res; | |
505 | struct pci_bus_region region; | |
506 | u32 l; | |
1da177e4 | 507 | |
7cc5997d | 508 | /* Set up the top and bottom of the PCI Memory segment for this bus. */ |
c7dabef8 BH |
509 | res = bus->resource[1]; |
510 | pcibios_resource_to_bus(bridge, ®ion, res); | |
511 | if (res->flags & IORESOURCE_MEM) { | |
1da177e4 LT |
512 | l = (region.start >> 16) & 0xfff0; |
513 | l |= region.end & 0xfff00000; | |
c7dabef8 | 514 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 515 | } else { |
1da177e4 | 516 | l = 0x0000fff0; |
1da177e4 LT |
517 | } |
518 | pci_write_config_dword(bridge, PCI_MEMORY_BASE, l); | |
7cc5997d YL |
519 | } |
520 | ||
521 | static void pci_setup_bridge_mmio_pref(struct pci_bus *bus) | |
522 | { | |
523 | struct pci_dev *bridge = bus->self; | |
524 | struct resource *res; | |
525 | struct pci_bus_region region; | |
526 | u32 l, bu, lu; | |
1da177e4 LT |
527 | |
528 | /* Clear out the upper 32 bits of PREF limit. | |
529 | If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily | |
530 | disables PREF range, which is ok. */ | |
531 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0); | |
532 | ||
533 | /* Set up PREF base/limit. */ | |
c40a22e0 | 534 | bu = lu = 0; |
c7dabef8 BH |
535 | res = bus->resource[2]; |
536 | pcibios_resource_to_bus(bridge, ®ion, res); | |
537 | if (res->flags & IORESOURCE_PREFETCH) { | |
1da177e4 LT |
538 | l = (region.start >> 16) & 0xfff0; |
539 | l |= region.end & 0xfff00000; | |
c7dabef8 | 540 | if (res->flags & IORESOURCE_MEM_64) { |
1f82de10 YL |
541 | bu = upper_32_bits(region.start); |
542 | lu = upper_32_bits(region.end); | |
1f82de10 | 543 | } |
c7dabef8 | 544 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 545 | } else { |
1da177e4 | 546 | l = 0x0000fff0; |
1da177e4 LT |
547 | } |
548 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); | |
549 | ||
59353ea3 AW |
550 | /* Set the upper 32 bits of PREF base & limit. */ |
551 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu); | |
552 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu); | |
7cc5997d YL |
553 | } |
554 | ||
555 | static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type) | |
556 | { | |
557 | struct pci_dev *bridge = bus->self; | |
558 | ||
7cc5997d YL |
559 | dev_info(&bridge->dev, "PCI bridge to [bus %02x-%02x]\n", |
560 | bus->secondary, bus->subordinate); | |
561 | ||
562 | if (type & IORESOURCE_IO) | |
563 | pci_setup_bridge_io(bus); | |
564 | ||
565 | if (type & IORESOURCE_MEM) | |
566 | pci_setup_bridge_mmio(bus); | |
567 | ||
568 | if (type & IORESOURCE_PREFETCH) | |
569 | pci_setup_bridge_mmio_pref(bus); | |
1da177e4 LT |
570 | |
571 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl); | |
572 | } | |
573 | ||
e2444273 | 574 | void pci_setup_bridge(struct pci_bus *bus) |
7cc5997d YL |
575 | { |
576 | unsigned long type = IORESOURCE_IO | IORESOURCE_MEM | | |
577 | IORESOURCE_PREFETCH; | |
578 | ||
579 | __pci_setup_bridge(bus, type); | |
580 | } | |
581 | ||
1da177e4 LT |
582 | /* Check whether the bridge supports optional I/O and |
583 | prefetchable memory ranges. If not, the respective | |
584 | base/limit registers must be read-only and read as 0. */ | |
96bde06a | 585 | static void pci_bridge_check_ranges(struct pci_bus *bus) |
1da177e4 LT |
586 | { |
587 | u16 io; | |
588 | u32 pmem; | |
589 | struct pci_dev *bridge = bus->self; | |
590 | struct resource *b_res; | |
591 | ||
592 | b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; | |
593 | b_res[1].flags |= IORESOURCE_MEM; | |
594 | ||
595 | pci_read_config_word(bridge, PCI_IO_BASE, &io); | |
596 | if (!io) { | |
597 | pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0); | |
598 | pci_read_config_word(bridge, PCI_IO_BASE, &io); | |
599 | pci_write_config_word(bridge, PCI_IO_BASE, 0x0); | |
600 | } | |
601 | if (io) | |
602 | b_res[0].flags |= IORESOURCE_IO; | |
603 | /* DECchip 21050 pass 2 errata: the bridge may miss an address | |
604 | disconnect boundary by one PCI data phase. | |
605 | Workaround: do not use prefetching on this device. */ | |
606 | if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) | |
607 | return; | |
608 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); | |
609 | if (!pmem) { | |
610 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, | |
611 | 0xfff0fff0); | |
612 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); | |
613 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); | |
614 | } | |
1f82de10 | 615 | if (pmem) { |
1da177e4 | 616 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; |
99586105 YL |
617 | if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == |
618 | PCI_PREF_RANGE_TYPE_64) { | |
1f82de10 | 619 | b_res[2].flags |= IORESOURCE_MEM_64; |
99586105 YL |
620 | b_res[2].flags |= PCI_PREF_RANGE_TYPE_64; |
621 | } | |
1f82de10 YL |
622 | } |
623 | ||
624 | /* double check if bridge does support 64 bit pref */ | |
625 | if (b_res[2].flags & IORESOURCE_MEM_64) { | |
626 | u32 mem_base_hi, tmp; | |
627 | pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
628 | &mem_base_hi); | |
629 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
630 | 0xffffffff); | |
631 | pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); | |
632 | if (!tmp) | |
633 | b_res[2].flags &= ~IORESOURCE_MEM_64; | |
634 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
635 | mem_base_hi); | |
636 | } | |
1da177e4 LT |
637 | } |
638 | ||
639 | /* Helper function for sizing routines: find first available | |
640 | bus resource of a given type. Note: we intentionally skip | |
641 | the bus resources which have already been assigned (that is, | |
642 | have non-NULL parent resource). */ | |
96bde06a | 643 | static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type) |
1da177e4 LT |
644 | { |
645 | int i; | |
646 | struct resource *r; | |
647 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | | |
648 | IORESOURCE_PREFETCH; | |
649 | ||
89a74ecc | 650 | pci_bus_for_each_resource(bus, r, i) { |
299de034 IK |
651 | if (r == &ioport_resource || r == &iomem_resource) |
652 | continue; | |
55a10984 JB |
653 | if (r && (r->flags & type_mask) == type && !r->parent) |
654 | return r; | |
1da177e4 LT |
655 | } |
656 | return NULL; | |
657 | } | |
658 | ||
13583b16 RP |
659 | static resource_size_t calculate_iosize(resource_size_t size, |
660 | resource_size_t min_size, | |
661 | resource_size_t size1, | |
662 | resource_size_t old_size, | |
663 | resource_size_t align) | |
664 | { | |
665 | if (size < min_size) | |
666 | size = min_size; | |
667 | if (old_size == 1 ) | |
668 | old_size = 0; | |
669 | /* To be fixed in 2.5: we should have sort of HAVE_ISA | |
670 | flag in the struct pci_bus. */ | |
671 | #if defined(CONFIG_ISA) || defined(CONFIG_EISA) | |
672 | size = (size & 0xff) + ((size & ~0xffUL) << 2); | |
673 | #endif | |
674 | size = ALIGN(size + size1, align); | |
675 | if (size < old_size) | |
676 | size = old_size; | |
677 | return size; | |
678 | } | |
679 | ||
680 | static resource_size_t calculate_memsize(resource_size_t size, | |
681 | resource_size_t min_size, | |
682 | resource_size_t size1, | |
683 | resource_size_t old_size, | |
684 | resource_size_t align) | |
685 | { | |
686 | if (size < min_size) | |
687 | size = min_size; | |
688 | if (old_size == 1 ) | |
689 | old_size = 0; | |
690 | if (size < old_size) | |
691 | size = old_size; | |
692 | size = ALIGN(size + size1, align); | |
693 | return size; | |
694 | } | |
695 | ||
c8adf9a3 RP |
696 | /** |
697 | * pbus_size_io() - size the io window of a given bus | |
698 | * | |
699 | * @bus : the bus | |
700 | * @min_size : the minimum io window that must to be allocated | |
701 | * @add_size : additional optional io window | |
9e8bf93a | 702 | * @realloc_head : track the additional io window on this list |
c8adf9a3 RP |
703 | * |
704 | * Sizing the IO windows of the PCI-PCI bridge is trivial, | |
705 | * since these windows have 4K granularity and the IO ranges | |
706 | * of non-bridge PCI devices are limited to 256 bytes. | |
707 | * We must be careful with the ISA aliasing though. | |
708 | */ | |
709 | static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size, | |
9e8bf93a | 710 | resource_size_t add_size, struct resource_list_x *realloc_head) |
1da177e4 LT |
711 | { |
712 | struct pci_dev *dev; | |
713 | struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO); | |
c8adf9a3 | 714 | unsigned long size = 0, size0 = 0, size1 = 0; |
be768912 | 715 | resource_size_t children_add_size = 0; |
1da177e4 LT |
716 | |
717 | if (!b_res) | |
718 | return; | |
719 | ||
720 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
721 | int i; | |
722 | ||
723 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
724 | struct resource *r = &dev->resource[i]; | |
725 | unsigned long r_size; | |
726 | ||
727 | if (r->parent || !(r->flags & IORESOURCE_IO)) | |
728 | continue; | |
022edd86 | 729 | r_size = resource_size(r); |
1da177e4 LT |
730 | |
731 | if (r_size < 0x400) | |
732 | /* Might be re-aligned for ISA */ | |
733 | size += r_size; | |
734 | else | |
735 | size1 += r_size; | |
be768912 | 736 | |
9e8bf93a RP |
737 | if (realloc_head) |
738 | children_add_size += get_res_add_size(realloc_head, r); | |
1da177e4 LT |
739 | } |
740 | } | |
c8adf9a3 RP |
741 | size0 = calculate_iosize(size, min_size, size1, |
742 | resource_size(b_res), 4096); | |
be768912 YL |
743 | if (children_add_size > add_size) |
744 | add_size = children_add_size; | |
9e8bf93a | 745 | size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 : |
a4ac9fea | 746 | calculate_iosize(size, min_size, add_size + size1, |
13583b16 | 747 | resource_size(b_res), 4096); |
c8adf9a3 | 748 | if (!size0 && !size1) { |
865df576 BH |
749 | if (b_res->start || b_res->end) |
750 | dev_info(&bus->self->dev, "disabling bridge window " | |
751 | "%pR to [bus %02x-%02x] (unused)\n", b_res, | |
752 | bus->secondary, bus->subordinate); | |
1da177e4 LT |
753 | b_res->flags = 0; |
754 | return; | |
755 | } | |
756 | /* Alignment of the IO window is always 4K */ | |
757 | b_res->start = 4096; | |
c8adf9a3 | 758 | b_res->end = b_res->start + size0 - 1; |
88452565 | 759 | b_res->flags |= IORESOURCE_STARTALIGN; |
9e8bf93a RP |
760 | if (size1 > size0 && realloc_head) |
761 | add_to_list(realloc_head, bus->self, b_res, size1-size0, 4096); | |
1da177e4 LT |
762 | } |
763 | ||
c8adf9a3 RP |
764 | /** |
765 | * pbus_size_mem() - size the memory window of a given bus | |
766 | * | |
767 | * @bus : the bus | |
768 | * @min_size : the minimum memory window that must to be allocated | |
769 | * @add_size : additional optional memory window | |
9e8bf93a | 770 | * @realloc_head : track the additional memory window on this list |
c8adf9a3 RP |
771 | * |
772 | * Calculate the size of the bus and minimal alignment which | |
773 | * guarantees that all child resources fit in this size. | |
774 | */ | |
28760489 | 775 | static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, |
c8adf9a3 RP |
776 | unsigned long type, resource_size_t min_size, |
777 | resource_size_t add_size, | |
9e8bf93a | 778 | struct resource_list_x *realloc_head) |
1da177e4 LT |
779 | { |
780 | struct pci_dev *dev; | |
c8adf9a3 | 781 | resource_size_t min_align, align, size, size0, size1; |
c40a22e0 | 782 | resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */ |
1da177e4 LT |
783 | int order, max_order; |
784 | struct resource *b_res = find_free_bus_resource(bus, type); | |
1f82de10 | 785 | unsigned int mem64_mask = 0; |
be768912 | 786 | resource_size_t children_add_size = 0; |
1da177e4 LT |
787 | |
788 | if (!b_res) | |
789 | return 0; | |
790 | ||
791 | memset(aligns, 0, sizeof(aligns)); | |
792 | max_order = 0; | |
793 | size = 0; | |
794 | ||
1f82de10 YL |
795 | mem64_mask = b_res->flags & IORESOURCE_MEM_64; |
796 | b_res->flags &= ~IORESOURCE_MEM_64; | |
797 | ||
1da177e4 LT |
798 | list_for_each_entry(dev, &bus->devices, bus_list) { |
799 | int i; | |
1f82de10 | 800 | |
1da177e4 LT |
801 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { |
802 | struct resource *r = &dev->resource[i]; | |
c40a22e0 | 803 | resource_size_t r_size; |
1da177e4 LT |
804 | |
805 | if (r->parent || (r->flags & mask) != type) | |
806 | continue; | |
022edd86 | 807 | r_size = resource_size(r); |
2aceefcb YL |
808 | #ifdef CONFIG_PCI_IOV |
809 | /* put SRIOV requested res to the optional list */ | |
9e8bf93a | 810 | if (realloc_head && i >= PCI_IOV_RESOURCES && |
2aceefcb YL |
811 | i <= PCI_IOV_RESOURCE_END) { |
812 | r->end = r->start - 1; | |
9e8bf93a | 813 | add_to_list(realloc_head, dev, r, r_size, 0/* dont' care */); |
2aceefcb YL |
814 | children_add_size += r_size; |
815 | continue; | |
816 | } | |
817 | #endif | |
1da177e4 | 818 | /* For bridges size != alignment */ |
6faf17f6 | 819 | align = pci_resource_alignment(dev, r); |
1da177e4 LT |
820 | order = __ffs(align) - 20; |
821 | if (order > 11) { | |
865df576 BH |
822 | dev_warn(&dev->dev, "disabling BAR %d: %pR " |
823 | "(bad alignment %#llx)\n", i, r, | |
824 | (unsigned long long) align); | |
1da177e4 LT |
825 | r->flags = 0; |
826 | continue; | |
827 | } | |
828 | size += r_size; | |
829 | if (order < 0) | |
830 | order = 0; | |
831 | /* Exclude ranges with size > align from | |
832 | calculation of the alignment. */ | |
833 | if (r_size == align) | |
834 | aligns[order] += align; | |
835 | if (order > max_order) | |
836 | max_order = order; | |
1f82de10 | 837 | mem64_mask &= r->flags & IORESOURCE_MEM_64; |
be768912 | 838 | |
9e8bf93a RP |
839 | if (realloc_head) |
840 | children_add_size += get_res_add_size(realloc_head, r); | |
1da177e4 LT |
841 | } |
842 | } | |
1da177e4 LT |
843 | align = 0; |
844 | min_align = 0; | |
845 | for (order = 0; order <= max_order; order++) { | |
8308c54d JF |
846 | resource_size_t align1 = 1; |
847 | ||
848 | align1 <<= (order + 20); | |
849 | ||
1da177e4 LT |
850 | if (!align) |
851 | min_align = align1; | |
6f6f8c2f | 852 | else if (ALIGN(align + min_align, min_align) < align1) |
1da177e4 LT |
853 | min_align = align1 >> 1; |
854 | align += aligns[order]; | |
855 | } | |
b42282e5 | 856 | size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align); |
be768912 YL |
857 | if (children_add_size > add_size) |
858 | add_size = children_add_size; | |
9e8bf93a | 859 | size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 : |
a4ac9fea | 860 | calculate_memsize(size, min_size, add_size, |
b42282e5 | 861 | resource_size(b_res), min_align); |
c8adf9a3 | 862 | if (!size0 && !size1) { |
865df576 BH |
863 | if (b_res->start || b_res->end) |
864 | dev_info(&bus->self->dev, "disabling bridge window " | |
865 | "%pR to [bus %02x-%02x] (unused)\n", b_res, | |
866 | bus->secondary, bus->subordinate); | |
1da177e4 LT |
867 | b_res->flags = 0; |
868 | return 1; | |
869 | } | |
870 | b_res->start = min_align; | |
c8adf9a3 RP |
871 | b_res->end = size0 + min_align - 1; |
872 | b_res->flags |= IORESOURCE_STARTALIGN | mem64_mask; | |
9e8bf93a RP |
873 | if (size1 > size0 && realloc_head) |
874 | add_to_list(realloc_head, bus->self, b_res, size1-size0, min_align); | |
1da177e4 LT |
875 | return 1; |
876 | } | |
877 | ||
0a2daa1c RP |
878 | unsigned long pci_cardbus_resource_alignment(struct resource *res) |
879 | { | |
880 | if (res->flags & IORESOURCE_IO) | |
881 | return pci_cardbus_io_size; | |
882 | if (res->flags & IORESOURCE_MEM) | |
883 | return pci_cardbus_mem_size; | |
884 | return 0; | |
885 | } | |
886 | ||
887 | static void pci_bus_size_cardbus(struct pci_bus *bus, | |
9e8bf93a | 888 | struct resource_list_x *realloc_head) |
1da177e4 LT |
889 | { |
890 | struct pci_dev *bridge = bus->self; | |
891 | struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; | |
892 | u16 ctrl; | |
893 | ||
894 | /* | |
895 | * Reserve some resources for CardBus. We reserve | |
896 | * a fixed amount of bus space for CardBus bridges. | |
897 | */ | |
934b7024 | 898 | b_res[0].start = 0; |
934b7024 | 899 | b_res[0].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN; |
9e8bf93a RP |
900 | if (realloc_head) |
901 | add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size, 0 /* dont care */); | |
1da177e4 | 902 | |
934b7024 | 903 | b_res[1].start = 0; |
934b7024 | 904 | b_res[1].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN; |
9e8bf93a RP |
905 | if (realloc_head) |
906 | add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size, 0 /* dont care */); | |
1da177e4 LT |
907 | |
908 | /* | |
909 | * Check whether prefetchable memory is supported | |
910 | * by this bridge. | |
911 | */ | |
912 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
913 | if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) { | |
914 | ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; | |
915 | pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); | |
916 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
917 | } | |
918 | ||
919 | /* | |
920 | * If we have prefetchable memory support, allocate | |
921 | * two regions. Otherwise, allocate one region of | |
922 | * twice the size. | |
923 | */ | |
924 | if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { | |
934b7024 | 925 | b_res[2].start = 0; |
934b7024 | 926 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_SIZEALIGN; |
9e8bf93a RP |
927 | if (realloc_head) |
928 | add_to_list(realloc_head, bridge, b_res+2, pci_cardbus_mem_size, 0 /* dont care */); | |
1da177e4 | 929 | |
934b7024 | 930 | b_res[3].start = 0; |
934b7024 | 931 | b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN; |
9e8bf93a RP |
932 | if (realloc_head) |
933 | add_to_list(realloc_head, bridge, b_res+3, pci_cardbus_mem_size, 0 /* dont care */); | |
1da177e4 | 934 | } else { |
934b7024 | 935 | b_res[3].start = 0; |
934b7024 | 936 | b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN; |
9e8bf93a RP |
937 | if (realloc_head) |
938 | add_to_list(realloc_head, bridge, b_res+3, pci_cardbus_mem_size * 2, 0 /* dont care */); | |
1da177e4 | 939 | } |
0a2daa1c RP |
940 | |
941 | /* set the size of the resource to zero, so that the resource does not | |
942 | * get assigned during required-resource allocation cycle but gets assigned | |
943 | * during the optional-resource allocation cycle. | |
944 | */ | |
945 | b_res[0].start = b_res[1].start = b_res[2].start = b_res[3].start = 1; | |
946 | b_res[0].end = b_res[1].end = b_res[2].end = b_res[3].end = 0; | |
1da177e4 LT |
947 | } |
948 | ||
c8adf9a3 | 949 | void __ref __pci_bus_size_bridges(struct pci_bus *bus, |
9e8bf93a | 950 | struct resource_list_x *realloc_head) |
1da177e4 LT |
951 | { |
952 | struct pci_dev *dev; | |
953 | unsigned long mask, prefmask; | |
c8adf9a3 | 954 | resource_size_t additional_mem_size = 0, additional_io_size = 0; |
1da177e4 LT |
955 | |
956 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
957 | struct pci_bus *b = dev->subordinate; | |
958 | if (!b) | |
959 | continue; | |
960 | ||
961 | switch (dev->class >> 8) { | |
962 | case PCI_CLASS_BRIDGE_CARDBUS: | |
9e8bf93a | 963 | pci_bus_size_cardbus(b, realloc_head); |
1da177e4 LT |
964 | break; |
965 | ||
966 | case PCI_CLASS_BRIDGE_PCI: | |
967 | default: | |
9e8bf93a | 968 | __pci_bus_size_bridges(b, realloc_head); |
1da177e4 LT |
969 | break; |
970 | } | |
971 | } | |
972 | ||
973 | /* The root bus? */ | |
974 | if (!bus->self) | |
975 | return; | |
976 | ||
977 | switch (bus->self->class >> 8) { | |
978 | case PCI_CLASS_BRIDGE_CARDBUS: | |
979 | /* don't size cardbuses yet. */ | |
980 | break; | |
981 | ||
982 | case PCI_CLASS_BRIDGE_PCI: | |
983 | pci_bridge_check_ranges(bus); | |
28760489 | 984 | if (bus->self->is_hotplug_bridge) { |
c8adf9a3 RP |
985 | additional_io_size = pci_hotplug_io_size; |
986 | additional_mem_size = pci_hotplug_mem_size; | |
28760489 | 987 | } |
c8adf9a3 RP |
988 | /* |
989 | * Follow thru | |
990 | */ | |
1da177e4 | 991 | default: |
19aa7ee4 YL |
992 | pbus_size_io(bus, realloc_head ? 0 : additional_io_size, |
993 | additional_io_size, realloc_head); | |
1da177e4 LT |
994 | /* If the bridge supports prefetchable range, size it |
995 | separately. If it doesn't, or its prefetchable window | |
996 | has already been allocated by arch code, try | |
997 | non-prefetchable range for both types of PCI memory | |
998 | resources. */ | |
999 | mask = IORESOURCE_MEM; | |
1000 | prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
19aa7ee4 YL |
1001 | if (pbus_size_mem(bus, prefmask, prefmask, |
1002 | realloc_head ? 0 : additional_mem_size, | |
1003 | additional_mem_size, realloc_head)) | |
1da177e4 | 1004 | mask = prefmask; /* Success, size non-prefetch only. */ |
28760489 | 1005 | else |
c8adf9a3 | 1006 | additional_mem_size += additional_mem_size; |
19aa7ee4 YL |
1007 | pbus_size_mem(bus, mask, IORESOURCE_MEM, |
1008 | realloc_head ? 0 : additional_mem_size, | |
1009 | additional_mem_size, realloc_head); | |
1da177e4 LT |
1010 | break; |
1011 | } | |
1012 | } | |
c8adf9a3 RP |
1013 | |
1014 | void __ref pci_bus_size_bridges(struct pci_bus *bus) | |
1015 | { | |
1016 | __pci_bus_size_bridges(bus, NULL); | |
1017 | } | |
1da177e4 LT |
1018 | EXPORT_SYMBOL(pci_bus_size_bridges); |
1019 | ||
568ddef8 | 1020 | static void __ref __pci_bus_assign_resources(const struct pci_bus *bus, |
9e8bf93a | 1021 | struct resource_list_x *realloc_head, |
568ddef8 | 1022 | struct resource_list_x *fail_head) |
1da177e4 LT |
1023 | { |
1024 | struct pci_bus *b; | |
1025 | struct pci_dev *dev; | |
1026 | ||
9e8bf93a | 1027 | pbus_assign_resources_sorted(bus, realloc_head, fail_head); |
1da177e4 | 1028 | |
1da177e4 LT |
1029 | list_for_each_entry(dev, &bus->devices, bus_list) { |
1030 | b = dev->subordinate; | |
1031 | if (!b) | |
1032 | continue; | |
1033 | ||
9e8bf93a | 1034 | __pci_bus_assign_resources(b, realloc_head, fail_head); |
1da177e4 LT |
1035 | |
1036 | switch (dev->class >> 8) { | |
1037 | case PCI_CLASS_BRIDGE_PCI: | |
6841ec68 YL |
1038 | if (!pci_is_enabled(dev)) |
1039 | pci_setup_bridge(b); | |
1da177e4 LT |
1040 | break; |
1041 | ||
1042 | case PCI_CLASS_BRIDGE_CARDBUS: | |
1043 | pci_setup_cardbus(b); | |
1044 | break; | |
1045 | ||
1046 | default: | |
80ccba11 BH |
1047 | dev_info(&dev->dev, "not setting up bridge for bus " |
1048 | "%04x:%02x\n", pci_domain_nr(b), b->number); | |
1da177e4 LT |
1049 | break; |
1050 | } | |
1051 | } | |
1052 | } | |
568ddef8 YL |
1053 | |
1054 | void __ref pci_bus_assign_resources(const struct pci_bus *bus) | |
1055 | { | |
c8adf9a3 | 1056 | __pci_bus_assign_resources(bus, NULL, NULL); |
568ddef8 | 1057 | } |
1da177e4 LT |
1058 | EXPORT_SYMBOL(pci_bus_assign_resources); |
1059 | ||
6841ec68 | 1060 | static void __ref __pci_bridge_assign_resources(const struct pci_dev *bridge, |
8424d759 | 1061 | struct resource_list_x *add_head, |
6841ec68 YL |
1062 | struct resource_list_x *fail_head) |
1063 | { | |
1064 | struct pci_bus *b; | |
1065 | ||
8424d759 YL |
1066 | pdev_assign_resources_sorted((struct pci_dev *)bridge, |
1067 | add_head, fail_head); | |
6841ec68 YL |
1068 | |
1069 | b = bridge->subordinate; | |
1070 | if (!b) | |
1071 | return; | |
1072 | ||
8424d759 | 1073 | __pci_bus_assign_resources(b, add_head, fail_head); |
6841ec68 YL |
1074 | |
1075 | switch (bridge->class >> 8) { | |
1076 | case PCI_CLASS_BRIDGE_PCI: | |
1077 | pci_setup_bridge(b); | |
1078 | break; | |
1079 | ||
1080 | case PCI_CLASS_BRIDGE_CARDBUS: | |
1081 | pci_setup_cardbus(b); | |
1082 | break; | |
1083 | ||
1084 | default: | |
1085 | dev_info(&bridge->dev, "not setting up bridge for bus " | |
1086 | "%04x:%02x\n", pci_domain_nr(b), b->number); | |
1087 | break; | |
1088 | } | |
1089 | } | |
5009b460 YL |
1090 | static void pci_bridge_release_resources(struct pci_bus *bus, |
1091 | unsigned long type) | |
1092 | { | |
1093 | int idx; | |
1094 | bool changed = false; | |
1095 | struct pci_dev *dev; | |
1096 | struct resource *r; | |
1097 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | | |
1098 | IORESOURCE_PREFETCH; | |
1099 | ||
1100 | dev = bus->self; | |
1101 | for (idx = PCI_BRIDGE_RESOURCES; idx <= PCI_BRIDGE_RESOURCE_END; | |
1102 | idx++) { | |
1103 | r = &dev->resource[idx]; | |
1104 | if ((r->flags & type_mask) != type) | |
1105 | continue; | |
1106 | if (!r->parent) | |
1107 | continue; | |
1108 | /* | |
1109 | * if there are children under that, we should release them | |
1110 | * all | |
1111 | */ | |
1112 | release_child_resources(r); | |
1113 | if (!release_resource(r)) { | |
1114 | dev_printk(KERN_DEBUG, &dev->dev, | |
1115 | "resource %d %pR released\n", idx, r); | |
1116 | /* keep the old size */ | |
1117 | r->end = resource_size(r) - 1; | |
1118 | r->start = 0; | |
1119 | r->flags = 0; | |
1120 | changed = true; | |
1121 | } | |
1122 | } | |
1123 | ||
1124 | if (changed) { | |
1125 | /* avoiding touch the one without PREF */ | |
1126 | if (type & IORESOURCE_PREFETCH) | |
1127 | type = IORESOURCE_PREFETCH; | |
1128 | __pci_setup_bridge(bus, type); | |
1129 | } | |
1130 | } | |
1131 | ||
1132 | enum release_type { | |
1133 | leaf_only, | |
1134 | whole_subtree, | |
1135 | }; | |
1136 | /* | |
1137 | * try to release pci bridge resources that is from leaf bridge, | |
1138 | * so we can allocate big new one later | |
1139 | */ | |
1140 | static void __ref pci_bus_release_bridge_resources(struct pci_bus *bus, | |
1141 | unsigned long type, | |
1142 | enum release_type rel_type) | |
1143 | { | |
1144 | struct pci_dev *dev; | |
1145 | bool is_leaf_bridge = true; | |
1146 | ||
1147 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1148 | struct pci_bus *b = dev->subordinate; | |
1149 | if (!b) | |
1150 | continue; | |
1151 | ||
1152 | is_leaf_bridge = false; | |
1153 | ||
1154 | if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
1155 | continue; | |
1156 | ||
1157 | if (rel_type == whole_subtree) | |
1158 | pci_bus_release_bridge_resources(b, type, | |
1159 | whole_subtree); | |
1160 | } | |
1161 | ||
1162 | if (pci_is_root_bus(bus)) | |
1163 | return; | |
1164 | ||
1165 | if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
1166 | return; | |
1167 | ||
1168 | if ((rel_type == whole_subtree) || is_leaf_bridge) | |
1169 | pci_bridge_release_resources(bus, type); | |
1170 | } | |
1171 | ||
76fbc263 YL |
1172 | static void pci_bus_dump_res(struct pci_bus *bus) |
1173 | { | |
89a74ecc BH |
1174 | struct resource *res; |
1175 | int i; | |
7c9342b8 | 1176 | |
89a74ecc | 1177 | pci_bus_for_each_resource(bus, res, i) { |
7c9342b8 | 1178 | if (!res || !res->end || !res->flags) |
76fbc263 YL |
1179 | continue; |
1180 | ||
c7dabef8 | 1181 | dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res); |
76fbc263 YL |
1182 | } |
1183 | } | |
1184 | ||
1185 | static void pci_bus_dump_resources(struct pci_bus *bus) | |
1186 | { | |
1187 | struct pci_bus *b; | |
1188 | struct pci_dev *dev; | |
1189 | ||
1190 | ||
1191 | pci_bus_dump_res(bus); | |
1192 | ||
1193 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1194 | b = dev->subordinate; | |
1195 | if (!b) | |
1196 | continue; | |
1197 | ||
1198 | pci_bus_dump_resources(b); | |
1199 | } | |
1200 | } | |
1201 | ||
da7822e5 YL |
1202 | static int __init pci_bus_get_depth(struct pci_bus *bus) |
1203 | { | |
1204 | int depth = 0; | |
1205 | struct pci_dev *dev; | |
1206 | ||
1207 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1208 | int ret; | |
1209 | struct pci_bus *b = dev->subordinate; | |
1210 | if (!b) | |
1211 | continue; | |
1212 | ||
1213 | ret = pci_bus_get_depth(b); | |
1214 | if (ret + 1 > depth) | |
1215 | depth = ret + 1; | |
1216 | } | |
1217 | ||
1218 | return depth; | |
1219 | } | |
1220 | static int __init pci_get_max_depth(void) | |
1221 | { | |
1222 | int depth = 0; | |
1223 | struct pci_bus *bus; | |
1224 | ||
1225 | list_for_each_entry(bus, &pci_root_buses, node) { | |
1226 | int ret; | |
1227 | ||
1228 | ret = pci_bus_get_depth(bus); | |
1229 | if (ret > depth) | |
1230 | depth = ret; | |
1231 | } | |
1232 | ||
1233 | return depth; | |
1234 | } | |
1235 | ||
f483d392 | 1236 | |
da7822e5 YL |
1237 | /* |
1238 | * first try will not touch pci bridge res | |
1239 | * second and later try will clear small leaf bridge res | |
1240 | * will stop till to the max deepth if can not find good one | |
1241 | */ | |
1da177e4 LT |
1242 | void __init |
1243 | pci_assign_unassigned_resources(void) | |
1244 | { | |
1245 | struct pci_bus *bus; | |
9e8bf93a | 1246 | struct resource_list_x realloc_list; /* list of resources that |
c8adf9a3 | 1247 | want additional resources */ |
19aa7ee4 | 1248 | struct resource_list_x *add_list = NULL; |
da7822e5 YL |
1249 | int tried_times = 0; |
1250 | enum release_type rel_type = leaf_only; | |
1251 | struct resource_list_x head, *list; | |
1252 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | | |
1253 | IORESOURCE_PREFETCH; | |
1254 | unsigned long failed_type; | |
19aa7ee4 | 1255 | int pci_try_num = 1; |
da7822e5 YL |
1256 | |
1257 | head.next = NULL; | |
9e8bf93a | 1258 | realloc_list.next = NULL; |
da7822e5 | 1259 | |
19aa7ee4 YL |
1260 | /* don't realloc if asked to do so */ |
1261 | if (pci_realloc_enabled()) { | |
1262 | int max_depth = pci_get_max_depth(); | |
1263 | ||
1264 | pci_try_num = max_depth + 1; | |
1265 | printk(KERN_DEBUG "PCI: max bus depth: %d pci_try_num: %d\n", | |
1266 | max_depth, pci_try_num); | |
1267 | } | |
da7822e5 YL |
1268 | |
1269 | again: | |
19aa7ee4 YL |
1270 | /* |
1271 | * last try will use add_list, otherwise will try good to have as | |
1272 | * must have, so can realloc parent bridge resource | |
1273 | */ | |
1274 | if (tried_times + 1 == pci_try_num) | |
1275 | add_list = &realloc_list; | |
1da177e4 LT |
1276 | /* Depth first, calculate sizes and alignments of all |
1277 | subordinate buses. */ | |
da7822e5 | 1278 | list_for_each_entry(bus, &pci_root_buses, node) |
19aa7ee4 | 1279 | __pci_bus_size_bridges(bus, add_list); |
c8adf9a3 | 1280 | |
1da177e4 | 1281 | /* Depth last, allocate resources and update the hardware. */ |
da7822e5 | 1282 | list_for_each_entry(bus, &pci_root_buses, node) |
19aa7ee4 YL |
1283 | __pci_bus_assign_resources(bus, add_list, &head); |
1284 | if (add_list) | |
1285 | BUG_ON(add_list->next); | |
da7822e5 YL |
1286 | tried_times++; |
1287 | ||
1288 | /* any device complain? */ | |
1289 | if (!head.next) | |
1290 | goto enable_and_dump; | |
f483d392 | 1291 | |
da7822e5 YL |
1292 | failed_type = 0; |
1293 | for (list = head.next; list;) { | |
1294 | failed_type |= list->flags; | |
1295 | list = list->next; | |
1296 | } | |
1297 | /* | |
1298 | * io port are tight, don't try extra | |
1299 | * or if reach the limit, don't want to try more | |
1300 | */ | |
1301 | failed_type &= type_mask; | |
1302 | if ((failed_type == IORESOURCE_IO) || (tried_times >= pci_try_num)) { | |
1303 | free_list(resource_list_x, &head); | |
1304 | goto enable_and_dump; | |
1305 | } | |
1306 | ||
1307 | printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n", | |
1308 | tried_times + 1); | |
1309 | ||
1310 | /* third times and later will not check if it is leaf */ | |
1311 | if ((tried_times + 1) > 2) | |
1312 | rel_type = whole_subtree; | |
1313 | ||
1314 | /* | |
1315 | * Try to release leaf bridge's resources that doesn't fit resource of | |
1316 | * child device under that bridge | |
1317 | */ | |
1318 | for (list = head.next; list;) { | |
1319 | bus = list->dev->bus; | |
1320 | pci_bus_release_bridge_resources(bus, list->flags & type_mask, | |
1321 | rel_type); | |
1322 | list = list->next; | |
1323 | } | |
1324 | /* restore size and flags */ | |
1325 | for (list = head.next; list;) { | |
1326 | struct resource *res = list->res; | |
1327 | ||
1328 | res->start = list->start; | |
1329 | res->end = list->end; | |
1330 | res->flags = list->flags; | |
1331 | if (list->dev->subordinate) | |
1332 | res->flags = 0; | |
1333 | ||
1334 | list = list->next; | |
1335 | } | |
1336 | free_list(resource_list_x, &head); | |
1337 | ||
1338 | goto again; | |
1339 | ||
1340 | enable_and_dump: | |
1341 | /* Depth last, update the hardware. */ | |
1342 | list_for_each_entry(bus, &pci_root_buses, node) | |
1343 | pci_enable_bridges(bus); | |
76fbc263 YL |
1344 | |
1345 | /* dump the resource on buses */ | |
da7822e5 | 1346 | list_for_each_entry(bus, &pci_root_buses, node) |
76fbc263 | 1347 | pci_bus_dump_resources(bus); |
1da177e4 | 1348 | } |
6841ec68 YL |
1349 | |
1350 | void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge) | |
1351 | { | |
1352 | struct pci_bus *parent = bridge->subordinate; | |
8424d759 YL |
1353 | struct resource_list_x add_list; /* list of resources that |
1354 | want additional resources */ | |
32180e40 YL |
1355 | int tried_times = 0; |
1356 | struct resource_list_x head, *list; | |
6841ec68 | 1357 | int retval; |
32180e40 YL |
1358 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | |
1359 | IORESOURCE_PREFETCH; | |
1360 | ||
1361 | head.next = NULL; | |
8424d759 | 1362 | add_list.next = NULL; |
6841ec68 | 1363 | |
32180e40 | 1364 | again: |
8424d759 YL |
1365 | __pci_bus_size_bridges(parent, &add_list); |
1366 | __pci_bridge_assign_resources(bridge, &add_list, &head); | |
1367 | BUG_ON(add_list.next); | |
32180e40 YL |
1368 | tried_times++; |
1369 | ||
1370 | if (!head.next) | |
3f579c34 | 1371 | goto enable_all; |
32180e40 YL |
1372 | |
1373 | if (tried_times >= 2) { | |
1374 | /* still fail, don't need to try more */ | |
094732a5 | 1375 | free_list(resource_list_x, &head); |
3f579c34 | 1376 | goto enable_all; |
32180e40 YL |
1377 | } |
1378 | ||
1379 | printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n", | |
1380 | tried_times + 1); | |
1381 | ||
1382 | /* | |
1383 | * Try to release leaf bridge's resources that doesn't fit resource of | |
1384 | * child device under that bridge | |
1385 | */ | |
1386 | for (list = head.next; list;) { | |
1387 | struct pci_bus *bus = list->dev->bus; | |
1388 | unsigned long flags = list->flags; | |
1389 | ||
1390 | pci_bus_release_bridge_resources(bus, flags & type_mask, | |
1391 | whole_subtree); | |
1392 | list = list->next; | |
1393 | } | |
1394 | /* restore size and flags */ | |
1395 | for (list = head.next; list;) { | |
1396 | struct resource *res = list->res; | |
1397 | ||
1398 | res->start = list->start; | |
1399 | res->end = list->end; | |
1400 | res->flags = list->flags; | |
1401 | if (list->dev->subordinate) | |
1402 | res->flags = 0; | |
1403 | ||
1404 | list = list->next; | |
1405 | } | |
094732a5 | 1406 | free_list(resource_list_x, &head); |
32180e40 YL |
1407 | |
1408 | goto again; | |
3f579c34 YL |
1409 | |
1410 | enable_all: | |
1411 | retval = pci_reenable_device(bridge); | |
1412 | pci_set_master(bridge); | |
1413 | pci_enable_bridges(parent); | |
6841ec68 YL |
1414 | } |
1415 | EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources); | |
9b03088f YL |
1416 | |
1417 | #ifdef CONFIG_HOTPLUG | |
1418 | /** | |
1419 | * pci_rescan_bus - scan a PCI bus for devices. | |
1420 | * @bus: PCI bus to scan | |
1421 | * | |
1422 | * Scan a PCI bus and child buses for new devices, adds them, | |
1423 | * and enables them. | |
1424 | * | |
1425 | * Returns the max number of subordinate bus discovered. | |
1426 | */ | |
1427 | unsigned int __ref pci_rescan_bus(struct pci_bus *bus) | |
1428 | { | |
1429 | unsigned int max; | |
1430 | struct pci_dev *dev; | |
1431 | struct resource_list_x add_list; /* list of resources that | |
1432 | want additional resources */ | |
1433 | ||
1434 | max = pci_scan_child_bus(bus); | |
1435 | ||
1436 | add_list.next = NULL; | |
1437 | down_read(&pci_bus_sem); | |
1438 | list_for_each_entry(dev, &bus->devices, bus_list) | |
1439 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || | |
1440 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) | |
1441 | if (dev->subordinate) | |
1442 | __pci_bus_size_bridges(dev->subordinate, | |
1443 | &add_list); | |
1444 | up_read(&pci_bus_sem); | |
1445 | __pci_bus_assign_resources(bus, &add_list, NULL); | |
1446 | BUG_ON(add_list.next); | |
1447 | ||
1448 | pci_enable_bridges(bus); | |
1449 | pci_bus_add_devices(bus); | |
1450 | ||
1451 | return max; | |
1452 | } | |
1453 | EXPORT_SYMBOL_GPL(pci_rescan_bus); | |
1454 | #endif |