projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Resources: insert identical resources above existing resources
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / pci / quirks.c
CommitLineData
1da177e4
LT		 1/*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
7586269c
DB		 10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 *
1da177e4
LT		 13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
16 */
17
1da177e4
LT		 18#include <linux/types.h>
19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/init.h>
22#include <linux/delay.h>
25be5e6c 23#include <linux/acpi.h>
bc56b9e0 24#include "pci.h"
1da177e4 25
bd8481e1
DT		 26/* The Mellanox Tavor device gives false positive parity errors
27 * Mark this device with a broken_parity_status, to allow
28 * PCI scanning code to "skip" this now blacklisted device.
29 */
30static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
31{
32 dev->broken_parity_status = 1; /* This device gives false positives */
33}
34DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
35DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
36
1da177e4
LT		 37/* Deal with broken BIOS'es that neglect to enable passive release,
38 which can cause problems in combination with the 82441FX/PPro MTRRs */
39static void __devinit quirk_passive_release(struct pci_dev *dev)
40{
41 struct pci_dev *d = NULL;
42 unsigned char dlc;
43
44 /* We have to make sure a particular bit is set in the PIIX3
45 ISA bridge, so we have to go out and find it. */
46 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
47 pci_read_config_byte(d, 0x82, &dlc);
48 if (!(dlc & 1<<1)) {
49 printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d));
50 dlc |= 1<<1;
51 pci_write_config_byte(d, 0x82, dlc);
52 }
53 }
54}
55DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release );
56
57/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
58 but VIA don't answer queries. If you happen to have good contacts at VIA
59 ask them for me please -- Alan
60
61 This appears to be BIOS not version dependent. So presumably there is a
62 chipset level fix */
63int isa_dma_bridge_buggy; /* Exported */
64
65static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
66{
67 if (!isa_dma_bridge_buggy) {
68 isa_dma_bridge_buggy=1;
69 printk(KERN_INFO "Activating ISA DMA hang workarounds.\n");
70 }
71}
72 /*
73 * Its not totally clear which chipsets are the problematic ones
74 * We know 82C586 and 82C596 variants are affected.
75 */
76DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs );
77DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs );
78DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs );
79DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs );
80DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs );
81DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs );
82DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs );
83
84int pci_pci_problems;
85
86/*
87 * Chipsets where PCI->PCI transfers vanish or hang
88 */
89static void __devinit quirk_nopcipci(struct pci_dev *dev)
90{
91 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
92 printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n");
93 pci_pci_problems |= PCIPCI_FAIL;
94 }
95}
96DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci );
97DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci );
98
99/*
100 * Triton requires workarounds to be used by the drivers
101 */
102static void __devinit quirk_triton(struct pci_dev *dev)
103{
104 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
105 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
106 pci_pci_problems |= PCIPCI_TRITON;
107 }
108}
109DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton );
110DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton );
111DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton );
112DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton );
113
114/*
115 * VIA Apollo KT133 needs PCI latency patch
116 * Made according to a windows driver based patch by George E. Breese
117 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
118 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
119 * the info on which Mr Breese based his work.
120 *
121 * Updated based on further information from the site and also on
122 * information provided by VIA
123 */
124static void __devinit quirk_vialatency(struct pci_dev *dev)
125{
126 struct pci_dev *p;
127 u8 rev;
128 u8 busarb;
129 /* Ok we have a potential problem chipset here. Now see if we have
130 a buggy southbridge */
131
132 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
133 if (p!=NULL) {
134 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
135 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
136 /* Check for buggy part revisions */
137 if (rev < 0x40 || rev > 0x42)
138 goto exit;
139 } else {
140 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
141 if (p==NULL) /* No problem parts */
142 goto exit;
143 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
144 /* Check for buggy part revisions */
145 if (rev < 0x10 || rev > 0x12)
146 goto exit;
147 }
148
149 /*
150 * Ok we have the problem. Now set the PCI master grant to
151 * occur every master grant. The apparent bug is that under high
152 * PCI load (quite common in Linux of course) you can get data
153 * loss when the CPU is held off the bus for 3 bus master requests
154 * This happens to include the IDE controllers....
155 *
156 * VIA only apply this fix when an SB Live! is present but under
157 * both Linux and Windows this isnt enough, and we have seen
158 * corruption without SB Live! but with things like 3 UDMA IDE
159 * controllers. So we ignore that bit of the VIA recommendation..
160 */
161
162 pci_read_config_byte(dev, 0x76, &busarb);
163 /* Set bit 4 and bi 5 of byte 76 to 0x01
164 "Master priority rotation on every PCI master grant */
165 busarb &= ~(1<<5);
166 busarb |= (1<<4);
167 pci_write_config_byte(dev, 0x76, busarb);
168 printk(KERN_INFO "Applying VIA southbridge workaround.\n");
169exit:
170 pci_dev_put(p);
171}
172DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency );
173DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency );
174DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency );
175
176/*
177 * VIA Apollo VP3 needs ETBF on BT848/878
178 */
179static void __devinit quirk_viaetbf(struct pci_dev *dev)
180{
181 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
182 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
183 pci_pci_problems |= PCIPCI_VIAETBF;
184 }
185}
186DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf );
187
188static void __devinit quirk_vsfx(struct pci_dev *dev)
189{
190 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
191 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
192 pci_pci_problems |= PCIPCI_VSFX;
193 }
194}
195DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx );
196
197/*
198 * Ali Magik requires workarounds to be used by the drivers
199 * that DMA to AGP space. Latency must be set to 0xA and triton
200 * workaround applied too
201 * [Info kindly provided by ALi]
202 */
203static void __init quirk_alimagik(struct pci_dev *dev)
204{
205 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
206 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
207 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
208 }
209}
210DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik );
211DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik );
212
213/*
214 * Natoma has some interesting boundary conditions with Zoran stuff
215 * at least
216 */
217static void __devinit quirk_natoma(struct pci_dev *dev)
218{
219 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
220 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
221 pci_pci_problems |= PCIPCI_NATOMA;
222 }
223}
224DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma );
225DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma );
226DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma );
227DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma );
228DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma );
229DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma );
230
231/*
232 * This chip can cause PCI parity errors if config register 0xA0 is read
233 * while DMAs are occurring.
234 */
235static void __devinit quirk_citrine(struct pci_dev *dev)
236{
237 dev->cfg_size = 0xA0;
238}
239DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine );
240
241/*
242 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
243 * If it's needed, re-allocate the region.
244 */
245static void __devinit quirk_s3_64M(struct pci_dev *dev)
246{
247 struct resource *r = &dev->resource[0];
248
249 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
250 r->start = 0;
251 r->end = 0x3ffffff;
252 }
253}
254DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M );
255DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M );
256
6693e74a
LT		 257static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
258 unsigned size, int nr, const char *name)
1da177e4
LT		 259{
260 region &= ~(size-1);
261 if (region) {
085ae41f 262 struct pci_bus_region bus_region;
1da177e4
LT		 263 struct resource *res = dev->resource + nr;
264
265 res->name = pci_name(dev);
266 res->start = region;
267 res->end = region + size - 1;
268 res->flags = IORESOURCE_IO;
085ae41f
DM		 269
270 /* Convert from PCI bus to resource space. */
271 bus_region.start = res->start;
272 bus_region.end = res->end;
273 pcibios_bus_to_resource(dev, res, &bus_region);
274
1da177e4 275 pci_claim_resource(dev, nr);
6693e74a 276 printk("PCI quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name);
1da177e4
LT		 277 }
278}
279
280/*
281 * ATI Northbridge setups MCE the processor if you even
282 * read somewhere between 0x3b0->0x3bb or read 0x3d3
283 */
284static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
285{
286 printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n");
287 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
288 request_region(0x3b0, 0x0C, "RadeonIGP");
289 request_region(0x3d3, 0x01, "RadeonIGP");
290}
291DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce );
292
293/*
294 * Let's make the southbridge information explicit instead
295 * of having to worry about people probing the ACPI areas,
296 * for example.. (Yes, it happens, and if you read the wrong
297 * ACPI register it will put the machine to sleep with no
298 * way of waking it up again. Bummer).
299 *
300 * ALI M7101: Two IO regions pointed to by words at
301 * 0xE0 (64 bytes of ACPI registers)
302 * 0xE2 (32 bytes of SMB registers)
303 */
304static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
305{
306 u16 region;
307
308 pci_read_config_word(dev, 0xE0, &region);
6693e74a 309 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
1da177e4 310 pci_read_config_word(dev, 0xE2, &region);
6693e74a 311 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
1da177e4
LT		 312}
313DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi );
314
6693e74a
LT		 315static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
316{
317 u32 devres;
318 u32 mask, size, base;
319
320 pci_read_config_dword(dev, port, &devres);
321 if ((devres & enable) != enable)
322 return;
323 mask = (devres >> 16) & 15;
324 base = devres & 0xffff;
325 size = 16;
326 for (;;) {
327 unsigned bit = size >> 1;
328 if ((bit & mask) == bit)
329 break;
330 size = bit;
331 }
332 /*
333 * For now we only print it out. Eventually we'll want to
334 * reserve it (at least if it's in the 0x1000+ range), but
335 * let's get enough confirmation reports first.
336 */
337 base &= -size;
338 printk("%s PIO at %04x-%04x\n", name, base, base + size - 1);
339}
340
341static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
342{
343 u32 devres;
344 u32 mask, size, base;
345
346 pci_read_config_dword(dev, port, &devres);
347 if ((devres & enable) != enable)
348 return;
349 base = devres & 0xffff0000;
350 mask = (devres & 0x3f) << 16;
351 size = 128 << 16;
352 for (;;) {
353 unsigned bit = size >> 1;
354 if ((bit & mask) == bit)
355 break;
356 size = bit;
357 }
358 /*
359 * For now we only print it out. Eventually we'll want to
360 * reserve it, but let's get enough confirmation reports first.
361 */
362 base &= -size;
363 printk("%s MMIO at %04x-%04x\n", name, base, base + size - 1);
364}
365
1da177e4
LT		 366/*
367 * PIIX4 ACPI: Two IO regions pointed to by longwords at
368 * 0x40 (64 bytes of ACPI registers)
08db2a70 369 * 0x90 (16 bytes of SMB registers)
6693e74a 370 * and a few strange programmable PIIX4 device resources.
1da177e4
LT		 371 */
372static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
373{
6693e74a 374 u32 region, res_a;
1da177e4
LT		 375
376 pci_read_config_dword(dev, 0x40, &region);
6693e74a 377 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
1da177e4 378 pci_read_config_dword(dev, 0x90, &region);
08db2a70 379 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
6693e74a
LT		 380
381 /* Device resource A has enables for some of the other ones */
382 pci_read_config_dword(dev, 0x5c, &res_a);
383
384 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
385 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
386
387 /* Device resource D is just bitfields for static resources */
388
389 /* Device 12 enabled? */
390 if (res_a & (1 << 29)) {
391 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
392 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
393 }
394 /* Device 13 enabled? */
395 if (res_a & (1 << 30)) {
396 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
397 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
398 }
399 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
400 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
1da177e4
LT		 401}
402DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi );
c6764664 403DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi );
1da177e4
LT		 404
405/*
406 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
407 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
408 * 0x58 (64 bytes of GPIO I/O space)
409 */
410static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
411{
412 u32 region;
413
414 pci_read_config_dword(dev, 0x40, &region);
6693e74a 415 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO");
1da177e4
LT		 416
417 pci_read_config_dword(dev, 0x58, &region);
6693e74a 418 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO");
1da177e4
LT		 419}
420DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi );
421DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi );
422DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi );
423DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi );
424DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi );
425DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi );
426DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi );
427DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi );
428DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi );
3aa8c4fe 429DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi );
1da177e4 430
2cea752f
RM		 431static void __devinit quirk_ich6_lpc_acpi(struct pci_dev *dev)
432{
433 u32 region;
434
435 pci_read_config_dword(dev, 0x40, &region);
436 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO");
437
438 pci_read_config_dword(dev, 0x48, &region);
439 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
440}
65ae4ddd 441DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc_acpi );
2cea752f
RM		 442DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc_acpi );
443
1da177e4
LT		 444/*
445 * VIA ACPI: One IO region pointed to by longword at
446 * 0x48 or 0x20 (256 bytes of ACPI registers)
447 */
448static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
449{
450 u8 rev;
451 u32 region;
452
453 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
454 if (rev & 0x10) {
455 pci_read_config_dword(dev, 0x48, &region);
456 region &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 457 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
1da177e4
LT		 458 }
459}
460DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi );
461
462/*
463 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
464 * 0x48 (256 bytes of ACPI registers)
465 * 0x70 (128 bytes of hardware monitoring register)
466 * 0x90 (16 bytes of SMB registers)
467 */
468static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
469{
470 u16 hm;
471 u32 smb;
472
473 quirk_vt82c586_acpi(dev);
474
475 pci_read_config_word(dev, 0x70, &hm);
476 hm &= PCI_BASE_ADDRESS_IO_MASK;
02f313b2 477 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
1da177e4
LT		 478
479 pci_read_config_dword(dev, 0x90, &smb);
480 smb &= PCI_BASE_ADDRESS_IO_MASK;
02f313b2 481 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
1da177e4
LT		 482}
483DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi );
484
6d85f29b
IK		 485/*
486 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
487 * 0x88 (128 bytes of power management registers)
488 * 0xd0 (16 bytes of SMB registers)
489 */
490static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
491{
492 u16 pm, smb;
493
494 pci_read_config_word(dev, 0x88, &pm);
495 pm &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 496 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
6d85f29b
IK		 497
498 pci_read_config_word(dev, 0xd0, &smb);
499 smb &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 500 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
6d85f29b
IK		 501}
502DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
503
1da177e4
LT		 504
505#ifdef CONFIG_X86_IO_APIC
506
507#include <asm/io_apic.h>
508
509/*
510 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
511 * devices to the external APIC.
512 *
513 * TODO: When we have device-specific interrupt routers,
514 * this code will go away from quirks.
515 */
516static void __devinit quirk_via_ioapic(struct pci_dev *dev)
517{
518 u8 tmp;
519
520 if (nr_ioapics < 1)
521 tmp = 0; /* nothing routed to external APIC */
522 else
523 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
524
525 printk(KERN_INFO "PCI: %sbling Via external APIC routing\n",
526 tmp == 0 ? "Disa" : "Ena");
527
528 /* Offset 0x58: External APIC IRQ output control */
529 pci_write_config_byte (dev, 0x58, tmp);
530}
531DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic );
532
a1740913
KW		 533/*
534 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
535 * This leads to doubled level interrupt rates.
536 * Set this bit to get rid of cycle wastage.
537 * Otherwise uncritical.
538 */
539static void __devinit quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
540{
541 u8 misc_control2;
542#define BYPASS_APIC_DEASSERT 8
543
544 pci_read_config_byte(dev, 0x5B, &misc_control2);
545 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
546 printk(KERN_INFO "PCI: Bypassing VIA 8237 APIC De-Assert Message\n");
547 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
548 }
549}
550DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
551
1da177e4
LT		 552/*
553 * The AMD io apic can hang the box when an apic irq is masked.
554 * We check all revs >= B0 (yet not in the pre production!) as the bug
555 * is currently marked NoFix
556 *
557 * We have multiple reports of hangs with this chipset that went away with
558 * noapic specified. For the moment we assume its the errata. We may be wrong
559 * of course. However the advice is demonstrably good even if so..
560 */
561static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
562{
563 u8 rev;
564
565 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
566 if (rev >= 0x02) {
567 printk(KERN_WARNING "I/O APIC: AMD Errata #22 may be present. In the event of instability try\n");
568 printk(KERN_WARNING " : booting with the \"noapic\" option.\n");
569 }
570}
571DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic );
572
573static void __init quirk_ioapic_rmw(struct pci_dev *dev)
574{
575 if (dev->devfn == 0 && dev->bus->number == 0)
576 sis_apic_bug = 1;
577}
578DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw );
579
580int pci_msi_quirk;
581
582#define AMD8131_revA0 0x01
583#define AMD8131_revB0 0x11
584#define AMD8131_MISC 0x40
585#define AMD8131_NIOAMODE_BIT 0
586static void __init quirk_amd_8131_ioapic(struct pci_dev *dev)
587{
588 unsigned char revid, tmp;
589
6e325a62
MT		 590 if (dev->subordinate) {
591 printk(KERN_WARNING "PCI: MSI quirk detected. "
592 "PCI_BUS_FLAGS_NO_MSI set for subordinate bus.\n");
593 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
594 }
1da177e4
LT		 595
596 if (nr_ioapics == 0)
597 return;
598
599 pci_read_config_byte(dev, PCI_REVISION_ID, &revid);
600 if (revid == AMD8131_revA0 || revid == AMD8131_revB0) {
601 printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n");
602 pci_read_config_byte( dev, AMD8131_MISC, &tmp);
603 tmp &= ~(1 << AMD8131_NIOAMODE_BIT);
604 pci_write_config_byte( dev, AMD8131_MISC, tmp);
605 }
606}
5da594b1 607DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic);
1da177e4 608
1e062767
NS		 609static void __init quirk_svw_msi(struct pci_dev *dev)
610{
611 pci_msi_quirk = 1;
612 printk(KERN_WARNING "PCI: MSI quirk detected. pci_msi_quirk set.\n");
613}
614DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_svw_msi );
1da177e4
LT		 615#endif /* CONFIG_X86_IO_APIC */
616
617
1da177e4
LT		 618/*
619 * FIXME: it is questionable that quirk_via_acpi
620 * is needed. It shows up as an ISA bridge, and does not
621 * support the PCI_INTERRUPT_LINE register at all. Therefore
622 * it seems like setting the pci_dev's 'irq' to the
623 * value of the ACPI SCI interrupt is only done for convenience.
624 * -jgarzik
625 */
626static void __devinit quirk_via_acpi(struct pci_dev *d)
627{
628 /*
629 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
630 */
631 u8 irq;
632 pci_read_config_byte(d, 0x42, &irq);
633 irq &= 0xf;
634 if (irq && (irq != 2))
635 d->irq = irq;
636}
637DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi );
638DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi );
639
93cffffa
BH		 640/*
641 * Via 686A/B: The PCI_INTERRUPT_LINE register for the on-chip
642 * devices, USB0/1, AC97, MC97, and ACPI, has an unusual feature:
643 * when written, it makes an internal connection to the PIC.
644 * For these devices, this register is defined to be 4 bits wide.
645 * Normally this is fine. However for IO-APIC motherboards, or
646 * non-x86 architectures (yes Via exists on PPC among other places),
647 * we must mask the PCI_INTERRUPT_LINE value versus 0xf to get
648 * interrupts delivered properly.
a7b862f6
CW		 649 *
650 * Some of the on-chip devices are actually '586 devices' so they are
651 * listed here.
93cffffa
BH		 652 */
653static void quirk_via_irq(struct pci_dev *dev)
25be5e6c
LB		 654{
655 u8 irq, new_irq;
656
25be5e6c
LB		 657 new_irq = dev->irq & 0xf;
658 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
659 if (new_irq != irq) {
75cf7456 660 printk(KERN_INFO "PCI: VIA IRQ fixup for %s, from %d to %d\n",
25be5e6c
LB		 661 pci_name(dev), irq, new_irq);
662 udelay(15); /* unknown if delay really needed */
663 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
664 }
665}
a7b862f6
CW		 666DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_via_irq);
667DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, quirk_via_irq);
668DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, quirk_via_irq);
669DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_irq);
1ae4f9ba 670DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, quirk_via_irq);
75cf7456
CW		 671DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_irq);
672DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_irq);
673DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_5, quirk_via_irq);
25be5e6c 674
1da177e4
LT		 675/*
676 * VIA VT82C598 has its device ID settable and many BIOSes
677 * set it to the ID of VT82C597 for backward compatibility.
678 * We need to switch it off to be able to recognize the real
679 * type of the chip.
680 */
681static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
682{
683 pci_write_config_byte(dev, 0xfc, 0);
684 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
685}
686DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id );
687
709cf5ea
MG		 688#ifdef CONFIG_ACPI_SLEEP
689
690/*
691 * Some VIA systems boot with the abnormal status flag set. This can cause
692 * the BIOS to re-POST the system on resume rather than passing control
693 * back to the OS. Clear the flag on boot
694 */
695static void __devinit quirk_via_abnormal_poweroff(struct pci_dev *dev)
696{
697 u32 reg;
698
699 acpi_hw_register_read(ACPI_MTX_DO_NOT_LOCK, ACPI_REGISTER_PM1_STATUS,
700 &reg);
701
702 if (reg & 0x800) {
703 printk("Clearing abnormal poweroff flag\n");
704 acpi_hw_register_write(ACPI_MTX_DO_NOT_LOCK,
705 ACPI_REGISTER_PM1_STATUS,
706 (u16)0x800);
707 }
708}
709
710DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_abnormal_poweroff);
711DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_abnormal_poweroff);
712
713#endif
714
1da177e4
LT		 715/*
716 * CardBus controllers have a legacy base address that enables them
717 * to respond as i82365 pcmcia controllers. We don't want them to
718 * do this even if the Linux CardBus driver is not loaded, because
719 * the Linux i82365 driver does not (and should not) handle CardBus.
720 */
721static void __devinit quirk_cardbus_legacy(struct pci_dev *dev)
722{
723 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
724 return;
725 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
726}
727DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
728
729/*
730 * Following the PCI ordering rules is optional on the AMD762. I'm not
731 * sure what the designers were smoking but let's not inhale...
732 *
733 * To be fair to AMD, it follows the spec by default, its BIOS people
734 * who turn it off!
735 */
736static void __devinit quirk_amd_ordering(struct pci_dev *dev)
737{
738 u32 pcic;
739 pci_read_config_dword(dev, 0x4C, &pcic);
740 if ((pcic&6)!=6) {
741 pcic |= 6;
742 printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n");
743 pci_write_config_dword(dev, 0x4C, pcic);
744 pci_read_config_dword(dev, 0x84, &pcic);
745 pcic |= (1<<23); /* Required in this mode */
746 pci_write_config_dword(dev, 0x84, pcic);
747 }
748}
749DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering );
750
751/*
752 * DreamWorks provided workaround for Dunord I-3000 problem
753 *
754 * This card decodes and responds to addresses not apparently
755 * assigned to it. We force a larger allocation to ensure that
756 * nothing gets put too close to it.
757 */
758static void __devinit quirk_dunord ( struct pci_dev * dev )
759{
760 struct resource *r = &dev->resource [1];
761 r->start = 0;
762 r->end = 0xffffff;
763}
764DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord );
765
766/*
767 * i82380FB mobile docking controller: its PCI-to-PCI bridge
768 * is subtractive decoding (transparent), and does indicate this
769 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
770 * instead of 0x01.
771 */
772static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
773{
774 dev->transparent = 1;
775}
776DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge );
777DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge );
778
779/*
780 * Common misconfiguration of the MediaGX/Geode PCI master that will
781 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
782 * datasheets found at http://www.national.com/ds/GX for info on what
783 * these bits do. <christer@weinigel.se>
784 */
785static void __init quirk_mediagx_master(struct pci_dev *dev)
786{
787 u8 reg;
788 pci_read_config_byte(dev, 0x41, &reg);
789 if (reg & 2) {
790 reg &= ~2;
791 printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
792 pci_write_config_byte(dev, 0x41, reg);
793 }
794}
795DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master );
796
797/*
798 * As per PCI spec, ignore base address registers 0-3 of the IDE controllers
799 * running in Compatible mode (bits 0 and 2 in the ProgIf for primary and
800 * secondary channels respectively). If the device reports Compatible mode
801 * but does use BAR0-3 for address decoding, we assume that firmware has
802 * programmed these BARs with standard values (0x1f0,0x3f4 and 0x170,0x374).
803 * Exceptions (if they exist) must be handled in chip/architecture specific
804 * fixups.
805 *
806 * Note: for non x86 people. You may need an arch specific quirk to handle
807 * moving IDE devices to native mode as well. Some plug in card devices power
808 * up in compatible mode and assume the BIOS will adjust them.
809 *
810 * Q: should we load the 0x1f0,0x3f4 into the registers or zap them as
811 * we do now ? We don't want is pci_enable_device to come along
812 * and assign new resources. Both approaches work for that.
813 */
814static void __devinit quirk_ide_bases(struct pci_dev *dev)
815{
816 struct resource *res;
817 int first_bar = 2, last_bar = 0;
818
819 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
820 return;
821
822 res = &dev->resource[0];
823
824 /* primary channel: ProgIf bit 0, BAR0, BAR1 */
825 if (!(dev->class & 1) && (res[0].flags || res[1].flags)) {
826 res[0].start = res[0].end = res[0].flags = 0;
827 res[1].start = res[1].end = res[1].flags = 0;
828 first_bar = 0;
829 last_bar = 1;
830 }
831
832 /* secondary channel: ProgIf bit 2, BAR2, BAR3 */
833 if (!(dev->class & 4) && (res[2].flags || res[3].flags)) {
834 res[2].start = res[2].end = res[2].flags = 0;
835 res[3].start = res[3].end = res[3].flags = 0;
836 last_bar = 3;
837 }
838
839 if (!last_bar)
840 return;
841
842 printk(KERN_INFO "PCI: Ignoring BAR%d-%d of IDE controller %s\n",
843 first_bar, last_bar, pci_name(dev));
844}
845DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_ide_bases);
846
847/*
848 * Ensure C0 rev restreaming is off. This is normally done by
849 * the BIOS but in the odd case it is not the results are corruption
850 * hence the presence of a Linux check
851 */
852static void __init quirk_disable_pxb(struct pci_dev *pdev)
853{
854 u16 config;
855 u8 rev;
856
857 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
858 if (rev != 0x04) /* Only C0 requires this */
859 return;
860 pci_read_config_word(pdev, 0x40, &config);
861 if (config & (1<<6)) {
862 config &= ~(1<<6);
863 pci_write_config_word(pdev, 0x40, config);
864 printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n");
865 }
866}
867DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb );
868
1da177e4
LT		 869
870/*
871 * Serverworks CSB5 IDE does not fully support native mode
872 */
873static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
874{
875 u8 prog;
876 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
877 if (prog & 5) {
878 prog &= ~5;
879 pdev->class &= ~5;
880 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
881 /* need to re-assign BARs for compat mode */
882 quirk_ide_bases(pdev);
883 }
884}
885DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide );
886
887/*
888 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
889 */
890static void __init quirk_ide_samemode(struct pci_dev *pdev)
891{
892 u8 prog;
893
894 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
895
896 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
897 printk(KERN_INFO "PCI: IDE mode mismatch; forcing legacy mode\n");
898 prog &= ~5;
899 pdev->class &= ~5;
900 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
901 /* need to re-assign BARs for compat mode */
902 quirk_ide_bases(pdev);
903 }
904}
905DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
906
907/* This was originally an Alpha specific thing, but it really fits here.
908 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
909 */
910static void __init quirk_eisa_bridge(struct pci_dev *dev)
911{
912 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
913}
914DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge );
915
7daa0c4f
JG		 916/*
917 * On the MSI-K8T-Neo2Fir Board, the internal Soundcard is disabled
918 * when a PCI-Soundcard is added. The BIOS only gives Options
919 * "Disabled" and "AUTO". This Quirk Sets the corresponding
920 * Register-Value to enable the Soundcard.
bd91fde9
CW		 921 *
922 * FIXME: Presently this quirk will run on anything that has an 8237
923 * which isn't correct, we need to check DMI tables or something in
924 * order to make sure it only runs on the MSI-K8T-Neo2Fir. Because it
925 * runs everywhere at present we suppress the printk output in most
926 * irrelevant cases.
7daa0c4f
JG		 927 */
928static void __init k8t_sound_hostbridge(struct pci_dev *dev)
929{
930 unsigned char val;
931
7daa0c4f
JG		 932 pci_read_config_byte(dev, 0x50, &val);
933 if (val == 0x88 || val == 0xc8) {
bd91fde9
CW		 934 /* Assume it's probably a MSI-K8T-Neo2Fir */
935 printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, attempting to turn soundcard ON\n");
7daa0c4f
JG		 936 pci_write_config_byte(dev, 0x50, val & (~0x40));
937
938 /* Verify the Change for Status output */
939 pci_read_config_byte(dev, 0x50, &val);
940 if (val & 0x40)
bd91fde9 941 printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, soundcard still off\n");
7daa0c4f 942 else
bd91fde9 943 printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, soundcard on\n");
7daa0c4f 944 }
7daa0c4f
JG		 945}
946DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, k8t_sound_hostbridge);
947
ce007ea5 948#ifndef CONFIG_ACPI_SLEEP
1da177e4
LT		 949/*
950 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
951 * is not activated. The myth is that Asus said that they do not want the
952 * users to be irritated by just another PCI Device in the Win98 device
953 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
954 * package 2.7.0 for details)
955 *
956 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
957 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
958 * becomes necessary to do this tweak in two steps -- I've chosen the Host
959 * bridge as trigger.
ce007ea5
CDH		 960 *
961 * Actually, leaving it unhidden and not redoing the quirk over suspend2ram
962 * will cause thermal management to break down, and causing machine to
963 * overheat.
1da177e4 964 */
ce007ea5 965static int __initdata asus_hides_smbus;
1da177e4
LT		 966
967static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
968{
969 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
970 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
971 switch(dev->subsystem_device) {
a00db371 972 case 0x8025: /* P4B-LX */
1da177e4
LT		 973 case 0x8070: /* P4B */
974 case 0x8088: /* P4B533 */
975 case 0x1626: /* L3C notebook */
976 asus_hides_smbus = 1;
977 }
978 if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
979 switch(dev->subsystem_device) {
980 case 0x80b1: /* P4GE-V */
981 case 0x80b2: /* P4PE */
982 case 0x8093: /* P4B533-V */
983 asus_hides_smbus = 1;
984 }
985 if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
986 switch(dev->subsystem_device) {
987 case 0x8030: /* P4T533 */
988 asus_hides_smbus = 1;
989 }
990 if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
991 switch (dev->subsystem_device) {
992 case 0x8070: /* P4G8X Deluxe */
993 asus_hides_smbus = 1;
994 }
321311af
JD		 995 if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
996 switch (dev->subsystem_device) {
997 case 0x80c9: /* PU-DLS */
998 asus_hides_smbus = 1;
999 }
1da177e4
LT		 1000 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1001 switch (dev->subsystem_device) {
1002 case 0x1751: /* M2N notebook */
1003 case 0x1821: /* M5N notebook */
1004 asus_hides_smbus = 1;
1005 }
1006 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1007 switch (dev->subsystem_device) {
1008 case 0x184b: /* W1N notebook */
1009 case 0x186a: /* M6Ne notebook */
1010 asus_hides_smbus = 1;
1011 }
acc06632
RM		 1012 if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) {
1013 switch (dev->subsystem_device) {
1014 case 0x1882: /* M6V notebook */
2d1e1c75 1015 case 0x1977: /* A6VA notebook */
acc06632
RM		 1016 asus_hides_smbus = 1;
1017 }
1018 }
1da177e4
LT		 1019 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1020 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1021 switch(dev->subsystem_device) {
1022 case 0x088C: /* HP Compaq nc8000 */
1023 case 0x0890: /* HP Compaq nc6000 */
1024 asus_hides_smbus = 1;
1025 }
1026 if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1027 switch (dev->subsystem_device) {
1028 case 0x12bc: /* HP D330L */
e3b1bd57 1029 case 0x12bd: /* HP D530 */
1da177e4
LT		 1030 asus_hides_smbus = 1;
1031 }
3c0a654e 1032 if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) {
1033 switch (dev->subsystem_device) {
1034 case 0x099c: /* HP Compaq nx6110 */
1035 asus_hides_smbus = 1;
1036 }
1037 }
1da177e4
LT		 1038 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_TOSHIBA)) {
1039 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1040 switch(dev->subsystem_device) {
1041 case 0x0001: /* Toshiba Satellite A40 */
1042 asus_hides_smbus = 1;
1043 }
e96e2f14
DG		 1044 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1045 switch(dev->subsystem_device) {
1046 case 0x0001: /* Toshiba Tecra M2 */
1047 asus_hides_smbus = 1;
1048 }
1da177e4
LT		 1049 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1050 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1051 switch(dev->subsystem_device) {
1052 case 0xC00C: /* Samsung P35 notebook */
1053 asus_hides_smbus = 1;
1054 }
c87f883e
RIZ		 1055 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1056 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1057 switch(dev->subsystem_device) {
1058 case 0x0058: /* Compaq Evo N620c */
1059 asus_hides_smbus = 1;
1060 }
1da177e4
LT		 1061 }
1062}
1063DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge );
1064DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge );
1065DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge );
1066DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge );
1067DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge );
321311af 1068DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge );
1da177e4
LT		 1069DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge );
1070DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge );
acc06632 1071DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge );
1da177e4
LT		 1072
1073static void __init asus_hides_smbus_lpc(struct pci_dev *dev)
1074{
1075 u16 val;
1076
1077 if (likely(!asus_hides_smbus))
1078 return;
1079
1080 pci_read_config_word(dev, 0xF2, &val);
1081 if (val & 0x8) {
1082 pci_write_config_word(dev, 0xF2, val & (~0x8));
1083 pci_read_config_word(dev, 0xF2, &val);
1084 if (val & 0x8)
1085 printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1086 else
1087 printk(KERN_INFO "PCI: Enabled i801 SMBus device\n");
1088 }
1089}
1090DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc );
1091DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc );
321311af 1092DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc );
1da177e4
LT		 1093DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc );
1094DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc );
1095DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc );
1096
acc06632
RM		 1097static void __init asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1098{
1099 u32 val, rcba;
1100 void __iomem *base;
1101
1102 if (likely(!asus_hides_smbus))
1103 return;
1104 pci_read_config_dword(dev, 0xF0, &rcba);
1105 base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); /* use bits 31:14, 16 kB aligned */
1106 if (base == NULL) return;
1107 val=readl(base + 0x3418); /* read the Function Disable register, dword mode only */
1108 writel(val & 0xFFFFFFF7, base + 0x3418); /* enable the SMBus device */
1109 iounmap(base);
1110 printk(KERN_INFO "PCI: Enabled ICH6/i801 SMBus device\n");
1111}
1112DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6 );
1113
ce007ea5
CDH		 1114#endif
1115
1da177e4
LT		 1116/*
1117 * SiS 96x south bridge: BIOS typically hides SMBus device...
1118 */
1119static void __init quirk_sis_96x_smbus(struct pci_dev *dev)
1120{
1121 u8 val = 0;
1122 printk(KERN_INFO "Enabling SiS 96x SMBus.\n");
1123 pci_read_config_byte(dev, 0x77, &val);
1124 pci_write_config_byte(dev, 0x77, val & ~0x10);
1125 pci_read_config_byte(dev, 0x77, &val);
1126}
1127
1da177e4
LT		 1128/*
1129 * ... This is further complicated by the fact that some SiS96x south
1130 * bridges pretend to be 85C503/5513 instead. In that case see if we
1131 * spotted a compatible north bridge to make sure.
1132 * (pci_find_device doesn't work yet)
1133 *
1134 * We can also enable the sis96x bit in the discovery register..
1135 */
1136static int __devinitdata sis_96x_compatible = 0;
1137
1138#define SIS_DETECT_REGISTER 0x40
1139
1140static void __init quirk_sis_503(struct pci_dev *dev)
1141{
1142 u8 reg;
1143 u16 devid;
1144
1145 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1146 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1147 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1148 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1149 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1150 return;
1151 }
1152
1153 /* Make people aware that we changed the config.. */
1154 printk(KERN_WARNING "Uncovering SIS%x that hid as a SIS503 (compatible=%d)\n", devid, sis_96x_compatible);
1155
1156 /*
1157 * Ok, it now shows up as a 96x.. The 96x quirks are after
1158 * the 503 quirk in the quirk table, so they'll automatically
1159 * run and enable things like the SMBus device
1160 */
1161 dev->device = devid;
1162}
1163
1164static void __init quirk_sis_96x_compatible(struct pci_dev *dev)
1165{
1166 sis_96x_compatible = 1;
1167}
1168DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_645, quirk_sis_96x_compatible );
1169DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_646, quirk_sis_96x_compatible );
1170DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_648, quirk_sis_96x_compatible );
1171DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_650, quirk_sis_96x_compatible );
1172DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_651, quirk_sis_96x_compatible );
1173DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_735, quirk_sis_96x_compatible );
1174
1175DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 );
e5548e96
BJD		 1176/*
1177 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1178 * and MC97 modem controller are disabled when a second PCI soundcard is
1179 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1180 * -- bjd
1181 */
1182static void __init asus_hides_ac97_lpc(struct pci_dev *dev)
1183{
1184 u8 val;
1185 int asus_hides_ac97 = 0;
1186
1187 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1188 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1189 asus_hides_ac97 = 1;
1190 }
1191
1192 if (!asus_hides_ac97)
1193 return;
1194
1195 pci_read_config_byte(dev, 0x50, &val);
1196 if (val & 0xc0) {
1197 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1198 pci_read_config_byte(dev, 0x50, &val);
1199 if (val & 0xc0)
1200 printk(KERN_INFO "PCI: onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
1201 else
1202 printk(KERN_INFO "PCI: enabled onboard AC97/MC97 devices\n");
1203 }
1204}
1205DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc );
1206
1da177e4
LT		 1207
1208DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus );
1209DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus );
1210DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus );
1211DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus );
1212
77967052 1213#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
15e0c694
AC		 1214
1215/*
1216 * If we are using libata we can drive this chip properly but must
1217 * do this early on to make the additional device appear during
1218 * the PCI scanning.
1219 */
1220
1221static void __devinit quirk_jmicron_dualfn(struct pci_dev *pdev)
1222{
1223 u32 conf;
1224 u8 hdr;
1225
1226 /* Only poke fn 0 */
1227 if (PCI_FUNC(pdev->devfn))
1228 return;
1229
1230 switch(pdev->device) {
1231 case PCI_DEVICE_ID_JMICRON_JMB365:
1232 case PCI_DEVICE_ID_JMICRON_JMB366:
1233 /* Redirect IDE second PATA port to the right spot */
1234 pci_read_config_dword(pdev, 0x80, &conf);
1235 conf |= (1 << 24);
1236 /* Fall through */
1237 pci_write_config_dword(pdev, 0x80, conf);
1238 case PCI_DEVICE_ID_JMICRON_JMB361:
1239 case PCI_DEVICE_ID_JMICRON_JMB363:
1240 pci_read_config_dword(pdev, 0x40, &conf);
1241 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1242 /* Set the class codes correctly and then direct IDE 0 */
1243 conf &= ~0x000F0200; /* Clear bit 9 and 16-19 */
1244 conf |= 0x00C20002; /* Set bit 1, 17, 22, 23 */
1245 pci_write_config_dword(pdev, 0x40, conf);
1246
1247 /* Reconfigure so that the PCI scanner discovers the
1248 device is now multifunction */
1249
1250 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1251 pdev->hdr_type = hdr & 0x7f;
1252 pdev->multifunction = !!(hdr & 0x80);
1253
1254 break;
1255 }
1256}
1257
1258DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, quirk_jmicron_dualfn);
1259
1260#endif
1261
1da177e4
LT		 1262#ifdef CONFIG_X86_IO_APIC
1263static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1264{
1265 int i;
1266
1267 if ((pdev->class >> 8) != 0xff00)
1268 return;
1269
1270 /* the first BAR is the location of the IO APIC...we must
1271 * not touch this (and it's already covered by the fixmap), so
1272 * forcibly insert it into the resource tree */
1273 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1274 insert_resource(&iomem_resource, &pdev->resource[0]);
1275
1276 /* The next five BARs all seem to be rubbish, so just clean
1277 * them out */
1278 for (i=1; i < 6; i++) {
1279 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1280 }
1281
1282}
1283DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic );
1284#endif
1285
2bd0fa3b
JB		 1286enum ide_combined_type { COMBINED = 0, IDE = 1, LIBATA = 2 };
1287/* Defaults to combined */
1288static enum ide_combined_type combined_mode;
1289
1290static int __init combined_setup(char *str)
1291{
1292 if (!strncmp(str, "ide", 3))
1293 combined_mode = IDE;
1294 else if (!strncmp(str, "libata", 6))
1295 combined_mode = LIBATA;
1296 else /* "combined" or anything else defaults to old behavior */
1297 combined_mode = COMBINED;
1298
1299 return 1;
1300}
1301__setup("combined_mode=", combined_setup);
1302
77967052 1303#ifdef CONFIG_SATA_INTEL_COMBINED
1da177e4
LT		 1304static void __devinit quirk_intel_ide_combined(struct pci_dev *pdev)
1305{
1306 u8 prog, comb, tmp;
1307 int ich = 0;
1308
1309 /*
1310 * Narrow down to Intel SATA PCI devices.
1311 */
1312 switch (pdev->device) {
1313 /* PCI ids taken from drivers/scsi/ata_piix.c */
1314 case 0x24d1:
1315 case 0x24df:
1316 case 0x25a3:
1317 case 0x25b0:
1318 ich = 5;
1319 break;
1320 case 0x2651:
1321 case 0x2652:
1322 case 0x2653:
c368ca4e 1323 case 0x2680: /* ESB2 */
1da177e4
LT		 1324 ich = 6;
1325 break;
1326 case 0x27c0:
1327 case 0x27c4:
1328 ich = 7;
1329 break;
012b265f
JG		 1330 case 0x2828: /* ICH8M */
1331 ich = 8;
1332 break;
1da177e4
LT		 1333 default:
1334 /* we do not handle this PCI device */
1335 return;
1336 }
1337
1338 /*
1339 * Read combined mode register.
1340 */
1341 pci_read_config_byte(pdev, 0x90, &tmp); /* combined mode reg */
1342
1343 if (ich == 5) {
1344 tmp &= 0x6; /* interesting bits 2:1, PATA primary/secondary */
1345 if (tmp == 0x4) /* bits 10x */
1346 comb = (1 << 0); /* SATA port 0, PATA port 1 */
1347 else if (tmp == 0x6) /* bits 11x */
1348 comb = (1 << 2); /* PATA port 0, SATA port 1 */
1349 else
1350 return; /* not in combined mode */
1351 } else {
012b265f 1352 WARN_ON((ich != 6) && (ich != 7) && (ich != 8));
1da177e4
LT		 1353 tmp &= 0x3; /* interesting bits 1:0 */
1354 if (tmp & (1 << 0))
1355 comb = (1 << 2); /* PATA port 0, SATA port 1 */
1356 else if (tmp & (1 << 1))
1357 comb = (1 << 0); /* SATA port 0, PATA port 1 */
1358 else
1359 return; /* not in combined mode */
1360 }
1361
1362 /*
1363 * Read programming interface register.
1364 * (Tells us if it's legacy or native mode)
1365 */
1366 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1367
1368 /* if SATA port is in native mode, we're ok. */
1369 if (prog & comb)
1370 return;
1371
2bd0fa3b
JB		 1372 /* Don't reserve any so the IDE driver can get them (but only if
1373 * combined_mode=ide).
1374 */
1375 if (combined_mode == IDE)
1376 return;
1377
1378 /* Grab them both for libata if combined_mode=libata. */
1379 if (combined_mode == LIBATA) {
1380 request_region(0x1f0, 8, "libata"); /* port 0 */
1381 request_region(0x170, 8, "libata"); /* port 1 */
1382 return;
1383 }
1384
1da177e4
LT		 1385 /* SATA port is in legacy mode. Reserve port so that
1386 * IDE driver does not attempt to use it. If request_region
1387 * fails, it will be obvious at boot time, so we don't bother
1388 * checking return values.
1389 */
1390 if (comb == (1 << 0))
1391 request_region(0x1f0, 8, "libata"); /* port 0 */
1392 else
1393 request_region(0x170, 8, "libata"); /* port 1 */
1394}
1395DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_intel_ide_combined );
77967052 1396#endif /* CONFIG_SATA_INTEL_COMBINED */
1da177e4
LT		 1397
1398
1399int pcie_mch_quirk;
1400
1401static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1402{
1403 pcie_mch_quirk = 1;
1404}
1405DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch );
1406DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch );
1407DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch );
1408
4602b88d
KA		 1409
1410/*
1411 * It's possible for the MSI to get corrupted if shpc and acpi
1412 * are used together on certain PXH-based systems.
1413 */
1414static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1415{
1416 disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI),
1417 PCI_CAP_ID_MSI);
1418 dev->no_msi = 1;
1419
1420 printk(KERN_WARNING "PCI: PXH quirk detected, "
1421 "disabling MSI for SHPC device\n");
1422}
1423DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1424DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1425DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1426DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1427DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1428
ffadcc2f
KCA		 1429/*
1430 * Some Intel PCI Express chipsets have trouble with downstream
1431 * device power management.
1432 */
1433static void quirk_intel_pcie_pm(struct pci_dev * dev)
1434{
1435 pci_pm_d3_delay = 120;
1436 dev->no_d1d2 = 1;
1437}
1438
1439DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1440DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1441DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1442DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1443DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1444DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1445DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1446DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1447DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1448DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1449DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1450DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1451DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1452DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1453DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1454DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1455DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1456DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1457DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1458DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1459DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
4602b88d 1460
c408a379
KA		 1461/*
1462 * Fixup the cardbus bridges on the IBM Dock II docking station
1463 */
1464static void __devinit quirk_ibm_dock2_cardbus(struct pci_dev *dev)
1465{
1466 u32 val;
1467
1468 /*
1469 * tie the 2 interrupt pins to INTA, and configure the
1470 * multifunction routing register to handle this.
1471 */
1472 if ((dev->subsystem_vendor == PCI_VENDOR_ID_IBM) &&
1473 (dev->subsystem_device == 0x0148)) {
1474 printk(KERN_INFO "PCI: Found IBM Dock II Cardbus Bridge "
1475 "applying quirk\n");
1476 pci_read_config_dword(dev, 0x8c, &val);
1477 val = ((val & 0xffffff00) | 0x1002);
1478 pci_write_config_dword(dev, 0x8c, val);
1479 pci_read_config_dword(dev, 0x80, &val);
1480 val = ((val & 0x00ffff00) | 0x2864c077);
1481 pci_write_config_dword(dev, 0x80, val);
1482 }
1483}
1484
1485DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1420,
1486 quirk_ibm_dock2_cardbus);
1487
1da177e4
LT		 1488static void __devinit quirk_netmos(struct pci_dev *dev)
1489{
1490 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1491 unsigned int num_serial = dev->subsystem_device & 0xf;
1492
1493 /*
1494 * These Netmos parts are multiport serial devices with optional
1495 * parallel ports. Even when parallel ports are present, they
1496 * are identified as class SERIAL, which means the serial driver
1497 * will claim them. To prevent this, mark them as class OTHER.
1498 * These combo devices should be claimed by parport_serial.
1499 *
1500 * The subdevice ID is of the form 0x00PS, where <P> is the number
1501 * of parallel ports and <S> is the number of serial ports.
1502 */
1503 switch (dev->device) {
1504 case PCI_DEVICE_ID_NETMOS_9735:
1505 case PCI_DEVICE_ID_NETMOS_9745:
1506 case PCI_DEVICE_ID_NETMOS_9835:
1507 case PCI_DEVICE_ID_NETMOS_9845:
1508 case PCI_DEVICE_ID_NETMOS_9855:
1509 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1510 num_parallel) {
1511 printk(KERN_INFO "PCI: Netmos %04x (%u parallel, "
1512 "%u serial); changing class SERIAL to OTHER "
1513 "(use parport_serial)\n",
1514 dev->device, num_parallel, num_serial);
1515 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1516 (dev->class & 0xff);
1517 }
1518 }
1519}
1520DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1521
16a74744
BH		 1522static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1523{
1524 u16 command;
1525 u32 bar;
1526 u8 __iomem *csr;
1527 u8 cmd_hi;
1528
1529 switch (dev->device) {
1530 /* PCI IDs taken from drivers/net/e100.c */
1531 case 0x1029:
1532 case 0x1030 ... 0x1034:
1533 case 0x1038 ... 0x103E:
1534 case 0x1050 ... 0x1057:
1535 case 0x1059:
1536 case 0x1064 ... 0x106B:
1537 case 0x1091 ... 0x1095:
1538 case 0x1209:
1539 case 0x1229:
1540 case 0x2449:
1541 case 0x2459:
1542 case 0x245D:
1543 case 0x27DC:
1544 break;
1545 default:
1546 return;
1547 }
1548
1549 /*
1550 * Some firmware hands off the e100 with interrupts enabled,
1551 * which can cause a flood of interrupts if packets are
1552 * received before the driver attaches to the device. So
1553 * disable all e100 interrupts here. The driver will
1554 * re-enable them when it's ready.
1555 */
1556 pci_read_config_word(dev, PCI_COMMAND, &command);
1557 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar);
1558
1559 if (!(command & PCI_COMMAND_MEMORY) || !bar)
1560 return;
1561
1562 csr = ioremap(bar, 8);
1563 if (!csr) {
1564 printk(KERN_WARNING "PCI: Can't map %s e100 registers\n",
1565 pci_name(dev));
1566 return;
1567 }
1568
1569 cmd_hi = readb(csr + 3);
1570 if (cmd_hi == 0) {
1571 printk(KERN_WARNING "PCI: Firmware left %s e100 interrupts "
1572 "enabled, disabling\n", pci_name(dev));
1573 writeb(1, csr + 3);
1574 }
1575
1576 iounmap(csr);
1577}
1578DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt);
a5312e28
IK		 1579
1580static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1581{
1582 /* rev 1 ncr53c810 chips don't set the class at all which means
1583 * they don't get their resources remapped. Fix that here.
1584 */
1585
1586 if (dev->class == PCI_CLASS_NOT_DEFINED) {
1587 printk(KERN_INFO "NCR 53c810 rev 1 detected, setting PCI class.\n");
1588 dev->class = PCI_CLASS_STORAGE_SCSI;
1589 }
1590}
1591DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1592
1593
1da177e4
LT		 1594static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end)
1595{
1596 while (f < end) {
1597 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
1598 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
1599 pr_debug("PCI: Calling quirk %p for %s\n", f->hook, pci_name(dev));
1600 f->hook(dev);
1601 }
1602 f++;
1603 }
1604}
1605
1606extern struct pci_fixup __start_pci_fixups_early[];
1607extern struct pci_fixup __end_pci_fixups_early[];
1608extern struct pci_fixup __start_pci_fixups_header[];
1609extern struct pci_fixup __end_pci_fixups_header[];
1610extern struct pci_fixup __start_pci_fixups_final[];
1611extern struct pci_fixup __end_pci_fixups_final[];
1612extern struct pci_fixup __start_pci_fixups_enable[];
1613extern struct pci_fixup __end_pci_fixups_enable[];
1614
1615
1616void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
1617{
1618 struct pci_fixup *start, *end;
1619
1620 switch(pass) {
1621 case pci_fixup_early:
1622 start = __start_pci_fixups_early;
1623 end = __end_pci_fixups_early;
1624 break;
1625
1626 case pci_fixup_header:
1627 start = __start_pci_fixups_header;
1628 end = __end_pci_fixups_header;
1629 break;
1630
1631 case pci_fixup_final:
1632 start = __start_pci_fixups_final;
1633 end = __end_pci_fixups_final;
1634 break;
1635
1636 case pci_fixup_enable:
1637 start = __start_pci_fixups_enable;
1638 end = __end_pci_fixups_enable;
1639 break;
1640
1641 default:
1642 /* stupid compiler warning, you would think with an enum... */
1643 return;
1644 }
1645 pci_do_fixups(dev, start, end);
1646}
1647
9d265124
DY		 1648/* Enable 1k I/O space granularity on the Intel P64H2 */
1649static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1650{
1651 u16 en1k;
1652 u8 io_base_lo, io_limit_lo;
1653 unsigned long base, limit;
1654 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1655
1656 pci_read_config_word(dev, 0x40, &en1k);
1657
1658 if (en1k & 0x200) {
1659 printk(KERN_INFO "PCI: Enable I/O Space to 1 KB Granularity\n");
1660
1661 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
1662 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
1663 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1664 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1665
1666 if (base <= limit) {
1667 res->start = base;
1668 res->end = limit + 0x3ff;
1669 }
1670 }
1671}
1672DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1673
cf34a8e0
BG		 1674/* Under some circumstances, AER is not linked with extended capabilities.
1675 * Force it to be linked by setting the corresponding control bit in the
1676 * config space.
1677 */
1678static void __devinit quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
1679{
1680 uint8_t b;
1681 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1682 if (!(b & 0x20)) {
1683 pci_write_config_byte(dev, 0xf41, b | 0x20);
1684 printk(KERN_INFO
1685 "PCI: Linking AER extended capability on %s\n",
1686 pci_name(dev));
1687 }
1688 }
1689}
1690DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1691 quirk_nvidia_ck804_pcie_aer_ext_cap);
1692
1da177e4
LT		 1693EXPORT_SYMBOL(pcie_mch_quirk);
1694#ifdef CONFIG_HOTPLUG
1695EXPORT_SYMBOL(pci_fixup_device);
1696#endif
kernel source for telekom puls (alcatel/mediatek)