projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'x86/ptrace' into x86/tsc
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / pci / quirks.c
CommitLineData
1da177e4
LT		 1/*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
7586269c
DB		 10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 *
1da177e4
LT		 13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
16 */
17
1da177e4
LT		 18#include <linux/types.h>
19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/init.h>
22#include <linux/delay.h>
25be5e6c 23#include <linux/acpi.h>
9f23ed3b 24#include <linux/kallsyms.h>
75e07fc3 25#include <linux/dmi.h>
bc56b9e0 26#include "pci.h"
1da177e4 27
3d137310
TP		 28int isa_dma_bridge_buggy;
29EXPORT_SYMBOL(isa_dma_bridge_buggy);
30int pci_pci_problems;
31EXPORT_SYMBOL(pci_pci_problems);
32int pcie_mch_quirk;
33EXPORT_SYMBOL(pcie_mch_quirk);
34
35#ifdef CONFIG_PCI_QUIRKS
bd8481e1
DT		 36/* The Mellanox Tavor device gives false positive parity errors
37 * Mark this device with a broken_parity_status, to allow
38 * PCI scanning code to "skip" this now blacklisted device.
39 */
40static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
41{
42 dev->broken_parity_status = 1; /* This device gives false positives */
43}
44DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
45DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
46
1da177e4
LT		 47/* Deal with broken BIOS'es that neglect to enable passive release,
48 which can cause problems in combination with the 82441FX/PPro MTRRs */
1597cacb 49static void quirk_passive_release(struct pci_dev *dev)
1da177e4
LT		 50{
51 struct pci_dev *d = NULL;
52 unsigned char dlc;
53
54 /* We have to make sure a particular bit is set in the PIIX3
55 ISA bridge, so we have to go out and find it. */
56 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
57 pci_read_config_byte(d, 0x82, &dlc);
58 if (!(dlc & 1<<1)) {
f0fda801 59 dev_err(&d->dev, "PIIX3: Enabling Passive Release\n");
1da177e4
LT		 60 dlc |= 1<<1;
61 pci_write_config_byte(d, 0x82, dlc);
62 }
63 }
64}
652c538e
AM		 65DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
66DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
1da177e4
LT		 67
68/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
69 but VIA don't answer queries. If you happen to have good contacts at VIA
70 ask them for me please -- Alan
71
72 This appears to be BIOS not version dependent. So presumably there is a
73 chipset level fix */
1da177e4
LT		 74
75static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
76{
77 if (!isa_dma_bridge_buggy) {
78 isa_dma_bridge_buggy=1;
f0fda801 79 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
1da177e4
LT		 80 }
81}
82 /*
83 * Its not totally clear which chipsets are the problematic ones
84 * We know 82C586 and 82C596 variants are affected.
85 */
652c538e
AM		 86DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
87DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
88DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
89DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
90DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
91DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
92DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
1da177e4 93
1da177e4
LT		 94/*
95 * Chipsets where PCI->PCI transfers vanish or hang
96 */
97static void __devinit quirk_nopcipci(struct pci_dev *dev)
98{
99 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
f0fda801 100 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
1da177e4
LT		 101 pci_pci_problems |= PCIPCI_FAIL;
102 }
103}
652c538e
AM		 104DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
105DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
236561e5
AC		 106
107static void __devinit quirk_nopciamd(struct pci_dev *dev)
108{
109 u8 rev;
110 pci_read_config_byte(dev, 0x08, &rev);
111 if (rev == 0x13) {
112 /* Erratum 24 */
f0fda801 113 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
236561e5
AC		 114 pci_pci_problems |= PCIAGP_FAIL;
115 }
116}
652c538e 117DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
1da177e4
LT		 118
119/*
120 * Triton requires workarounds to be used by the drivers
121 */
122static void __devinit quirk_triton(struct pci_dev *dev)
123{
124 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
f0fda801 125 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 126 pci_pci_problems |= PCIPCI_TRITON;
127 }
128}
652c538e
AM		 129DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
130DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
131DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
132DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
1da177e4
LT		 133
134/*
135 * VIA Apollo KT133 needs PCI latency patch
136 * Made according to a windows driver based patch by George E. Breese
137 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
138 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
139 * the info on which Mr Breese based his work.
140 *
141 * Updated based on further information from the site and also on
142 * information provided by VIA
143 */
1597cacb 144static void quirk_vialatency(struct pci_dev *dev)
1da177e4
LT		 145{
146 struct pci_dev *p;
1da177e4
LT		 147 u8 busarb;
148 /* Ok we have a potential problem chipset here. Now see if we have
149 a buggy southbridge */
150
151 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
152 if (p!=NULL) {
1da177e4
LT		 153 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
154 /* Check for buggy part revisions */
2b1afa87 155 if (p->revision < 0x40 || p->revision > 0x42)
1da177e4
LT		 156 goto exit;
157 } else {
158 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
159 if (p==NULL) /* No problem parts */
160 goto exit;
1da177e4 161 /* Check for buggy part revisions */
2b1afa87 162 if (p->revision < 0x10 || p->revision > 0x12)
1da177e4
LT		 163 goto exit;
164 }
165
166 /*
167 * Ok we have the problem. Now set the PCI master grant to
168 * occur every master grant. The apparent bug is that under high
169 * PCI load (quite common in Linux of course) you can get data
170 * loss when the CPU is held off the bus for 3 bus master requests
171 * This happens to include the IDE controllers....
172 *
173 * VIA only apply this fix when an SB Live! is present but under
174 * both Linux and Windows this isnt enough, and we have seen
175 * corruption without SB Live! but with things like 3 UDMA IDE
176 * controllers. So we ignore that bit of the VIA recommendation..
177 */
178
179 pci_read_config_byte(dev, 0x76, &busarb);
180 /* Set bit 4 and bi 5 of byte 76 to 0x01
181 "Master priority rotation on every PCI master grant */
182 busarb &= ~(1<<5);
183 busarb |= (1<<4);
184 pci_write_config_byte(dev, 0x76, busarb);
f0fda801 185 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
1da177e4
LT		 186exit:
187 pci_dev_put(p);
188}
652c538e
AM		 189DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
190DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
191DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
1597cacb 192/* Must restore this on a resume from RAM */
652c538e
AM		 193DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
194DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
195DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
1da177e4
LT		 196
197/*
198 * VIA Apollo VP3 needs ETBF on BT848/878
199 */
200static void __devinit quirk_viaetbf(struct pci_dev *dev)
201{
202 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
f0fda801 203 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 204 pci_pci_problems |= PCIPCI_VIAETBF;
205 }
206}
652c538e 207DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
1da177e4
LT		 208
209static void __devinit quirk_vsfx(struct pci_dev *dev)
210{
211 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
f0fda801 212 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 213 pci_pci_problems |= PCIPCI_VSFX;
214 }
215}
652c538e 216DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
1da177e4
LT		 217
218/*
219 * Ali Magik requires workarounds to be used by the drivers
220 * that DMA to AGP space. Latency must be set to 0xA and triton
221 * workaround applied too
222 * [Info kindly provided by ALi]
223 */
224static void __init quirk_alimagik(struct pci_dev *dev)
225{
226 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
f0fda801 227 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 228 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
229 }
230}
652c538e
AM		 231DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
232DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
1da177e4
LT		 233
234/*
235 * Natoma has some interesting boundary conditions with Zoran stuff
236 * at least
237 */
238static void __devinit quirk_natoma(struct pci_dev *dev)
239{
240 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
f0fda801 241 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 242 pci_pci_problems |= PCIPCI_NATOMA;
243 }
244}
652c538e
AM		 245DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
246DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
247DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
248DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
249DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
250DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
1da177e4
LT		 251
252/*
253 * This chip can cause PCI parity errors if config register 0xA0 is read
254 * while DMAs are occurring.
255 */
256static void __devinit quirk_citrine(struct pci_dev *dev)
257{
258 dev->cfg_size = 0xA0;
259}
652c538e 260DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
1da177e4
LT		 261
262/*
263 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
264 * If it's needed, re-allocate the region.
265 */
266static void __devinit quirk_s3_64M(struct pci_dev *dev)
267{
268 struct resource *r = &dev->resource[0];
269
270 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
271 r->start = 0;
272 r->end = 0x3ffffff;
273 }
274}
652c538e
AM		 275DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
276DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
1da177e4 277
6693e74a
LT		 278static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
279 unsigned size, int nr, const char *name)
1da177e4
LT		 280{
281 region &= ~(size-1);
282 if (region) {
085ae41f 283 struct pci_bus_region bus_region;
1da177e4
LT		 284 struct resource *res = dev->resource + nr;
285
286 res->name = pci_name(dev);
287 res->start = region;
288 res->end = region + size - 1;
289 res->flags = IORESOURCE_IO;
085ae41f
DM		 290
291 /* Convert from PCI bus to resource space. */
292 bus_region.start = res->start;
293 bus_region.end = res->end;
294 pcibios_bus_to_resource(dev, res, &bus_region);
295
1da177e4 296 pci_claim_resource(dev, nr);
f0fda801 297 dev_info(&dev->dev, "quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name);
1da177e4
LT		 298 }
299}
300
301/*
302 * ATI Northbridge setups MCE the processor if you even
303 * read somewhere between 0x3b0->0x3bb or read 0x3d3
304 */
305static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
306{
f0fda801 307 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
1da177e4
LT		 308 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
309 request_region(0x3b0, 0x0C, "RadeonIGP");
310 request_region(0x3d3, 0x01, "RadeonIGP");
311}
652c538e 312DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
1da177e4
LT		 313
314/*
315 * Let's make the southbridge information explicit instead
316 * of having to worry about people probing the ACPI areas,
317 * for example.. (Yes, it happens, and if you read the wrong
318 * ACPI register it will put the machine to sleep with no
319 * way of waking it up again. Bummer).
320 *
321 * ALI M7101: Two IO regions pointed to by words at
322 * 0xE0 (64 bytes of ACPI registers)
323 * 0xE2 (32 bytes of SMB registers)
324 */
325static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
326{
327 u16 region;
328
329 pci_read_config_word(dev, 0xE0, &region);
6693e74a 330 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
1da177e4 331 pci_read_config_word(dev, 0xE2, &region);
6693e74a 332 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
1da177e4 333}
652c538e 334DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
1da177e4 335
6693e74a
LT		 336static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
337{
338 u32 devres;
339 u32 mask, size, base;
340
341 pci_read_config_dword(dev, port, &devres);
342 if ((devres & enable) != enable)
343 return;
344 mask = (devres >> 16) & 15;
345 base = devres & 0xffff;
346 size = 16;
347 for (;;) {
348 unsigned bit = size >> 1;
349 if ((bit & mask) == bit)
350 break;
351 size = bit;
352 }
353 /*
354 * For now we only print it out. Eventually we'll want to
355 * reserve it (at least if it's in the 0x1000+ range), but
356 * let's get enough confirmation reports first.
357 */
358 base &= -size;
f0fda801 359 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
6693e74a
LT		 360}
361
362static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
363{
364 u32 devres;
365 u32 mask, size, base;
366
367 pci_read_config_dword(dev, port, &devres);
368 if ((devres & enable) != enable)
369 return;
370 base = devres & 0xffff0000;
371 mask = (devres & 0x3f) << 16;
372 size = 128 << 16;
373 for (;;) {
374 unsigned bit = size >> 1;
375 if ((bit & mask) == bit)
376 break;
377 size = bit;
378 }
379 /*
380 * For now we only print it out. Eventually we'll want to
381 * reserve it, but let's get enough confirmation reports first.
382 */
383 base &= -size;
f0fda801 384 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
6693e74a
LT		 385}
386
1da177e4
LT		 387/*
388 * PIIX4 ACPI: Two IO regions pointed to by longwords at
389 * 0x40 (64 bytes of ACPI registers)
08db2a70 390 * 0x90 (16 bytes of SMB registers)
6693e74a 391 * and a few strange programmable PIIX4 device resources.
1da177e4
LT		 392 */
393static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
394{
6693e74a 395 u32 region, res_a;
1da177e4
LT		 396
397 pci_read_config_dword(dev, 0x40, &region);
6693e74a 398 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
1da177e4 399 pci_read_config_dword(dev, 0x90, &region);
08db2a70 400 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
6693e74a
LT		 401
402 /* Device resource A has enables for some of the other ones */
403 pci_read_config_dword(dev, 0x5c, &res_a);
404
405 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
406 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
407
408 /* Device resource D is just bitfields for static resources */
409
410 /* Device 12 enabled? */
411 if (res_a & (1 << 29)) {
412 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
413 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
414 }
415 /* Device 13 enabled? */
416 if (res_a & (1 << 30)) {
417 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
418 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
419 }
420 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
421 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
1da177e4 422}
652c538e
AM		 423DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
424DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
1da177e4
LT		 425
426/*
427 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
428 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
429 * 0x58 (64 bytes of GPIO I/O space)
430 */
431static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
432{
433 u32 region;
434
435 pci_read_config_dword(dev, 0x40, &region);
6693e74a 436 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO");
1da177e4
LT		 437
438 pci_read_config_dword(dev, 0x58, &region);
6693e74a 439 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO");
1da177e4 440}
652c538e
AM		 441DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
442DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
443DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
444DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
445DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
446DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
447DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
448DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
449DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
450DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
1da177e4 451
2cea752f
RM		 452static void __devinit quirk_ich6_lpc_acpi(struct pci_dev *dev)
453{
454 u32 region;
455
456 pci_read_config_dword(dev, 0x40, &region);
457 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO");
458
459 pci_read_config_dword(dev, 0x48, &region);
460 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
461}
652c538e
AM		 462DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc_acpi);
463DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc_acpi);
464DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich6_lpc_acpi);
465DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich6_lpc_acpi);
466DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich6_lpc_acpi);
467DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich6_lpc_acpi);
468DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich6_lpc_acpi);
469DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich6_lpc_acpi);
470DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich6_lpc_acpi);
471DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich6_lpc_acpi);
472DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich6_lpc_acpi);
473DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich6_lpc_acpi);
474DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich6_lpc_acpi);
475DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich6_lpc_acpi);
2cea752f 476
1da177e4
LT		 477/*
478 * VIA ACPI: One IO region pointed to by longword at
479 * 0x48 or 0x20 (256 bytes of ACPI registers)
480 */
481static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
482{
1da177e4
LT		 483 u32 region;
484
651472fb 485 if (dev->revision & 0x10) {
1da177e4
LT		 486 pci_read_config_dword(dev, 0x48, &region);
487 region &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 488 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
1da177e4
LT		 489 }
490}
652c538e 491DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
1da177e4
LT		 492
493/*
494 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
495 * 0x48 (256 bytes of ACPI registers)
496 * 0x70 (128 bytes of hardware monitoring register)
497 * 0x90 (16 bytes of SMB registers)
498 */
499static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
500{
501 u16 hm;
502 u32 smb;
503
504 quirk_vt82c586_acpi(dev);
505
506 pci_read_config_word(dev, 0x70, &hm);
507 hm &= PCI_BASE_ADDRESS_IO_MASK;
02f313b2 508 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
1da177e4
LT		 509
510 pci_read_config_dword(dev, 0x90, &smb);
511 smb &= PCI_BASE_ADDRESS_IO_MASK;
02f313b2 512 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
1da177e4 513}
652c538e 514DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
1da177e4 515
6d85f29b
IK		 516/*
517 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
518 * 0x88 (128 bytes of power management registers)
519 * 0xd0 (16 bytes of SMB registers)
520 */
521static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
522{
523 u16 pm, smb;
524
525 pci_read_config_word(dev, 0x88, &pm);
526 pm &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 527 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
6d85f29b
IK		 528
529 pci_read_config_word(dev, 0xd0, &smb);
530 smb &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 531 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
6d85f29b
IK		 532}
533DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
534
1da177e4
LT		 535
536#ifdef CONFIG_X86_IO_APIC
537
538#include <asm/io_apic.h>
539
540/*
541 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
542 * devices to the external APIC.
543 *
544 * TODO: When we have device-specific interrupt routers,
545 * this code will go away from quirks.
546 */
1597cacb 547static void quirk_via_ioapic(struct pci_dev *dev)
1da177e4
LT		 548{
549 u8 tmp;
550
551 if (nr_ioapics < 1)
552 tmp = 0; /* nothing routed to external APIC */
553 else
554 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
555
f0fda801 556 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
1da177e4
LT		 557 tmp == 0 ? "Disa" : "Ena");
558
559 /* Offset 0x58: External APIC IRQ output control */
560 pci_write_config_byte (dev, 0x58, tmp);
561}
652c538e 562DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
e1a2a51e 563DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
1da177e4 564
a1740913
KW		 565/*
566 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
567 * This leads to doubled level interrupt rates.
568 * Set this bit to get rid of cycle wastage.
569 * Otherwise uncritical.
570 */
1597cacb 571static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
a1740913
KW		 572{
573 u8 misc_control2;
574#define BYPASS_APIC_DEASSERT 8
575
576 pci_read_config_byte(dev, 0x5B, &misc_control2);
577 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
f0fda801 578 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
a1740913
KW		 579 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
580 }
581}
582DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
e1a2a51e 583DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
a1740913 584
1da177e4
LT		 585/*
586 * The AMD io apic can hang the box when an apic irq is masked.
587 * We check all revs >= B0 (yet not in the pre production!) as the bug
588 * is currently marked NoFix
589 *
590 * We have multiple reports of hangs with this chipset that went away with
236561e5 591 * noapic specified. For the moment we assume it's the erratum. We may be wrong
1da177e4
LT		 592 * of course. However the advice is demonstrably good even if so..
593 */
594static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
595{
44c10138 596 if (dev->revision >= 0x02) {
f0fda801 597 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
598 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
1da177e4
LT		 599 }
600}
652c538e 601DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
1da177e4
LT		 602
603static void __init quirk_ioapic_rmw(struct pci_dev *dev)
604{
605 if (dev->devfn == 0 && dev->bus->number == 0)
606 sis_apic_bug = 1;
607}
652c538e 608DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
1da177e4 609
1da177e4
LT		 610#define AMD8131_revA0 0x01
611#define AMD8131_revB0 0x11
612#define AMD8131_MISC 0x40
613#define AMD8131_NIOAMODE_BIT 0
1597cacb 614static void quirk_amd_8131_ioapic(struct pci_dev *dev)
1da177e4 615{
44c10138 616 unsigned char tmp;
1da177e4 617
1da177e4
LT		 618 if (nr_ioapics == 0)
619 return;
620
44c10138 621 if (dev->revision == AMD8131_revA0 || dev->revision == AMD8131_revB0) {
f0fda801 622 dev_info(&dev->dev, "Fixing up AMD8131 IOAPIC mode\n");
1da177e4
LT		 623 pci_read_config_byte( dev, AMD8131_MISC, &tmp);
624 tmp &= ~(1 << AMD8131_NIOAMODE_BIT);
625 pci_write_config_byte( dev, AMD8131_MISC, tmp);
626 }
627}
5da594b1 628DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic);
e1a2a51e 629DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic);
1da177e4
LT		 630#endif /* CONFIG_X86_IO_APIC */
631
d556ad4b
PO		 632/*
633 * Some settings of MMRBC can lead to data corruption so block changes.
634 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
635 */
636static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev)
637{
aa288d4d 638 if (dev->subordinate && dev->revision <= 0x12) {
f0fda801 639 dev_info(&dev->dev, "AMD8131 rev %x detected; "
640 "disabling PCI-X MMRBC\n", dev->revision);
d556ad4b
PO		 641 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
642 }
643}
644DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
1da177e4 645
1da177e4
LT		 646/*
647 * FIXME: it is questionable that quirk_via_acpi
648 * is needed. It shows up as an ISA bridge, and does not
649 * support the PCI_INTERRUPT_LINE register at all. Therefore
650 * it seems like setting the pci_dev's 'irq' to the
651 * value of the ACPI SCI interrupt is only done for convenience.
652 * -jgarzik
653 */
654static void __devinit quirk_via_acpi(struct pci_dev *d)
655{
656 /*
657 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
658 */
659 u8 irq;
660 pci_read_config_byte(d, 0x42, &irq);
661 irq &= 0xf;
662 if (irq && (irq != 2))
663 d->irq = irq;
664}
652c538e
AM		 665DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
666DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
1da177e4 667
09d6029f
DD		 668
669/*
1597cacb 670 * VIA bridges which have VLink
09d6029f 671 */
1597cacb 672
c06bb5d4
JD		 673static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
674
675static void quirk_via_bridge(struct pci_dev *dev)
676{
677 /* See what bridge we have and find the device ranges */
678 switch (dev->device) {
679 case PCI_DEVICE_ID_VIA_82C686:
cb7468ef
JD		 680 /* The VT82C686 is special, it attaches to PCI and can have
681 any device number. All its subdevices are functions of
682 that single device. */
683 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
684 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
c06bb5d4
JD		 685 break;
686 case PCI_DEVICE_ID_VIA_8237:
687 case PCI_DEVICE_ID_VIA_8237A:
688 via_vlink_dev_lo = 15;
689 break;
690 case PCI_DEVICE_ID_VIA_8235:
691 via_vlink_dev_lo = 16;
692 break;
693 case PCI_DEVICE_ID_VIA_8231:
694 case PCI_DEVICE_ID_VIA_8233_0:
695 case PCI_DEVICE_ID_VIA_8233A:
696 case PCI_DEVICE_ID_VIA_8233C_0:
697 via_vlink_dev_lo = 17;
698 break;
699 }
700}
701DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
702DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
703DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
704DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
705DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
706DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
707DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
708DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
09d6029f 709
1597cacb
AC		 710/**
711 * quirk_via_vlink - VIA VLink IRQ number update
712 * @dev: PCI device
713 *
714 * If the device we are dealing with is on a PIC IRQ we need to
715 * ensure that the IRQ line register which usually is not relevant
716 * for PCI cards, is actually written so that interrupts get sent
c06bb5d4
JD		 717 * to the right place.
718 * We only do this on systems where a VIA south bridge was detected,
719 * and only for VIA devices on the motherboard (see quirk_via_bridge
720 * above).
1597cacb
AC		 721 */
722
723static void quirk_via_vlink(struct pci_dev *dev)
25be5e6c
LB		 724{
725 u8 irq, new_irq;
726
c06bb5d4
JD		 727 /* Check if we have VLink at all */
728 if (via_vlink_dev_lo == -1)
09d6029f
DD		 729 return;
730
731 new_irq = dev->irq;
732
733 /* Don't quirk interrupts outside the legacy IRQ range */
734 if (!new_irq || new_irq > 15)
735 return;
736
1597cacb 737 /* Internal device ? */
c06bb5d4
JD		 738 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
739 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
1597cacb
AC		 740 return;
741
742 /* This is an internal VLink device on a PIC interrupt. The BIOS
743 ought to have set this but may not have, so we redo it */
744
25be5e6c
LB		 745 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
746 if (new_irq != irq) {
f0fda801 747 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
748 irq, new_irq);
25be5e6c
LB		 749 udelay(15); /* unknown if delay really needed */
750 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
751 }
752}
1597cacb 753DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
25be5e6c 754
1da177e4
LT		 755/*
756 * VIA VT82C598 has its device ID settable and many BIOSes
757 * set it to the ID of VT82C597 for backward compatibility.
758 * We need to switch it off to be able to recognize the real
759 * type of the chip.
760 */
761static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
762{
763 pci_write_config_byte(dev, 0xfc, 0);
764 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
765}
652c538e 766DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
1da177e4
LT		 767
768/*
769 * CardBus controllers have a legacy base address that enables them
770 * to respond as i82365 pcmcia controllers. We don't want them to
771 * do this even if the Linux CardBus driver is not loaded, because
772 * the Linux i82365 driver does not (and should not) handle CardBus.
773 */
1597cacb 774static void quirk_cardbus_legacy(struct pci_dev *dev)
1da177e4
LT		 775{
776 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
777 return;
778 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
779}
780DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
e1a2a51e 781DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
1da177e4
LT		 782
783/*
784 * Following the PCI ordering rules is optional on the AMD762. I'm not
785 * sure what the designers were smoking but let's not inhale...
786 *
787 * To be fair to AMD, it follows the spec by default, its BIOS people
788 * who turn it off!
789 */
1597cacb 790static void quirk_amd_ordering(struct pci_dev *dev)
1da177e4
LT		 791{
792 u32 pcic;
793 pci_read_config_dword(dev, 0x4C, &pcic);
794 if ((pcic&6)!=6) {
795 pcic |= 6;
f0fda801 796 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1da177e4
LT		 797 pci_write_config_dword(dev, 0x4C, pcic);
798 pci_read_config_dword(dev, 0x84, &pcic);
799 pcic |= (1<<23); /* Required in this mode */
800 pci_write_config_dword(dev, 0x84, pcic);
801 }
802}
652c538e 803DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
e1a2a51e 804DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1da177e4
LT		 805
806/*
807 * DreamWorks provided workaround for Dunord I-3000 problem
808 *
809 * This card decodes and responds to addresses not apparently
810 * assigned to it. We force a larger allocation to ensure that
811 * nothing gets put too close to it.
812 */
813static void __devinit quirk_dunord ( struct pci_dev * dev )
814{
815 struct resource *r = &dev->resource [1];
816 r->start = 0;
817 r->end = 0xffffff;
818}
652c538e 819DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1da177e4
LT		 820
821/*
822 * i82380FB mobile docking controller: its PCI-to-PCI bridge
823 * is subtractive decoding (transparent), and does indicate this
824 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
825 * instead of 0x01.
826 */
827static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
828{
829 dev->transparent = 1;
830}
652c538e
AM		 831DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
832DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1da177e4
LT		 833
834/*
835 * Common misconfiguration of the MediaGX/Geode PCI master that will
836 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
837 * datasheets found at http://www.national.com/ds/GX for info on what
838 * these bits do. <christer@weinigel.se>
839 */
1597cacb 840static void quirk_mediagx_master(struct pci_dev *dev)
1da177e4
LT		 841{
842 u8 reg;
843 pci_read_config_byte(dev, 0x41, &reg);
844 if (reg & 2) {
845 reg &= ~2;
f0fda801 846 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
1da177e4
LT		 847 pci_write_config_byte(dev, 0x41, reg);
848 }
849}
652c538e
AM		 850DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
851DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1da177e4 852
1da177e4
LT		 853/*
854 * Ensure C0 rev restreaming is off. This is normally done by
855 * the BIOS but in the odd case it is not the results are corruption
856 * hence the presence of a Linux check
857 */
1597cacb 858static void quirk_disable_pxb(struct pci_dev *pdev)
1da177e4
LT		 859{
860 u16 config;
1da177e4 861
44c10138 862 if (pdev->revision != 0x04) /* Only C0 requires this */
1da177e4
LT		 863 return;
864 pci_read_config_word(pdev, 0x40, &config);
865 if (config & (1<<6)) {
866 config &= ~(1<<6);
867 pci_write_config_word(pdev, 0x40, config);
f0fda801 868 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
1da177e4
LT		 869 }
870}
652c538e 871DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
e1a2a51e 872DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1da177e4 873
05a7d22b 874static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev)
ab17443a 875{
05a7d22b
CC		 876 /* set sb600/sb700/sb800 sata to ahci mode */
877 u8 tmp;
ab17443a 878
05a7d22b
CC		 879 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
880 if (tmp == 0x01) {
ab17443a
CH		 881 pci_read_config_byte(pdev, 0x40, &tmp);
882 pci_write_config_byte(pdev, 0x40, tmp|1);
883 pci_write_config_byte(pdev, 0x9, 1);
884 pci_write_config_byte(pdev, 0xa, 6);
885 pci_write_config_byte(pdev, 0x40, tmp);
886
c9f89475 887 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
05a7d22b 888 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
ab17443a
CH		 889 }
890}
05a7d22b 891DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
e1a2a51e 892DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
05a7d22b 893DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
e1a2a51e 894DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
ab17443a 895
1da177e4
LT		 896/*
897 * Serverworks CSB5 IDE does not fully support native mode
898 */
899static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
900{
901 u8 prog;
902 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
903 if (prog & 5) {
904 prog &= ~5;
905 pdev->class &= ~5;
906 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
368c73d4 907 /* PCI layer will sort out resources */
1da177e4
LT		 908 }
909}
652c538e 910DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1da177e4
LT		 911
912/*
913 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
914 */
915static void __init quirk_ide_samemode(struct pci_dev *pdev)
916{
917 u8 prog;
918
919 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
920
921 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
f0fda801 922 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
1da177e4
LT		 923 prog &= ~5;
924 pdev->class &= ~5;
925 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1da177e4
LT		 926 }
927}
368c73d4 928DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1da177e4 929
979b1791
AC		 930/*
931 * Some ATA devices break if put into D3
932 */
933
934static void __devinit quirk_no_ata_d3(struct pci_dev *pdev)
935{
936 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
937 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE)
938 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
939}
940DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, quirk_no_ata_d3);
941DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, quirk_no_ata_d3);
942
1da177e4
LT		 943/* This was originally an Alpha specific thing, but it really fits here.
944 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
945 */
946static void __init quirk_eisa_bridge(struct pci_dev *dev)
947{
948 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
949}
652c538e 950DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1da177e4 951
7daa0c4f 952
1da177e4
LT		 953/*
954 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
955 * is not activated. The myth is that Asus said that they do not want the
956 * users to be irritated by just another PCI Device in the Win98 device
957 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
958 * package 2.7.0 for details)
959 *
960 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
961 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
d7698edc 962 * becomes necessary to do this tweak in two steps -- the chosen trigger
963 * is either the Host bridge (preferred) or on-board VGA controller.
9208ee82
JD		 964 *
965 * Note that we used to unhide the SMBus that way on Toshiba laptops
966 * (Satellite A40 and Tecra M2) but then found that the thermal management
967 * was done by SMM code, which could cause unsynchronized concurrent
968 * accesses to the SMBus registers, with potentially bad effects. Thus you
969 * should be very careful when adding new entries: if SMM is accessing the
970 * Intel SMBus, this is a very good reason to leave it hidden.
a99acc83
JD		 971 *
972 * Likewise, many recent laptops use ACPI for thermal management. If the
973 * ACPI DSDT code accesses the SMBus, then Linux should not access it
974 * natively, and keeping the SMBus hidden is the right thing to do. If you
975 * are about to add an entry in the table below, please first disassemble
976 * the DSDT and double-check that there is no code accessing the SMBus.
1da177e4 977 */
9d24a81e 978static int asus_hides_smbus;
1da177e4
LT		 979
980static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
981{
982 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
983 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
984 switch(dev->subsystem_device) {
a00db371 985 case 0x8025: /* P4B-LX */
1da177e4
LT		 986 case 0x8070: /* P4B */
987 case 0x8088: /* P4B533 */
988 case 0x1626: /* L3C notebook */
989 asus_hides_smbus = 1;
990 }
2f2d39d2 991 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1da177e4
LT		 992 switch(dev->subsystem_device) {
993 case 0x80b1: /* P4GE-V */
994 case 0x80b2: /* P4PE */
995 case 0x8093: /* P4B533-V */
996 asus_hides_smbus = 1;
997 }
2f2d39d2 998 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1da177e4
LT		 999 switch(dev->subsystem_device) {
1000 case 0x8030: /* P4T533 */
1001 asus_hides_smbus = 1;
1002 }
2f2d39d2 1003 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1da177e4
LT		 1004 switch (dev->subsystem_device) {
1005 case 0x8070: /* P4G8X Deluxe */
1006 asus_hides_smbus = 1;
1007 }
2f2d39d2 1008 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
321311af
JD		 1009 switch (dev->subsystem_device) {
1010 case 0x80c9: /* PU-DLS */
1011 asus_hides_smbus = 1;
1012 }
2f2d39d2 1013 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1da177e4
LT		 1014 switch (dev->subsystem_device) {
1015 case 0x1751: /* M2N notebook */
1016 case 0x1821: /* M5N notebook */
1017 asus_hides_smbus = 1;
1018 }
2f2d39d2 1019 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1da177e4
LT		 1020 switch (dev->subsystem_device) {
1021 case 0x184b: /* W1N notebook */
1022 case 0x186a: /* M6Ne notebook */
1023 asus_hides_smbus = 1;
1024 }
2f2d39d2 1025 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
2e45785c
JD		 1026 switch (dev->subsystem_device) {
1027 case 0x80f2: /* P4P800-X */
1028 asus_hides_smbus = 1;
1029 }
2f2d39d2 1030 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
acc06632
RM		 1031 switch (dev->subsystem_device) {
1032 case 0x1882: /* M6V notebook */
2d1e1c75 1033 case 0x1977: /* A6VA notebook */
acc06632
RM		 1034 asus_hides_smbus = 1;
1035 }
1da177e4
LT		 1036 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1037 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1038 switch(dev->subsystem_device) {
1039 case 0x088C: /* HP Compaq nc8000 */
1040 case 0x0890: /* HP Compaq nc6000 */
1041 asus_hides_smbus = 1;
1042 }
2f2d39d2 1043 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1da177e4
LT		 1044 switch (dev->subsystem_device) {
1045 case 0x12bc: /* HP D330L */
e3b1bd57 1046 case 0x12bd: /* HP D530 */
1da177e4
LT		 1047 asus_hides_smbus = 1;
1048 }
677cc644
JD		 1049 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1050 switch (dev->subsystem_device) {
1051 case 0x12bf: /* HP xw4100 */
1052 asus_hides_smbus = 1;
1053 }
1da177e4
LT		 1054 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1055 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1056 switch(dev->subsystem_device) {
1057 case 0xC00C: /* Samsung P35 notebook */
1058 asus_hides_smbus = 1;
1059 }
c87f883e
RIZ		 1060 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1061 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1062 switch(dev->subsystem_device) {
1063 case 0x0058: /* Compaq Evo N620c */
1064 asus_hides_smbus = 1;
1065 }
d7698edc 1066 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1067 switch(dev->subsystem_device) {
1068 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1069 /* Motherboard doesn't have Host bridge
1070 * subvendor/subdevice IDs, therefore checking
1071 * its on-board VGA controller */
1072 asus_hides_smbus = 1;
1073 }
10260d9a
JD		 1074 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_IG)
1075 switch(dev->subsystem_device) {
1076 case 0x00b8: /* Compaq Evo D510 CMT */
1077 case 0x00b9: /* Compaq Evo D510 SFF */
1078 asus_hides_smbus = 1;
1079 }
27e46859
KH		 1080 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1081 switch (dev->subsystem_device) {
1082 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1083 /* Motherboard doesn't have host bridge
1084 * subvendor/subdevice IDs, therefore checking
1085 * its on-board VGA controller */
1086 asus_hides_smbus = 1;
1087 }
1da177e4
LT		 1088 }
1089}
652c538e
AM		 1090DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1091DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1092DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1093DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
677cc644 1094DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
652c538e
AM		 1095DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1096DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1097DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1098DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1099DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1100
1101DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
10260d9a 1102DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_IG, asus_hides_smbus_hostbridge);
27e46859 1103DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
d7698edc 1104
1597cacb 1105static void asus_hides_smbus_lpc(struct pci_dev *dev)
1da177e4
LT		 1106{
1107 u16 val;
1108
1109 if (likely(!asus_hides_smbus))
1110 return;
1111
1112 pci_read_config_word(dev, 0xF2, &val);
1113 if (val & 0x8) {
1114 pci_write_config_word(dev, 0xF2, val & (~0x8));
1115 pci_read_config_word(dev, 0xF2, &val);
1116 if (val & 0x8)
f0fda801 1117 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1da177e4 1118 else
f0fda801 1119 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1da177e4
LT		 1120 }
1121}
652c538e
AM		 1122DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1123DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1124DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1125DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1126DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1127DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1128DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
e1a2a51e
RW		 1129DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1130DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1131DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1132DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1133DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1134DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1135DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1597cacb 1136
e1a2a51e
RW		 1137/* It appears we just have one such device. If not, we have a warning */
1138static void __iomem *asus_rcba_base;
1139static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
acc06632 1140{
e1a2a51e 1141 u32 rcba;
acc06632
RM		 1142
1143 if (likely(!asus_hides_smbus))
1144 return;
e1a2a51e
RW		 1145 WARN_ON(asus_rcba_base);
1146
acc06632 1147 pci_read_config_dword(dev, 0xF0, &rcba);
e1a2a51e
RW		 1148 /* use bits 31:14, 16 kB aligned */
1149 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1150 if (asus_rcba_base == NULL)
1151 return;
1152}
1153
1154static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1155{
1156 u32 val;
1157
1158 if (likely(!asus_hides_smbus || !asus_rcba_base))
1159 return;
1160 /* read the Function Disable register, dword mode only */
1161 val = readl(asus_rcba_base + 0x3418);
1162 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1163}
1164
1165static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1166{
1167 if (likely(!asus_hides_smbus || !asus_rcba_base))
1168 return;
1169 iounmap(asus_rcba_base);
1170 asus_rcba_base = NULL;
f0fda801 1171 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
acc06632 1172}
e1a2a51e
RW		 1173
1174static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1175{
1176 asus_hides_smbus_lpc_ich6_suspend(dev);
1177 asus_hides_smbus_lpc_ich6_resume_early(dev);
1178 asus_hides_smbus_lpc_ich6_resume(dev);
1179}
652c538e 1180DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
e1a2a51e
RW		 1181DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1182DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1183DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
ce007ea5 1184
1da177e4
LT		 1185/*
1186 * SiS 96x south bridge: BIOS typically hides SMBus device...
1187 */
1597cacb 1188static void quirk_sis_96x_smbus(struct pci_dev *dev)
1da177e4
LT		 1189{
1190 u8 val = 0;
1da177e4 1191 pci_read_config_byte(dev, 0x77, &val);
2f5c33b3 1192 if (val & 0x10) {
f0fda801 1193 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
2f5c33b3
MH		 1194 pci_write_config_byte(dev, 0x77, val & ~0x10);
1195 }
1da177e4 1196}
652c538e
AM		 1197DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1198DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1199DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1200DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
e1a2a51e
RW		 1201DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1202DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1203DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1204DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1da177e4 1205
1da177e4
LT		 1206/*
1207 * ... This is further complicated by the fact that some SiS96x south
1208 * bridges pretend to be 85C503/5513 instead. In that case see if we
1209 * spotted a compatible north bridge to make sure.
1210 * (pci_find_device doesn't work yet)
1211 *
1212 * We can also enable the sis96x bit in the discovery register..
1213 */
1da177e4
LT		 1214#define SIS_DETECT_REGISTER 0x40
1215
1597cacb 1216static void quirk_sis_503(struct pci_dev *dev)
1da177e4
LT		 1217{
1218 u8 reg;
1219 u16 devid;
1220
1221 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1222 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1223 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1224 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1225 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1226 return;
1227 }
1228
1da177e4 1229 /*
2f5c33b3
MH		 1230 * Ok, it now shows up as a 96x.. run the 96x quirk by
1231 * hand in case it has already been processed.
1232 * (depends on link order, which is apparently not guaranteed)
1da177e4
LT		 1233 */
1234 dev->device = devid;
2f5c33b3 1235 quirk_sis_96x_smbus(dev);
1da177e4 1236}
652c538e 1237DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
e1a2a51e 1238DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1da177e4 1239
1da177e4 1240
e5548e96
BJD		 1241/*
1242 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1243 * and MC97 modem controller are disabled when a second PCI soundcard is
1244 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1245 * -- bjd
1246 */
1597cacb 1247static void asus_hides_ac97_lpc(struct pci_dev *dev)
e5548e96
BJD		 1248{
1249 u8 val;
1250 int asus_hides_ac97 = 0;
1251
1252 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1253 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1254 asus_hides_ac97 = 1;
1255 }
1256
1257 if (!asus_hides_ac97)
1258 return;
1259
1260 pci_read_config_byte(dev, 0x50, &val);
1261 if (val & 0xc0) {
1262 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1263 pci_read_config_byte(dev, 0x50, &val);
1264 if (val & 0xc0)
f0fda801 1265 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
e5548e96 1266 else
f0fda801 1267 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
e5548e96
BJD		 1268 }
1269}
652c538e 1270DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
e1a2a51e 1271DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1597cacb 1272
77967052 1273#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
15e0c694
AC		 1274
1275/*
1276 * If we are using libata we can drive this chip properly but must
1277 * do this early on to make the additional device appear during
1278 * the PCI scanning.
1279 */
5ee2ae7f 1280static void quirk_jmicron_ata(struct pci_dev *pdev)
15e0c694 1281{
e34bb370 1282 u32 conf1, conf5, class;
15e0c694
AC		 1283 u8 hdr;
1284
1285 /* Only poke fn 0 */
1286 if (PCI_FUNC(pdev->devfn))
1287 return;
1288
5ee2ae7f
TH		 1289 pci_read_config_dword(pdev, 0x40, &conf1);
1290 pci_read_config_dword(pdev, 0x80, &conf5);
15e0c694 1291
5ee2ae7f
TH		 1292 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1293 conf5 &= ~(1 << 24); /* Clear bit 24 */
1294
1295 switch (pdev->device) {
1296 case PCI_DEVICE_ID_JMICRON_JMB360:
1297 /* The controller should be in single function ahci mode */
1298 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1299 break;
1300
1301 case PCI_DEVICE_ID_JMICRON_JMB365:
1302 case PCI_DEVICE_ID_JMICRON_JMB366:
1303 /* Redirect IDE second PATA port to the right spot */
1304 conf5 |= (1 << 24);
1305 /* Fall through */
1306 case PCI_DEVICE_ID_JMICRON_JMB361:
1307 case PCI_DEVICE_ID_JMICRON_JMB363:
1308 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1309 /* Set the class codes correctly and then direct IDE 0 */
3a9e3a51 1310 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
5ee2ae7f
TH		 1311 break;
1312
1313 case PCI_DEVICE_ID_JMICRON_JMB368:
1314 /* The controller should be in single function IDE mode */
1315 conf1 |= 0x00C00000; /* Set 22, 23 */
1316 break;
15e0c694 1317 }
5ee2ae7f
TH		 1318
1319 pci_write_config_dword(pdev, 0x40, conf1);
1320 pci_write_config_dword(pdev, 0x80, conf5);
1321
1322 /* Update pdev accordingly */
1323 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1324 pdev->hdr_type = hdr & 0x7f;
1325 pdev->multifunction = !!(hdr & 0x80);
e34bb370
TH		 1326
1327 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1328 pdev->class = class >> 8;
15e0c694 1329}
5ee2ae7f
TH		 1330DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1331DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1332DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1333DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1334DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1335DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
e1a2a51e
RW		 1336DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1337DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1338DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1339DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1340DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1341DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
15e0c694
AC		 1342
1343#endif
1344
1da177e4
LT		 1345#ifdef CONFIG_X86_IO_APIC
1346static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1347{
1348 int i;
1349
1350 if ((pdev->class >> 8) != 0xff00)
1351 return;
1352
1353 /* the first BAR is the location of the IO APIC...we must
1354 * not touch this (and it's already covered by the fixmap), so
1355 * forcibly insert it into the resource tree */
1356 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1357 insert_resource(&iomem_resource, &pdev->resource[0]);
1358
1359 /* The next five BARs all seem to be rubbish, so just clean
1360 * them out */
1361 for (i=1; i < 6; i++) {
1362 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1363 }
1364
1365}
652c538e 1366DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1da177e4
LT		 1367#endif
1368
1da177e4
LT		 1369static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1370{
1371 pcie_mch_quirk = 1;
1372}
652c538e
AM		 1373DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1374DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1375DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1da177e4 1376
4602b88d
KA		 1377
1378/*
1379 * It's possible for the MSI to get corrupted if shpc and acpi
1380 * are used together on certain PXH-based systems.
1381 */
1382static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1383{
f5f2b131 1384 pci_msi_off(dev);
4602b88d 1385 dev->no_msi = 1;
f0fda801 1386 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
4602b88d
KA		 1387}
1388DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1389DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1390DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1391DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1392DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1393
ffadcc2f
KCA		 1394/*
1395 * Some Intel PCI Express chipsets have trouble with downstream
1396 * device power management.
1397 */
1398static void quirk_intel_pcie_pm(struct pci_dev * dev)
1399{
1400 pci_pm_d3_delay = 120;
1401 dev->no_d1d2 = 1;
1402}
1403
1404DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1405DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1406DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1407DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1408DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1409DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1410DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1411DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1412DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1413DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1414DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1415DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1416DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1417DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1418DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1419DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1420DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1421DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1422DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1423DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1424DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
4602b88d 1425
33dced2e
SS		 1426/*
1427 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1428 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1429 * Re-allocate the region if needed...
1430 */
1431static void __init quirk_tc86c001_ide(struct pci_dev *dev)
1432{
1433 struct resource *r = &dev->resource[0];
1434
1435 if (r->start & 0x8) {
1436 r->start = 0;
1437 r->end = 0xf;
1438 }
1439}
1440DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1441 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1442 quirk_tc86c001_ide);
1443
1da177e4
LT		 1444static void __devinit quirk_netmos(struct pci_dev *dev)
1445{
1446 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1447 unsigned int num_serial = dev->subsystem_device & 0xf;
1448
1449 /*
1450 * These Netmos parts are multiport serial devices with optional
1451 * parallel ports. Even when parallel ports are present, they
1452 * are identified as class SERIAL, which means the serial driver
1453 * will claim them. To prevent this, mark them as class OTHER.
1454 * These combo devices should be claimed by parport_serial.
1455 *
1456 * The subdevice ID is of the form 0x00PS, where <P> is the number
1457 * of parallel ports and <S> is the number of serial ports.
1458 */
1459 switch (dev->device) {
1460 case PCI_DEVICE_ID_NETMOS_9735:
1461 case PCI_DEVICE_ID_NETMOS_9745:
1462 case PCI_DEVICE_ID_NETMOS_9835:
1463 case PCI_DEVICE_ID_NETMOS_9845:
1464 case PCI_DEVICE_ID_NETMOS_9855:
1465 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1466 num_parallel) {
f0fda801 1467 dev_info(&dev->dev, "Netmos %04x (%u parallel, "
1da177e4
LT		 1468 "%u serial); changing class SERIAL to OTHER "
1469 "(use parport_serial)\n",
1470 dev->device, num_parallel, num_serial);
1471 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1472 (dev->class & 0xff);
1473 }
1474 }
1475}
1476DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1477
16a74744
BH		 1478static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1479{
e64aeccb 1480 u16 command, pmcsr;
16a74744
BH		 1481 u8 __iomem *csr;
1482 u8 cmd_hi;
e64aeccb 1483 int pm;
16a74744
BH		 1484
1485 switch (dev->device) {
1486 /* PCI IDs taken from drivers/net/e100.c */
1487 case 0x1029:
1488 case 0x1030 ... 0x1034:
1489 case 0x1038 ... 0x103E:
1490 case 0x1050 ... 0x1057:
1491 case 0x1059:
1492 case 0x1064 ... 0x106B:
1493 case 0x1091 ... 0x1095:
1494 case 0x1209:
1495 case 0x1229:
1496 case 0x2449:
1497 case 0x2459:
1498 case 0x245D:
1499 case 0x27DC:
1500 break;
1501 default:
1502 return;
1503 }
1504
1505 /*
1506 * Some firmware hands off the e100 with interrupts enabled,
1507 * which can cause a flood of interrupts if packets are
1508 * received before the driver attaches to the device. So
1509 * disable all e100 interrupts here. The driver will
1510 * re-enable them when it's ready.
1511 */
1512 pci_read_config_word(dev, PCI_COMMAND, &command);
16a74744 1513
1bef7dc0 1514 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
16a74744
BH		 1515 return;
1516
e64aeccb
IK		 1517 /*
1518 * Check that the device is in the D0 power state. If it's not,
1519 * there is no point to look any further.
1520 */
1521 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1522 if (pm) {
1523 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
1524 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1525 return;
1526 }
1527
1bef7dc0
BH		 1528 /* Convert from PCI bus to resource space. */
1529 csr = ioremap(pci_resource_start(dev, 0), 8);
16a74744 1530 if (!csr) {
f0fda801 1531 dev_warn(&dev->dev, "Can't map e100 registers\n");
16a74744
BH		 1532 return;
1533 }
1534
1535 cmd_hi = readb(csr + 3);
1536 if (cmd_hi == 0) {
f0fda801 1537 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; "
1538 "disabling\n");
16a74744
BH		 1539 writeb(1, csr + 3);
1540 }
1541
1542 iounmap(csr);
1543}
4e68fc97 1544DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt);
a5312e28
IK		 1545
1546static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1547{
1548 /* rev 1 ncr53c810 chips don't set the class at all which means
1549 * they don't get their resources remapped. Fix that here.
1550 */
1551
1552 if (dev->class == PCI_CLASS_NOT_DEFINED) {
f0fda801 1553 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n");
a5312e28
IK		 1554 dev->class = PCI_CLASS_STORAGE_SCSI;
1555 }
1556}
1557DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1558
9d265124
DY		 1559/* Enable 1k I/O space granularity on the Intel P64H2 */
1560static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1561{
1562 u16 en1k;
1563 u8 io_base_lo, io_limit_lo;
1564 unsigned long base, limit;
1565 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1566
1567 pci_read_config_word(dev, 0x40, &en1k);
1568
1569 if (en1k & 0x200) {
f0fda801 1570 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
9d265124
DY		 1571
1572 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
1573 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
1574 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1575 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1576
1577 if (base <= limit) {
1578 res->start = base;
1579 res->end = limit + 0x3ff;
1580 }
1581 }
1582}
1583DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1584
15a260d5
DY		 1585/* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2
1586 * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge()
1587 * in drivers/pci/setup-bus.c
1588 */
1589static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev)
1590{
1591 u16 en1k, iobl_adr, iobl_adr_1k;
1592 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1593
1594 pci_read_config_word(dev, 0x40, &en1k);
1595
1596 if (en1k & 0x200) {
1597 pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr);
1598
1599 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00);
1600
1601 if (iobl_adr != iobl_adr_1k) {
f0fda801 1602 dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n",
15a260d5
DY		 1603 iobl_adr,iobl_adr_1k);
1604 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k);
1605 }
1606 }
1607}
1608DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl);
1609
cf34a8e0
BG		 1610/* Under some circumstances, AER is not linked with extended capabilities.
1611 * Force it to be linked by setting the corresponding control bit in the
1612 * config space.
1613 */
1597cacb 1614static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
cf34a8e0
BG		 1615{
1616 uint8_t b;
1617 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1618 if (!(b & 0x20)) {
1619 pci_write_config_byte(dev, 0xf41, b | 0x20);
f0fda801 1620 dev_info(&dev->dev,
1621 "Linking AER extended capability\n");
cf34a8e0
BG		 1622 }
1623 }
1624}
1625DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1626 quirk_nvidia_ck804_pcie_aer_ext_cap);
e1a2a51e 1627DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1597cacb 1628 quirk_nvidia_ck804_pcie_aer_ext_cap);
cf34a8e0 1629
53a9bf42
TY		 1630static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
1631{
1632 /*
1633 * Disable PCI Bus Parking and PCI Master read caching on CX700
1634 * which causes unspecified timing errors with a VT6212L on the PCI
1635 * bus leading to USB2.0 packet loss. The defaults are that these
1636 * features are turned off but some BIOSes turn them on.
1637 */
1638
1639 uint8_t b;
1640 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
1641 if (b & 0x40) {
1642 /* Turn off PCI Bus Parking */
1643 pci_write_config_byte(dev, 0x76, b ^ 0x40);
1644
bc043274
TY		 1645 dev_info(&dev->dev,
1646 "Disabling VIA CX700 PCI parking\n");
1647 }
1648 }
1649
1650 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
1651 if (b != 0) {
53a9bf42
TY		 1652 /* Turn off PCI Master read caching */
1653 pci_write_config_byte(dev, 0x72, 0x0);
bc043274
TY		 1654
1655 /* Set PCI Master Bus time-out to "1x16 PCLK" */
53a9bf42 1656 pci_write_config_byte(dev, 0x75, 0x1);
bc043274
TY		 1657
1658 /* Disable "Read FIFO Timer" */
53a9bf42
TY		 1659 pci_write_config_byte(dev, 0x77, 0x0);
1660
d6505a52 1661 dev_info(&dev->dev,
bc043274 1662 "Disabling VIA CX700 PCI caching\n");
53a9bf42
TY		 1663 }
1664 }
1665}
1666DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
1667
99cb233d
BL		 1668/*
1669 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
1670 * VPD end tag will hang the device. This problem was initially
1671 * observed when a vpd entry was created in sysfs
1672 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
1673 * will dump 32k of data. Reading a full 32k will cause an access
1674 * beyond the VPD end tag causing the device to hang. Once the device
1675 * is hung, the bnx2 driver will not be able to reset the device.
1676 * We believe that it is legal to read beyond the end tag and
1677 * therefore the solution is to limit the read/write length.
1678 */
1679static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
1680{
9d82d8ea 1681 /*
35405f25
DH		 1682 * Only disable the VPD capability for 5706, 5706S, 5708,
1683 * 5708S and 5709 rev. A
9d82d8ea 1684 */
99cb233d 1685 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
35405f25 1686 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
99cb233d 1687 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
9d82d8ea 1688 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
99cb233d
BL		 1689 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
1690 (dev->revision & 0xf0) == 0x0)) {
1691 if (dev->vpd)
1692 dev->vpd->len = 0x80;
1693 }
1694}
1695
bffadffd
YZ		 1696DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1697 PCI_DEVICE_ID_NX2_5706,
1698 quirk_brcm_570x_limit_vpd);
1699DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1700 PCI_DEVICE_ID_NX2_5706S,
1701 quirk_brcm_570x_limit_vpd);
1702DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1703 PCI_DEVICE_ID_NX2_5708,
1704 quirk_brcm_570x_limit_vpd);
1705DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1706 PCI_DEVICE_ID_NX2_5708S,
1707 quirk_brcm_570x_limit_vpd);
1708DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1709 PCI_DEVICE_ID_NX2_5709,
1710 quirk_brcm_570x_limit_vpd);
1711DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1712 PCI_DEVICE_ID_NX2_5709S,
1713 quirk_brcm_570x_limit_vpd);
99cb233d 1714
3f79e107 1715#ifdef CONFIG_PCI_MSI
ebdf7d39
TH		 1716/* Some chipsets do not support MSI. We cannot easily rely on setting
1717 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
1718 * some other busses controlled by the chipset even if Linux is not
1719 * aware of it. Instead of setting the flag on all busses in the
1720 * machine, simply disable MSI globally.
3f79e107 1721 */
ebdf7d39 1722static void __init quirk_disable_all_msi(struct pci_dev *dev)
3f79e107 1723{
88187dfa 1724 pci_no_msi();
f0fda801 1725 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
3f79e107 1726}
ebdf7d39
TH		 1727DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
1728DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
1729DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
66d715c9 1730DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
184b812f 1731DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
3f79e107
BG		 1732
1733/* Disable MSI on chipsets that are known to not support it */
1734static void __devinit quirk_disable_msi(struct pci_dev *dev)
1735{
1736 if (dev->subordinate) {
f0fda801 1737 dev_warn(&dev->dev, "MSI quirk detected; "
1738 "subordinate MSI disabled\n");
3f79e107
BG		 1739 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1740 }
1741}
1742DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
6397c75c
BG		 1743
1744/* Go through the list of Hypertransport capabilities and
1745 * return 1 if a HT MSI capability is found and enabled */
1746static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
1747{
7a380507
ME		 1748 int pos, ttl = 48;
1749
1750 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
1751 while (pos && ttl--) {
1752 u8 flags;
1753
1754 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
1755 &flags) == 0)
1756 {
f0fda801 1757 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
7a380507 1758 flags & HT_MSI_FLAGS_ENABLE ?
f0fda801 1759 "enabled" : "disabled");
7a380507 1760 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
6397c75c 1761 }
7a380507
ME		 1762
1763 pos = pci_find_next_ht_capability(dev, pos,
1764 HT_CAPTYPE_MSI_MAPPING);
6397c75c
BG		 1765 }
1766 return 0;
1767}
1768
1769/* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
1770static void __devinit quirk_msi_ht_cap(struct pci_dev *dev)
1771{
1772 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
f0fda801 1773 dev_warn(&dev->dev, "MSI quirk detected; "
1774 "subordinate MSI disabled\n");
6397c75c
BG		 1775 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1776 }
1777}
1778DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
1779 quirk_msi_ht_cap);
6bae1d96
SD		 1780
1781
6397c75c
BG		 1782/* The nVidia CK804 chipset may have 2 HT MSI mappings.
1783 * MSI are supported if the MSI capability set in any of these mappings.
1784 */
1785static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
1786{
1787 struct pci_dev *pdev;
1788
1789 if (!dev->subordinate)
1790 return;
1791
1792 /* check HT MSI cap on this chipset and the root one.
1793 * a single one having MSI is enough to be sure that MSI are supported.
1794 */
11f242f0 1795 pdev = pci_get_slot(dev->bus, 0);
9ac0ce85
JJ		 1796 if (!pdev)
1797 return;
0c875c28 1798 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
f0fda801 1799 dev_warn(&dev->dev, "MSI quirk detected; "
1800 "subordinate MSI disabled\n");
6397c75c
BG		 1801 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1802 }
11f242f0 1803 pci_dev_put(pdev);
6397c75c
BG		 1804}
1805DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1806 quirk_nvidia_ck804_msi_ht_cap);
ba698ad4 1807
415b6d0e
BH		 1808/* Force enable MSI mapping capability on HT bridges */
1809static void __devinit ht_enable_msi_mapping(struct pci_dev *dev)
9dc625e7
PC		 1810{
1811 int pos, ttl = 48;
1812
1813 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
1814 while (pos && ttl--) {
1815 u8 flags;
1816
1817 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
1818 &flags) == 0) {
1819 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
1820
1821 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
1822 flags | HT_MSI_FLAGS_ENABLE);
1823 }
1824 pos = pci_find_next_ht_capability(dev, pos,
1825 HT_CAPTYPE_MSI_MAPPING);
1826 }
1827}
415b6d0e
BH		 1828DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
1829 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
1830 ht_enable_msi_mapping);
9dc625e7 1831
75e07fc3
AP		 1832/* The P5N32-SLI Premium motherboard from Asus has a problem with msi
1833 * for the MCP55 NIC. It is not yet determined whether the msi problem
1834 * also affects other devices. As for now, turn off msi for this device.
1835 */
1836static void __devinit nvenet_msi_disable(struct pci_dev *dev)
1837{
1838 if (dmi_name_in_vendors("P5N32-SLI PREMIUM")) {
1839 dev_info(&dev->dev,
1840 "Disabling msi for MCP55 NIC on P5N32-SLI Premium\n");
1841 dev->no_msi = 1;
1842 }
1843}
1844DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
1845 PCI_DEVICE_ID_NVIDIA_NVENET_15,
1846 nvenet_msi_disable);
1847
9dc625e7
PC		 1848static void __devinit nv_msi_ht_cap_quirk(struct pci_dev *dev)
1849{
1850 struct pci_dev *host_bridge;
1851 int pos, ttl = 48;
1852
1853 /*
1854 * HT MSI mapping should be disabled on devices that are below
1855 * a non-Hypertransport host bridge. Locate the host bridge...
1856 */
1857 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
1858 if (host_bridge == NULL) {
1859 dev_warn(&dev->dev,
1860 "nv_msi_ht_cap_quirk didn't locate host bridge\n");
1861 return;
1862 }
1863
1864 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
1865 if (pos != 0) {
1866 /* Host bridge is to HT */
1867 ht_enable_msi_mapping(dev);
1868 return;
1869 }
1870
1871 /* Host bridge is not to HT, disable HT MSI mapping on this device */
1872 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
1873 while (pos && ttl--) {
1874 u8 flags;
1875
1876 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
1877 &flags) == 0) {
415b6d0e 1878 dev_info(&dev->dev, "Disabling HT MSI mapping");
9dc625e7
PC		 1879 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
1880 flags & ~HT_MSI_FLAGS_ENABLE);
1881 }
1882 pos = pci_find_next_ht_capability(dev, pos,
1883 HT_CAPTYPE_MSI_MAPPING);
1884 }
1885}
1886DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk);
439a7733 1887DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk);
9dc625e7 1888
ba698ad4
DM		 1889static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev)
1890{
1891 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
1892}
4600c9d7
SH		 1893static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
1894{
1895 struct pci_dev *p;
1896
1897 /* SB700 MSI issue will be fixed at HW level from revision A21,
1898 * we need check PCI REVISION ID of SMBus controller to get SB700
1899 * revision.
1900 */
1901 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1902 NULL);
1903 if (!p)
1904 return;
1905
1906 if ((p->revision < 0x3B) && (p->revision >= 0x30))
1907 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
1908 pci_dev_put(p);
1909}
ba698ad4
DM		 1910DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1911 PCI_DEVICE_ID_TIGON3_5780,
1912 quirk_msi_intx_disable_bug);
1913DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1914 PCI_DEVICE_ID_TIGON3_5780S,
1915 quirk_msi_intx_disable_bug);
1916DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1917 PCI_DEVICE_ID_TIGON3_5714,
1918 quirk_msi_intx_disable_bug);
1919DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1920 PCI_DEVICE_ID_TIGON3_5714S,
1921 quirk_msi_intx_disable_bug);
1922DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1923 PCI_DEVICE_ID_TIGON3_5715,
1924 quirk_msi_intx_disable_bug);
1925DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1926 PCI_DEVICE_ID_TIGON3_5715S,
1927 quirk_msi_intx_disable_bug);
1928
bc38b411 1929DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
4600c9d7 1930 quirk_msi_intx_disable_ati_bug);
bc38b411 1931DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
4600c9d7 1932 quirk_msi_intx_disable_ati_bug);
bc38b411 1933DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
4600c9d7 1934 quirk_msi_intx_disable_ati_bug);
bc38b411 1935DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
4600c9d7 1936 quirk_msi_intx_disable_ati_bug);
bc38b411 1937DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
4600c9d7 1938 quirk_msi_intx_disable_ati_bug);
bc38b411
DM		 1939
1940DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
1941 quirk_msi_intx_disable_bug);
1942DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
1943 quirk_msi_intx_disable_bug);
1944DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
1945 quirk_msi_intx_disable_bug);
1946
3f79e107 1947#endif /* CONFIG_PCI_MSI */
3d137310
TP		 1948
1949static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end)
1950{
1951 while (f < end) {
1952 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
1953 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
c9bbb4ab 1954 dev_dbg(&dev->dev, "calling %pF\n", f->hook);
3d137310
TP		 1955 f->hook(dev);
1956 }
1957 f++;
1958 }
1959}
1960
1961extern struct pci_fixup __start_pci_fixups_early[];
1962extern struct pci_fixup __end_pci_fixups_early[];
1963extern struct pci_fixup __start_pci_fixups_header[];
1964extern struct pci_fixup __end_pci_fixups_header[];
1965extern struct pci_fixup __start_pci_fixups_final[];
1966extern struct pci_fixup __end_pci_fixups_final[];
1967extern struct pci_fixup __start_pci_fixups_enable[];
1968extern struct pci_fixup __end_pci_fixups_enable[];
1969extern struct pci_fixup __start_pci_fixups_resume[];
1970extern struct pci_fixup __end_pci_fixups_resume[];
1971extern struct pci_fixup __start_pci_fixups_resume_early[];
1972extern struct pci_fixup __end_pci_fixups_resume_early[];
1973extern struct pci_fixup __start_pci_fixups_suspend[];
1974extern struct pci_fixup __end_pci_fixups_suspend[];
1975
1976
1977void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
1978{
1979 struct pci_fixup *start, *end;
1980
1981 switch(pass) {
1982 case pci_fixup_early:
1983 start = __start_pci_fixups_early;
1984 end = __end_pci_fixups_early;
1985 break;
1986
1987 case pci_fixup_header:
1988 start = __start_pci_fixups_header;
1989 end = __end_pci_fixups_header;
1990 break;
1991
1992 case pci_fixup_final:
1993 start = __start_pci_fixups_final;
1994 end = __end_pci_fixups_final;
1995 break;
1996
1997 case pci_fixup_enable:
1998 start = __start_pci_fixups_enable;
1999 end = __end_pci_fixups_enable;
2000 break;
2001
2002 case pci_fixup_resume:
2003 start = __start_pci_fixups_resume;
2004 end = __end_pci_fixups_resume;
2005 break;
2006
2007 case pci_fixup_resume_early:
2008 start = __start_pci_fixups_resume_early;
2009 end = __end_pci_fixups_resume_early;
2010 break;
2011
2012 case pci_fixup_suspend:
2013 start = __start_pci_fixups_suspend;
2014 end = __end_pci_fixups_suspend;
2015 break;
2016
2017 default:
2018 /* stupid compiler warning, you would think with an enum... */
2019 return;
2020 }
2021 pci_do_fixups(dev, start, end);
2022}
2023#else
2024void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) {}
2025#endif
2026EXPORT_SYMBOL(pci_fixup_device);
kernel source for telekom puls (alcatel/mediatek)