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[PATCH] x86: Add the check for all the cores in a package in cache information
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / pci / quirks.c
CommitLineData
1da177e4
LT		 1/*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
10 * The bridge optimization stuff has been removed. If you really
11 * have a silly BIOS which is unable to set your host bridge right,
12 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
13 */
14
15#include <linux/config.h>
16#include <linux/types.h>
17#include <linux/kernel.h>
18#include <linux/pci.h>
19#include <linux/init.h>
20#include <linux/delay.h>
25be5e6c 21#include <linux/acpi.h>
bc56b9e0 22#include "pci.h"
1da177e4
LT		 23
24/* Deal with broken BIOS'es that neglect to enable passive release,
25 which can cause problems in combination with the 82441FX/PPro MTRRs */
26static void __devinit quirk_passive_release(struct pci_dev *dev)
27{
28 struct pci_dev *d = NULL;
29 unsigned char dlc;
30
31 /* We have to make sure a particular bit is set in the PIIX3
32 ISA bridge, so we have to go out and find it. */
33 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
34 pci_read_config_byte(d, 0x82, &dlc);
35 if (!(dlc & 1<<1)) {
36 printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d));
37 dlc |= 1<<1;
38 pci_write_config_byte(d, 0x82, dlc);
39 }
40 }
41}
42DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release );
43
44/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
45 but VIA don't answer queries. If you happen to have good contacts at VIA
46 ask them for me please -- Alan
47
48 This appears to be BIOS not version dependent. So presumably there is a
49 chipset level fix */
50int isa_dma_bridge_buggy; /* Exported */
51
52static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
53{
54 if (!isa_dma_bridge_buggy) {
55 isa_dma_bridge_buggy=1;
56 printk(KERN_INFO "Activating ISA DMA hang workarounds.\n");
57 }
58}
59 /*
60 * Its not totally clear which chipsets are the problematic ones
61 * We know 82C586 and 82C596 variants are affected.
62 */
63DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs );
64DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs );
65DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs );
66DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs );
67DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs );
68DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs );
69DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs );
70
71int pci_pci_problems;
72
73/*
74 * Chipsets where PCI->PCI transfers vanish or hang
75 */
76static void __devinit quirk_nopcipci(struct pci_dev *dev)
77{
78 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
79 printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n");
80 pci_pci_problems |= PCIPCI_FAIL;
81 }
82}
83DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci );
84DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci );
85
86/*
87 * Triton requires workarounds to be used by the drivers
88 */
89static void __devinit quirk_triton(struct pci_dev *dev)
90{
91 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
92 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
93 pci_pci_problems |= PCIPCI_TRITON;
94 }
95}
96DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton );
97DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton );
98DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton );
99DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton );
100
101/*
102 * VIA Apollo KT133 needs PCI latency patch
103 * Made according to a windows driver based patch by George E. Breese
104 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
105 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
106 * the info on which Mr Breese based his work.
107 *
108 * Updated based on further information from the site and also on
109 * information provided by VIA
110 */
111static void __devinit quirk_vialatency(struct pci_dev *dev)
112{
113 struct pci_dev *p;
114 u8 rev;
115 u8 busarb;
116 /* Ok we have a potential problem chipset here. Now see if we have
117 a buggy southbridge */
118
119 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
120 if (p!=NULL) {
121 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
122 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
123 /* Check for buggy part revisions */
124 if (rev < 0x40 || rev > 0x42)
125 goto exit;
126 } else {
127 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
128 if (p==NULL) /* No problem parts */
129 goto exit;
130 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
131 /* Check for buggy part revisions */
132 if (rev < 0x10 || rev > 0x12)
133 goto exit;
134 }
135
136 /*
137 * Ok we have the problem. Now set the PCI master grant to
138 * occur every master grant. The apparent bug is that under high
139 * PCI load (quite common in Linux of course) you can get data
140 * loss when the CPU is held off the bus for 3 bus master requests
141 * This happens to include the IDE controllers....
142 *
143 * VIA only apply this fix when an SB Live! is present but under
144 * both Linux and Windows this isnt enough, and we have seen
145 * corruption without SB Live! but with things like 3 UDMA IDE
146 * controllers. So we ignore that bit of the VIA recommendation..
147 */
148
149 pci_read_config_byte(dev, 0x76, &busarb);
150 /* Set bit 4 and bi 5 of byte 76 to 0x01
151 "Master priority rotation on every PCI master grant */
152 busarb &= ~(1<<5);
153 busarb |= (1<<4);
154 pci_write_config_byte(dev, 0x76, busarb);
155 printk(KERN_INFO "Applying VIA southbridge workaround.\n");
156exit:
157 pci_dev_put(p);
158}
159DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency );
160DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency );
161DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency );
162
163/*
164 * VIA Apollo VP3 needs ETBF on BT848/878
165 */
166static void __devinit quirk_viaetbf(struct pci_dev *dev)
167{
168 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
169 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
170 pci_pci_problems |= PCIPCI_VIAETBF;
171 }
172}
173DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf );
174
175static void __devinit quirk_vsfx(struct pci_dev *dev)
176{
177 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
178 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
179 pci_pci_problems |= PCIPCI_VSFX;
180 }
181}
182DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx );
183
184/*
185 * Ali Magik requires workarounds to be used by the drivers
186 * that DMA to AGP space. Latency must be set to 0xA and triton
187 * workaround applied too
188 * [Info kindly provided by ALi]
189 */
190static void __init quirk_alimagik(struct pci_dev *dev)
191{
192 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
193 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
194 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
195 }
196}
197DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik );
198DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik );
199
200/*
201 * Natoma has some interesting boundary conditions with Zoran stuff
202 * at least
203 */
204static void __devinit quirk_natoma(struct pci_dev *dev)
205{
206 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
207 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
208 pci_pci_problems |= PCIPCI_NATOMA;
209 }
210}
211DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma );
212DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma );
213DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma );
214DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma );
215DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma );
216DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma );
217
218/*
219 * This chip can cause PCI parity errors if config register 0xA0 is read
220 * while DMAs are occurring.
221 */
222static void __devinit quirk_citrine(struct pci_dev *dev)
223{
224 dev->cfg_size = 0xA0;
225}
226DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine );
227
228/*
229 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
230 * If it's needed, re-allocate the region.
231 */
232static void __devinit quirk_s3_64M(struct pci_dev *dev)
233{
234 struct resource *r = &dev->resource[0];
235
236 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
237 r->start = 0;
238 r->end = 0x3ffffff;
239 }
240}
241DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M );
242DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M );
243
244static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region, unsigned size, int nr)
245{
246 region &= ~(size-1);
247 if (region) {
248 struct resource *res = dev->resource + nr;
249
250 res->name = pci_name(dev);
251 res->start = region;
252 res->end = region + size - 1;
253 res->flags = IORESOURCE_IO;
254 pci_claim_resource(dev, nr);
255 }
256}
257
258/*
259 * ATI Northbridge setups MCE the processor if you even
260 * read somewhere between 0x3b0->0x3bb or read 0x3d3
261 */
262static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
263{
264 printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n");
265 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
266 request_region(0x3b0, 0x0C, "RadeonIGP");
267 request_region(0x3d3, 0x01, "RadeonIGP");
268}
269DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce );
270
271/*
272 * Let's make the southbridge information explicit instead
273 * of having to worry about people probing the ACPI areas,
274 * for example.. (Yes, it happens, and if you read the wrong
275 * ACPI register it will put the machine to sleep with no
276 * way of waking it up again. Bummer).
277 *
278 * ALI M7101: Two IO regions pointed to by words at
279 * 0xE0 (64 bytes of ACPI registers)
280 * 0xE2 (32 bytes of SMB registers)
281 */
282static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
283{
284 u16 region;
285
286 pci_read_config_word(dev, 0xE0, &region);
287 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES);
288 pci_read_config_word(dev, 0xE2, &region);
289 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1);
290}
291DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi );
292
293/*
294 * PIIX4 ACPI: Two IO regions pointed to by longwords at
295 * 0x40 (64 bytes of ACPI registers)
296 * 0x90 (32 bytes of SMB registers)
297 */
298static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
299{
300 u32 region;
301
302 pci_read_config_dword(dev, 0x40, &region);
303 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES);
304 pci_read_config_dword(dev, 0x90, &region);
305 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1);
306}
307DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi );
308
309/*
310 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
311 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
312 * 0x58 (64 bytes of GPIO I/O space)
313 */
314static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
315{
316 u32 region;
317
318 pci_read_config_dword(dev, 0x40, &region);
319 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES);
320
321 pci_read_config_dword(dev, 0x58, &region);
322 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1);
323}
324DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi );
325DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi );
326DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi );
327DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi );
328DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi );
329DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi );
330DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi );
331DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi );
332DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi );
3aa8c4fe 333DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi );
1da177e4
LT		 334
335/*
336 * VIA ACPI: One IO region pointed to by longword at
337 * 0x48 or 0x20 (256 bytes of ACPI registers)
338 */
339static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
340{
341 u8 rev;
342 u32 region;
343
344 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
345 if (rev & 0x10) {
346 pci_read_config_dword(dev, 0x48, &region);
347 region &= PCI_BASE_ADDRESS_IO_MASK;
348 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES);
349 }
350}
351DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi );
352
353/*
354 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
355 * 0x48 (256 bytes of ACPI registers)
356 * 0x70 (128 bytes of hardware monitoring register)
357 * 0x90 (16 bytes of SMB registers)
358 */
359static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
360{
361 u16 hm;
362 u32 smb;
363
364 quirk_vt82c586_acpi(dev);
365
366 pci_read_config_word(dev, 0x70, &hm);
367 hm &= PCI_BASE_ADDRESS_IO_MASK;
368 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1);
369
370 pci_read_config_dword(dev, 0x90, &smb);
371 smb &= PCI_BASE_ADDRESS_IO_MASK;
372 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2);
373}
374DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi );
375
6d85f29b
IK		 376/*
377 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
378 * 0x88 (128 bytes of power management registers)
379 * 0xd0 (16 bytes of SMB registers)
380 */
381static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
382{
383 u16 pm, smb;
384
385 pci_read_config_word(dev, 0x88, &pm);
386 pm &= PCI_BASE_ADDRESS_IO_MASK;
387 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES);
388
389 pci_read_config_word(dev, 0xd0, &smb);
390 smb &= PCI_BASE_ADDRESS_IO_MASK;
391 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1);
392}
393DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
394
1da177e4
LT		 395
396#ifdef CONFIG_X86_IO_APIC
397
398#include <asm/io_apic.h>
399
400/*
401 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
402 * devices to the external APIC.
403 *
404 * TODO: When we have device-specific interrupt routers,
405 * this code will go away from quirks.
406 */
407static void __devinit quirk_via_ioapic(struct pci_dev *dev)
408{
409 u8 tmp;
410
411 if (nr_ioapics < 1)
412 tmp = 0; /* nothing routed to external APIC */
413 else
414 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
415
416 printk(KERN_INFO "PCI: %sbling Via external APIC routing\n",
417 tmp == 0 ? "Disa" : "Ena");
418
419 /* Offset 0x58: External APIC IRQ output control */
420 pci_write_config_byte (dev, 0x58, tmp);
421}
422DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic );
423
424/*
425 * The AMD io apic can hang the box when an apic irq is masked.
426 * We check all revs >= B0 (yet not in the pre production!) as the bug
427 * is currently marked NoFix
428 *
429 * We have multiple reports of hangs with this chipset that went away with
430 * noapic specified. For the moment we assume its the errata. We may be wrong
431 * of course. However the advice is demonstrably good even if so..
432 */
433static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
434{
435 u8 rev;
436
437 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
438 if (rev >= 0x02) {
439 printk(KERN_WARNING "I/O APIC: AMD Errata #22 may be present. In the event of instability try\n");
440 printk(KERN_WARNING " : booting with the \"noapic\" option.\n");
441 }
442}
443DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic );
444
445static void __init quirk_ioapic_rmw(struct pci_dev *dev)
446{
447 if (dev->devfn == 0 && dev->bus->number == 0)
448 sis_apic_bug = 1;
449}
450DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw );
451
452int pci_msi_quirk;
453
454#define AMD8131_revA0 0x01
455#define AMD8131_revB0 0x11
456#define AMD8131_MISC 0x40
457#define AMD8131_NIOAMODE_BIT 0
458static void __init quirk_amd_8131_ioapic(struct pci_dev *dev)
459{
460 unsigned char revid, tmp;
461
462 pci_msi_quirk = 1;
463 printk(KERN_WARNING "PCI: MSI quirk detected. pci_msi_quirk set.\n");
464
465 if (nr_ioapics == 0)
466 return;
467
468 pci_read_config_byte(dev, PCI_REVISION_ID, &revid);
469 if (revid == AMD8131_revA0 || revid == AMD8131_revB0) {
470 printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n");
471 pci_read_config_byte( dev, AMD8131_MISC, &tmp);
472 tmp &= ~(1 << AMD8131_NIOAMODE_BIT);
473 pci_write_config_byte( dev, AMD8131_MISC, tmp);
474 }
475}
476DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_APIC, quirk_amd_8131_ioapic );
477
1e062767
NS		 478static void __init quirk_svw_msi(struct pci_dev *dev)
479{
480 pci_msi_quirk = 1;
481 printk(KERN_WARNING "PCI: MSI quirk detected. pci_msi_quirk set.\n");
482}
483DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_svw_msi );
1da177e4
LT		 484#endif /* CONFIG_X86_IO_APIC */
485
486
1da177e4
LT		 487/*
488 * FIXME: it is questionable that quirk_via_acpi
489 * is needed. It shows up as an ISA bridge, and does not
490 * support the PCI_INTERRUPT_LINE register at all. Therefore
491 * it seems like setting the pci_dev's 'irq' to the
492 * value of the ACPI SCI interrupt is only done for convenience.
493 * -jgarzik
494 */
495static void __devinit quirk_via_acpi(struct pci_dev *d)
496{
497 /*
498 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
499 */
500 u8 irq;
501 pci_read_config_byte(d, 0x42, &irq);
502 irq &= 0xf;
503 if (irq && (irq != 2))
504 d->irq = irq;
505}
506DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi );
507DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi );
508
93cffffa
BH		 509/*
510 * Via 686A/B: The PCI_INTERRUPT_LINE register for the on-chip
511 * devices, USB0/1, AC97, MC97, and ACPI, has an unusual feature:
512 * when written, it makes an internal connection to the PIC.
513 * For these devices, this register is defined to be 4 bits wide.
514 * Normally this is fine. However for IO-APIC motherboards, or
515 * non-x86 architectures (yes Via exists on PPC among other places),
516 * we must mask the PCI_INTERRUPT_LINE value versus 0xf to get
517 * interrupts delivered properly.
518 */
519static void quirk_via_irq(struct pci_dev *dev)
25be5e6c
LB		 520{
521 u8 irq, new_irq;
522
25be5e6c
LB		 523 new_irq = dev->irq & 0xf;
524 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
525 if (new_irq != irq) {
93cffffa 526 printk(KERN_INFO "PCI: Via IRQ fixup for %s, from %d to %d\n",
25be5e6c
LB		 527 pci_name(dev), irq, new_irq);
528 udelay(15); /* unknown if delay really needed */
529 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
530 }
531}
93cffffa 532DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_irq);
25be5e6c 533
1da177e4
LT		 534/*
535 * PIIX3 USB: We have to disable USB interrupts that are
536 * hardwired to PIRQD# and may be shared with an
537 * external device.
538 *
539 * Legacy Support Register (LEGSUP):
540 * bit13: USB PIRQ Enable (USBPIRQDEN),
541 * bit4: Trap/SMI On IRQ Enable (USBSMIEN).
542 *
543 * We mask out all r/wc bits, too.
544 */
545static void __devinit quirk_piix3_usb(struct pci_dev *dev)
546{
547 u16 legsup;
548
549 pci_read_config_word(dev, 0xc0, &legsup);
550 legsup &= 0x50ef;
551 pci_write_config_word(dev, 0xc0, legsup);
552}
553DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_2, quirk_piix3_usb );
554DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_2, quirk_piix3_usb );
555
556/*
557 * VIA VT82C598 has its device ID settable and many BIOSes
558 * set it to the ID of VT82C597 for backward compatibility.
559 * We need to switch it off to be able to recognize the real
560 * type of the chip.
561 */
562static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
563{
564 pci_write_config_byte(dev, 0xfc, 0);
565 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
566}
567DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id );
568
569/*
570 * CardBus controllers have a legacy base address that enables them
571 * to respond as i82365 pcmcia controllers. We don't want them to
572 * do this even if the Linux CardBus driver is not loaded, because
573 * the Linux i82365 driver does not (and should not) handle CardBus.
574 */
575static void __devinit quirk_cardbus_legacy(struct pci_dev *dev)
576{
577 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
578 return;
579 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
580}
581DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
582
583/*
584 * Following the PCI ordering rules is optional on the AMD762. I'm not
585 * sure what the designers were smoking but let's not inhale...
586 *
587 * To be fair to AMD, it follows the spec by default, its BIOS people
588 * who turn it off!
589 */
590static void __devinit quirk_amd_ordering(struct pci_dev *dev)
591{
592 u32 pcic;
593 pci_read_config_dword(dev, 0x4C, &pcic);
594 if ((pcic&6)!=6) {
595 pcic |= 6;
596 printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n");
597 pci_write_config_dword(dev, 0x4C, pcic);
598 pci_read_config_dword(dev, 0x84, &pcic);
599 pcic |= (1<<23); /* Required in this mode */
600 pci_write_config_dword(dev, 0x84, pcic);
601 }
602}
603DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering );
604
605/*
606 * DreamWorks provided workaround for Dunord I-3000 problem
607 *
608 * This card decodes and responds to addresses not apparently
609 * assigned to it. We force a larger allocation to ensure that
610 * nothing gets put too close to it.
611 */
612static void __devinit quirk_dunord ( struct pci_dev * dev )
613{
614 struct resource *r = &dev->resource [1];
615 r->start = 0;
616 r->end = 0xffffff;
617}
618DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord );
619
620/*
621 * i82380FB mobile docking controller: its PCI-to-PCI bridge
622 * is subtractive decoding (transparent), and does indicate this
623 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
624 * instead of 0x01.
625 */
626static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
627{
628 dev->transparent = 1;
629}
630DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge );
631DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge );
632
633/*
634 * Common misconfiguration of the MediaGX/Geode PCI master that will
635 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
636 * datasheets found at http://www.national.com/ds/GX for info on what
637 * these bits do. <christer@weinigel.se>
638 */
639static void __init quirk_mediagx_master(struct pci_dev *dev)
640{
641 u8 reg;
642 pci_read_config_byte(dev, 0x41, &reg);
643 if (reg & 2) {
644 reg &= ~2;
645 printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
646 pci_write_config_byte(dev, 0x41, reg);
647 }
648}
649DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master );
650
651/*
652 * As per PCI spec, ignore base address registers 0-3 of the IDE controllers
653 * running in Compatible mode (bits 0 and 2 in the ProgIf for primary and
654 * secondary channels respectively). If the device reports Compatible mode
655 * but does use BAR0-3 for address decoding, we assume that firmware has
656 * programmed these BARs with standard values (0x1f0,0x3f4 and 0x170,0x374).
657 * Exceptions (if they exist) must be handled in chip/architecture specific
658 * fixups.
659 *
660 * Note: for non x86 people. You may need an arch specific quirk to handle
661 * moving IDE devices to native mode as well. Some plug in card devices power
662 * up in compatible mode and assume the BIOS will adjust them.
663 *
664 * Q: should we load the 0x1f0,0x3f4 into the registers or zap them as
665 * we do now ? We don't want is pci_enable_device to come along
666 * and assign new resources. Both approaches work for that.
667 */
668static void __devinit quirk_ide_bases(struct pci_dev *dev)
669{
670 struct resource *res;
671 int first_bar = 2, last_bar = 0;
672
673 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
674 return;
675
676 res = &dev->resource[0];
677
678 /* primary channel: ProgIf bit 0, BAR0, BAR1 */
679 if (!(dev->class & 1) && (res[0].flags || res[1].flags)) {
680 res[0].start = res[0].end = res[0].flags = 0;
681 res[1].start = res[1].end = res[1].flags = 0;
682 first_bar = 0;
683 last_bar = 1;
684 }
685
686 /* secondary channel: ProgIf bit 2, BAR2, BAR3 */
687 if (!(dev->class & 4) && (res[2].flags || res[3].flags)) {
688 res[2].start = res[2].end = res[2].flags = 0;
689 res[3].start = res[3].end = res[3].flags = 0;
690 last_bar = 3;
691 }
692
693 if (!last_bar)
694 return;
695
696 printk(KERN_INFO "PCI: Ignoring BAR%d-%d of IDE controller %s\n",
697 first_bar, last_bar, pci_name(dev));
698}
699DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_ide_bases);
700
701/*
702 * Ensure C0 rev restreaming is off. This is normally done by
703 * the BIOS but in the odd case it is not the results are corruption
704 * hence the presence of a Linux check
705 */
706static void __init quirk_disable_pxb(struct pci_dev *pdev)
707{
708 u16 config;
709 u8 rev;
710
711 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
712 if (rev != 0x04) /* Only C0 requires this */
713 return;
714 pci_read_config_word(pdev, 0x40, &config);
715 if (config & (1<<6)) {
716 config &= ~(1<<6);
717 pci_write_config_word(pdev, 0x40, config);
718 printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n");
719 }
720}
721DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb );
722
1da177e4
LT		 723
724/*
725 * Serverworks CSB5 IDE does not fully support native mode
726 */
727static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
728{
729 u8 prog;
730 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
731 if (prog & 5) {
732 prog &= ~5;
733 pdev->class &= ~5;
734 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
735 /* need to re-assign BARs for compat mode */
736 quirk_ide_bases(pdev);
737 }
738}
739DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide );
740
741/*
742 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
743 */
744static void __init quirk_ide_samemode(struct pci_dev *pdev)
745{
746 u8 prog;
747
748 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
749
750 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
751 printk(KERN_INFO "PCI: IDE mode mismatch; forcing legacy mode\n");
752 prog &= ~5;
753 pdev->class &= ~5;
754 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
755 /* need to re-assign BARs for compat mode */
756 quirk_ide_bases(pdev);
757 }
758}
759DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
760
761/* This was originally an Alpha specific thing, but it really fits here.
762 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
763 */
764static void __init quirk_eisa_bridge(struct pci_dev *dev)
765{
766 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
767}
768DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge );
769
770/*
771 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
772 * is not activated. The myth is that Asus said that they do not want the
773 * users to be irritated by just another PCI Device in the Win98 device
774 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
775 * package 2.7.0 for details)
776 *
777 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
778 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
779 * becomes necessary to do this tweak in two steps -- I've chosen the Host
780 * bridge as trigger.
781 */
782static int __initdata asus_hides_smbus = 0;
783
784static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
785{
786 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
787 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
788 switch(dev->subsystem_device) {
a00db371 789 case 0x8025: /* P4B-LX */
1da177e4
LT		 790 case 0x8070: /* P4B */
791 case 0x8088: /* P4B533 */
792 case 0x1626: /* L3C notebook */
793 asus_hides_smbus = 1;
794 }
795 if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
796 switch(dev->subsystem_device) {
797 case 0x80b1: /* P4GE-V */
798 case 0x80b2: /* P4PE */
799 case 0x8093: /* P4B533-V */
800 asus_hides_smbus = 1;
801 }
802 if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
803 switch(dev->subsystem_device) {
804 case 0x8030: /* P4T533 */
805 asus_hides_smbus = 1;
806 }
807 if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
808 switch (dev->subsystem_device) {
809 case 0x8070: /* P4G8X Deluxe */
810 asus_hides_smbus = 1;
811 }
812 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
813 switch (dev->subsystem_device) {
814 case 0x1751: /* M2N notebook */
815 case 0x1821: /* M5N notebook */
816 asus_hides_smbus = 1;
817 }
818 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
819 switch (dev->subsystem_device) {
820 case 0x184b: /* W1N notebook */
821 case 0x186a: /* M6Ne notebook */
822 asus_hides_smbus = 1;
823 }
824 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
825 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
826 switch(dev->subsystem_device) {
827 case 0x088C: /* HP Compaq nc8000 */
828 case 0x0890: /* HP Compaq nc6000 */
829 asus_hides_smbus = 1;
830 }
831 if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
832 switch (dev->subsystem_device) {
833 case 0x12bc: /* HP D330L */
834 asus_hides_smbus = 1;
835 }
836 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_TOSHIBA)) {
837 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
838 switch(dev->subsystem_device) {
839 case 0x0001: /* Toshiba Satellite A40 */
840 asus_hides_smbus = 1;
841 }
e96e2f14
DG		 842 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
843 switch(dev->subsystem_device) {
844 case 0x0001: /* Toshiba Tecra M2 */
845 asus_hides_smbus = 1;
846 }
1da177e4
LT		 847 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
848 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
849 switch(dev->subsystem_device) {
850 case 0xC00C: /* Samsung P35 notebook */
851 asus_hides_smbus = 1;
852 }
853 }
854}
855DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge );
856DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge );
857DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge );
858DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge );
859DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge );
860DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge );
861DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge );
862
863static void __init asus_hides_smbus_lpc(struct pci_dev *dev)
864{
865 u16 val;
866
867 if (likely(!asus_hides_smbus))
868 return;
869
870 pci_read_config_word(dev, 0xF2, &val);
871 if (val & 0x8) {
872 pci_write_config_word(dev, 0xF2, val & (~0x8));
873 pci_read_config_word(dev, 0xF2, &val);
874 if (val & 0x8)
875 printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
876 else
877 printk(KERN_INFO "PCI: Enabled i801 SMBus device\n");
878 }
879}
880DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc );
881DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc );
882DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc );
883DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc );
884DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc );
885
886/*
887 * SiS 96x south bridge: BIOS typically hides SMBus device...
888 */
889static void __init quirk_sis_96x_smbus(struct pci_dev *dev)
890{
891 u8 val = 0;
892 printk(KERN_INFO "Enabling SiS 96x SMBus.\n");
893 pci_read_config_byte(dev, 0x77, &val);
894 pci_write_config_byte(dev, 0x77, val & ~0x10);
895 pci_read_config_byte(dev, 0x77, &val);
896}
897
898
899#define UHCI_USBLEGSUP 0xc0 /* legacy support */
900#define UHCI_USBCMD 0 /* command register */
901#define UHCI_USBSTS 2 /* status register */
902#define UHCI_USBINTR 4 /* interrupt register */
903#define UHCI_USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */
904#define UHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */
905#define UHCI_USBCMD_GRESET (1 << 2) /* Global reset */
906#define UHCI_USBCMD_CONFIGURE (1 << 6) /* config semaphore */
907#define UHCI_USBSTS_HALTED (1 << 5) /* HCHalted bit */
908
909#define OHCI_CONTROL 0x04
910#define OHCI_CMDSTATUS 0x08
911#define OHCI_INTRSTATUS 0x0c
912#define OHCI_INTRENABLE 0x10
913#define OHCI_INTRDISABLE 0x14
914#define OHCI_OCR (1 << 3) /* ownership change request */
915#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
916#define OHCI_INTR_OC (1 << 30) /* ownership change */
917
918#define EHCI_HCC_PARAMS 0x08 /* extended capabilities */
919#define EHCI_USBCMD 0 /* command register */
920#define EHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */
921#define EHCI_USBSTS 4 /* status register */
922#define EHCI_USBSTS_HALTED (1 << 12) /* HCHalted bit */
923#define EHCI_USBINTR 8 /* interrupt register */
924#define EHCI_USBLEGSUP 0 /* legacy support register */
925#define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */
926#define EHCI_USBLEGSUP_OS (1 << 24) /* OS semaphore */
927#define EHCI_USBLEGCTLSTS 4 /* legacy control/status */
928#define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */
929
930int usb_early_handoff __devinitdata = 0;
931static int __init usb_handoff_early(char *str)
932{
933 usb_early_handoff = 1;
934 return 0;
935}
936__setup("usb-handoff", usb_handoff_early);
937
938static void __devinit quirk_usb_handoff_uhci(struct pci_dev *pdev)
939{
940 unsigned long base = 0;
941 int wait_time, delta;
942 u16 val, sts;
943 int i;
944
945 for (i = 0; i < PCI_ROM_RESOURCE; i++)
946 if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) {
947 base = pci_resource_start(pdev, i);
948 break;
949 }
950
951 if (!base)
952 return;
953
954 /*
955 * stop controller
956 */
957 sts = inw(base + UHCI_USBSTS);
958 val = inw(base + UHCI_USBCMD);
959 val &= ~(u16)(UHCI_USBCMD_RUN | UHCI_USBCMD_CONFIGURE);
960 outw(val, base + UHCI_USBCMD);
961
962 /*
963 * wait while it stops if it was running
964 */
965 if ((sts & UHCI_USBSTS_HALTED) == 0)
966 {
967 wait_time = 1000;
968 delta = 100;
969
970 do {
971 outw(0x1f, base + UHCI_USBSTS);
972 udelay(delta);
973 wait_time -= delta;
974 val = inw(base + UHCI_USBSTS);
975 if (val & UHCI_USBSTS_HALTED)
976 break;
977 } while (wait_time > 0);
978 }
979
980 /*
981 * disable interrupts & legacy support
982 */
983 outw(0, base + UHCI_USBINTR);
984 outw(0x1f, base + UHCI_USBSTS);
985 pci_read_config_word(pdev, UHCI_USBLEGSUP, &val);
986 if (val & 0xbf)
987 pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_DEFAULT);
988
989}
990
991static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev)
992{
993 void __iomem *base;
994 int wait_time;
995
996 base = ioremap_nocache(pci_resource_start(pdev, 0),
997 pci_resource_len(pdev, 0));
998 if (base == NULL) return;
999
1000 if (readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
1001 wait_time = 500; /* 0.5 seconds */
1002 writel(OHCI_INTR_OC, base + OHCI_INTRENABLE);
1003 writel(OHCI_OCR, base + OHCI_CMDSTATUS);
1004 while (wait_time > 0 &&
1005 readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
1006 wait_time -= 10;
1007 msleep(10);
1008 }
1009 }
1010
1011 /*
1012 * disable interrupts
1013 */
1014 writel(~(u32)0, base + OHCI_INTRDISABLE);
1015 writel(~(u32)0, base + OHCI_INTRSTATUS);
1016
1017 iounmap(base);
1018}
1019
1020static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev)
1021{
1022 int wait_time, delta;
1023 void __iomem *base, *op_reg_base;
1024 u32 hcc_params, val, temp;
1025 u8 cap_length;
1026
1027 base = ioremap_nocache(pci_resource_start(pdev, 0),
1028 pci_resource_len(pdev, 0));
1029 if (base == NULL) return;
1030
1031 cap_length = readb(base);
1032 op_reg_base = base + cap_length;
1033 hcc_params = readl(base + EHCI_HCC_PARAMS);
1034 hcc_params = (hcc_params >> 8) & 0xff;
1035 if (hcc_params) {
1036 pci_read_config_dword(pdev,
1037 hcc_params + EHCI_USBLEGSUP,
1038 &val);
1039 if (((val & 0xff) == 1) && (val & EHCI_USBLEGSUP_BIOS)) {
1040 /*
1041 * Ok, BIOS is in smm mode, try to hand off...
1042 */
1043 pci_read_config_dword(pdev,
1044 hcc_params + EHCI_USBLEGCTLSTS,
1045 &temp);
1046 pci_write_config_dword(pdev,
1047 hcc_params + EHCI_USBLEGCTLSTS,
1048 temp | EHCI_USBLEGCTLSTS_SOOE);
1049 val |= EHCI_USBLEGSUP_OS;
1050 pci_write_config_dword(pdev,
1051 hcc_params + EHCI_USBLEGSUP,
1052 val);
1053
1054 wait_time = 500;
1055 do {
1056 msleep(10);
1057 wait_time -= 10;
1058 pci_read_config_dword(pdev,
1059 hcc_params + EHCI_USBLEGSUP,
1060 &val);
1061 } while (wait_time && (val & EHCI_USBLEGSUP_BIOS));
1062 if (!wait_time) {
1063 /*
1064 * well, possibly buggy BIOS...
1065 */
1066 printk(KERN_WARNING "EHCI early BIOS handoff "
1067 "failed (BIOS bug ?)\n");
1068 pci_write_config_dword(pdev,
1069 hcc_params + EHCI_USBLEGSUP,
1070 EHCI_USBLEGSUP_OS);
1071 pci_write_config_dword(pdev,
1072 hcc_params + EHCI_USBLEGCTLSTS,
1073 0);
1074 }
1075 }
1076 }
1077
1078 /*
1079 * halt EHCI & disable its interrupts in any case
1080 */
1081 val = readl(op_reg_base + EHCI_USBSTS);
1082 if ((val & EHCI_USBSTS_HALTED) == 0) {
1083 val = readl(op_reg_base + EHCI_USBCMD);
1084 val &= ~EHCI_USBCMD_RUN;
1085 writel(val, op_reg_base + EHCI_USBCMD);
1086
1087 wait_time = 2000;
1088 delta = 100;
1089 do {
1090 writel(0x3f, op_reg_base + EHCI_USBSTS);
1091 udelay(delta);
1092 wait_time -= delta;
1093 val = readl(op_reg_base + EHCI_USBSTS);
1094 if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) {
1095 break;
1096 }
1097 } while (wait_time > 0);
1098 }
1099 writel(0, op_reg_base + EHCI_USBINTR);
1100 writel(0x3f, op_reg_base + EHCI_USBSTS);
1101
1102 iounmap(base);
1103
1104 return;
1105}
1106
1107
1108
1109static void __devinit quirk_usb_early_handoff(struct pci_dev *pdev)
1110{
1111 if (!usb_early_handoff)
1112 return;
1113
1114 if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x00)) { /* UHCI */
1115 quirk_usb_handoff_uhci(pdev);
1116 } else if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x10)) { /* OHCI */
1117 quirk_usb_handoff_ohci(pdev);
1118 } else if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x20)) { /* EHCI */
1119 quirk_usb_disable_ehci(pdev);
1120 }
1121
1122 return;
1123}
1124DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_usb_early_handoff);
1125
1126/*
1127 * ... This is further complicated by the fact that some SiS96x south
1128 * bridges pretend to be 85C503/5513 instead. In that case see if we
1129 * spotted a compatible north bridge to make sure.
1130 * (pci_find_device doesn't work yet)
1131 *
1132 * We can also enable the sis96x bit in the discovery register..
1133 */
1134static int __devinitdata sis_96x_compatible = 0;
1135
1136#define SIS_DETECT_REGISTER 0x40
1137
1138static void __init quirk_sis_503(struct pci_dev *dev)
1139{
1140 u8 reg;
1141 u16 devid;
1142
1143 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1144 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1145 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1146 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1147 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1148 return;
1149 }
1150
1151 /* Make people aware that we changed the config.. */
1152 printk(KERN_WARNING "Uncovering SIS%x that hid as a SIS503 (compatible=%d)\n", devid, sis_96x_compatible);
1153
1154 /*
1155 * Ok, it now shows up as a 96x.. The 96x quirks are after
1156 * the 503 quirk in the quirk table, so they'll automatically
1157 * run and enable things like the SMBus device
1158 */
1159 dev->device = devid;
1160}
1161
1162static void __init quirk_sis_96x_compatible(struct pci_dev *dev)
1163{
1164 sis_96x_compatible = 1;
1165}
1166DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_645, quirk_sis_96x_compatible );
1167DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_646, quirk_sis_96x_compatible );
1168DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_648, quirk_sis_96x_compatible );
1169DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_650, quirk_sis_96x_compatible );
1170DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_651, quirk_sis_96x_compatible );
1171DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_735, quirk_sis_96x_compatible );
1172
1173DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 );
1174
1175DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus );
1176DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus );
1177DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus );
1178DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus );
1179
1180#ifdef CONFIG_X86_IO_APIC
1181static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1182{
1183 int i;
1184
1185 if ((pdev->class >> 8) != 0xff00)
1186 return;
1187
1188 /* the first BAR is the location of the IO APIC...we must
1189 * not touch this (and it's already covered by the fixmap), so
1190 * forcibly insert it into the resource tree */
1191 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1192 insert_resource(&iomem_resource, &pdev->resource[0]);
1193
1194 /* The next five BARs all seem to be rubbish, so just clean
1195 * them out */
1196 for (i=1; i < 6; i++) {
1197 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1198 }
1199
1200}
1201DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic );
1202#endif
1203
1204#ifdef CONFIG_SCSI_SATA
1205static void __devinit quirk_intel_ide_combined(struct pci_dev *pdev)
1206{
1207 u8 prog, comb, tmp;
1208 int ich = 0;
1209
1210 /*
1211 * Narrow down to Intel SATA PCI devices.
1212 */
1213 switch (pdev->device) {
1214 /* PCI ids taken from drivers/scsi/ata_piix.c */
1215 case 0x24d1:
1216 case 0x24df:
1217 case 0x25a3:
1218 case 0x25b0:
1219 ich = 5;
1220 break;
1221 case 0x2651:
1222 case 0x2652:
1223 case 0x2653:
c368ca4e 1224 case 0x2680: /* ESB2 */
1da177e4
LT		 1225 ich = 6;
1226 break;
1227 case 0x27c0:
1228 case 0x27c4:
1229 ich = 7;
1230 break;
1231 default:
1232 /* we do not handle this PCI device */
1233 return;
1234 }
1235
1236 /*
1237 * Read combined mode register.
1238 */
1239 pci_read_config_byte(pdev, 0x90, &tmp); /* combined mode reg */
1240
1241 if (ich == 5) {
1242 tmp &= 0x6; /* interesting bits 2:1, PATA primary/secondary */
1243 if (tmp == 0x4) /* bits 10x */
1244 comb = (1 << 0); /* SATA port 0, PATA port 1 */
1245 else if (tmp == 0x6) /* bits 11x */
1246 comb = (1 << 2); /* PATA port 0, SATA port 1 */
1247 else
1248 return; /* not in combined mode */
1249 } else {
1250 WARN_ON((ich != 6) && (ich != 7));
1251 tmp &= 0x3; /* interesting bits 1:0 */
1252 if (tmp & (1 << 0))
1253 comb = (1 << 2); /* PATA port 0, SATA port 1 */
1254 else if (tmp & (1 << 1))
1255 comb = (1 << 0); /* SATA port 0, PATA port 1 */
1256 else
1257 return; /* not in combined mode */
1258 }
1259
1260 /*
1261 * Read programming interface register.
1262 * (Tells us if it's legacy or native mode)
1263 */
1264 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1265
1266 /* if SATA port is in native mode, we're ok. */
1267 if (prog & comb)
1268 return;
1269
1270 /* SATA port is in legacy mode. Reserve port so that
1271 * IDE driver does not attempt to use it. If request_region
1272 * fails, it will be obvious at boot time, so we don't bother
1273 * checking return values.
1274 */
1275 if (comb == (1 << 0))
1276 request_region(0x1f0, 8, "libata"); /* port 0 */
1277 else
1278 request_region(0x170, 8, "libata"); /* port 1 */
1279}
1280DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_intel_ide_combined );
1281#endif /* CONFIG_SCSI_SATA */
1282
1283
1284int pcie_mch_quirk;
1285
1286static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1287{
1288 pcie_mch_quirk = 1;
1289}
1290DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch );
1291DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch );
1292DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch );
1293
4602b88d
KA		 1294
1295/*
1296 * It's possible for the MSI to get corrupted if shpc and acpi
1297 * are used together on certain PXH-based systems.
1298 */
1299static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1300{
1301 disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI),
1302 PCI_CAP_ID_MSI);
1303 dev->no_msi = 1;
1304
1305 printk(KERN_WARNING "PCI: PXH quirk detected, "
1306 "disabling MSI for SHPC device\n");
1307}
1308DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1309DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1310DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1311DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1312DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1313
1314
1da177e4
LT		 1315static void __devinit quirk_netmos(struct pci_dev *dev)
1316{
1317 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1318 unsigned int num_serial = dev->subsystem_device & 0xf;
1319
1320 /*
1321 * These Netmos parts are multiport serial devices with optional
1322 * parallel ports. Even when parallel ports are present, they
1323 * are identified as class SERIAL, which means the serial driver
1324 * will claim them. To prevent this, mark them as class OTHER.
1325 * These combo devices should be claimed by parport_serial.
1326 *
1327 * The subdevice ID is of the form 0x00PS, where <P> is the number
1328 * of parallel ports and <S> is the number of serial ports.
1329 */
1330 switch (dev->device) {
1331 case PCI_DEVICE_ID_NETMOS_9735:
1332 case PCI_DEVICE_ID_NETMOS_9745:
1333 case PCI_DEVICE_ID_NETMOS_9835:
1334 case PCI_DEVICE_ID_NETMOS_9845:
1335 case PCI_DEVICE_ID_NETMOS_9855:
1336 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1337 num_parallel) {
1338 printk(KERN_INFO "PCI: Netmos %04x (%u parallel, "
1339 "%u serial); changing class SERIAL to OTHER "
1340 "(use parport_serial)\n",
1341 dev->device, num_parallel, num_serial);
1342 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1343 (dev->class & 0xff);
1344 }
1345 }
1346}
1347DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1348
1349static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end)
1350{
1351 while (f < end) {
1352 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
1353 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
1354 pr_debug("PCI: Calling quirk %p for %s\n", f->hook, pci_name(dev));
1355 f->hook(dev);
1356 }
1357 f++;
1358 }
1359}
1360
1361extern struct pci_fixup __start_pci_fixups_early[];
1362extern struct pci_fixup __end_pci_fixups_early[];
1363extern struct pci_fixup __start_pci_fixups_header[];
1364extern struct pci_fixup __end_pci_fixups_header[];
1365extern struct pci_fixup __start_pci_fixups_final[];
1366extern struct pci_fixup __end_pci_fixups_final[];
1367extern struct pci_fixup __start_pci_fixups_enable[];
1368extern struct pci_fixup __end_pci_fixups_enable[];
1369
1370
1371void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
1372{
1373 struct pci_fixup *start, *end;
1374
1375 switch(pass) {
1376 case pci_fixup_early:
1377 start = __start_pci_fixups_early;
1378 end = __end_pci_fixups_early;
1379 break;
1380
1381 case pci_fixup_header:
1382 start = __start_pci_fixups_header;
1383 end = __end_pci_fixups_header;
1384 break;
1385
1386 case pci_fixup_final:
1387 start = __start_pci_fixups_final;
1388 end = __end_pci_fixups_final;
1389 break;
1390
1391 case pci_fixup_enable:
1392 start = __start_pci_fixups_enable;
1393 end = __end_pci_fixups_enable;
1394 break;
1395
1396 default:
1397 /* stupid compiler warning, you would think with an enum... */
1398 return;
1399 }
1400 pci_do_fixups(dev, start, end);
1401}
1402
1403EXPORT_SYMBOL(pcie_mch_quirk);
1404#ifdef CONFIG_HOTPLUG
1405EXPORT_SYMBOL(pci_fixup_device);
1406#endif
kernel source for telekom puls (alcatel/mediatek)