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PCI: expose boot VGA device via sysfs.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / pci / quirks.c
CommitLineData
1da177e4
LT		 1/*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
7586269c
DB		 10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 *
1da177e4
LT		 13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
16 */
17
1da177e4
LT		 18#include <linux/types.h>
19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/init.h>
22#include <linux/delay.h>
25be5e6c 23#include <linux/acpi.h>
9f23ed3b 24#include <linux/kallsyms.h>
75e07fc3 25#include <linux/dmi.h>
649426ef 26#include <linux/pci-aspm.h>
32a9a682 27#include <linux/ioport.h>
bc56b9e0 28#include "pci.h"
1da177e4 29
3d137310
TP		 30int isa_dma_bridge_buggy;
31EXPORT_SYMBOL(isa_dma_bridge_buggy);
32int pci_pci_problems;
33EXPORT_SYMBOL(pci_pci_problems);
34int pcie_mch_quirk;
35EXPORT_SYMBOL(pcie_mch_quirk);
36
37#ifdef CONFIG_PCI_QUIRKS
32a9a682
YS		 38/*
39 * This quirk function disables the device and releases resources
40 * which is specified by kernel's boot parameter 'pci=resource_alignment='.
41 * It also rounds up size to specified alignment.
42 * Later on, the kernel will assign page-aligned memory resource back
43 * to that device.
44 */
45static void __devinit quirk_resource_alignment(struct pci_dev *dev)
46{
47 int i;
48 struct resource *r;
49 resource_size_t align, size;
50
51 if (!pci_is_reassigndev(dev))
52 return;
53
54 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
55 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
56 dev_warn(&dev->dev,
57 "Can't reassign resources to host bridge.\n");
58 return;
59 }
60
61 dev_info(&dev->dev, "Disabling device and release resources.\n");
62 pci_disable_device(dev);
63
64 align = pci_specified_resource_alignment(dev);
65 for (i=0; i < PCI_BRIDGE_RESOURCES; i++) {
66 r = &dev->resource[i];
67 if (!(r->flags & IORESOURCE_MEM))
68 continue;
69 size = resource_size(r);
70 if (size < align) {
71 size = align;
72 dev_info(&dev->dev,
73 "Rounding up size of resource #%d to %#llx.\n",
74 i, (unsigned long long)size);
75 }
76 r->end = size - 1;
77 r->start = 0;
78 }
79 /* Need to disable bridge's resource window,
80 * to enable the kernel to reassign new resource
81 * window later on.
82 */
83 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
84 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
85 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
86 r = &dev->resource[i];
87 if (!(r->flags & IORESOURCE_MEM))
88 continue;
89 r->end = resource_size(r) - 1;
90 r->start = 0;
91 }
92 pci_disable_bridge_window(dev);
93 }
94}
95DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_resource_alignment);
96
bd8481e1
DT		 97/* The Mellanox Tavor device gives false positive parity errors
98 * Mark this device with a broken_parity_status, to allow
99 * PCI scanning code to "skip" this now blacklisted device.
100 */
101static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
102{
103 dev->broken_parity_status = 1; /* This device gives false positives */
104}
105DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
106DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
107
1da177e4
LT		 108/* Deal with broken BIOS'es that neglect to enable passive release,
109 which can cause problems in combination with the 82441FX/PPro MTRRs */
1597cacb 110static void quirk_passive_release(struct pci_dev *dev)
1da177e4
LT		 111{
112 struct pci_dev *d = NULL;
113 unsigned char dlc;
114
115 /* We have to make sure a particular bit is set in the PIIX3
116 ISA bridge, so we have to go out and find it. */
117 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
118 pci_read_config_byte(d, 0x82, &dlc);
119 if (!(dlc & 1<<1)) {
999da9fd 120 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
1da177e4
LT		 121 dlc |= 1<<1;
122 pci_write_config_byte(d, 0x82, dlc);
123 }
124 }
125}
652c538e
AM		 126DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
127DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
1da177e4
LT		 128
129/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
130 but VIA don't answer queries. If you happen to have good contacts at VIA
131 ask them for me please -- Alan
132
133 This appears to be BIOS not version dependent. So presumably there is a
134 chipset level fix */
1da177e4
LT		 135
136static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
137{
138 if (!isa_dma_bridge_buggy) {
139 isa_dma_bridge_buggy=1;
f0fda801 140 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
1da177e4
LT		 141 }
142}
143 /*
144 * Its not totally clear which chipsets are the problematic ones
145 * We know 82C586 and 82C596 variants are affected.
146 */
652c538e
AM		 147DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
148DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
149DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
150DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
151DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
152DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
153DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
1da177e4 154
1da177e4
LT		 155/*
156 * Chipsets where PCI->PCI transfers vanish or hang
157 */
158static void __devinit quirk_nopcipci(struct pci_dev *dev)
159{
160 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
f0fda801 161 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
1da177e4
LT		 162 pci_pci_problems |= PCIPCI_FAIL;
163 }
164}
652c538e
AM		 165DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
166DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
236561e5
AC		 167
168static void __devinit quirk_nopciamd(struct pci_dev *dev)
169{
170 u8 rev;
171 pci_read_config_byte(dev, 0x08, &rev);
172 if (rev == 0x13) {
173 /* Erratum 24 */
f0fda801 174 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
236561e5
AC		 175 pci_pci_problems |= PCIAGP_FAIL;
176 }
177}
652c538e 178DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
1da177e4
LT		 179
180/*
181 * Triton requires workarounds to be used by the drivers
182 */
183static void __devinit quirk_triton(struct pci_dev *dev)
184{
185 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
f0fda801 186 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 187 pci_pci_problems |= PCIPCI_TRITON;
188 }
189}
652c538e
AM		 190DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
191DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
192DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
193DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
1da177e4
LT		 194
195/*
196 * VIA Apollo KT133 needs PCI latency patch
197 * Made according to a windows driver based patch by George E. Breese
198 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
199 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
200 * the info on which Mr Breese based his work.
201 *
202 * Updated based on further information from the site and also on
203 * information provided by VIA
204 */
1597cacb 205static void quirk_vialatency(struct pci_dev *dev)
1da177e4
LT		 206{
207 struct pci_dev *p;
1da177e4
LT		 208 u8 busarb;
209 /* Ok we have a potential problem chipset here. Now see if we have
210 a buggy southbridge */
211
212 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
213 if (p!=NULL) {
1da177e4
LT		 214 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
215 /* Check for buggy part revisions */
2b1afa87 216 if (p->revision < 0x40 || p->revision > 0x42)
1da177e4
LT		 217 goto exit;
218 } else {
219 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
220 if (p==NULL) /* No problem parts */
221 goto exit;
1da177e4 222 /* Check for buggy part revisions */
2b1afa87 223 if (p->revision < 0x10 || p->revision > 0x12)
1da177e4
LT		 224 goto exit;
225 }
226
227 /*
228 * Ok we have the problem. Now set the PCI master grant to
229 * occur every master grant. The apparent bug is that under high
230 * PCI load (quite common in Linux of course) you can get data
231 * loss when the CPU is held off the bus for 3 bus master requests
232 * This happens to include the IDE controllers....
233 *
234 * VIA only apply this fix when an SB Live! is present but under
235 * both Linux and Windows this isnt enough, and we have seen
236 * corruption without SB Live! but with things like 3 UDMA IDE
237 * controllers. So we ignore that bit of the VIA recommendation..
238 */
239
240 pci_read_config_byte(dev, 0x76, &busarb);
241 /* Set bit 4 and bi 5 of byte 76 to 0x01
242 "Master priority rotation on every PCI master grant */
243 busarb &= ~(1<<5);
244 busarb |= (1<<4);
245 pci_write_config_byte(dev, 0x76, busarb);
f0fda801 246 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
1da177e4
LT		 247exit:
248 pci_dev_put(p);
249}
652c538e
AM		 250DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
251DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
252DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
1597cacb 253/* Must restore this on a resume from RAM */
652c538e
AM		 254DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
255DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
256DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
1da177e4
LT		 257
258/*
259 * VIA Apollo VP3 needs ETBF on BT848/878
260 */
261static void __devinit quirk_viaetbf(struct pci_dev *dev)
262{
263 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
f0fda801 264 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 265 pci_pci_problems |= PCIPCI_VIAETBF;
266 }
267}
652c538e 268DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
1da177e4
LT		 269
270static void __devinit quirk_vsfx(struct pci_dev *dev)
271{
272 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
f0fda801 273 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 274 pci_pci_problems |= PCIPCI_VSFX;
275 }
276}
652c538e 277DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
1da177e4
LT		 278
279/*
280 * Ali Magik requires workarounds to be used by the drivers
281 * that DMA to AGP space. Latency must be set to 0xA and triton
282 * workaround applied too
283 * [Info kindly provided by ALi]
284 */
285static void __init quirk_alimagik(struct pci_dev *dev)
286{
287 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
f0fda801 288 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 289 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
290 }
291}
652c538e
AM		 292DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
293DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
1da177e4
LT		 294
295/*
296 * Natoma has some interesting boundary conditions with Zoran stuff
297 * at least
298 */
299static void __devinit quirk_natoma(struct pci_dev *dev)
300{
301 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
f0fda801 302 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 303 pci_pci_problems |= PCIPCI_NATOMA;
304 }
305}
652c538e
AM		 306DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
307DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
308DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
309DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
310DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
311DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
1da177e4
LT		 312
313/*
314 * This chip can cause PCI parity errors if config register 0xA0 is read
315 * while DMAs are occurring.
316 */
317static void __devinit quirk_citrine(struct pci_dev *dev)
318{
319 dev->cfg_size = 0xA0;
320}
652c538e 321DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
1da177e4
LT		 322
323/*
324 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
325 * If it's needed, re-allocate the region.
326 */
327static void __devinit quirk_s3_64M(struct pci_dev *dev)
328{
329 struct resource *r = &dev->resource[0];
330
331 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
332 r->start = 0;
333 r->end = 0x3ffffff;
334 }
335}
652c538e
AM		 336DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
337DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
1da177e4 338
6693e74a
LT		 339static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
340 unsigned size, int nr, const char *name)
1da177e4
LT		 341{
342 region &= ~(size-1);
343 if (region) {
085ae41f 344 struct pci_bus_region bus_region;
1da177e4
LT		 345 struct resource *res = dev->resource + nr;
346
347 res->name = pci_name(dev);
348 res->start = region;
349 res->end = region + size - 1;
350 res->flags = IORESOURCE_IO;
085ae41f
DM		 351
352 /* Convert from PCI bus to resource space. */
353 bus_region.start = res->start;
354 bus_region.end = res->end;
355 pcibios_bus_to_resource(dev, res, &bus_region);
356
1da177e4 357 pci_claim_resource(dev, nr);
f0fda801 358 dev_info(&dev->dev, "quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name);
1da177e4
LT		 359 }
360}
361
362/*
363 * ATI Northbridge setups MCE the processor if you even
364 * read somewhere between 0x3b0->0x3bb or read 0x3d3
365 */
366static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
367{
f0fda801 368 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
1da177e4
LT		 369 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
370 request_region(0x3b0, 0x0C, "RadeonIGP");
371 request_region(0x3d3, 0x01, "RadeonIGP");
372}
652c538e 373DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
1da177e4
LT		 374
375/*
376 * Let's make the southbridge information explicit instead
377 * of having to worry about people probing the ACPI areas,
378 * for example.. (Yes, it happens, and if you read the wrong
379 * ACPI register it will put the machine to sleep with no
380 * way of waking it up again. Bummer).
381 *
382 * ALI M7101: Two IO regions pointed to by words at
383 * 0xE0 (64 bytes of ACPI registers)
384 * 0xE2 (32 bytes of SMB registers)
385 */
386static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
387{
388 u16 region;
389
390 pci_read_config_word(dev, 0xE0, &region);
6693e74a 391 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
1da177e4 392 pci_read_config_word(dev, 0xE2, &region);
6693e74a 393 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
1da177e4 394}
652c538e 395DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
1da177e4 396
6693e74a
LT		 397static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
398{
399 u32 devres;
400 u32 mask, size, base;
401
402 pci_read_config_dword(dev, port, &devres);
403 if ((devres & enable) != enable)
404 return;
405 mask = (devres >> 16) & 15;
406 base = devres & 0xffff;
407 size = 16;
408 for (;;) {
409 unsigned bit = size >> 1;
410 if ((bit & mask) == bit)
411 break;
412 size = bit;
413 }
414 /*
415 * For now we only print it out. Eventually we'll want to
416 * reserve it (at least if it's in the 0x1000+ range), but
417 * let's get enough confirmation reports first.
418 */
419 base &= -size;
f0fda801 420 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
6693e74a
LT		 421}
422
423static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
424{
425 u32 devres;
426 u32 mask, size, base;
427
428 pci_read_config_dword(dev, port, &devres);
429 if ((devres & enable) != enable)
430 return;
431 base = devres & 0xffff0000;
432 mask = (devres & 0x3f) << 16;
433 size = 128 << 16;
434 for (;;) {
435 unsigned bit = size >> 1;
436 if ((bit & mask) == bit)
437 break;
438 size = bit;
439 }
440 /*
441 * For now we only print it out. Eventually we'll want to
442 * reserve it, but let's get enough confirmation reports first.
443 */
444 base &= -size;
f0fda801 445 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
6693e74a
LT		 446}
447
1da177e4
LT		 448/*
449 * PIIX4 ACPI: Two IO regions pointed to by longwords at
450 * 0x40 (64 bytes of ACPI registers)
08db2a70 451 * 0x90 (16 bytes of SMB registers)
6693e74a 452 * and a few strange programmable PIIX4 device resources.
1da177e4
LT		 453 */
454static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
455{
6693e74a 456 u32 region, res_a;
1da177e4
LT		 457
458 pci_read_config_dword(dev, 0x40, &region);
6693e74a 459 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
1da177e4 460 pci_read_config_dword(dev, 0x90, &region);
08db2a70 461 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
6693e74a
LT		 462
463 /* Device resource A has enables for some of the other ones */
464 pci_read_config_dword(dev, 0x5c, &res_a);
465
466 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
467 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
468
469 /* Device resource D is just bitfields for static resources */
470
471 /* Device 12 enabled? */
472 if (res_a & (1 << 29)) {
473 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
474 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
475 }
476 /* Device 13 enabled? */
477 if (res_a & (1 << 30)) {
478 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
479 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
480 }
481 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
482 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
1da177e4 483}
652c538e
AM		 484DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
485DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
1da177e4
LT		 486
487/*
488 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
489 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
490 * 0x58 (64 bytes of GPIO I/O space)
491 */
492static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
493{
494 u32 region;
495
496 pci_read_config_dword(dev, 0x40, &region);
6693e74a 497 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO");
1da177e4
LT		 498
499 pci_read_config_dword(dev, 0x58, &region);
6693e74a 500 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO");
1da177e4 501}
652c538e
AM		 502DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
503DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
504DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
505DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
506DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
507DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
508DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
509DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
510DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
511DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
1da177e4 512
894886e5 513static void __devinit ich6_lpc_acpi_gpio(struct pci_dev *dev)
2cea752f
RM		 514{
515 u32 region;
516
517 pci_read_config_dword(dev, 0x40, &region);
518 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO");
519
520 pci_read_config_dword(dev, 0x48, &region);
521 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
522}
894886e5
LT		 523
524static void __devinit ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
525{
526 u32 val;
527 u32 size, base;
528
529 pci_read_config_dword(dev, reg, &val);
530
531 /* Enabled? */
532 if (!(val & 1))
533 return;
534 base = val & 0xfffc;
535 if (dynsize) {
536 /*
537 * This is not correct. It is 16, 32 or 64 bytes depending on
538 * register D31:F0:ADh bits 5:4.
539 *
540 * But this gets us at least _part_ of it.
541 */
542 size = 16;
543 } else {
544 size = 128;
545 }
546 base &= ~(size-1);
547
548 /* Just print it out for now. We should reserve it after more debugging */
549 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
550}
551
552static void __devinit quirk_ich6_lpc(struct pci_dev *dev)
553{
554 /* Shared ACPI/GPIO decode with all ICH6+ */
555 ich6_lpc_acpi_gpio(dev);
556
557 /* ICH6-specific generic IO decode */
558 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
559 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
560}
561DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
562DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
563
564static void __devinit ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
565{
566 u32 val;
567 u32 mask, base;
568
569 pci_read_config_dword(dev, reg, &val);
570
571 /* Enabled? */
572 if (!(val & 1))
573 return;
574
575 /*
576 * IO base in bits 15:2, mask in bits 23:18, both
577 * are dword-based
578 */
579 base = val & 0xfffc;
580 mask = (val >> 16) & 0xfc;
581 mask |= 3;
582
583 /* Just print it out for now. We should reserve it after more debugging */
584 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
585}
586
587/* ICH7-10 has the same common LPC generic IO decode registers */
588static void __devinit quirk_ich7_lpc(struct pci_dev *dev)
589{
590 /* We share the common ACPI/DPIO decode with ICH6 */
591 ich6_lpc_acpi_gpio(dev);
592
593 /* And have 4 ICH7+ generic decodes */
594 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
595 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
596 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
597 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
598}
599DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
600DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
601DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
602DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
603DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
604DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
605DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
606DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
607DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
608DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
609DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
610DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
611DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
2cea752f 612
1da177e4
LT		 613/*
614 * VIA ACPI: One IO region pointed to by longword at
615 * 0x48 or 0x20 (256 bytes of ACPI registers)
616 */
617static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
618{
1da177e4
LT		 619 u32 region;
620
651472fb 621 if (dev->revision & 0x10) {
1da177e4
LT		 622 pci_read_config_dword(dev, 0x48, &region);
623 region &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 624 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
1da177e4
LT		 625 }
626}
652c538e 627DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
1da177e4
LT		 628
629/*
630 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
631 * 0x48 (256 bytes of ACPI registers)
632 * 0x70 (128 bytes of hardware monitoring register)
633 * 0x90 (16 bytes of SMB registers)
634 */
635static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
636{
637 u16 hm;
638 u32 smb;
639
640 quirk_vt82c586_acpi(dev);
641
642 pci_read_config_word(dev, 0x70, &hm);
643 hm &= PCI_BASE_ADDRESS_IO_MASK;
02f313b2 644 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
1da177e4
LT		 645
646 pci_read_config_dword(dev, 0x90, &smb);
647 smb &= PCI_BASE_ADDRESS_IO_MASK;
02f313b2 648 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
1da177e4 649}
652c538e 650DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
1da177e4 651
6d85f29b
IK		 652/*
653 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
654 * 0x88 (128 bytes of power management registers)
655 * 0xd0 (16 bytes of SMB registers)
656 */
657static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
658{
659 u16 pm, smb;
660
661 pci_read_config_word(dev, 0x88, &pm);
662 pm &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 663 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
6d85f29b
IK		 664
665 pci_read_config_word(dev, 0xd0, &smb);
666 smb &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 667 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
6d85f29b
IK		 668}
669DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
670
1da177e4
LT		 671
672#ifdef CONFIG_X86_IO_APIC
673
674#include <asm/io_apic.h>
675
676/*
677 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
678 * devices to the external APIC.
679 *
680 * TODO: When we have device-specific interrupt routers,
681 * this code will go away from quirks.
682 */
1597cacb 683static void quirk_via_ioapic(struct pci_dev *dev)
1da177e4
LT		 684{
685 u8 tmp;
686
687 if (nr_ioapics < 1)
688 tmp = 0; /* nothing routed to external APIC */
689 else
690 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
691
f0fda801 692 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
1da177e4
LT		 693 tmp == 0 ? "Disa" : "Ena");
694
695 /* Offset 0x58: External APIC IRQ output control */
696 pci_write_config_byte (dev, 0x58, tmp);
697}
652c538e 698DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
e1a2a51e 699DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
1da177e4 700
a1740913
KW		 701/*
702 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
703 * This leads to doubled level interrupt rates.
704 * Set this bit to get rid of cycle wastage.
705 * Otherwise uncritical.
706 */
1597cacb 707static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
a1740913
KW		 708{
709 u8 misc_control2;
710#define BYPASS_APIC_DEASSERT 8
711
712 pci_read_config_byte(dev, 0x5B, &misc_control2);
713 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
f0fda801 714 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
a1740913
KW		 715 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
716 }
717}
718DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
e1a2a51e 719DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
a1740913 720
1da177e4
LT		 721/*
722 * The AMD io apic can hang the box when an apic irq is masked.
723 * We check all revs >= B0 (yet not in the pre production!) as the bug
724 * is currently marked NoFix
725 *
726 * We have multiple reports of hangs with this chipset that went away with
236561e5 727 * noapic specified. For the moment we assume it's the erratum. We may be wrong
1da177e4
LT		 728 * of course. However the advice is demonstrably good even if so..
729 */
730static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
731{
44c10138 732 if (dev->revision >= 0x02) {
f0fda801 733 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
734 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
1da177e4
LT		 735 }
736}
652c538e 737DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
1da177e4
LT		 738
739static void __init quirk_ioapic_rmw(struct pci_dev *dev)
740{
741 if (dev->devfn == 0 && dev->bus->number == 0)
742 sis_apic_bug = 1;
743}
652c538e 744DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
1da177e4
LT		 745#endif /* CONFIG_X86_IO_APIC */
746
d556ad4b
PO		 747/*
748 * Some settings of MMRBC can lead to data corruption so block changes.
749 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
750 */
751static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev)
752{
aa288d4d 753 if (dev->subordinate && dev->revision <= 0x12) {
f0fda801 754 dev_info(&dev->dev, "AMD8131 rev %x detected; "
755 "disabling PCI-X MMRBC\n", dev->revision);
d556ad4b
PO		 756 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
757 }
758}
759DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
1da177e4 760
1da177e4
LT		 761/*
762 * FIXME: it is questionable that quirk_via_acpi
763 * is needed. It shows up as an ISA bridge, and does not
764 * support the PCI_INTERRUPT_LINE register at all. Therefore
765 * it seems like setting the pci_dev's 'irq' to the
766 * value of the ACPI SCI interrupt is only done for convenience.
767 * -jgarzik
768 */
769static void __devinit quirk_via_acpi(struct pci_dev *d)
770{
771 /*
772 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
773 */
774 u8 irq;
775 pci_read_config_byte(d, 0x42, &irq);
776 irq &= 0xf;
777 if (irq && (irq != 2))
778 d->irq = irq;
779}
652c538e
AM		 780DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
781DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
1da177e4 782
09d6029f
DD		 783
784/*
1597cacb 785 * VIA bridges which have VLink
09d6029f 786 */
1597cacb 787
c06bb5d4
JD		 788static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
789
790static void quirk_via_bridge(struct pci_dev *dev)
791{
792 /* See what bridge we have and find the device ranges */
793 switch (dev->device) {
794 case PCI_DEVICE_ID_VIA_82C686:
cb7468ef
JD		 795 /* The VT82C686 is special, it attaches to PCI and can have
796 any device number. All its subdevices are functions of
797 that single device. */
798 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
799 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
c06bb5d4
JD		 800 break;
801 case PCI_DEVICE_ID_VIA_8237:
802 case PCI_DEVICE_ID_VIA_8237A:
803 via_vlink_dev_lo = 15;
804 break;
805 case PCI_DEVICE_ID_VIA_8235:
806 via_vlink_dev_lo = 16;
807 break;
808 case PCI_DEVICE_ID_VIA_8231:
809 case PCI_DEVICE_ID_VIA_8233_0:
810 case PCI_DEVICE_ID_VIA_8233A:
811 case PCI_DEVICE_ID_VIA_8233C_0:
812 via_vlink_dev_lo = 17;
813 break;
814 }
815}
816DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
817DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
818DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
819DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
820DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
821DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
822DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
823DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
09d6029f 824
1597cacb
AC		 825/**
826 * quirk_via_vlink - VIA VLink IRQ number update
827 * @dev: PCI device
828 *
829 * If the device we are dealing with is on a PIC IRQ we need to
830 * ensure that the IRQ line register which usually is not relevant
831 * for PCI cards, is actually written so that interrupts get sent
c06bb5d4
JD		 832 * to the right place.
833 * We only do this on systems where a VIA south bridge was detected,
834 * and only for VIA devices on the motherboard (see quirk_via_bridge
835 * above).
1597cacb
AC		 836 */
837
838static void quirk_via_vlink(struct pci_dev *dev)
25be5e6c
LB		 839{
840 u8 irq, new_irq;
841
c06bb5d4
JD		 842 /* Check if we have VLink at all */
843 if (via_vlink_dev_lo == -1)
09d6029f
DD		 844 return;
845
846 new_irq = dev->irq;
847
848 /* Don't quirk interrupts outside the legacy IRQ range */
849 if (!new_irq || new_irq > 15)
850 return;
851
1597cacb 852 /* Internal device ? */
c06bb5d4
JD		 853 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
854 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
1597cacb
AC		 855 return;
856
857 /* This is an internal VLink device on a PIC interrupt. The BIOS
858 ought to have set this but may not have, so we redo it */
859
25be5e6c
LB		 860 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
861 if (new_irq != irq) {
f0fda801 862 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
863 irq, new_irq);
25be5e6c
LB		 864 udelay(15); /* unknown if delay really needed */
865 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
866 }
867}
1597cacb 868DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
25be5e6c 869
1da177e4
LT		 870/*
871 * VIA VT82C598 has its device ID settable and many BIOSes
872 * set it to the ID of VT82C597 for backward compatibility.
873 * We need to switch it off to be able to recognize the real
874 * type of the chip.
875 */
876static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
877{
878 pci_write_config_byte(dev, 0xfc, 0);
879 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
880}
652c538e 881DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
1da177e4
LT		 882
883/*
884 * CardBus controllers have a legacy base address that enables them
885 * to respond as i82365 pcmcia controllers. We don't want them to
886 * do this even if the Linux CardBus driver is not loaded, because
887 * the Linux i82365 driver does not (and should not) handle CardBus.
888 */
1597cacb 889static void quirk_cardbus_legacy(struct pci_dev *dev)
1da177e4
LT		 890{
891 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
892 return;
893 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
894}
895DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
e1a2a51e 896DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
1da177e4
LT		 897
898/*
899 * Following the PCI ordering rules is optional on the AMD762. I'm not
900 * sure what the designers were smoking but let's not inhale...
901 *
902 * To be fair to AMD, it follows the spec by default, its BIOS people
903 * who turn it off!
904 */
1597cacb 905static void quirk_amd_ordering(struct pci_dev *dev)
1da177e4
LT		 906{
907 u32 pcic;
908 pci_read_config_dword(dev, 0x4C, &pcic);
909 if ((pcic&6)!=6) {
910 pcic |= 6;
f0fda801 911 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1da177e4
LT		 912 pci_write_config_dword(dev, 0x4C, pcic);
913 pci_read_config_dword(dev, 0x84, &pcic);
914 pcic |= (1<<23); /* Required in this mode */
915 pci_write_config_dword(dev, 0x84, pcic);
916 }
917}
652c538e 918DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
e1a2a51e 919DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1da177e4
LT		 920
921/*
922 * DreamWorks provided workaround for Dunord I-3000 problem
923 *
924 * This card decodes and responds to addresses not apparently
925 * assigned to it. We force a larger allocation to ensure that
926 * nothing gets put too close to it.
927 */
928static void __devinit quirk_dunord ( struct pci_dev * dev )
929{
930 struct resource *r = &dev->resource [1];
931 r->start = 0;
932 r->end = 0xffffff;
933}
652c538e 934DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1da177e4
LT		 935
936/*
937 * i82380FB mobile docking controller: its PCI-to-PCI bridge
938 * is subtractive decoding (transparent), and does indicate this
939 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
940 * instead of 0x01.
941 */
942static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
943{
944 dev->transparent = 1;
945}
652c538e
AM		 946DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
947DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1da177e4
LT		 948
949/*
950 * Common misconfiguration of the MediaGX/Geode PCI master that will
951 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
952 * datasheets found at http://www.national.com/ds/GX for info on what
953 * these bits do. <christer@weinigel.se>
954 */
1597cacb 955static void quirk_mediagx_master(struct pci_dev *dev)
1da177e4
LT		 956{
957 u8 reg;
958 pci_read_config_byte(dev, 0x41, &reg);
959 if (reg & 2) {
960 reg &= ~2;
f0fda801 961 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
1da177e4
LT		 962 pci_write_config_byte(dev, 0x41, reg);
963 }
964}
652c538e
AM		 965DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
966DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1da177e4 967
1da177e4
LT		 968/*
969 * Ensure C0 rev restreaming is off. This is normally done by
970 * the BIOS but in the odd case it is not the results are corruption
971 * hence the presence of a Linux check
972 */
1597cacb 973static void quirk_disable_pxb(struct pci_dev *pdev)
1da177e4
LT		 974{
975 u16 config;
1da177e4 976
44c10138 977 if (pdev->revision != 0x04) /* Only C0 requires this */
1da177e4
LT		 978 return;
979 pci_read_config_word(pdev, 0x40, &config);
980 if (config & (1<<6)) {
981 config &= ~(1<<6);
982 pci_write_config_word(pdev, 0x40, config);
f0fda801 983 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
1da177e4
LT		 984 }
985}
652c538e 986DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
e1a2a51e 987DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1da177e4 988
05a7d22b 989static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev)
ab17443a 990{
05a7d22b
CC		 991 /* set sb600/sb700/sb800 sata to ahci mode */
992 u8 tmp;
ab17443a 993
05a7d22b
CC		 994 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
995 if (tmp == 0x01) {
ab17443a
CH		 996 pci_read_config_byte(pdev, 0x40, &tmp);
997 pci_write_config_byte(pdev, 0x40, tmp|1);
998 pci_write_config_byte(pdev, 0x9, 1);
999 pci_write_config_byte(pdev, 0xa, 6);
1000 pci_write_config_byte(pdev, 0x40, tmp);
1001
c9f89475 1002 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
05a7d22b 1003 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
ab17443a
CH		 1004 }
1005}
05a7d22b 1006DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
e1a2a51e 1007DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
05a7d22b 1008DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
e1a2a51e 1009DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
ab17443a 1010
1da177e4
LT		 1011/*
1012 * Serverworks CSB5 IDE does not fully support native mode
1013 */
1014static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
1015{
1016 u8 prog;
1017 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1018 if (prog & 5) {
1019 prog &= ~5;
1020 pdev->class &= ~5;
1021 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
368c73d4 1022 /* PCI layer will sort out resources */
1da177e4
LT		 1023 }
1024}
652c538e 1025DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1da177e4
LT		 1026
1027/*
1028 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1029 */
1030static void __init quirk_ide_samemode(struct pci_dev *pdev)
1031{
1032 u8 prog;
1033
1034 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1035
1036 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
f0fda801 1037 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
1da177e4
LT		 1038 prog &= ~5;
1039 pdev->class &= ~5;
1040 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1da177e4
LT		 1041 }
1042}
368c73d4 1043DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1da177e4 1044
979b1791
AC		 1045/*
1046 * Some ATA devices break if put into D3
1047 */
1048
1049static void __devinit quirk_no_ata_d3(struct pci_dev *pdev)
1050{
1051 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1052 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE)
1053 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1054}
1055DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, quirk_no_ata_d3);
1056DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, quirk_no_ata_d3);
1057
1da177e4
LT		 1058/* This was originally an Alpha specific thing, but it really fits here.
1059 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1060 */
1061static void __init quirk_eisa_bridge(struct pci_dev *dev)
1062{
1063 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1064}
652c538e 1065DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1da177e4 1066
7daa0c4f 1067
1da177e4
LT		 1068/*
1069 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1070 * is not activated. The myth is that Asus said that they do not want the
1071 * users to be irritated by just another PCI Device in the Win98 device
1072 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1073 * package 2.7.0 for details)
1074 *
1075 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1076 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
d7698edc 1077 * becomes necessary to do this tweak in two steps -- the chosen trigger
1078 * is either the Host bridge (preferred) or on-board VGA controller.
9208ee82
JD		 1079 *
1080 * Note that we used to unhide the SMBus that way on Toshiba laptops
1081 * (Satellite A40 and Tecra M2) but then found that the thermal management
1082 * was done by SMM code, which could cause unsynchronized concurrent
1083 * accesses to the SMBus registers, with potentially bad effects. Thus you
1084 * should be very careful when adding new entries: if SMM is accessing the
1085 * Intel SMBus, this is a very good reason to leave it hidden.
a99acc83
JD		 1086 *
1087 * Likewise, many recent laptops use ACPI for thermal management. If the
1088 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1089 * natively, and keeping the SMBus hidden is the right thing to do. If you
1090 * are about to add an entry in the table below, please first disassemble
1091 * the DSDT and double-check that there is no code accessing the SMBus.
1da177e4 1092 */
9d24a81e 1093static int asus_hides_smbus;
1da177e4
LT		 1094
1095static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
1096{
1097 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1098 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1099 switch(dev->subsystem_device) {
a00db371 1100 case 0x8025: /* P4B-LX */
1da177e4
LT		 1101 case 0x8070: /* P4B */
1102 case 0x8088: /* P4B533 */
1103 case 0x1626: /* L3C notebook */
1104 asus_hides_smbus = 1;
1105 }
2f2d39d2 1106 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1da177e4
LT		 1107 switch(dev->subsystem_device) {
1108 case 0x80b1: /* P4GE-V */
1109 case 0x80b2: /* P4PE */
1110 case 0x8093: /* P4B533-V */
1111 asus_hides_smbus = 1;
1112 }
2f2d39d2 1113 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1da177e4
LT		 1114 switch(dev->subsystem_device) {
1115 case 0x8030: /* P4T533 */
1116 asus_hides_smbus = 1;
1117 }
2f2d39d2 1118 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1da177e4
LT		 1119 switch (dev->subsystem_device) {
1120 case 0x8070: /* P4G8X Deluxe */
1121 asus_hides_smbus = 1;
1122 }
2f2d39d2 1123 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
321311af
JD		 1124 switch (dev->subsystem_device) {
1125 case 0x80c9: /* PU-DLS */
1126 asus_hides_smbus = 1;
1127 }
2f2d39d2 1128 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1da177e4
LT		 1129 switch (dev->subsystem_device) {
1130 case 0x1751: /* M2N notebook */
1131 case 0x1821: /* M5N notebook */
1132 asus_hides_smbus = 1;
1133 }
2f2d39d2 1134 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1da177e4
LT		 1135 switch (dev->subsystem_device) {
1136 case 0x184b: /* W1N notebook */
1137 case 0x186a: /* M6Ne notebook */
1138 asus_hides_smbus = 1;
1139 }
2f2d39d2 1140 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
2e45785c
JD		 1141 switch (dev->subsystem_device) {
1142 case 0x80f2: /* P4P800-X */
1143 asus_hides_smbus = 1;
1144 }
2f2d39d2 1145 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
acc06632
RM		 1146 switch (dev->subsystem_device) {
1147 case 0x1882: /* M6V notebook */
2d1e1c75 1148 case 0x1977: /* A6VA notebook */
acc06632
RM		 1149 asus_hides_smbus = 1;
1150 }
1da177e4
LT		 1151 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1152 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1153 switch(dev->subsystem_device) {
1154 case 0x088C: /* HP Compaq nc8000 */
1155 case 0x0890: /* HP Compaq nc6000 */
1156 asus_hides_smbus = 1;
1157 }
2f2d39d2 1158 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1da177e4
LT		 1159 switch (dev->subsystem_device) {
1160 case 0x12bc: /* HP D330L */
e3b1bd57 1161 case 0x12bd: /* HP D530 */
1da177e4
LT		 1162 asus_hides_smbus = 1;
1163 }
677cc644
JD		 1164 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1165 switch (dev->subsystem_device) {
1166 case 0x12bf: /* HP xw4100 */
1167 asus_hides_smbus = 1;
1168 }
1da177e4
LT		 1169 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1170 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1171 switch(dev->subsystem_device) {
1172 case 0xC00C: /* Samsung P35 notebook */
1173 asus_hides_smbus = 1;
1174 }
c87f883e
RIZ		 1175 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1176 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1177 switch(dev->subsystem_device) {
1178 case 0x0058: /* Compaq Evo N620c */
1179 asus_hides_smbus = 1;
1180 }
d7698edc 1181 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1182 switch(dev->subsystem_device) {
1183 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1184 /* Motherboard doesn't have Host bridge
1185 * subvendor/subdevice IDs, therefore checking
1186 * its on-board VGA controller */
1187 asus_hides_smbus = 1;
1188 }
10260d9a
JD		 1189 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_IG)
1190 switch(dev->subsystem_device) {
1191 case 0x00b8: /* Compaq Evo D510 CMT */
1192 case 0x00b9: /* Compaq Evo D510 SFF */
1193 asus_hides_smbus = 1;
1194 }
27e46859
KH		 1195 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1196 switch (dev->subsystem_device) {
1197 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1198 /* Motherboard doesn't have host bridge
1199 * subvendor/subdevice IDs, therefore checking
1200 * its on-board VGA controller */
1201 asus_hides_smbus = 1;
1202 }
1da177e4
LT		 1203 }
1204}
652c538e
AM		 1205DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1206DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1207DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1208DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
677cc644 1209DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
652c538e
AM		 1210DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1211DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1212DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1213DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1214DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1215
1216DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
10260d9a 1217DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_IG, asus_hides_smbus_hostbridge);
27e46859 1218DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
d7698edc 1219
1597cacb 1220static void asus_hides_smbus_lpc(struct pci_dev *dev)
1da177e4
LT		 1221{
1222 u16 val;
1223
1224 if (likely(!asus_hides_smbus))
1225 return;
1226
1227 pci_read_config_word(dev, 0xF2, &val);
1228 if (val & 0x8) {
1229 pci_write_config_word(dev, 0xF2, val & (~0x8));
1230 pci_read_config_word(dev, 0xF2, &val);
1231 if (val & 0x8)
f0fda801 1232 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1da177e4 1233 else
f0fda801 1234 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1da177e4
LT		 1235 }
1236}
652c538e
AM		 1237DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1238DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1239DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1240DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1241DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1242DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1243DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
e1a2a51e
RW		 1244DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1245DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1246DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1247DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1248DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1249DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1250DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1597cacb 1251
e1a2a51e
RW		 1252/* It appears we just have one such device. If not, we have a warning */
1253static void __iomem *asus_rcba_base;
1254static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
acc06632 1255{
e1a2a51e 1256 u32 rcba;
acc06632
RM		 1257
1258 if (likely(!asus_hides_smbus))
1259 return;
e1a2a51e
RW		 1260 WARN_ON(asus_rcba_base);
1261
acc06632 1262 pci_read_config_dword(dev, 0xF0, &rcba);
e1a2a51e
RW		 1263 /* use bits 31:14, 16 kB aligned */
1264 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1265 if (asus_rcba_base == NULL)
1266 return;
1267}
1268
1269static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1270{
1271 u32 val;
1272
1273 if (likely(!asus_hides_smbus || !asus_rcba_base))
1274 return;
1275 /* read the Function Disable register, dword mode only */
1276 val = readl(asus_rcba_base + 0x3418);
1277 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1278}
1279
1280static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1281{
1282 if (likely(!asus_hides_smbus || !asus_rcba_base))
1283 return;
1284 iounmap(asus_rcba_base);
1285 asus_rcba_base = NULL;
f0fda801 1286 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
acc06632 1287}
e1a2a51e
RW		 1288
1289static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1290{
1291 asus_hides_smbus_lpc_ich6_suspend(dev);
1292 asus_hides_smbus_lpc_ich6_resume_early(dev);
1293 asus_hides_smbus_lpc_ich6_resume(dev);
1294}
652c538e 1295DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
e1a2a51e
RW		 1296DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1297DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1298DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
ce007ea5 1299
1da177e4
LT		 1300/*
1301 * SiS 96x south bridge: BIOS typically hides SMBus device...
1302 */
1597cacb 1303static void quirk_sis_96x_smbus(struct pci_dev *dev)
1da177e4
LT		 1304{
1305 u8 val = 0;
1da177e4 1306 pci_read_config_byte(dev, 0x77, &val);
2f5c33b3 1307 if (val & 0x10) {
f0fda801 1308 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
2f5c33b3
MH		 1309 pci_write_config_byte(dev, 0x77, val & ~0x10);
1310 }
1da177e4 1311}
652c538e
AM		 1312DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1313DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1314DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1315DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
e1a2a51e
RW		 1316DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1317DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1318DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1319DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1da177e4 1320
1da177e4
LT		 1321/*
1322 * ... This is further complicated by the fact that some SiS96x south
1323 * bridges pretend to be 85C503/5513 instead. In that case see if we
1324 * spotted a compatible north bridge to make sure.
1325 * (pci_find_device doesn't work yet)
1326 *
1327 * We can also enable the sis96x bit in the discovery register..
1328 */
1da177e4
LT		 1329#define SIS_DETECT_REGISTER 0x40
1330
1597cacb 1331static void quirk_sis_503(struct pci_dev *dev)
1da177e4
LT		 1332{
1333 u8 reg;
1334 u16 devid;
1335
1336 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1337 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1338 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1339 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1340 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1341 return;
1342 }
1343
1da177e4 1344 /*
2f5c33b3
MH		 1345 * Ok, it now shows up as a 96x.. run the 96x quirk by
1346 * hand in case it has already been processed.
1347 * (depends on link order, which is apparently not guaranteed)
1da177e4
LT		 1348 */
1349 dev->device = devid;
2f5c33b3 1350 quirk_sis_96x_smbus(dev);
1da177e4 1351}
652c538e 1352DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
e1a2a51e 1353DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1da177e4 1354
1da177e4 1355
e5548e96
BJD		 1356/*
1357 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1358 * and MC97 modem controller are disabled when a second PCI soundcard is
1359 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1360 * -- bjd
1361 */
1597cacb 1362static void asus_hides_ac97_lpc(struct pci_dev *dev)
e5548e96
BJD		 1363{
1364 u8 val;
1365 int asus_hides_ac97 = 0;
1366
1367 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1368 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1369 asus_hides_ac97 = 1;
1370 }
1371
1372 if (!asus_hides_ac97)
1373 return;
1374
1375 pci_read_config_byte(dev, 0x50, &val);
1376 if (val & 0xc0) {
1377 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1378 pci_read_config_byte(dev, 0x50, &val);
1379 if (val & 0xc0)
f0fda801 1380 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
e5548e96 1381 else
f0fda801 1382 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
e5548e96
BJD		 1383 }
1384}
652c538e 1385DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
e1a2a51e 1386DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1597cacb 1387
77967052 1388#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
15e0c694
AC		 1389
1390/*
1391 * If we are using libata we can drive this chip properly but must
1392 * do this early on to make the additional device appear during
1393 * the PCI scanning.
1394 */
5ee2ae7f 1395static void quirk_jmicron_ata(struct pci_dev *pdev)
15e0c694 1396{
e34bb370 1397 u32 conf1, conf5, class;
15e0c694
AC		 1398 u8 hdr;
1399
1400 /* Only poke fn 0 */
1401 if (PCI_FUNC(pdev->devfn))
1402 return;
1403
5ee2ae7f
TH		 1404 pci_read_config_dword(pdev, 0x40, &conf1);
1405 pci_read_config_dword(pdev, 0x80, &conf5);
15e0c694 1406
5ee2ae7f
TH		 1407 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1408 conf5 &= ~(1 << 24); /* Clear bit 24 */
1409
1410 switch (pdev->device) {
1411 case PCI_DEVICE_ID_JMICRON_JMB360:
1412 /* The controller should be in single function ahci mode */
1413 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1414 break;
1415
1416 case PCI_DEVICE_ID_JMICRON_JMB365:
1417 case PCI_DEVICE_ID_JMICRON_JMB366:
1418 /* Redirect IDE second PATA port to the right spot */
1419 conf5 |= (1 << 24);
1420 /* Fall through */
1421 case PCI_DEVICE_ID_JMICRON_JMB361:
1422 case PCI_DEVICE_ID_JMICRON_JMB363:
1423 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1424 /* Set the class codes correctly and then direct IDE 0 */
3a9e3a51 1425 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
5ee2ae7f
TH		 1426 break;
1427
1428 case PCI_DEVICE_ID_JMICRON_JMB368:
1429 /* The controller should be in single function IDE mode */
1430 conf1 |= 0x00C00000; /* Set 22, 23 */
1431 break;
15e0c694 1432 }
5ee2ae7f
TH		 1433
1434 pci_write_config_dword(pdev, 0x40, conf1);
1435 pci_write_config_dword(pdev, 0x80, conf5);
1436
1437 /* Update pdev accordingly */
1438 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1439 pdev->hdr_type = hdr & 0x7f;
1440 pdev->multifunction = !!(hdr & 0x80);
e34bb370
TH		 1441
1442 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1443 pdev->class = class >> 8;
15e0c694 1444}
5ee2ae7f
TH		 1445DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1446DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1447DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1448DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1449DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1450DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
e1a2a51e
RW		 1451DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1452DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1453DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1454DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1455DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1456DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
15e0c694
AC		 1457
1458#endif
1459
1da177e4
LT		 1460#ifdef CONFIG_X86_IO_APIC
1461static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1462{
1463 int i;
1464
1465 if ((pdev->class >> 8) != 0xff00)
1466 return;
1467
1468 /* the first BAR is the location of the IO APIC...we must
1469 * not touch this (and it's already covered by the fixmap), so
1470 * forcibly insert it into the resource tree */
1471 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1472 insert_resource(&iomem_resource, &pdev->resource[0]);
1473
1474 /* The next five BARs all seem to be rubbish, so just clean
1475 * them out */
1476 for (i=1; i < 6; i++) {
1477 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1478 }
1479
1480}
652c538e 1481DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1da177e4
LT		 1482#endif
1483
1da177e4
LT		 1484static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1485{
1486 pcie_mch_quirk = 1;
1487}
652c538e
AM		 1488DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1489DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1490DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1da177e4 1491
4602b88d
KA		 1492
1493/*
1494 * It's possible for the MSI to get corrupted if shpc and acpi
1495 * are used together on certain PXH-based systems.
1496 */
1497static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1498{
f5f2b131 1499 pci_msi_off(dev);
4602b88d 1500 dev->no_msi = 1;
f0fda801 1501 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
4602b88d
KA		 1502}
1503DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1504DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1505DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1506DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1507DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1508
ffadcc2f
KCA		 1509/*
1510 * Some Intel PCI Express chipsets have trouble with downstream
1511 * device power management.
1512 */
1513static void quirk_intel_pcie_pm(struct pci_dev * dev)
1514{
1515 pci_pm_d3_delay = 120;
1516 dev->no_d1d2 = 1;
1517}
1518
1519DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1520DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1521DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1522DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1523DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1524DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1525DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1526DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1527DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1528DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1529DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1530DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1531DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1532DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1533DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1534DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1535DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1536DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1537DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1538DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1539DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
4602b88d 1540
426b3b8d 1541#ifdef CONFIG_X86_IO_APIC
e1d3a908
SA		 1542/*
1543 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1544 * remap the original interrupt in the linux kernel to the boot interrupt, so
1545 * that a PCI device's interrupt handler is installed on the boot interrupt
1546 * line instead.
1547 */
1548static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1549{
41b9eb26 1550 if (noioapicquirk || noioapicreroute)
e1d3a908
SA		 1551 return;
1552
1553 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1554
1555 printk(KERN_INFO "PCI quirk: reroute interrupts for 0x%04x:0x%04x\n",
1556 dev->vendor, dev->device);
1557 return;
1558}
88d1dce3
OD		 1559DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1560DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1561DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1562DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1563DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1564DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1565DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1566DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1567DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1568DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1569DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1570DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1571DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1572DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1573DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1574DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
e1d3a908 1575
426b3b8d
SA		 1576/*
1577 * On some chipsets we can disable the generation of legacy INTx boot
1578 * interrupts.
1579 */
1580
1581/*
1582 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1583 * 300641-004US, section 5.7.3.
1584 */
1585#define INTEL_6300_IOAPIC_ABAR 0x40
1586#define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1587
1588static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1589{
1590 u16 pci_config_word;
1591
1592 if (noioapicquirk)
1593 return;
1594
1595 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1596 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1597 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1598
1599 printk(KERN_INFO "disabled boot interrupt on device 0x%04x:0x%04x\n",
1600 dev->vendor, dev->device);
1601}
88d1dce3
OD		 1602DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1603DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
77251188
OD		 1604
1605/*
1606 * disable boot interrupts on HT-1000
1607 */
1608#define BC_HT1000_FEATURE_REG 0x64
1609#define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1610#define BC_HT1000_MAP_IDX 0xC00
1611#define BC_HT1000_MAP_DATA 0xC01
1612
1613static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1614{
1615 u32 pci_config_dword;
1616 u8 irq;
1617
1618 if (noioapicquirk)
1619 return;
1620
1621 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1622 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1623 BC_HT1000_PIC_REGS_ENABLE);
1624
1625 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1626 outb(irq, BC_HT1000_MAP_IDX);
1627 outb(0x00, BC_HT1000_MAP_DATA);
1628 }
1629
1630 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1631
1632 printk(KERN_INFO "disabled boot interrupts on PCI device"
1633 "0x%04x:0x%04x\n", dev->vendor, dev->device);
1634}
88d1dce3
OD		 1635DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1636DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
542622da
OD		 1637
1638/*
1639 * disable boot interrupts on AMD and ATI chipsets
1640 */
1641/*
1642 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1643 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1644 * (due to an erratum).
1645 */
1646#define AMD_813X_MISC 0x40
1647#define AMD_813X_NOIOAMODE (1<<0)
bbe19443 1648#define AMD_813X_REV_B2 0x13
542622da
OD		 1649
1650static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1651{
1652 u32 pci_config_dword;
1653
1654 if (noioapicquirk)
1655 return;
bbe19443
SA		 1656 if (dev->revision == AMD_813X_REV_B2)
1657 return;
542622da
OD		 1658
1659 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1660 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1661 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1662
1663 printk(KERN_INFO "disabled boot interrupts on PCI device "
1664 "0x%04x:0x%04x\n", dev->vendor, dev->device);
1665}
88d1dce3
OD		 1666DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1667DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
542622da
OD		 1668
1669#define AMD_8111_PCI_IRQ_ROUTING 0x56
1670
1671static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1672{
1673 u16 pci_config_word;
1674
1675 if (noioapicquirk)
1676 return;
1677
1678 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1679 if (!pci_config_word) {
1680 printk(KERN_INFO "boot interrupts on PCI device 0x%04x:0x%04x "
1681 "already disabled\n",
1682 dev->vendor, dev->device);
1683 return;
1684 }
1685 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
1686 printk(KERN_INFO "disabled boot interrupts on PCI device "
1687 "0x%04x:0x%04x\n", dev->vendor, dev->device);
1688}
88d1dce3
OD		 1689DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1690DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
426b3b8d
SA		 1691#endif /* CONFIG_X86_IO_APIC */
1692
33dced2e
SS		 1693/*
1694 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1695 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1696 * Re-allocate the region if needed...
1697 */
1698static void __init quirk_tc86c001_ide(struct pci_dev *dev)
1699{
1700 struct resource *r = &dev->resource[0];
1701
1702 if (r->start & 0x8) {
1703 r->start = 0;
1704 r->end = 0xf;
1705 }
1706}
1707DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1708 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1709 quirk_tc86c001_ide);
1710
1da177e4
LT		 1711static void __devinit quirk_netmos(struct pci_dev *dev)
1712{
1713 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1714 unsigned int num_serial = dev->subsystem_device & 0xf;
1715
1716 /*
1717 * These Netmos parts are multiport serial devices with optional
1718 * parallel ports. Even when parallel ports are present, they
1719 * are identified as class SERIAL, which means the serial driver
1720 * will claim them. To prevent this, mark them as class OTHER.
1721 * These combo devices should be claimed by parport_serial.
1722 *
1723 * The subdevice ID is of the form 0x00PS, where <P> is the number
1724 * of parallel ports and <S> is the number of serial ports.
1725 */
1726 switch (dev->device) {
4c9c1686
JS		 1727 case PCI_DEVICE_ID_NETMOS_9835:
1728 /* Well, this rule doesn't hold for the following 9835 device */
1729 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1730 dev->subsystem_device == 0x0299)
1731 return;
1da177e4
LT		 1732 case PCI_DEVICE_ID_NETMOS_9735:
1733 case PCI_DEVICE_ID_NETMOS_9745:
1da177e4
LT		 1734 case PCI_DEVICE_ID_NETMOS_9845:
1735 case PCI_DEVICE_ID_NETMOS_9855:
1736 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1737 num_parallel) {
f0fda801 1738 dev_info(&dev->dev, "Netmos %04x (%u parallel, "
1da177e4
LT		 1739 "%u serial); changing class SERIAL to OTHER "
1740 "(use parport_serial)\n",
1741 dev->device, num_parallel, num_serial);
1742 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1743 (dev->class & 0xff);
1744 }
1745 }
1746}
1747DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1748
16a74744
BH		 1749static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1750{
e64aeccb 1751 u16 command, pmcsr;
16a74744
BH		 1752 u8 __iomem *csr;
1753 u8 cmd_hi;
e64aeccb 1754 int pm;
16a74744
BH		 1755
1756 switch (dev->device) {
1757 /* PCI IDs taken from drivers/net/e100.c */
1758 case 0x1029:
1759 case 0x1030 ... 0x1034:
1760 case 0x1038 ... 0x103E:
1761 case 0x1050 ... 0x1057:
1762 case 0x1059:
1763 case 0x1064 ... 0x106B:
1764 case 0x1091 ... 0x1095:
1765 case 0x1209:
1766 case 0x1229:
1767 case 0x2449:
1768 case 0x2459:
1769 case 0x245D:
1770 case 0x27DC:
1771 break;
1772 default:
1773 return;
1774 }
1775
1776 /*
1777 * Some firmware hands off the e100 with interrupts enabled,
1778 * which can cause a flood of interrupts if packets are
1779 * received before the driver attaches to the device. So
1780 * disable all e100 interrupts here. The driver will
1781 * re-enable them when it's ready.
1782 */
1783 pci_read_config_word(dev, PCI_COMMAND, &command);
16a74744 1784
1bef7dc0 1785 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
16a74744
BH		 1786 return;
1787
e64aeccb
IK		 1788 /*
1789 * Check that the device is in the D0 power state. If it's not,
1790 * there is no point to look any further.
1791 */
1792 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1793 if (pm) {
1794 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
1795 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1796 return;
1797 }
1798
1bef7dc0
BH		 1799 /* Convert from PCI bus to resource space. */
1800 csr = ioremap(pci_resource_start(dev, 0), 8);
16a74744 1801 if (!csr) {
f0fda801 1802 dev_warn(&dev->dev, "Can't map e100 registers\n");
16a74744
BH		 1803 return;
1804 }
1805
1806 cmd_hi = readb(csr + 3);
1807 if (cmd_hi == 0) {
f0fda801 1808 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; "
1809 "disabling\n");
16a74744
BH		 1810 writeb(1, csr + 3);
1811 }
1812
1813 iounmap(csr);
1814}
4e68fc97 1815DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt);
a5312e28 1816
649426ef
AD		 1817/*
1818 * The 82575 and 82598 may experience data corruption issues when transitioning
1819 * out of L0S. To prevent this we need to disable L0S on the pci-e link
1820 */
1821static void __devinit quirk_disable_aspm_l0s(struct pci_dev *dev)
1822{
1823 dev_info(&dev->dev, "Disabling L0s\n");
1824 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
1825}
1826DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
1827DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
1828DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
1829DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
1830DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
1831DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
1832DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
1833DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
1834DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
1835DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
1836DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
1837DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
1838DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
1839DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
1840
a5312e28
IK		 1841static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1842{
1843 /* rev 1 ncr53c810 chips don't set the class at all which means
1844 * they don't get their resources remapped. Fix that here.
1845 */
1846
1847 if (dev->class == PCI_CLASS_NOT_DEFINED) {
f0fda801 1848 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n");
a5312e28
IK		 1849 dev->class = PCI_CLASS_STORAGE_SCSI;
1850 }
1851}
1852DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1853
9d265124
DY		 1854/* Enable 1k I/O space granularity on the Intel P64H2 */
1855static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1856{
1857 u16 en1k;
1858 u8 io_base_lo, io_limit_lo;
1859 unsigned long base, limit;
1860 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1861
1862 pci_read_config_word(dev, 0x40, &en1k);
1863
1864 if (en1k & 0x200) {
f0fda801 1865 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
9d265124
DY		 1866
1867 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
1868 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
1869 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1870 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1871
1872 if (base <= limit) {
1873 res->start = base;
1874 res->end = limit + 0x3ff;
1875 }
1876 }
1877}
1878DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1879
15a260d5
DY		 1880/* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2
1881 * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge()
1882 * in drivers/pci/setup-bus.c
1883 */
1884static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev)
1885{
1886 u16 en1k, iobl_adr, iobl_adr_1k;
1887 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1888
1889 pci_read_config_word(dev, 0x40, &en1k);
1890
1891 if (en1k & 0x200) {
1892 pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr);
1893
1894 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00);
1895
1896 if (iobl_adr != iobl_adr_1k) {
f0fda801 1897 dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n",
15a260d5
DY		 1898 iobl_adr,iobl_adr_1k);
1899 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k);
1900 }
1901 }
1902}
1903DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl);
1904
cf34a8e0
BG		 1905/* Under some circumstances, AER is not linked with extended capabilities.
1906 * Force it to be linked by setting the corresponding control bit in the
1907 * config space.
1908 */
1597cacb 1909static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
cf34a8e0
BG		 1910{
1911 uint8_t b;
1912 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1913 if (!(b & 0x20)) {
1914 pci_write_config_byte(dev, 0xf41, b | 0x20);
f0fda801 1915 dev_info(&dev->dev,
1916 "Linking AER extended capability\n");
cf34a8e0
BG		 1917 }
1918 }
1919}
1920DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1921 quirk_nvidia_ck804_pcie_aer_ext_cap);
e1a2a51e 1922DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1597cacb 1923 quirk_nvidia_ck804_pcie_aer_ext_cap);
cf34a8e0 1924
53a9bf42
TY		 1925static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
1926{
1927 /*
1928 * Disable PCI Bus Parking and PCI Master read caching on CX700
1929 * which causes unspecified timing errors with a VT6212L on the PCI
1930 * bus leading to USB2.0 packet loss. The defaults are that these
1931 * features are turned off but some BIOSes turn them on.
1932 */
1933
1934 uint8_t b;
1935 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
1936 if (b & 0x40) {
1937 /* Turn off PCI Bus Parking */
1938 pci_write_config_byte(dev, 0x76, b ^ 0x40);
1939
bc043274
TY		 1940 dev_info(&dev->dev,
1941 "Disabling VIA CX700 PCI parking\n");
1942 }
1943 }
1944
1945 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
1946 if (b != 0) {
53a9bf42
TY		 1947 /* Turn off PCI Master read caching */
1948 pci_write_config_byte(dev, 0x72, 0x0);
bc043274
TY		 1949
1950 /* Set PCI Master Bus time-out to "1x16 PCLK" */
53a9bf42 1951 pci_write_config_byte(dev, 0x75, 0x1);
bc043274
TY		 1952
1953 /* Disable "Read FIFO Timer" */
53a9bf42
TY		 1954 pci_write_config_byte(dev, 0x77, 0x0);
1955
d6505a52 1956 dev_info(&dev->dev,
bc043274 1957 "Disabling VIA CX700 PCI caching\n");
53a9bf42
TY		 1958 }
1959 }
1960}
1961DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
1962
99cb233d
BL		 1963/*
1964 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
1965 * VPD end tag will hang the device. This problem was initially
1966 * observed when a vpd entry was created in sysfs
1967 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
1968 * will dump 32k of data. Reading a full 32k will cause an access
1969 * beyond the VPD end tag causing the device to hang. Once the device
1970 * is hung, the bnx2 driver will not be able to reset the device.
1971 * We believe that it is legal to read beyond the end tag and
1972 * therefore the solution is to limit the read/write length.
1973 */
1974static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
1975{
9d82d8ea 1976 /*
35405f25
DH		 1977 * Only disable the VPD capability for 5706, 5706S, 5708,
1978 * 5708S and 5709 rev. A
9d82d8ea 1979 */
99cb233d 1980 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
35405f25 1981 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
99cb233d 1982 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
9d82d8ea 1983 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
99cb233d
BL		 1984 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
1985 (dev->revision & 0xf0) == 0x0)) {
1986 if (dev->vpd)
1987 dev->vpd->len = 0x80;
1988 }
1989}
1990
bffadffd
YZ		 1991DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1992 PCI_DEVICE_ID_NX2_5706,
1993 quirk_brcm_570x_limit_vpd);
1994DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1995 PCI_DEVICE_ID_NX2_5706S,
1996 quirk_brcm_570x_limit_vpd);
1997DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1998 PCI_DEVICE_ID_NX2_5708,
1999 quirk_brcm_570x_limit_vpd);
2000DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2001 PCI_DEVICE_ID_NX2_5708S,
2002 quirk_brcm_570x_limit_vpd);
2003DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2004 PCI_DEVICE_ID_NX2_5709,
2005 quirk_brcm_570x_limit_vpd);
2006DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2007 PCI_DEVICE_ID_NX2_5709S,
2008 quirk_brcm_570x_limit_vpd);
99cb233d 2009
3f79e107 2010#ifdef CONFIG_PCI_MSI
ebdf7d39
TH		 2011/* Some chipsets do not support MSI. We cannot easily rely on setting
2012 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2013 * some other busses controlled by the chipset even if Linux is not
2014 * aware of it. Instead of setting the flag on all busses in the
2015 * machine, simply disable MSI globally.
3f79e107 2016 */
ebdf7d39 2017static void __init quirk_disable_all_msi(struct pci_dev *dev)
3f79e107 2018{
88187dfa 2019 pci_no_msi();
f0fda801 2020 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
3f79e107 2021}
ebdf7d39
TH		 2022DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2023DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2024DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
66d715c9 2025DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
184b812f 2026DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
3f79e107
BG		 2027
2028/* Disable MSI on chipsets that are known to not support it */
2029static void __devinit quirk_disable_msi(struct pci_dev *dev)
2030{
2031 if (dev->subordinate) {
f0fda801 2032 dev_warn(&dev->dev, "MSI quirk detected; "
2033 "subordinate MSI disabled\n");
3f79e107
BG		 2034 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2035 }
2036}
2037DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
6397c75c
BG		 2038
2039/* Go through the list of Hypertransport capabilities and
2040 * return 1 if a HT MSI capability is found and enabled */
2041static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
2042{
7a380507
ME		 2043 int pos, ttl = 48;
2044
2045 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2046 while (pos && ttl--) {
2047 u8 flags;
2048
2049 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2050 &flags) == 0)
2051 {
f0fda801 2052 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
7a380507 2053 flags & HT_MSI_FLAGS_ENABLE ?
f0fda801 2054 "enabled" : "disabled");
7a380507 2055 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
6397c75c 2056 }
7a380507
ME		 2057
2058 pos = pci_find_next_ht_capability(dev, pos,
2059 HT_CAPTYPE_MSI_MAPPING);
6397c75c
BG		 2060 }
2061 return 0;
2062}
2063
2064/* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2065static void __devinit quirk_msi_ht_cap(struct pci_dev *dev)
2066{
2067 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
f0fda801 2068 dev_warn(&dev->dev, "MSI quirk detected; "
2069 "subordinate MSI disabled\n");
6397c75c
BG		 2070 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2071 }
2072}
2073DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2074 quirk_msi_ht_cap);
6bae1d96 2075
6397c75c
BG		 2076/* The nVidia CK804 chipset may have 2 HT MSI mappings.
2077 * MSI are supported if the MSI capability set in any of these mappings.
2078 */
2079static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2080{
2081 struct pci_dev *pdev;
2082
2083 if (!dev->subordinate)
2084 return;
2085
2086 /* check HT MSI cap on this chipset and the root one.
2087 * a single one having MSI is enough to be sure that MSI are supported.
2088 */
11f242f0 2089 pdev = pci_get_slot(dev->bus, 0);
9ac0ce85
JJ		 2090 if (!pdev)
2091 return;
0c875c28 2092 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
f0fda801 2093 dev_warn(&dev->dev, "MSI quirk detected; "
2094 "subordinate MSI disabled\n");
6397c75c
BG		 2095 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2096 }
11f242f0 2097 pci_dev_put(pdev);
6397c75c
BG		 2098}
2099DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2100 quirk_nvidia_ck804_msi_ht_cap);
ba698ad4 2101
415b6d0e
BH		 2102/* Force enable MSI mapping capability on HT bridges */
2103static void __devinit ht_enable_msi_mapping(struct pci_dev *dev)
9dc625e7
PC		 2104{
2105 int pos, ttl = 48;
2106
2107 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2108 while (pos && ttl--) {
2109 u8 flags;
2110
2111 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2112 &flags) == 0) {
2113 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2114
2115 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2116 flags | HT_MSI_FLAGS_ENABLE);
2117 }
2118 pos = pci_find_next_ht_capability(dev, pos,
2119 HT_CAPTYPE_MSI_MAPPING);
2120 }
2121}
415b6d0e
BH		 2122DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2123 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2124 ht_enable_msi_mapping);
9dc625e7 2125
e0ae4f55
YL		 2126DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2127 ht_enable_msi_mapping);
2128
75e07fc3
AP		 2129/* The P5N32-SLI Premium motherboard from Asus has a problem with msi
2130 * for the MCP55 NIC. It is not yet determined whether the msi problem
2131 * also affects other devices. As for now, turn off msi for this device.
2132 */
2133static void __devinit nvenet_msi_disable(struct pci_dev *dev)
2134{
2135 if (dmi_name_in_vendors("P5N32-SLI PREMIUM")) {
2136 dev_info(&dev->dev,
2137 "Disabling msi for MCP55 NIC on P5N32-SLI Premium\n");
2138 dev->no_msi = 1;
2139 }
2140}
2141DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2142 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2143 nvenet_msi_disable);
2144
1dec6b05 2145static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev)
9dc625e7
PC		 2146{
2147 struct pci_dev *host_bridge;
1dec6b05
YL		 2148 int pos;
2149 int i, dev_no;
2150 int found = 0;
2151
2152 dev_no = dev->devfn >> 3;
2153 for (i = dev_no; i >= 0; i--) {
2154 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2155 if (!host_bridge)
2156 continue;
2157
2158 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2159 if (pos != 0) {
2160 found = 1;
2161 break;
2162 }
2163 pci_dev_put(host_bridge);
2164 }
2165
2166 if (!found)
2167 return;
2168
2169 /* root did that ! */
2170 if (msi_ht_cap_enabled(host_bridge))
2171 goto out;
2172
2173 ht_enable_msi_mapping(dev);
2174
2175out:
2176 pci_dev_put(host_bridge);
2177}
2178
2179static void __devinit ht_disable_msi_mapping(struct pci_dev *dev)
2180{
2181 int pos, ttl = 48;
2182
2183 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2184 while (pos && ttl--) {
2185 u8 flags;
2186
2187 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2188 &flags) == 0) {
6a958d5b 2189 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
1dec6b05
YL		 2190
2191 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2192 flags & ~HT_MSI_FLAGS_ENABLE);
2193 }
2194 pos = pci_find_next_ht_capability(dev, pos,
2195 HT_CAPTYPE_MSI_MAPPING);
2196 }
2197}
2198
2199static int __devinit ht_check_msi_mapping(struct pci_dev *dev)
2200{
9dc625e7 2201 int pos, ttl = 48;
1dec6b05
YL		 2202 int found = 0;
2203
2204 /* check if there is HT MSI cap or enabled on this device */
2205 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2206 while (pos && ttl--) {
2207 u8 flags;
2208
2209 if (found < 1)
2210 found = 1;
2211 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2212 &flags) == 0) {
2213 if (flags & HT_MSI_FLAGS_ENABLE) {
2214 if (found < 2) {
2215 found = 2;
2216 break;
2217 }
2218 }
2219 }
2220 pos = pci_find_next_ht_capability(dev, pos,
2221 HT_CAPTYPE_MSI_MAPPING);
2222 }
2223
2224 return found;
2225}
2226
2227static void __devinit nv_msi_ht_cap_quirk(struct pci_dev *dev)
2228{
2229 struct pci_dev *host_bridge;
2230 int pos;
2231 int found;
2232
7726c330
PP		 2233 /* Enabling HT MSI mapping on this device breaks MCP51 */
2234 if (dev->device == 0x270)
2235 return;
2236
1dec6b05
YL		 2237 /* check if there is HT MSI cap or enabled on this device */
2238 found = ht_check_msi_mapping(dev);
2239
2240 /* no HT MSI CAP */
2241 if (found == 0)
2242 return;
9dc625e7
PC		 2243
2244 /*
2245 * HT MSI mapping should be disabled on devices that are below
2246 * a non-Hypertransport host bridge. Locate the host bridge...
2247 */
2248 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2249 if (host_bridge == NULL) {
2250 dev_warn(&dev->dev,
2251 "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2252 return;
2253 }
2254
2255 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2256 if (pos != 0) {
2257 /* Host bridge is to HT */
1dec6b05
YL		 2258 if (found == 1) {
2259 /* it is not enabled, try to enable it */
2260 nv_ht_enable_msi_mapping(dev);
2261 }
9dc625e7
PC		 2262 return;
2263 }
2264
1dec6b05
YL		 2265 /* HT MSI is not enabled */
2266 if (found == 1)
2267 return;
9dc625e7 2268
1dec6b05
YL		 2269 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2270 ht_disable_msi_mapping(dev);
9dc625e7
PC		 2271}
2272DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk);
439a7733 2273DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk);
9dc625e7 2274
ba698ad4
DM		 2275static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev)
2276{
2277 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2278}
4600c9d7
SH		 2279static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2280{
2281 struct pci_dev *p;
2282
2283 /* SB700 MSI issue will be fixed at HW level from revision A21,
2284 * we need check PCI REVISION ID of SMBus controller to get SB700
2285 * revision.
2286 */
2287 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2288 NULL);
2289 if (!p)
2290 return;
2291
2292 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2293 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2294 pci_dev_put(p);
2295}
ba698ad4
DM		 2296DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2297 PCI_DEVICE_ID_TIGON3_5780,
2298 quirk_msi_intx_disable_bug);
2299DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2300 PCI_DEVICE_ID_TIGON3_5780S,
2301 quirk_msi_intx_disable_bug);
2302DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2303 PCI_DEVICE_ID_TIGON3_5714,
2304 quirk_msi_intx_disable_bug);
2305DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2306 PCI_DEVICE_ID_TIGON3_5714S,
2307 quirk_msi_intx_disable_bug);
2308DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2309 PCI_DEVICE_ID_TIGON3_5715,
2310 quirk_msi_intx_disable_bug);
2311DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2312 PCI_DEVICE_ID_TIGON3_5715S,
2313 quirk_msi_intx_disable_bug);
2314
bc38b411 2315DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
4600c9d7 2316 quirk_msi_intx_disable_ati_bug);
bc38b411 2317DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
4600c9d7 2318 quirk_msi_intx_disable_ati_bug);
bc38b411 2319DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
4600c9d7 2320 quirk_msi_intx_disable_ati_bug);
bc38b411 2321DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
4600c9d7 2322 quirk_msi_intx_disable_ati_bug);
bc38b411 2323DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
4600c9d7 2324 quirk_msi_intx_disable_ati_bug);
bc38b411
DM		 2325
2326DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2327 quirk_msi_intx_disable_bug);
2328DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2329 quirk_msi_intx_disable_bug);
2330DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2331 quirk_msi_intx_disable_bug);
2332
3f79e107 2333#endif /* CONFIG_PCI_MSI */
3d137310 2334
bfb0f330
JB		 2335static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
2336 struct pci_fixup *end)
3d137310
TP		 2337{
2338 while (f < end) {
2339 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
bfb0f330 2340 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
c9bbb4ab 2341 dev_dbg(&dev->dev, "calling %pF\n", f->hook);
3d137310
TP		 2342 f->hook(dev);
2343 }
2344 f++;
2345 }
2346}
2347
2348extern struct pci_fixup __start_pci_fixups_early[];
2349extern struct pci_fixup __end_pci_fixups_early[];
2350extern struct pci_fixup __start_pci_fixups_header[];
2351extern struct pci_fixup __end_pci_fixups_header[];
2352extern struct pci_fixup __start_pci_fixups_final[];
2353extern struct pci_fixup __end_pci_fixups_final[];
2354extern struct pci_fixup __start_pci_fixups_enable[];
2355extern struct pci_fixup __end_pci_fixups_enable[];
2356extern struct pci_fixup __start_pci_fixups_resume[];
2357extern struct pci_fixup __end_pci_fixups_resume[];
2358extern struct pci_fixup __start_pci_fixups_resume_early[];
2359extern struct pci_fixup __end_pci_fixups_resume_early[];
2360extern struct pci_fixup __start_pci_fixups_suspend[];
2361extern struct pci_fixup __end_pci_fixups_suspend[];
2362
2363
2364void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
2365{
2366 struct pci_fixup *start, *end;
2367
2368 switch(pass) {
2369 case pci_fixup_early:
2370 start = __start_pci_fixups_early;
2371 end = __end_pci_fixups_early;
2372 break;
2373
2374 case pci_fixup_header:
2375 start = __start_pci_fixups_header;
2376 end = __end_pci_fixups_header;
2377 break;
2378
2379 case pci_fixup_final:
2380 start = __start_pci_fixups_final;
2381 end = __end_pci_fixups_final;
2382 break;
2383
2384 case pci_fixup_enable:
2385 start = __start_pci_fixups_enable;
2386 end = __end_pci_fixups_enable;
2387 break;
2388
2389 case pci_fixup_resume:
2390 start = __start_pci_fixups_resume;
2391 end = __end_pci_fixups_resume;
2392 break;
2393
2394 case pci_fixup_resume_early:
2395 start = __start_pci_fixups_resume_early;
2396 end = __end_pci_fixups_resume_early;
2397 break;
2398
2399 case pci_fixup_suspend:
2400 start = __start_pci_fixups_suspend;
2401 end = __end_pci_fixups_suspend;
2402 break;
2403
2404 default:
2405 /* stupid compiler warning, you would think with an enum... */
2406 return;
2407 }
2408 pci_do_fixups(dev, start, end);
2409}
2410#else
2411void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) {}
2412#endif
2413EXPORT_SYMBOL(pci_fixup_device);
kernel source for telekom puls (alcatel/mediatek)