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[PATCH] PCI: fix problems with MSI-X on ia64
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / pci / probe.c
CommitLineData
1da177e4
LT		 1/*
2 * probe.c - PCI detection and setup code
3 */
4
5#include <linux/kernel.h>
6#include <linux/delay.h>
7#include <linux/init.h>
8#include <linux/pci.h>
9#include <linux/slab.h>
10#include <linux/module.h>
11#include <linux/cpumask.h>
bc56b9e0 12#include "pci.h"
1da177e4
LT		 13
14#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
15#define CARDBUS_RESERVE_BUSNR 3
16#define PCI_CFG_SPACE_SIZE 256
17#define PCI_CFG_SPACE_EXP_SIZE 4096
18
19/* Ugh. Need to stop exporting this to modules. */
20LIST_HEAD(pci_root_buses);
21EXPORT_SYMBOL(pci_root_buses);
22
23LIST_HEAD(pci_devices);
24
25#ifdef HAVE_PCI_LEGACY
26/**
27 * pci_create_legacy_files - create legacy I/O port and memory files
28 * @b: bus to create files under
29 *
30 * Some platforms allow access to legacy I/O port and ISA memory space on
31 * a per-bus basis. This routine creates the files and ties them into
32 * their associated read, write and mmap files from pci-sysfs.c
33 */
34static void pci_create_legacy_files(struct pci_bus *b)
35{
36 b->legacy_io = kmalloc(sizeof(struct bin_attribute) * 2,
37 GFP_ATOMIC);
38 if (b->legacy_io) {
39 memset(b->legacy_io, 0, sizeof(struct bin_attribute) * 2);
40 b->legacy_io->attr.name = "legacy_io";
41 b->legacy_io->size = 0xffff;
42 b->legacy_io->attr.mode = S_IRUSR | S_IWUSR;
43 b->legacy_io->attr.owner = THIS_MODULE;
44 b->legacy_io->read = pci_read_legacy_io;
45 b->legacy_io->write = pci_write_legacy_io;
46 class_device_create_bin_file(&b->class_dev, b->legacy_io);
47
48 /* Allocated above after the legacy_io struct */
49 b->legacy_mem = b->legacy_io + 1;
50 b->legacy_mem->attr.name = "legacy_mem";
51 b->legacy_mem->size = 1024*1024;
52 b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR;
53 b->legacy_mem->attr.owner = THIS_MODULE;
54 b->legacy_mem->mmap = pci_mmap_legacy_mem;
55 class_device_create_bin_file(&b->class_dev, b->legacy_mem);
56 }
57}
58
59void pci_remove_legacy_files(struct pci_bus *b)
60{
61 if (b->legacy_io) {
62 class_device_remove_bin_file(&b->class_dev, b->legacy_io);
63 class_device_remove_bin_file(&b->class_dev, b->legacy_mem);
64 kfree(b->legacy_io); /* both are allocated here */
65 }
66}
67#else /* !HAVE_PCI_LEGACY */
68static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
69void pci_remove_legacy_files(struct pci_bus *bus) { return; }
70#endif /* HAVE_PCI_LEGACY */
71
72/*
73 * PCI Bus Class Devices
74 */
4327edf6
AC		 75static ssize_t pci_bus_show_cpuaffinity(struct class_device *class_dev,
76 char *buf)
1da177e4 77{
1da177e4 78 int ret;
4327edf6 79 cpumask_t cpumask;
1da177e4 80
4327edf6 81 cpumask = pcibus_to_cpumask(to_pci_bus(class_dev));
1da177e4
LT		 82 ret = cpumask_scnprintf(buf, PAGE_SIZE, cpumask);
83 if (ret < PAGE_SIZE)
84 buf[ret++] = '\n';
85 return ret;
86}
87CLASS_DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpuaffinity, NULL);
88
89/*
90 * PCI Bus Class
91 */
92static void release_pcibus_dev(struct class_device *class_dev)
93{
94 struct pci_bus *pci_bus = to_pci_bus(class_dev);
95
96 if (pci_bus->bridge)
97 put_device(pci_bus->bridge);
98 kfree(pci_bus);
99}
100
101static struct class pcibus_class = {
102 .name = "pci_bus",
103 .release = &release_pcibus_dev,
104};
105
106static int __init pcibus_class_init(void)
107{
108 return class_register(&pcibus_class);
109}
110postcore_initcall(pcibus_class_init);
111
112/*
113 * Translate the low bits of the PCI base
114 * to the resource type
115 */
116static inline unsigned int pci_calc_resource_flags(unsigned int flags)
117{
118 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
119 return IORESOURCE_IO;
120
121 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
122 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
123
124 return IORESOURCE_MEM;
125}
126
127/*
128 * Find the extent of a PCI decode..
129 */
f797f9cc 130static u32 pci_size(u32 base, u32 maxbase, u32 mask)
1da177e4
LT		 131{
132 u32 size = mask & maxbase; /* Find the significant bits */
133 if (!size)
134 return 0;
135
136 /* Get the lowest of them to find the decode size, and
137 from that the extent. */
138 size = (size & ~(size-1)) - 1;
139
140 /* base == maxbase can be valid only if the BAR has
141 already been programmed with all 1s. */
142 if (base == maxbase && ((base | size) & mask) != mask)
143 return 0;
144
145 return size;
146}
147
148static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
149{
150 unsigned int pos, reg, next;
151 u32 l, sz;
152 struct resource *res;
153
154 for(pos=0; pos<howmany; pos = next) {
155 next = pos+1;
156 res = &dev->resource[pos];
157 res->name = pci_name(dev);
158 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
159 pci_read_config_dword(dev, reg, &l);
160 pci_write_config_dword(dev, reg, ~0);
161 pci_read_config_dword(dev, reg, &sz);
162 pci_write_config_dword(dev, reg, l);
163 if (!sz || sz == 0xffffffff)
164 continue;
165 if (l == 0xffffffff)
166 l = 0;
167 if ((l & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY) {
3c6de929 168 sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);
1da177e4
LT		 169 if (!sz)
170 continue;
171 res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
172 res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
173 } else {
174 sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
175 if (!sz)
176 continue;
177 res->start = l & PCI_BASE_ADDRESS_IO_MASK;
178 res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
179 }
180 res->end = res->start + (unsigned long) sz;
181 res->flags |= pci_calc_resource_flags(l);
182 if ((l & (PCI_BASE_ADDRESS_SPACE | PCI_BASE_ADDRESS_MEM_TYPE_MASK))
183 == (PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64)) {
184 pci_read_config_dword(dev, reg+4, &l);
185 next++;
186#if BITS_PER_LONG == 64
187 res->start |= ((unsigned long) l) << 32;
188 res->end = res->start + sz;
189 pci_write_config_dword(dev, reg+4, ~0);
190 pci_read_config_dword(dev, reg+4, &sz);
191 pci_write_config_dword(dev, reg+4, l);
192 sz = pci_size(l, sz, 0xffffffff);
193 if (sz) {
194 /* This BAR needs > 4GB? Wow. */
195 res->end |= (unsigned long)sz<<32;
196 }
197#else
198 if (l) {
199 printk(KERN_ERR "PCI: Unable to handle 64-bit address for device %s\n", pci_name(dev));
200 res->start = 0;
201 res->flags = 0;
202 continue;
203 }
204#endif
205 }
206 }
207 if (rom) {
208 dev->rom_base_reg = rom;
209 res = &dev->resource[PCI_ROM_RESOURCE];
210 res->name = pci_name(dev);
211 pci_read_config_dword(dev, rom, &l);
212 pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
213 pci_read_config_dword(dev, rom, &sz);
214 pci_write_config_dword(dev, rom, l);
215 if (l == 0xffffffff)
216 l = 0;
217 if (sz && sz != 0xffffffff) {
3c6de929 218 sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK);
1da177e4
LT		 219 if (sz) {
220 res->flags = (l & IORESOURCE_ROM_ENABLE) |
221 IORESOURCE_MEM | IORESOURCE_PREFETCH |
222 IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
223 res->start = l & PCI_ROM_ADDRESS_MASK;
224 res->end = res->start + (unsigned long) sz;
225 }
226 }
227 }
228}
229
230void __devinit pci_read_bridge_bases(struct pci_bus *child)
231{
232 struct pci_dev *dev = child->self;
233 u8 io_base_lo, io_limit_lo;
234 u16 mem_base_lo, mem_limit_lo;
235 unsigned long base, limit;
236 struct resource *res;
237 int i;
238
239 if (!dev) /* It's a host bus, nothing to read */
240 return;
241
242 if (dev->transparent) {
243 printk(KERN_INFO "PCI: Transparent bridge - %s\n", pci_name(dev));
90b54929
IK		 244 for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++)
245 child->resource[i] = child->parent->resource[i - 3];
1da177e4
LT		 246 }
247
248 for(i=0; i<3; i++)
249 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
250
251 res = child->resource[0];
252 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
253 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
254 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
255 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
256
257 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
258 u16 io_base_hi, io_limit_hi;
259 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
260 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
261 base |= (io_base_hi << 16);
262 limit |= (io_limit_hi << 16);
263 }
264
265 if (base <= limit) {
266 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
9d265124
DY		 267 if (!res->start)
268 res->start = base;
269 if (!res->end)
270 res->end = limit + 0xfff;
1da177e4
LT		 271 }
272
273 res = child->resource[1];
274 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
275 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
276 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
277 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
278 if (base <= limit) {
279 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
280 res->start = base;
281 res->end = limit + 0xfffff;
282 }
283
284 res = child->resource[2];
285 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
286 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
287 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
288 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
289
290 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
291 u32 mem_base_hi, mem_limit_hi;
292 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
293 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
294
295 /*
296 * Some bridges set the base > limit by default, and some
297 * (broken) BIOSes do not initialize them. If we find
298 * this, just assume they are not being used.
299 */
300 if (mem_base_hi <= mem_limit_hi) {
301#if BITS_PER_LONG == 64
302 base |= ((long) mem_base_hi) << 32;
303 limit |= ((long) mem_limit_hi) << 32;
304#else
305 if (mem_base_hi || mem_limit_hi) {
306 printk(KERN_ERR "PCI: Unable to handle 64-bit address space for bridge %s\n", pci_name(dev));
307 return;
308 }
309#endif
310 }
311 }
312 if (base <= limit) {
313 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
314 res->start = base;
315 res->end = limit + 0xfffff;
316 }
317}
318
319static struct pci_bus * __devinit pci_alloc_bus(void)
320{
321 struct pci_bus *b;
322
323 b = kmalloc(sizeof(*b), GFP_KERNEL);
324 if (b) {
325 memset(b, 0, sizeof(*b));
326 INIT_LIST_HEAD(&b->node);
327 INIT_LIST_HEAD(&b->children);
328 INIT_LIST_HEAD(&b->devices);
329 }
330 return b;
331}
332
333static struct pci_bus * __devinit
334pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr)
335{
336 struct pci_bus *child;
337 int i;
338
339 /*
340 * Allocate a new bus, and inherit stuff from the parent..
341 */
342 child = pci_alloc_bus();
343 if (!child)
344 return NULL;
345
346 child->self = bridge;
347 child->parent = parent;
348 child->ops = parent->ops;
349 child->sysdata = parent->sysdata;
6e325a62 350 child->bus_flags = parent->bus_flags;
1da177e4
LT		 351 child->bridge = get_device(&bridge->dev);
352
353 child->class_dev.class = &pcibus_class;
354 sprintf(child->class_dev.class_id, "%04x:%02x", pci_domain_nr(child), busnr);
355 class_device_register(&child->class_dev);
356 class_device_create_file(&child->class_dev, &class_device_attr_cpuaffinity);
357
358 /*
359 * Set up the primary, secondary and subordinate
360 * bus numbers.
361 */
362 child->number = child->secondary = busnr;
363 child->primary = parent->secondary;
364 child->subordinate = 0xff;
365
366 /* Set up default resource pointers and names.. */
367 for (i = 0; i < 4; i++) {
368 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
369 child->resource[i]->name = child->name;
370 }
371 bridge->subordinate = child;
372
373 return child;
374}
375
376struct pci_bus * __devinit pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
377{
378 struct pci_bus *child;
379
380 child = pci_alloc_child_bus(parent, dev, busnr);
e4ea9bb7
RS		 381 if (child) {
382 spin_lock(&pci_bus_lock);
1da177e4 383 list_add_tail(&child->node, &parent->children);
e4ea9bb7
RS		 384 spin_unlock(&pci_bus_lock);
385 }
1da177e4
LT		 386 return child;
387}
388
389static void pci_enable_crs(struct pci_dev *dev)
390{
391 u16 cap, rpctl;
392 int rpcap = pci_find_capability(dev, PCI_CAP_ID_EXP);
393 if (!rpcap)
394 return;
395
396 pci_read_config_word(dev, rpcap + PCI_CAP_FLAGS, &cap);
397 if (((cap & PCI_EXP_FLAGS_TYPE) >> 4) != PCI_EXP_TYPE_ROOT_PORT)
398 return;
399
400 pci_read_config_word(dev, rpcap + PCI_EXP_RTCTL, &rpctl);
401 rpctl |= PCI_EXP_RTCTL_CRSSVE;
402 pci_write_config_word(dev, rpcap + PCI_EXP_RTCTL, rpctl);
403}
404
26f674ae
GKH		 405static void __devinit pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
406{
407 struct pci_bus *parent = child->parent;
12f44f46
IK		 408
409 /* Attempts to fix that up are really dangerous unless
410 we're going to re-assign all bus numbers. */
411 if (!pcibios_assign_all_busses())
412 return;
413
26f674ae
GKH		 414 while (parent->parent && parent->subordinate < max) {
415 parent->subordinate = max;
416 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
417 parent = parent->parent;
418 }
419}
420
1da177e4
LT		 421unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus);
422
423/*
424 * If it's a bridge, configure it and scan the bus behind it.
425 * For CardBus bridges, we don't scan behind as the devices will
426 * be handled by the bridge driver itself.
427 *
428 * We need to process bridges in two passes -- first we scan those
429 * already configured by the BIOS and after we are done with all of
430 * them, we proceed to assigning numbers to the remaining buses in
431 * order to avoid overlaps between old and new bus numbers.
432 */
433int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass)
434{
435 struct pci_bus *child;
436 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
49887941 437 u32 buses, i, j = 0;
1da177e4
LT		 438 u16 bctl;
439
440 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
441
442 pr_debug("PCI: Scanning behind PCI bridge %s, config %06x, pass %d\n",
443 pci_name(dev), buses & 0xffffff, pass);
444
445 /* Disable MasterAbortMode during probing to avoid reporting
446 of bus errors (in some architectures) */
447 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
448 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
449 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
450
451 pci_enable_crs(dev);
452
453 if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) {
454 unsigned int cmax, busnr;
455 /*
456 * Bus already configured by firmware, process it in the first
457 * pass and just note the configuration.
458 */
459 if (pass)
bbe8f9a3 460 goto out;
1da177e4
LT		 461 busnr = (buses >> 8) & 0xFF;
462
463 /*
464 * If we already got to this bus through a different bridge,
465 * ignore it. This can happen with the i450NX chipset.
466 */
467 if (pci_find_bus(pci_domain_nr(bus), busnr)) {
468 printk(KERN_INFO "PCI: Bus %04x:%02x already known\n",
469 pci_domain_nr(bus), busnr);
bbe8f9a3 470 goto out;
1da177e4
LT		 471 }
472
6ef6f0e3 473 child = pci_add_new_bus(bus, dev, busnr);
1da177e4 474 if (!child)
bbe8f9a3 475 goto out;
1da177e4
LT		 476 child->primary = buses & 0xFF;
477 child->subordinate = (buses >> 16) & 0xFF;
478 child->bridge_ctl = bctl;
479
480 cmax = pci_scan_child_bus(child);
481 if (cmax > max)
482 max = cmax;
483 if (child->subordinate > max)
484 max = child->subordinate;
485 } else {
486 /*
487 * We need to assign a number to this bus which we always
488 * do in the second pass.
489 */
12f44f46
IK		 490 if (!pass) {
491 if (pcibios_assign_all_busses())
492 /* Temporarily disable forwarding of the
493 configuration cycles on all bridges in
494 this bus segment to avoid possible
495 conflicts in the second pass between two
496 bridges programmed with overlapping
497 bus ranges. */
498 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
499 buses & ~0xffffff);
bbe8f9a3 500 goto out;
12f44f46 501 }
1da177e4
LT		 502
503 /* Clear errors */
504 pci_write_config_word(dev, PCI_STATUS, 0xffff);
505
cc57450f
RS		 506 /* Prevent assigning a bus number that already exists.
507 * This can happen when a bridge is hot-plugged */
508 if (pci_find_bus(pci_domain_nr(bus), max+1))
bbe8f9a3 509 goto out;
6ef6f0e3 510 child = pci_add_new_bus(bus, dev, ++max);
1da177e4
LT		 511 buses = (buses & 0xff000000)
512 | ((unsigned int)(child->primary) << 0)
513 | ((unsigned int)(child->secondary) << 8)
514 | ((unsigned int)(child->subordinate) << 16);
515
516 /*
517 * yenta.c forces a secondary latency timer of 176.
518 * Copy that behaviour here.
519 */
520 if (is_cardbus) {
521 buses &= ~0xff000000;
522 buses |= CARDBUS_LATENCY_TIMER << 24;
523 }
524
525 /*
526 * We need to blast all three values with a single write.
527 */
528 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
529
530 if (!is_cardbus) {
10f4338c 531 child->bridge_ctl = bctl | PCI_BRIDGE_CTL_NO_ISA;
26f674ae
GKH		 532 /*
533 * Adjust subordinate busnr in parent buses.
534 * We do this before scanning for children because
535 * some devices may not be detected if the bios
536 * was lazy.
537 */
538 pci_fixup_parent_subordinate_busnr(child, max);
1da177e4
LT		 539 /* Now we can scan all subordinate buses... */
540 max = pci_scan_child_bus(child);
e3ac86d8
KA		 541 /*
542 * now fix it up again since we have found
543 * the real value of max.
544 */
545 pci_fixup_parent_subordinate_busnr(child, max);
1da177e4
LT		 546 } else {
547 /*
548 * For CardBus bridges, we leave 4 bus numbers
549 * as cards with a PCI-to-PCI bridge can be
550 * inserted later.
551 */
49887941
DB		 552 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
553 struct pci_bus *parent = bus;
cc57450f
RS		 554 if (pci_find_bus(pci_domain_nr(bus),
555 max+i+1))
556 break;
49887941
DB		 557 while (parent->parent) {
558 if ((!pcibios_assign_all_busses()) &&
559 (parent->subordinate > max) &&
560 (parent->subordinate <= max+i)) {
561 j = 1;
562 }
563 parent = parent->parent;
564 }
565 if (j) {
566 /*
567 * Often, there are two cardbus bridges
568 * -- try to leave one valid bus number
569 * for each one.
570 */
571 i /= 2;
572 break;
573 }
574 }
cc57450f 575 max += i;
26f674ae 576 pci_fixup_parent_subordinate_busnr(child, max);
1da177e4
LT		 577 }
578 /*
579 * Set the subordinate bus number to its real value.
580 */
581 child->subordinate = max;
582 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
583 }
584
1da177e4
LT		 585 sprintf(child->name, (is_cardbus ? "PCI CardBus #%02x" : "PCI Bus #%02x"), child->number);
586
49887941
DB		 587 while (bus->parent) {
588 if ((child->subordinate > bus->subordinate) ||
589 (child->number > bus->subordinate) ||
590 (child->number < bus->number) ||
591 (child->subordinate < bus->number)) {
592 printk(KERN_WARNING "PCI: Bus #%02x (-#%02x) may be "
593 "hidden behind%s bridge #%02x (-#%02x)%s\n",
594 child->number, child->subordinate,
595 bus->self->transparent ? " transparent" : " ",
596 bus->number, bus->subordinate,
597 pcibios_assign_all_busses() ? " " :
598 " (try 'pci=assign-busses')");
599 }
600 bus = bus->parent;
601 }
602
bbe8f9a3
RB		 603out:
604 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
605
1da177e4
LT		 606 return max;
607}
608
609/*
610 * Read interrupt line and base address registers.
611 * The architecture-dependent code can tweak these, of course.
612 */
613static void pci_read_irq(struct pci_dev *dev)
614{
615 unsigned char irq;
616
617 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
ffeff788 618 dev->pin = irq;
1da177e4
LT		 619 if (irq)
620 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
621 dev->irq = irq;
622}
623
624/**
625 * pci_setup_device - fill in class and map information of a device
626 * @dev: the device structure to fill
627 *
628 * Initialize the device structure with information about the device's
629 * vendor,class,memory and IO-space addresses,IRQ lines etc.
630 * Called at initialisation of the PCI subsystem and by CardBus services.
631 * Returns 0 on success and -1 if unknown type of device (not normal, bridge
632 * or CardBus).
633 */
634static int pci_setup_device(struct pci_dev * dev)
635{
636 u32 class;
637
638 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
639 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
640
641 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
642 class >>= 8; /* upper 3 bytes */
643 dev->class = class;
644 class >>= 8;
645
646 pr_debug("PCI: Found %s [%04x/%04x] %06x %02x\n", pci_name(dev),
647 dev->vendor, dev->device, class, dev->hdr_type);
648
649 /* "Unknown power state" */
3fe9d19f 650 dev->current_state = PCI_UNKNOWN;
1da177e4
LT		 651
652 /* Early fixups, before probing the BARs */
653 pci_fixup_device(pci_fixup_early, dev);
654 class = dev->class >> 8;
655
656 switch (dev->hdr_type) { /* header type */
657 case PCI_HEADER_TYPE_NORMAL: /* standard header */
658 if (class == PCI_CLASS_BRIDGE_PCI)
659 goto bad;
660 pci_read_irq(dev);
661 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
662 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
663 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
664 break;
665
666 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
667 if (class != PCI_CLASS_BRIDGE_PCI)
668 goto bad;
669 /* The PCI-to-PCI bridge spec requires that subtractive
670 decoding (i.e. transparent) bridge must have programming
671 interface code of 0x01. */
3efd273b 672 pci_read_irq(dev);
1da177e4
LT		 673 dev->transparent = ((dev->class & 0xff) == 1);
674 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
675 break;
676
677 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
678 if (class != PCI_CLASS_BRIDGE_CARDBUS)
679 goto bad;
680 pci_read_irq(dev);
681 pci_read_bases(dev, 1, 0);
682 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
683 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
684 break;
685
686 default: /* unknown header */
687 printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
688 pci_name(dev), dev->hdr_type);
689 return -1;
690
691 bad:
692 printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
693 pci_name(dev), class, dev->hdr_type);
694 dev->class = PCI_CLASS_NOT_DEFINED;
695 }
696
697 /* We found a fine healthy device, go go go... */
698 return 0;
699}
700
701/**
702 * pci_release_dev - free a pci device structure when all users of it are finished.
703 * @dev: device that's been disconnected
704 *
705 * Will be called only by the device core when all users of this pci device are
706 * done.
707 */
708static void pci_release_dev(struct device *dev)
709{
710 struct pci_dev *pci_dev;
711
712 pci_dev = to_pci_dev(dev);
713 kfree(pci_dev);
714}
715
716/**
717 * pci_cfg_space_size - get the configuration space size of the PCI device.
8f7020d3 718 * @dev: PCI device
1da177e4
LT		 719 *
720 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
721 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
722 * access it. Maybe we don't have a way to generate extended config space
723 * accesses, or the device is behind a reverse Express bridge. So we try
724 * reading the dword at 0x100 which must either be 0 or a valid extended
725 * capability header.
726 */
ac7dc65a 727int pci_cfg_space_size(struct pci_dev *dev)
1da177e4
LT		 728{
729 int pos;
730 u32 status;
731
732 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
733 if (!pos) {
734 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
735 if (!pos)
736 goto fail;
737
738 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
739 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
740 goto fail;
741 }
742
743 if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL)
744 goto fail;
745 if (status == 0xffffffff)
746 goto fail;
747
748 return PCI_CFG_SPACE_EXP_SIZE;
749
750 fail:
751 return PCI_CFG_SPACE_SIZE;
752}
753
754static void pci_release_bus_bridge_dev(struct device *dev)
755{
756 kfree(dev);
757}
758
759/*
760 * Read the config data for a PCI device, sanity-check it
761 * and fill in the dev structure...
762 */
763static struct pci_dev * __devinit
764pci_scan_device(struct pci_bus *bus, int devfn)
765{
766 struct pci_dev *dev;
767 u32 l;
768 u8 hdr_type;
769 int delay = 1;
770
771 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
772 return NULL;
773
774 /* some broken boards return 0 or ~0 if a slot is empty: */
775 if (l == 0xffffffff || l == 0x00000000 ||
776 l == 0x0000ffff || l == 0xffff0000)
777 return NULL;
778
779 /* Configuration request Retry Status */
780 while (l == 0xffff0001) {
781 msleep(delay);
782 delay *= 2;
783 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
784 return NULL;
785 /* Card hasn't responded in 60 seconds? Must be stuck. */
786 if (delay > 60 * 1000) {
787 printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "
788 "responding\n", pci_domain_nr(bus),
789 bus->number, PCI_SLOT(devfn),
790 PCI_FUNC(devfn));
791 return NULL;
792 }
793 }
794
795 if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type))
796 return NULL;
797
798 dev = kmalloc(sizeof(struct pci_dev), GFP_KERNEL);
799 if (!dev)
800 return NULL;
801
802 memset(dev, 0, sizeof(struct pci_dev));
803 dev->bus = bus;
804 dev->sysdata = bus->sysdata;
805 dev->dev.parent = bus->bridge;
806 dev->dev.bus = &pci_bus_type;
807 dev->devfn = devfn;
808 dev->hdr_type = hdr_type & 0x7f;
809 dev->multifunction = !!(hdr_type & 0x80);
810 dev->vendor = l & 0xffff;
811 dev->device = (l >> 16) & 0xffff;
812 dev->cfg_size = pci_cfg_space_size(dev);
813
814 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
815 set this higher, assuming the system even supports it. */
816 dev->dma_mask = 0xffffffff;
817 if (pci_setup_device(dev) < 0) {
818 kfree(dev);
819 return NULL;
820 }
1da177e4
LT		 821
822 return dev;
823}
824
cdb9b9f7 825void __devinit pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1da177e4 826{
cdb9b9f7
PM		 827 device_initialize(&dev->dev);
828 dev->dev.release = pci_release_dev;
829 pci_dev_get(dev);
1da177e4 830
cdb9b9f7
PM		 831 dev->dev.dma_mask = &dev->dma_mask;
832 dev->dev.coherent_dma_mask = 0xffffffffull;
1da177e4 833
1da177e4
LT		 834 /* Fix up broken headers */
835 pci_fixup_device(pci_fixup_header, dev);
836
837 /*
838 * Add the device to our list of discovered devices
839 * and the bus list for fixup functions, etc.
840 */
841 INIT_LIST_HEAD(&dev->global_list);
e4ea9bb7 842 spin_lock(&pci_bus_lock);
1da177e4 843 list_add_tail(&dev->bus_list, &bus->devices);
e4ea9bb7 844 spin_unlock(&pci_bus_lock);
cdb9b9f7
PM		 845}
846
847struct pci_dev * __devinit
848pci_scan_single_device(struct pci_bus *bus, int devfn)
849{
850 struct pci_dev *dev;
851
852 dev = pci_scan_device(bus, devfn);
853 if (!dev)
854 return NULL;
855
856 pci_device_add(dev, bus);
857 pci_scan_msi_device(dev);
1da177e4
LT		 858
859 return dev;
860}
861
862/**
863 * pci_scan_slot - scan a PCI slot on a bus for devices.
864 * @bus: PCI bus to scan
865 * @devfn: slot number to scan (must have zero function.)
866 *
867 * Scan a PCI slot on the specified PCI bus for devices, adding
868 * discovered devices to the @bus->devices list. New devices
869 * will have an empty dev->global_list head.
870 */
871int __devinit pci_scan_slot(struct pci_bus *bus, int devfn)
872{
873 int func, nr = 0;
874 int scan_all_fns;
875
876 scan_all_fns = pcibios_scan_all_fns(bus, devfn);
877
878 for (func = 0; func < 8; func++, devfn++) {
879 struct pci_dev *dev;
880
881 dev = pci_scan_single_device(bus, devfn);
882 if (dev) {
883 nr++;
884
885 /*
886 * If this is a single function device,
887 * don't scan past the first function.
888 */
889 if (!dev->multifunction) {
890 if (func > 0) {
891 dev->multifunction = 1;
892 } else {
893 break;
894 }
895 }
896 } else {
897 if (func == 0 && !scan_all_fns)
898 break;
899 }
900 }
901 return nr;
902}
903
904unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
905{
906 unsigned int devfn, pass, max = bus->secondary;
907 struct pci_dev *dev;
908
909 pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
910
911 /* Go find them, Rover! */
912 for (devfn = 0; devfn < 0x100; devfn += 8)
913 pci_scan_slot(bus, devfn);
914
915 /*
916 * After performing arch-dependent fixup of the bus, look behind
917 * all PCI-to-PCI bridges on this bus.
918 */
919 pr_debug("PCI: Fixups for bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
920 pcibios_fixup_bus(bus);
921 for (pass=0; pass < 2; pass++)
922 list_for_each_entry(dev, &bus->devices, bus_list) {
923 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
924 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
925 max = pci_scan_bridge(bus, dev, max, pass);
926 }
927
928 /*
929 * We've scanned the bus and so we know all about what's on
930 * the other side of any bridges that may be on this bus plus
931 * any devices.
932 *
933 * Return how far we've got finding sub-buses.
934 */
935 pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n",
936 pci_domain_nr(bus), bus->number, max);
937 return max;
938}
939
940unsigned int __devinit pci_do_scan_bus(struct pci_bus *bus)
941{
942 unsigned int max;
943
944 max = pci_scan_child_bus(bus);
945
946 /*
947 * Make the discovered devices available.
948 */
949 pci_bus_add_devices(bus);
950
951 return max;
952}
953
cdb9b9f7
PM		 954struct pci_bus * __devinit pci_create_bus(struct device *parent,
955 int bus, struct pci_ops *ops, void *sysdata)
1da177e4
LT		 956{
957 int error;
958 struct pci_bus *b;
959 struct device *dev;
960
961 b = pci_alloc_bus();
962 if (!b)
963 return NULL;
964
965 dev = kmalloc(sizeof(*dev), GFP_KERNEL);
966 if (!dev){
967 kfree(b);
968 return NULL;
969 }
970
971 b->sysdata = sysdata;
972 b->ops = ops;
973
974 if (pci_find_bus(pci_domain_nr(b), bus)) {
975 /* If we already got to this bus through a different bridge, ignore it */
976 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus);
977 goto err_out;
978 }
e4ea9bb7 979 spin_lock(&pci_bus_lock);
1da177e4 980 list_add_tail(&b->node, &pci_root_buses);
e4ea9bb7 981 spin_unlock(&pci_bus_lock);
1da177e4
LT		 982
983 memset(dev, 0, sizeof(*dev));
984 dev->parent = parent;
985 dev->release = pci_release_bus_bridge_dev;
986 sprintf(dev->bus_id, "pci%04x:%02x", pci_domain_nr(b), bus);
987 error = device_register(dev);
988 if (error)
989 goto dev_reg_err;
990 b->bridge = get_device(dev);
991
992 b->class_dev.class = &pcibus_class;
993 sprintf(b->class_dev.class_id, "%04x:%02x", pci_domain_nr(b), bus);
994 error = class_device_register(&b->class_dev);
995 if (error)
996 goto class_dev_reg_err;
997 error = class_device_create_file(&b->class_dev, &class_device_attr_cpuaffinity);
998 if (error)
999 goto class_dev_create_file_err;
1000
1001 /* Create legacy_io and legacy_mem files for this bus */
1002 pci_create_legacy_files(b);
1003
1004 error = sysfs_create_link(&b->class_dev.kobj, &b->bridge->kobj, "bridge");
1005 if (error)
1006 goto sys_create_link_err;
1007
1008 b->number = b->secondary = bus;
1009 b->resource[0] = &ioport_resource;
1010 b->resource[1] = &iomem_resource;
1011
1da177e4
LT		 1012 return b;
1013
1014sys_create_link_err:
1015 class_device_remove_file(&b->class_dev, &class_device_attr_cpuaffinity);
1016class_dev_create_file_err:
1017 class_device_unregister(&b->class_dev);
1018class_dev_reg_err:
1019 device_unregister(dev);
1020dev_reg_err:
e4ea9bb7 1021 spin_lock(&pci_bus_lock);
1da177e4 1022 list_del(&b->node);
e4ea9bb7 1023 spin_unlock(&pci_bus_lock);
1da177e4
LT		 1024err_out:
1025 kfree(dev);
1026 kfree(b);
1027 return NULL;
1028}
cdb9b9f7
PM		 1029EXPORT_SYMBOL_GPL(pci_create_bus);
1030
1031struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
1032 int bus, struct pci_ops *ops, void *sysdata)
1033{
1034 struct pci_bus *b;
1035
1036 b = pci_create_bus(parent, bus, ops, sysdata);
1037 if (b)
1038 b->subordinate = pci_scan_child_bus(b);
1039 return b;
1040}
1da177e4
LT		 1041EXPORT_SYMBOL(pci_scan_bus_parented);
1042
1043#ifdef CONFIG_HOTPLUG
1044EXPORT_SYMBOL(pci_add_new_bus);
1045EXPORT_SYMBOL(pci_do_scan_bus);
1046EXPORT_SYMBOL(pci_scan_slot);
1047EXPORT_SYMBOL(pci_scan_bridge);
1048EXPORT_SYMBOL(pci_scan_single_device);
1049EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1050#endif
kernel source for telekom puls (alcatel/mediatek)