[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / pci / pcie / portdrv.h

/*
 * File:	portdrv.h
 * Purpose:	PCI Express Port Bus Driver's Internal Data Structures
 *
 * Copyright (C) 2004 Intel
 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
 */

#ifndef _PORTDRV_H_
#define _PORTDRV_H_

#include <linux/compiler.h>

#if !defined(PCI_CAP_ID_PME)
#define PCI_CAP_ID_PME			1
#endif

#if !defined(PCI_CAP_ID_EXP)
#define PCI_CAP_ID_EXP			0x10
#endif

#define PORT_TYPE_MASK			0xf
#define PORT_TO_SLOT_MASK		0x100
#define SLOT_HP_CAPABLE_MASK		0x40
#define PCIE_CAPABILITIES_REG		0x2
#define PCIE_SLOT_CAPABILITIES_REG	0x14
#define PCIE_PORT_DEVICE_MAXSERVICES	4
#define PCIE_PORT_MSI_VECTOR_MASK	0x1f
/*
 * According to the PCI Express Base Specification 2.0, the indices of the MSI-X
 * table entires used by port services must not exceed 31
 */
#define PCIE_PORT_MAX_MSIX_ENTRIES	32

#define get_descriptor_id(type, service) (((type - 4) << 4) | service)

extern struct bus_type pcie_port_bus_type;
extern int pcie_port_device_probe(struct pci_dev *dev);
extern int pcie_port_device_register(struct pci_dev *dev);
#ifdef CONFIG_PM
extern int pcie_port_device_suspend(struct device *dev);
extern int pcie_port_device_resume(struct device *dev);
#endif
extern void pcie_port_device_remove(struct pci_dev *dev);
extern int __must_check pcie_port_bus_register(void);
extern void pcie_port_bus_unregister(void);

#endif /* _PORTDRV_H_ */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* File: portdrv.h
	3	* Purpose: PCI Express Port Bus Driver's Internal Data Structures
	4	*
	5	* Copyright (C) 2004 Intel
	6	* Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
	7	*/
	8
	9	#ifndef _PORTDRV_H_
	10	#define _PORTDRV_H_
	11
3ec6a8d0 AM	12	#include <linux/compiler.h>
3ec6a8d0 AM	13
1da177e4 LT	14	#if !defined(PCI_CAP_ID_PME)
	15	#define PCI_CAP_ID_PME 1
	16	#endif
	17
	18	#if !defined(PCI_CAP_ID_EXP)
	19	#define PCI_CAP_ID_EXP 0x10
	20	#endif
	21
	22	#define PORT_TYPE_MASK 0xf
	23	#define PORT_TO_SLOT_MASK 0x100
	24	#define SLOT_HP_CAPABLE_MASK 0x40
	25	#define PCIE_CAPABILITIES_REG 0x2
	26	#define PCIE_SLOT_CAPABILITIES_REG 0x14
	27	#define PCIE_PORT_DEVICE_MAXSERVICES 4
b43d4513 RW	28	#define PCIE_PORT_MSI_VECTOR_MASK 0x1f
	29	/*
	30	* According to the PCI Express Base Specification 2.0, the indices of the MSI-X
	31	* table entires used by port services must not exceed 31
	32	*/
	33	#define PCIE_PORT_MAX_MSIX_ENTRIES 32
1da177e4 LT	34
	35	#define get_descriptor_id(type, service) (((type - 4) << 4) \| service)
	36
	37	extern struct bus_type pcie_port_bus_type;
	38	extern int pcie_port_device_probe(struct pci_dev *dev);
	39	extern int pcie_port_device_register(struct pci_dev *dev);
	40	#ifdef CONFIG_PM
3a3c244c RW	41	extern int pcie_port_device_suspend(struct device *dev);
3a3c244c RW	42	extern int pcie_port_device_resume(struct device *dev);
1da177e4 LT	43	#endif
1da177e4 LT	44	extern void pcie_port_device_remove(struct pci_dev *dev);
3ec6a8d0	45	extern int __must_check pcie_port_bus_register(void);
1da177e4 LT	46	extern void pcie_port_bus_unregister(void);
	47
	48	#endif /* _PORTDRV_H_ */