Commit | Line | Data |
---|---|---|
7d715a6c SL |
1 | /* |
2 | * File: drivers/pci/pcie/aspm.c | |
3 | * Enabling PCIE link L0s/L1 state and Clock Power Management | |
4 | * | |
5 | * Copyright (C) 2007 Intel | |
6 | * Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com) | |
7 | * Copyright (C) Shaohua Li (shaohua.li@intel.com) | |
8 | */ | |
9 | ||
10 | #include <linux/kernel.h> | |
11 | #include <linux/module.h> | |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/pci_regs.h> | |
15 | #include <linux/errno.h> | |
16 | #include <linux/pm.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/slab.h> | |
2a42d9db | 19 | #include <linux/jiffies.h> |
987a4c78 | 20 | #include <linux/delay.h> |
7d715a6c SL |
21 | #include <linux/pci-aspm.h> |
22 | #include "../pci.h" | |
23 | ||
24 | #ifdef MODULE_PARAM_PREFIX | |
25 | #undef MODULE_PARAM_PREFIX | |
26 | #endif | |
27 | #define MODULE_PARAM_PREFIX "pcie_aspm." | |
28 | ||
b6c2e54d KK |
29 | struct aspm_latency { |
30 | u32 l0s; /* L0s latency (nsec) */ | |
31 | u32 l1; /* L1 latency (nsec) */ | |
7d715a6c SL |
32 | }; |
33 | ||
34 | struct pcie_link_state { | |
5cde89d8 | 35 | struct pci_dev *pdev; /* Upstream component of the Link */ |
5c92ffb1 | 36 | struct pcie_link_state *root; /* pointer to the root port link */ |
5cde89d8 KK |
37 | struct pcie_link_state *parent; /* pointer to the parent Link state */ |
38 | struct list_head sibling; /* node in link_list */ | |
39 | struct list_head children; /* list of child link states */ | |
40 | struct list_head link; /* node in parent's children list */ | |
7d715a6c SL |
41 | |
42 | /* ASPM state */ | |
80bfdbe3 KK |
43 | u32 aspm_support:2; /* Supported ASPM state */ |
44 | u32 aspm_enabled:2; /* Enabled ASPM state */ | |
45 | u32 aspm_default:2; /* Default ASPM state by BIOS */ | |
46 | ||
4d246e45 KK |
47 | /* Clock PM state */ |
48 | u32 clkpm_capable:1; /* Clock PM capable? */ | |
49 | u32 clkpm_enabled:1; /* Current Clock PM state */ | |
50 | u32 clkpm_default:1; /* Default Clock PM state by BIOS */ | |
51 | ||
b6c2e54d KK |
52 | /* Latencies */ |
53 | struct aspm_latency latency; /* Exit latency */ | |
7d715a6c | 54 | /* |
b6c2e54d KK |
55 | * Endpoint acceptable latencies. A pcie downstream port only |
56 | * has one slot under it, so at most there are 8 functions. | |
7d715a6c | 57 | */ |
b6c2e54d | 58 | struct aspm_latency acceptable[8]; |
7d715a6c SL |
59 | }; |
60 | ||
d6d38574 | 61 | static int aspm_disabled, aspm_force; |
7d715a6c SL |
62 | static DEFINE_MUTEX(aspm_lock); |
63 | static LIST_HEAD(link_list); | |
64 | ||
65 | #define POLICY_DEFAULT 0 /* BIOS default setting */ | |
66 | #define POLICY_PERFORMANCE 1 /* high performance */ | |
67 | #define POLICY_POWERSAVE 2 /* high power saving */ | |
68 | static int aspm_policy; | |
69 | static const char *policy_str[] = { | |
70 | [POLICY_DEFAULT] = "default", | |
71 | [POLICY_PERFORMANCE] = "performance", | |
72 | [POLICY_POWERSAVE] = "powersave" | |
73 | }; | |
74 | ||
987a4c78 AP |
75 | #define LINK_RETRAIN_TIMEOUT HZ |
76 | ||
5aa63583 | 77 | static int policy_to_aspm_state(struct pcie_link_state *link) |
7d715a6c | 78 | { |
7d715a6c SL |
79 | switch (aspm_policy) { |
80 | case POLICY_PERFORMANCE: | |
81 | /* Disable ASPM and Clock PM */ | |
82 | return 0; | |
83 | case POLICY_POWERSAVE: | |
84 | /* Enable ASPM L0s/L1 */ | |
80bfdbe3 | 85 | return PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1; |
7d715a6c | 86 | case POLICY_DEFAULT: |
5aa63583 | 87 | return link->aspm_default; |
7d715a6c SL |
88 | } |
89 | return 0; | |
90 | } | |
91 | ||
5aa63583 | 92 | static int policy_to_clkpm_state(struct pcie_link_state *link) |
7d715a6c | 93 | { |
7d715a6c SL |
94 | switch (aspm_policy) { |
95 | case POLICY_PERFORMANCE: | |
96 | /* Disable ASPM and Clock PM */ | |
97 | return 0; | |
98 | case POLICY_POWERSAVE: | |
99 | /* Disable Clock PM */ | |
100 | return 1; | |
101 | case POLICY_DEFAULT: | |
5aa63583 | 102 | return link->clkpm_default; |
7d715a6c SL |
103 | } |
104 | return 0; | |
105 | } | |
106 | ||
430842e2 | 107 | static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable) |
7d715a6c | 108 | { |
7d715a6c SL |
109 | int pos; |
110 | u16 reg16; | |
5aa63583 KK |
111 | struct pci_dev *child; |
112 | struct pci_bus *linkbus = link->pdev->subordinate; | |
7d715a6c | 113 | |
5aa63583 KK |
114 | list_for_each_entry(child, &linkbus->devices, bus_list) { |
115 | pos = pci_find_capability(child, PCI_CAP_ID_EXP); | |
7d715a6c SL |
116 | if (!pos) |
117 | return; | |
5aa63583 | 118 | pci_read_config_word(child, pos + PCI_EXP_LNKCTL, ®16); |
7d715a6c SL |
119 | if (enable) |
120 | reg16 |= PCI_EXP_LNKCTL_CLKREQ_EN; | |
121 | else | |
122 | reg16 &= ~PCI_EXP_LNKCTL_CLKREQ_EN; | |
5aa63583 | 123 | pci_write_config_word(child, pos + PCI_EXP_LNKCTL, reg16); |
7d715a6c | 124 | } |
5aa63583 | 125 | link->clkpm_enabled = !!enable; |
7d715a6c SL |
126 | } |
127 | ||
430842e2 KK |
128 | static void pcie_set_clkpm(struct pcie_link_state *link, int enable) |
129 | { | |
130 | /* Don't enable Clock PM if the link is not Clock PM capable */ | |
131 | if (!link->clkpm_capable && enable) | |
132 | return; | |
133 | /* Need nothing if the specified equals to current state */ | |
134 | if (link->clkpm_enabled == enable) | |
135 | return; | |
136 | pcie_set_clkpm_nocheck(link, enable); | |
137 | } | |
138 | ||
8d349ace | 139 | static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist) |
7d715a6c | 140 | { |
5aa63583 | 141 | int pos, capable = 1, enabled = 1; |
7d715a6c SL |
142 | u32 reg32; |
143 | u16 reg16; | |
5aa63583 KK |
144 | struct pci_dev *child; |
145 | struct pci_bus *linkbus = link->pdev->subordinate; | |
7d715a6c SL |
146 | |
147 | /* All functions should have the same cap and state, take the worst */ | |
5aa63583 KK |
148 | list_for_each_entry(child, &linkbus->devices, bus_list) { |
149 | pos = pci_find_capability(child, PCI_CAP_ID_EXP); | |
7d715a6c SL |
150 | if (!pos) |
151 | return; | |
5aa63583 | 152 | pci_read_config_dword(child, pos + PCI_EXP_LNKCAP, ®32); |
7d715a6c SL |
153 | if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) { |
154 | capable = 0; | |
155 | enabled = 0; | |
156 | break; | |
157 | } | |
5aa63583 | 158 | pci_read_config_word(child, pos + PCI_EXP_LNKCTL, ®16); |
7d715a6c SL |
159 | if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN)) |
160 | enabled = 0; | |
161 | } | |
5aa63583 KK |
162 | link->clkpm_enabled = enabled; |
163 | link->clkpm_default = enabled; | |
8d349ace | 164 | link->clkpm_capable = (blacklist) ? 0 : capable; |
46bbdfa4 SL |
165 | } |
166 | ||
5aa63583 | 167 | static bool pcie_aspm_downstream_has_switch(struct pcie_link_state *link) |
46bbdfa4 | 168 | { |
5aa63583 KK |
169 | struct pci_dev *child; |
170 | struct pci_bus *linkbus = link->pdev->subordinate; | |
46bbdfa4 | 171 | |
5aa63583 KK |
172 | list_for_each_entry(child, &linkbus->devices, bus_list) { |
173 | if (child->pcie_type == PCI_EXP_TYPE_UPSTREAM) | |
46bbdfa4 SL |
174 | return true; |
175 | } | |
176 | return false; | |
7d715a6c SL |
177 | } |
178 | ||
179 | /* | |
180 | * pcie_aspm_configure_common_clock: check if the 2 ends of a link | |
181 | * could use common clock. If they are, configure them to use the | |
182 | * common clock. That will reduce the ASPM state exit latency. | |
183 | */ | |
5aa63583 | 184 | static void pcie_aspm_configure_common_clock(struct pcie_link_state *link) |
7d715a6c | 185 | { |
5aa63583 KK |
186 | int ppos, cpos, same_clock = 1; |
187 | u16 reg16, parent_reg, child_reg[8]; | |
2a42d9db | 188 | unsigned long start_jiffies; |
5aa63583 KK |
189 | struct pci_dev *child, *parent = link->pdev; |
190 | struct pci_bus *linkbus = parent->subordinate; | |
7d715a6c | 191 | /* |
5aa63583 | 192 | * All functions of a slot should have the same Slot Clock |
7d715a6c | 193 | * Configuration, so just check one function |
5aa63583 KK |
194 | */ |
195 | child = list_entry(linkbus->devices.next, struct pci_dev, bus_list); | |
196 | BUG_ON(!child->is_pcie); | |
7d715a6c SL |
197 | |
198 | /* Check downstream component if bit Slot Clock Configuration is 1 */ | |
5aa63583 KK |
199 | cpos = pci_find_capability(child, PCI_CAP_ID_EXP); |
200 | pci_read_config_word(child, cpos + PCI_EXP_LNKSTA, ®16); | |
7d715a6c SL |
201 | if (!(reg16 & PCI_EXP_LNKSTA_SLC)) |
202 | same_clock = 0; | |
203 | ||
204 | /* Check upstream component if bit Slot Clock Configuration is 1 */ | |
5aa63583 KK |
205 | ppos = pci_find_capability(parent, PCI_CAP_ID_EXP); |
206 | pci_read_config_word(parent, ppos + PCI_EXP_LNKSTA, ®16); | |
7d715a6c SL |
207 | if (!(reg16 & PCI_EXP_LNKSTA_SLC)) |
208 | same_clock = 0; | |
209 | ||
210 | /* Configure downstream component, all functions */ | |
5aa63583 KK |
211 | list_for_each_entry(child, &linkbus->devices, bus_list) { |
212 | cpos = pci_find_capability(child, PCI_CAP_ID_EXP); | |
213 | pci_read_config_word(child, cpos + PCI_EXP_LNKCTL, ®16); | |
214 | child_reg[PCI_FUNC(child->devfn)] = reg16; | |
7d715a6c SL |
215 | if (same_clock) |
216 | reg16 |= PCI_EXP_LNKCTL_CCC; | |
217 | else | |
218 | reg16 &= ~PCI_EXP_LNKCTL_CCC; | |
5aa63583 | 219 | pci_write_config_word(child, cpos + PCI_EXP_LNKCTL, reg16); |
7d715a6c SL |
220 | } |
221 | ||
222 | /* Configure upstream component */ | |
5aa63583 | 223 | pci_read_config_word(parent, ppos + PCI_EXP_LNKCTL, ®16); |
2a42d9db | 224 | parent_reg = reg16; |
7d715a6c SL |
225 | if (same_clock) |
226 | reg16 |= PCI_EXP_LNKCTL_CCC; | |
227 | else | |
228 | reg16 &= ~PCI_EXP_LNKCTL_CCC; | |
5aa63583 | 229 | pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, reg16); |
7d715a6c | 230 | |
5aa63583 | 231 | /* Retrain link */ |
7d715a6c | 232 | reg16 |= PCI_EXP_LNKCTL_RL; |
5aa63583 | 233 | pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, reg16); |
7d715a6c | 234 | |
5aa63583 | 235 | /* Wait for link training end. Break out after waiting for timeout */ |
2a42d9db | 236 | start_jiffies = jiffies; |
987a4c78 | 237 | for (;;) { |
5aa63583 | 238 | pci_read_config_word(parent, ppos + PCI_EXP_LNKSTA, ®16); |
7d715a6c SL |
239 | if (!(reg16 & PCI_EXP_LNKSTA_LT)) |
240 | break; | |
987a4c78 AP |
241 | if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) |
242 | break; | |
243 | msleep(1); | |
7d715a6c | 244 | } |
5aa63583 KK |
245 | if (!(reg16 & PCI_EXP_LNKSTA_LT)) |
246 | return; | |
247 | ||
248 | /* Training failed. Restore common clock configurations */ | |
249 | dev_printk(KERN_ERR, &parent->dev, | |
250 | "ASPM: Could not configure common clock\n"); | |
251 | list_for_each_entry(child, &linkbus->devices, bus_list) { | |
252 | cpos = pci_find_capability(child, PCI_CAP_ID_EXP); | |
253 | pci_write_config_word(child, cpos + PCI_EXP_LNKCTL, | |
254 | child_reg[PCI_FUNC(child->devfn)]); | |
2a42d9db | 255 | } |
5aa63583 | 256 | pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, parent_reg); |
7d715a6c SL |
257 | } |
258 | ||
5e0eaa7d KK |
259 | /* Convert L0s latency encoding to ns */ |
260 | static u32 calc_l0s_latency(u32 encoding) | |
7d715a6c | 261 | { |
5e0eaa7d KK |
262 | if (encoding == 0x7) |
263 | return (5 * 1000); /* > 4us */ | |
264 | return (64 << encoding); | |
265 | } | |
7d715a6c | 266 | |
5e0eaa7d KK |
267 | /* Convert L0s acceptable latency encoding to ns */ |
268 | static u32 calc_l0s_acceptable(u32 encoding) | |
269 | { | |
270 | if (encoding == 0x7) | |
271 | return -1U; | |
272 | return (64 << encoding); | |
7d715a6c SL |
273 | } |
274 | ||
5e0eaa7d KK |
275 | /* Convert L1 latency encoding to ns */ |
276 | static u32 calc_l1_latency(u32 encoding) | |
7d715a6c | 277 | { |
5e0eaa7d KK |
278 | if (encoding == 0x7) |
279 | return (65 * 1000); /* > 64us */ | |
280 | return (1000 << encoding); | |
281 | } | |
7d715a6c | 282 | |
5e0eaa7d KK |
283 | /* Convert L1 acceptable latency encoding to ns */ |
284 | static u32 calc_l1_acceptable(u32 encoding) | |
285 | { | |
286 | if (encoding == 0x7) | |
287 | return -1U; | |
288 | return (1000 << encoding); | |
7d715a6c SL |
289 | } |
290 | ||
291 | static void pcie_aspm_get_cap_device(struct pci_dev *pdev, u32 *state, | |
7ab70991 | 292 | u32 *l0s, u32 *l1, u32 *enabled) |
7d715a6c SL |
293 | { |
294 | int pos; | |
295 | u16 reg16; | |
5e0eaa7d | 296 | u32 reg32, encoding; |
7d715a6c | 297 | |
80bfdbe3 | 298 | *l0s = *l1 = *enabled = 0; |
7d715a6c SL |
299 | pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); |
300 | pci_read_config_dword(pdev, pos + PCI_EXP_LNKCAP, ®32); | |
301 | *state = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10; | |
302 | if (*state != PCIE_LINK_STATE_L0S && | |
7ab70991 | 303 | *state != (PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_L0S)) |
7d715a6c SL |
304 | *state = 0; |
305 | if (*state == 0) | |
306 | return; | |
307 | ||
5e0eaa7d KK |
308 | encoding = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12; |
309 | *l0s = calc_l0s_latency(encoding); | |
7d715a6c | 310 | if (*state & PCIE_LINK_STATE_L1) { |
5e0eaa7d KK |
311 | encoding = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15; |
312 | *l1 = calc_l1_latency(encoding); | |
7d715a6c SL |
313 | } |
314 | pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, ®16); | |
7ab70991 | 315 | *enabled = reg16 & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); |
7d715a6c SL |
316 | } |
317 | ||
8d349ace | 318 | static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) |
7d715a6c | 319 | { |
80bfdbe3 | 320 | u32 support, l0s, l1, enabled; |
5aa63583 KK |
321 | struct pci_dev *child, *parent = link->pdev; |
322 | struct pci_bus *linkbus = parent->subordinate; | |
7d715a6c | 323 | |
8d349ace KK |
324 | if (blacklist) { |
325 | /* Set support state to 0, so we will disable ASPM later */ | |
326 | link->aspm_support = 0; | |
327 | link->aspm_default = 0; | |
328 | link->aspm_enabled = PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1; | |
329 | return; | |
330 | } | |
331 | ||
332 | /* Configure common clock before checking latencies */ | |
333 | pcie_aspm_configure_common_clock(link); | |
334 | ||
7d715a6c | 335 | /* upstream component states */ |
5aa63583 KK |
336 | pcie_aspm_get_cap_device(parent, &support, &l0s, &l1, &enabled); |
337 | link->aspm_support = support; | |
338 | link->latency.l0s = l0s; | |
339 | link->latency.l1 = l1; | |
340 | link->aspm_enabled = enabled; | |
80bfdbe3 | 341 | |
7d715a6c | 342 | /* downstream component states, all functions have the same setting */ |
5aa63583 KK |
343 | child = list_entry(linkbus->devices.next, struct pci_dev, bus_list); |
344 | pcie_aspm_get_cap_device(child, &support, &l0s, &l1, &enabled); | |
345 | link->aspm_support &= support; | |
346 | link->latency.l0s = max_t(u32, link->latency.l0s, l0s); | |
347 | link->latency.l1 = max_t(u32, link->latency.l1, l1); | |
348 | ||
349 | if (!link->aspm_support) | |
7d715a6c | 350 | return; |
80bfdbe3 | 351 | |
5aa63583 KK |
352 | link->aspm_enabled &= link->aspm_support; |
353 | link->aspm_default = link->aspm_enabled; | |
7d715a6c SL |
354 | |
355 | /* ENDPOINT states*/ | |
5aa63583 | 356 | list_for_each_entry(child, &linkbus->devices, bus_list) { |
7d715a6c | 357 | int pos; |
5e0eaa7d | 358 | u32 reg32, encoding; |
b6c2e54d | 359 | struct aspm_latency *acceptable = |
5aa63583 | 360 | &link->acceptable[PCI_FUNC(child->devfn)]; |
7d715a6c | 361 | |
5aa63583 KK |
362 | if (child->pcie_type != PCI_EXP_TYPE_ENDPOINT && |
363 | child->pcie_type != PCI_EXP_TYPE_LEG_END) | |
7d715a6c SL |
364 | continue; |
365 | ||
5aa63583 KK |
366 | pos = pci_find_capability(child, PCI_CAP_ID_EXP); |
367 | pci_read_config_dword(child, pos + PCI_EXP_DEVCAP, ®32); | |
5e0eaa7d KK |
368 | encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6; |
369 | acceptable->l0s = calc_l0s_acceptable(encoding); | |
5aa63583 | 370 | if (link->aspm_support & PCIE_LINK_STATE_L1) { |
5e0eaa7d KK |
371 | encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9; |
372 | acceptable->l1 = calc_l1_acceptable(encoding); | |
7d715a6c SL |
373 | } |
374 | } | |
375 | } | |
376 | ||
f7ea3d7f KK |
377 | /** |
378 | * __pcie_aspm_check_state_one - check latency for endpoint device. | |
379 | * @endpoint: pointer to the struct pci_dev of endpoint device | |
380 | * | |
381 | * TBD: The latency from the endpoint to root complex vary per switch's | |
382 | * upstream link state above the device. Here we just do a simple check | |
383 | * which assumes all links above the device can be in L1 state, that | |
384 | * is we just consider the worst case. If switch's upstream link can't | |
385 | * be put into L0S/L1, then our check is too strictly. | |
386 | */ | |
387 | static u32 __pcie_aspm_check_state_one(struct pci_dev *endpoint, u32 state) | |
7d715a6c | 388 | { |
f7ea3d7f | 389 | u32 l1_switch_latency = 0; |
b6c2e54d | 390 | struct aspm_latency *acceptable; |
f7ea3d7f | 391 | struct pcie_link_state *link; |
7d715a6c | 392 | |
f7ea3d7f KK |
393 | link = endpoint->bus->self->link_state; |
394 | state &= link->aspm_support; | |
395 | acceptable = &link->acceptable[PCI_FUNC(endpoint->devfn)]; | |
7d715a6c | 396 | |
f7ea3d7f | 397 | while (link && state) { |
b6c2e54d | 398 | if ((state & PCIE_LINK_STATE_L0S) && |
f7ea3d7f | 399 | (link->latency.l0s > acceptable->l0s)) |
b6c2e54d | 400 | state &= ~PCIE_LINK_STATE_L0S; |
b6c2e54d | 401 | if ((state & PCIE_LINK_STATE_L1) && |
f7ea3d7f | 402 | (link->latency.l1 + l1_switch_latency > acceptable->l1)) |
b6c2e54d | 403 | state &= ~PCIE_LINK_STATE_L1; |
f7ea3d7f KK |
404 | link = link->parent; |
405 | /* | |
406 | * Every switch on the path to root complex need 1 | |
407 | * more microsecond for L1. Spec doesn't mention L0s. | |
408 | */ | |
409 | l1_switch_latency += 1000; | |
7d715a6c SL |
410 | } |
411 | return state; | |
412 | } | |
413 | ||
5aa63583 | 414 | static u32 pcie_aspm_check_state(struct pcie_link_state *link, u32 state) |
7d715a6c | 415 | { |
5aa63583 KK |
416 | pci_power_t power_state; |
417 | struct pci_dev *child; | |
418 | struct pci_bus *linkbus = link->pdev->subordinate; | |
7d715a6c | 419 | |
46bbdfa4 | 420 | /* If no child, ignore the link */ |
5aa63583 | 421 | if (list_empty(&linkbus->devices)) |
46bbdfa4 | 422 | return state; |
5aa63583 KK |
423 | |
424 | list_for_each_entry(child, &linkbus->devices, bus_list) { | |
425 | /* | |
426 | * If downstream component of a link is pci bridge, we | |
427 | * disable ASPM for now for the link | |
428 | */ | |
429 | if (child->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE) | |
430 | return 0; | |
431 | ||
432 | if ((child->pcie_type != PCI_EXP_TYPE_ENDPOINT && | |
433 | child->pcie_type != PCI_EXP_TYPE_LEG_END)) | |
7d715a6c SL |
434 | continue; |
435 | /* Device not in D0 doesn't need check latency */ | |
5aa63583 KK |
436 | power_state = child->current_state; |
437 | if (power_state == PCI_D1 || power_state == PCI_D2 || | |
438 | power_state == PCI_D3hot || power_state == PCI_D3cold) | |
7d715a6c | 439 | continue; |
5aa63583 | 440 | state = __pcie_aspm_check_state_one(child, state); |
7d715a6c SL |
441 | } |
442 | return state; | |
443 | } | |
444 | ||
445 | static void __pcie_aspm_config_one_dev(struct pci_dev *pdev, unsigned int state) | |
446 | { | |
447 | u16 reg16; | |
448 | int pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); | |
449 | ||
450 | pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, ®16); | |
451 | reg16 &= ~0x3; | |
452 | reg16 |= state; | |
453 | pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16); | |
454 | } | |
455 | ||
5aa63583 | 456 | static void __pcie_aspm_config_link(struct pcie_link_state *link, u32 state) |
7d715a6c | 457 | { |
5aa63583 KK |
458 | struct pci_dev *child, *parent = link->pdev; |
459 | struct pci_bus *linkbus = parent->subordinate; | |
7d715a6c | 460 | |
46bbdfa4 | 461 | /* If no child, disable the link */ |
5aa63583 | 462 | if (list_empty(&linkbus->devices)) |
46bbdfa4 | 463 | state = 0; |
7d715a6c | 464 | /* |
5aa63583 KK |
465 | * If the downstream component has pci bridge function, don't |
466 | * do ASPM now. | |
7d715a6c | 467 | */ |
5aa63583 KK |
468 | list_for_each_entry(child, &linkbus->devices, bus_list) { |
469 | if (child->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE) | |
470 | return; | |
7d715a6c | 471 | } |
7d715a6c | 472 | /* |
5aa63583 KK |
473 | * Spec 2.0 suggests all functions should be configured the |
474 | * same setting for ASPM. Enabling ASPM L1 should be done in | |
475 | * upstream component first and then downstream, and vice | |
476 | * versa for disabling ASPM L1. Spec doesn't mention L0S. | |
7d715a6c SL |
477 | */ |
478 | if (state & PCIE_LINK_STATE_L1) | |
5aa63583 | 479 | __pcie_aspm_config_one_dev(parent, state); |
7d715a6c | 480 | |
5aa63583 KK |
481 | list_for_each_entry(child, &linkbus->devices, bus_list) |
482 | __pcie_aspm_config_one_dev(child, state); | |
7d715a6c SL |
483 | |
484 | if (!(state & PCIE_LINK_STATE_L1)) | |
5aa63583 | 485 | __pcie_aspm_config_one_dev(parent, state); |
7d715a6c | 486 | |
5aa63583 | 487 | link->aspm_enabled = state; |
7d715a6c SL |
488 | } |
489 | ||
5aa63583 KK |
490 | /* Check the whole hierarchy, and configure each link in the hierarchy */ |
491 | static void __pcie_aspm_configure_link_state(struct pcie_link_state *link, | |
492 | u32 state) | |
7d715a6c | 493 | { |
5c92ffb1 | 494 | struct pcie_link_state *leaf, *root = link->root; |
7d715a6c | 495 | |
5aa63583 | 496 | state &= (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); |
7d715a6c | 497 | |
5aa63583 | 498 | /* Check all links who have specific root port link */ |
dc64cd11 | 499 | list_for_each_entry(leaf, &link_list, sibling) { |
5c92ffb1 | 500 | if (!list_empty(&leaf->children) || (leaf->root != root)) |
46bbdfa4 | 501 | continue; |
5aa63583 | 502 | state = pcie_aspm_check_state(leaf, state); |
46bbdfa4 | 503 | } |
5aa63583 KK |
504 | /* Check root port link too in case it hasn't children */ |
505 | state = pcie_aspm_check_state(root, state); | |
506 | if (link->aspm_enabled == state) | |
7d715a6c | 507 | return; |
46bbdfa4 | 508 | /* |
5aa63583 | 509 | * We must change the hierarchy. See comments in |
46bbdfa4 SL |
510 | * __pcie_aspm_config_link for the order |
511 | **/ | |
512 | if (state & PCIE_LINK_STATE_L1) { | |
dc64cd11 | 513 | list_for_each_entry(leaf, &link_list, sibling) { |
5c92ffb1 | 514 | if (leaf->root == root) |
5aa63583 | 515 | __pcie_aspm_config_link(leaf, state); |
46bbdfa4 SL |
516 | } |
517 | } else { | |
dc64cd11 | 518 | list_for_each_entry_reverse(leaf, &link_list, sibling) { |
5c92ffb1 | 519 | if (leaf->root == root) |
5aa63583 | 520 | __pcie_aspm_config_link(leaf, state); |
46bbdfa4 SL |
521 | } |
522 | } | |
7d715a6c SL |
523 | } |
524 | ||
525 | /* | |
526 | * pcie_aspm_configure_link_state: enable/disable PCI express link state | |
527 | * @pdev: the root port or switch downstream port | |
528 | */ | |
5aa63583 KK |
529 | static void pcie_aspm_configure_link_state(struct pcie_link_state *link, |
530 | u32 state) | |
7d715a6c SL |
531 | { |
532 | down_read(&pci_bus_sem); | |
533 | mutex_lock(&aspm_lock); | |
5aa63583 | 534 | __pcie_aspm_configure_link_state(link, state); |
7d715a6c SL |
535 | mutex_unlock(&aspm_lock); |
536 | up_read(&pci_bus_sem); | |
537 | } | |
538 | ||
5aa63583 | 539 | static void free_link_state(struct pcie_link_state *link) |
7d715a6c | 540 | { |
5aa63583 KK |
541 | link->pdev->link_state = NULL; |
542 | kfree(link); | |
7d715a6c SL |
543 | } |
544 | ||
ddc9753f SL |
545 | static int pcie_aspm_sanity_check(struct pci_dev *pdev) |
546 | { | |
3647584d KK |
547 | struct pci_dev *child; |
548 | int pos; | |
149e1637 | 549 | u32 reg32; |
ddc9753f | 550 | /* |
3647584d KK |
551 | * Some functions in a slot might not all be PCIE functions, |
552 | * very strange. Disable ASPM for the whole slot | |
ddc9753f | 553 | */ |
3647584d KK |
554 | list_for_each_entry(child, &pdev->subordinate->devices, bus_list) { |
555 | pos = pci_find_capability(child, PCI_CAP_ID_EXP); | |
556 | if (!pos) | |
ddc9753f | 557 | return -EINVAL; |
149e1637 SL |
558 | /* |
559 | * Disable ASPM for pre-1.1 PCIe device, we follow MS to use | |
560 | * RBER bit to determine if a function is 1.1 version device | |
561 | */ | |
3647584d | 562 | pci_read_config_dword(child, pos + PCI_EXP_DEVCAP, ®32); |
e1f4f59d | 563 | if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) { |
3647584d | 564 | dev_printk(KERN_INFO, &child->dev, "disabling ASPM" |
f393d9b1 VL |
565 | " on pre-1.1 PCIe device. You can enable it" |
566 | " with 'pcie_aspm=force'\n"); | |
149e1637 SL |
567 | return -EINVAL; |
568 | } | |
ddc9753f SL |
569 | } |
570 | return 0; | |
571 | } | |
572 | ||
8d349ace KK |
573 | static struct pcie_link_state *pcie_aspm_setup_link_state(struct pci_dev *pdev) |
574 | { | |
575 | struct pcie_link_state *link; | |
576 | int blacklist = !!pcie_aspm_sanity_check(pdev); | |
577 | ||
578 | link = kzalloc(sizeof(*link), GFP_KERNEL); | |
579 | if (!link) | |
580 | return NULL; | |
581 | INIT_LIST_HEAD(&link->sibling); | |
582 | INIT_LIST_HEAD(&link->children); | |
583 | INIT_LIST_HEAD(&link->link); | |
584 | link->pdev = pdev; | |
8d349ace KK |
585 | if (pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM) { |
586 | struct pcie_link_state *parent; | |
587 | parent = pdev->bus->parent->self->link_state; | |
588 | if (!parent) { | |
589 | kfree(link); | |
590 | return NULL; | |
591 | } | |
592 | link->parent = parent; | |
593 | list_add(&link->link, &parent->children); | |
594 | } | |
5c92ffb1 KK |
595 | /* Setup a pointer to the root port link */ |
596 | if (!link->parent) | |
597 | link->root = link; | |
598 | else | |
599 | link->root = link->parent->root; | |
600 | ||
8d349ace KK |
601 | list_add(&link->sibling, &link_list); |
602 | ||
603 | pdev->link_state = link; | |
604 | ||
605 | /* Check ASPM capability */ | |
606 | pcie_aspm_cap_init(link, blacklist); | |
607 | ||
608 | /* Check Clock PM capability */ | |
609 | pcie_clkpm_cap_init(link, blacklist); | |
610 | ||
611 | return link; | |
612 | } | |
613 | ||
7d715a6c SL |
614 | /* |
615 | * pcie_aspm_init_link_state: Initiate PCI express link state. | |
616 | * It is called after the pcie and its children devices are scaned. | |
617 | * @pdev: the root port or switch downstream port | |
618 | */ | |
619 | void pcie_aspm_init_link_state(struct pci_dev *pdev) | |
620 | { | |
8d349ace KK |
621 | u32 state; |
622 | struct pcie_link_state *link; | |
7d715a6c SL |
623 | |
624 | if (aspm_disabled || !pdev->is_pcie || pdev->link_state) | |
625 | return; | |
626 | if (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && | |
8d349ace | 627 | pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) |
7d715a6c | 628 | return; |
8d349ace | 629 | |
8e822df7 SL |
630 | /* VIA has a strange chipset, root port is under a bridge */ |
631 | if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT && | |
8d349ace | 632 | pdev->bus->self) |
8e822df7 | 633 | return; |
8d349ace | 634 | |
7d715a6c SL |
635 | down_read(&pci_bus_sem); |
636 | if (list_empty(&pdev->subordinate->devices)) | |
637 | goto out; | |
638 | ||
639 | mutex_lock(&aspm_lock); | |
8d349ace KK |
640 | link = pcie_aspm_setup_link_state(pdev); |
641 | if (!link) | |
642 | goto unlock; | |
643 | /* | |
644 | * Setup initial ASPM state | |
645 | * | |
646 | * If link has switch, delay the link config. The leaf link | |
647 | * initialization will config the whole hierarchy. But we must | |
648 | * make sure BIOS doesn't set unsupported link state. | |
649 | */ | |
efdf8288 | 650 | if (pcie_aspm_downstream_has_switch(link)) { |
8d349ace KK |
651 | state = pcie_aspm_check_state(link, link->aspm_default); |
652 | __pcie_aspm_config_link(link, state); | |
46bbdfa4 | 653 | } else { |
8d349ace KK |
654 | state = policy_to_aspm_state(link); |
655 | __pcie_aspm_configure_link_state(link, state); | |
46bbdfa4 | 656 | } |
7d715a6c | 657 | |
8d349ace KK |
658 | /* Setup initial Clock PM state */ |
659 | state = (link->clkpm_capable) ? policy_to_clkpm_state(link) : 0; | |
430842e2 | 660 | pcie_set_clkpm(link, state); |
8d349ace | 661 | unlock: |
7d715a6c SL |
662 | mutex_unlock(&aspm_lock); |
663 | out: | |
664 | up_read(&pci_bus_sem); | |
665 | } | |
666 | ||
667 | /* @pdev: the endpoint device */ | |
668 | void pcie_aspm_exit_link_state(struct pci_dev *pdev) | |
669 | { | |
670 | struct pci_dev *parent = pdev->bus->self; | |
671 | struct pcie_link_state *link_state = parent->link_state; | |
672 | ||
673 | if (aspm_disabled || !pdev->is_pcie || !parent || !link_state) | |
674 | return; | |
675 | if (parent->pcie_type != PCI_EXP_TYPE_ROOT_PORT && | |
676 | parent->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) | |
677 | return; | |
678 | down_read(&pci_bus_sem); | |
679 | mutex_lock(&aspm_lock); | |
680 | ||
681 | /* | |
682 | * All PCIe functions are in one slot, remove one function will remove | |
3419c75e | 683 | * the whole slot, so just wait until we are the last function left. |
7d715a6c | 684 | */ |
3419c75e | 685 | if (!list_is_last(&pdev->bus_list, &parent->subordinate->devices)) |
7d715a6c SL |
686 | goto out; |
687 | ||
688 | /* All functions are removed, so just disable ASPM for the link */ | |
689 | __pcie_aspm_config_one_dev(parent, 0); | |
dc64cd11 | 690 | list_del(&link_state->sibling); |
46bbdfa4 | 691 | list_del(&link_state->link); |
7d715a6c SL |
692 | /* Clock PM is for endpoint device */ |
693 | ||
5aa63583 | 694 | free_link_state(link_state); |
7d715a6c SL |
695 | out: |
696 | mutex_unlock(&aspm_lock); | |
697 | up_read(&pci_bus_sem); | |
698 | } | |
699 | ||
700 | /* @pdev: the root port or switch downstream port */ | |
701 | void pcie_aspm_pm_state_change(struct pci_dev *pdev) | |
702 | { | |
703 | struct pcie_link_state *link_state = pdev->link_state; | |
704 | ||
705 | if (aspm_disabled || !pdev->is_pcie || !pdev->link_state) | |
706 | return; | |
707 | if (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && | |
708 | pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) | |
709 | return; | |
710 | /* | |
711 | * devices changed PM state, we should recheck if latency meets all | |
712 | * functions' requirement | |
713 | */ | |
5aa63583 | 714 | pcie_aspm_configure_link_state(link_state, link_state->aspm_enabled); |
7d715a6c SL |
715 | } |
716 | ||
717 | /* | |
718 | * pci_disable_link_state - disable pci device's link state, so the link will | |
719 | * never enter specific states | |
720 | */ | |
721 | void pci_disable_link_state(struct pci_dev *pdev, int state) | |
722 | { | |
723 | struct pci_dev *parent = pdev->bus->self; | |
724 | struct pcie_link_state *link_state; | |
725 | ||
726 | if (aspm_disabled || !pdev->is_pcie) | |
727 | return; | |
728 | if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT || | |
729 | pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM) | |
730 | parent = pdev; | |
731 | if (!parent || !parent->link_state) | |
732 | return; | |
733 | ||
734 | down_read(&pci_bus_sem); | |
735 | mutex_lock(&aspm_lock); | |
736 | link_state = parent->link_state; | |
80bfdbe3 | 737 | link_state->aspm_support &= ~state; |
5aa63583 | 738 | __pcie_aspm_configure_link_state(link_state, link_state->aspm_enabled); |
430842e2 KK |
739 | if (state & PCIE_LINK_STATE_CLKPM) { |
740 | link_state->clkpm_capable = 0; | |
741 | pcie_set_clkpm(link_state, 0); | |
742 | } | |
7d715a6c SL |
743 | mutex_unlock(&aspm_lock); |
744 | up_read(&pci_bus_sem); | |
745 | } | |
746 | EXPORT_SYMBOL(pci_disable_link_state); | |
747 | ||
748 | static int pcie_aspm_set_policy(const char *val, struct kernel_param *kp) | |
749 | { | |
750 | int i; | |
7d715a6c SL |
751 | struct pcie_link_state *link_state; |
752 | ||
753 | for (i = 0; i < ARRAY_SIZE(policy_str); i++) | |
754 | if (!strncmp(val, policy_str[i], strlen(policy_str[i]))) | |
755 | break; | |
756 | if (i >= ARRAY_SIZE(policy_str)) | |
757 | return -EINVAL; | |
758 | if (i == aspm_policy) | |
759 | return 0; | |
760 | ||
761 | down_read(&pci_bus_sem); | |
762 | mutex_lock(&aspm_lock); | |
763 | aspm_policy = i; | |
dc64cd11 | 764 | list_for_each_entry(link_state, &link_list, sibling) { |
5aa63583 KK |
765 | __pcie_aspm_configure_link_state(link_state, |
766 | policy_to_aspm_state(link_state)); | |
430842e2 | 767 | pcie_set_clkpm(link_state, policy_to_clkpm_state(link_state)); |
7d715a6c SL |
768 | } |
769 | mutex_unlock(&aspm_lock); | |
770 | up_read(&pci_bus_sem); | |
771 | return 0; | |
772 | } | |
773 | ||
774 | static int pcie_aspm_get_policy(char *buffer, struct kernel_param *kp) | |
775 | { | |
776 | int i, cnt = 0; | |
777 | for (i = 0; i < ARRAY_SIZE(policy_str); i++) | |
778 | if (i == aspm_policy) | |
779 | cnt += sprintf(buffer + cnt, "[%s] ", policy_str[i]); | |
780 | else | |
781 | cnt += sprintf(buffer + cnt, "%s ", policy_str[i]); | |
782 | return cnt; | |
783 | } | |
784 | ||
785 | module_param_call(policy, pcie_aspm_set_policy, pcie_aspm_get_policy, | |
786 | NULL, 0644); | |
787 | ||
788 | #ifdef CONFIG_PCIEASPM_DEBUG | |
789 | static ssize_t link_state_show(struct device *dev, | |
790 | struct device_attribute *attr, | |
791 | char *buf) | |
792 | { | |
793 | struct pci_dev *pci_device = to_pci_dev(dev); | |
794 | struct pcie_link_state *link_state = pci_device->link_state; | |
795 | ||
80bfdbe3 | 796 | return sprintf(buf, "%d\n", link_state->aspm_enabled); |
7d715a6c SL |
797 | } |
798 | ||
799 | static ssize_t link_state_store(struct device *dev, | |
800 | struct device_attribute *attr, | |
801 | const char *buf, | |
802 | size_t n) | |
803 | { | |
5aa63583 | 804 | struct pci_dev *pdev = to_pci_dev(dev); |
7d715a6c SL |
805 | int state; |
806 | ||
807 | if (n < 1) | |
808 | return -EINVAL; | |
809 | state = buf[0]-'0'; | |
810 | if (state >= 0 && state <= 3) { | |
811 | /* setup link aspm state */ | |
5aa63583 | 812 | pcie_aspm_configure_link_state(pdev->link_state, state); |
7d715a6c SL |
813 | return n; |
814 | } | |
815 | ||
816 | return -EINVAL; | |
817 | } | |
818 | ||
819 | static ssize_t clk_ctl_show(struct device *dev, | |
820 | struct device_attribute *attr, | |
821 | char *buf) | |
822 | { | |
823 | struct pci_dev *pci_device = to_pci_dev(dev); | |
824 | struct pcie_link_state *link_state = pci_device->link_state; | |
825 | ||
4d246e45 | 826 | return sprintf(buf, "%d\n", link_state->clkpm_enabled); |
7d715a6c SL |
827 | } |
828 | ||
829 | static ssize_t clk_ctl_store(struct device *dev, | |
830 | struct device_attribute *attr, | |
831 | const char *buf, | |
832 | size_t n) | |
833 | { | |
430842e2 | 834 | struct pci_dev *pdev = to_pci_dev(dev); |
7d715a6c SL |
835 | int state; |
836 | ||
837 | if (n < 1) | |
838 | return -EINVAL; | |
839 | state = buf[0]-'0'; | |
840 | ||
841 | down_read(&pci_bus_sem); | |
842 | mutex_lock(&aspm_lock); | |
430842e2 | 843 | pcie_set_clkpm_nocheck(pdev->link_state, !!state); |
7d715a6c SL |
844 | mutex_unlock(&aspm_lock); |
845 | up_read(&pci_bus_sem); | |
846 | ||
847 | return n; | |
848 | } | |
849 | ||
850 | static DEVICE_ATTR(link_state, 0644, link_state_show, link_state_store); | |
851 | static DEVICE_ATTR(clk_ctl, 0644, clk_ctl_show, clk_ctl_store); | |
852 | ||
853 | static char power_group[] = "power"; | |
854 | void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev) | |
855 | { | |
856 | struct pcie_link_state *link_state = pdev->link_state; | |
857 | ||
858 | if (!pdev->is_pcie || (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && | |
859 | pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) || !link_state) | |
860 | return; | |
861 | ||
80bfdbe3 | 862 | if (link_state->aspm_support) |
7d715a6c SL |
863 | sysfs_add_file_to_group(&pdev->dev.kobj, |
864 | &dev_attr_link_state.attr, power_group); | |
4d246e45 | 865 | if (link_state->clkpm_capable) |
7d715a6c SL |
866 | sysfs_add_file_to_group(&pdev->dev.kobj, |
867 | &dev_attr_clk_ctl.attr, power_group); | |
868 | } | |
869 | ||
870 | void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev) | |
871 | { | |
872 | struct pcie_link_state *link_state = pdev->link_state; | |
873 | ||
874 | if (!pdev->is_pcie || (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && | |
875 | pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) || !link_state) | |
876 | return; | |
877 | ||
80bfdbe3 | 878 | if (link_state->aspm_support) |
7d715a6c SL |
879 | sysfs_remove_file_from_group(&pdev->dev.kobj, |
880 | &dev_attr_link_state.attr, power_group); | |
4d246e45 | 881 | if (link_state->clkpm_capable) |
7d715a6c SL |
882 | sysfs_remove_file_from_group(&pdev->dev.kobj, |
883 | &dev_attr_clk_ctl.attr, power_group); | |
884 | } | |
885 | #endif | |
886 | ||
887 | static int __init pcie_aspm_disable(char *str) | |
888 | { | |
d6d38574 SL |
889 | if (!strcmp(str, "off")) { |
890 | aspm_disabled = 1; | |
891 | printk(KERN_INFO "PCIe ASPM is disabled\n"); | |
892 | } else if (!strcmp(str, "force")) { | |
893 | aspm_force = 1; | |
894 | printk(KERN_INFO "PCIe ASPM is forcedly enabled\n"); | |
895 | } | |
7d715a6c SL |
896 | return 1; |
897 | } | |
898 | ||
d6d38574 | 899 | __setup("pcie_aspm=", pcie_aspm_disable); |
7d715a6c | 900 | |
5fde244d SL |
901 | void pcie_no_aspm(void) |
902 | { | |
d6d38574 SL |
903 | if (!aspm_force) |
904 | aspm_disabled = 1; | |
5fde244d SL |
905 | } |
906 | ||
3e1b1600 AP |
907 | /** |
908 | * pcie_aspm_enabled - is PCIe ASPM enabled? | |
909 | * | |
910 | * Returns true if ASPM has not been disabled by the command-line option | |
911 | * pcie_aspm=off. | |
912 | **/ | |
913 | int pcie_aspm_enabled(void) | |
7d715a6c | 914 | { |
3e1b1600 | 915 | return !aspm_disabled; |
7d715a6c | 916 | } |
3e1b1600 | 917 | EXPORT_SYMBOL(pcie_aspm_enabled); |
7d715a6c | 918 |