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Linux 3.8-rc2
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / pci / pci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * PCI Bus Services, see include/linux/pci.h for further explanation.
3 *
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
5 * David Mosberger-Tang
6 *
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
8 */
9
10#include <linux/kernel.h>
11#include <linux/delay.h>
12#include <linux/init.h>
13#include <linux/pci.h>
075c1771 14#include <linux/pm.h>
5a0e3ad6 15#include <linux/slab.h>
1da177e4
LT		 16#include <linux/module.h>
17#include <linux/spinlock.h>
4e57b681 18#include <linux/string.h>
229f5afd 19#include <linux/log2.h>
7d715a6c 20#include <linux/pci-aspm.h>
c300bd2f 21#include <linux/pm_wakeup.h>
8dd7f803 22#include <linux/interrupt.h>
32a9a682 23#include <linux/device.h>
b67ea761 24#include <linux/pm_runtime.h>
284f5f9d 25#include <asm-generic/pci-bridge.h>
32a9a682 26#include <asm/setup.h>
bc56b9e0 27#include "pci.h"
1da177e4 28
00240c38
AS		 29const char *pci_power_names[] = {
30 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
31};
32EXPORT_SYMBOL_GPL(pci_power_names);
33
93177a74
RW		 34int isa_dma_bridge_buggy;
35EXPORT_SYMBOL(isa_dma_bridge_buggy);
36
37int pci_pci_problems;
38EXPORT_SYMBOL(pci_pci_problems);
39
1ae861e6
RW		 40unsigned int pci_pm_d3_delay;
41
df17e62e
MG		 42static void pci_pme_list_scan(struct work_struct *work);
43
44static LIST_HEAD(pci_pme_list);
45static DEFINE_MUTEX(pci_pme_list_mutex);
46static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
47
48struct pci_pme_device {
49 struct list_head list;
50 struct pci_dev *dev;
51};
52
53#define PME_TIMEOUT 1000 /* How long between PME checks */
54
1ae861e6
RW		 55static void pci_dev_d3_sleep(struct pci_dev *dev)
56{
57 unsigned int delay = dev->d3_delay;
58
59 if (delay < pci_pm_d3_delay)
60 delay = pci_pm_d3_delay;
61
62 msleep(delay);
63}
1da177e4 64
32a2eea7
JG		 65#ifdef CONFIG_PCI_DOMAINS
66int pci_domains_supported = 1;
67#endif
68
4516a618
AN		 69#define DEFAULT_CARDBUS_IO_SIZE (256)
70#define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
71/* pci=cbmemsize=nnM,cbiosize=nn can override this */
72unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
73unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
74
28760489
EB		 75#define DEFAULT_HOTPLUG_IO_SIZE (256)
76#define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
77/* pci=hpmemsize=nnM,hpiosize=nn can override this */
78unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
79unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
80
5f39e670 81enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
b03e7495 82
ac1aa47b
JB		 83/*
84 * The default CLS is used if arch didn't set CLS explicitly and not
85 * all pci devices agree on the same value. Arch can override either
86 * the dfl or actual value as it sees fit. Don't forget this is
87 * measured in 32-bit words, not bytes.
88 */
15856ad5 89u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
ac1aa47b
JB		 90u8 pci_cache_line_size;
91
96c55900
MS		 92/*
93 * If we set up a device for bus mastering, we need to check the latency
94 * timer as certain BIOSes forget to set it properly.
95 */
96unsigned int pcibios_max_latency = 255;
97
6748dcc2
RW		 98/* If set, the PCIe ARI capability will not be used. */
99static bool pcie_ari_disabled;
100
1da177e4
LT		 101/**
102 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
103 * @bus: pointer to PCI bus structure to search
104 *
105 * Given a PCI bus, returns the highest PCI bus number present in the set
106 * including the given PCI bus and its list of child PCI buses.
107 */
96bde06a 108unsigned char pci_bus_max_busnr(struct pci_bus* bus)
1da177e4
LT		 109{
110 struct list_head *tmp;
111 unsigned char max, n;
112
b918c62e 113 max = bus->busn_res.end;
1da177e4
LT		 114 list_for_each(tmp, &bus->children) {
115 n = pci_bus_max_busnr(pci_bus_b(tmp));
116 if(n > max)
117 max = n;
118 }
119 return max;
120}
b82db5ce 121EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
1da177e4 122
1684f5dd
AM		 123#ifdef CONFIG_HAS_IOMEM
124void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
125{
126 /*
127 * Make sure the BAR is actually a memory resource, not an IO resource
128 */
129 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
130 WARN_ON(1);
131 return NULL;
132 }
133 return ioremap_nocache(pci_resource_start(pdev, bar),
134 pci_resource_len(pdev, bar));
135}
136EXPORT_SYMBOL_GPL(pci_ioremap_bar);
137#endif
138
687d5fe3
ME		 139#define PCI_FIND_CAP_TTL 48
140
141static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
142 u8 pos, int cap, int *ttl)
24a4e377
RD		 143{
144 u8 id;
24a4e377 145
687d5fe3 146 while ((*ttl)--) {
24a4e377
RD		 147 pci_bus_read_config_byte(bus, devfn, pos, &pos);
148 if (pos < 0x40)
149 break;
150 pos &= ~3;
151 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
152 &id);
153 if (id == 0xff)
154 break;
155 if (id == cap)
156 return pos;
157 pos += PCI_CAP_LIST_NEXT;
158 }
159 return 0;
160}
161
687d5fe3
ME		 162static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
163 u8 pos, int cap)
164{
165 int ttl = PCI_FIND_CAP_TTL;
166
167 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
168}
169
24a4e377
RD		 170int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
171{
172 return __pci_find_next_cap(dev->bus, dev->devfn,
173 pos + PCI_CAP_LIST_NEXT, cap);
174}
175EXPORT_SYMBOL_GPL(pci_find_next_capability);
176
d3bac118
ME		 177static int __pci_bus_find_cap_start(struct pci_bus *bus,
178 unsigned int devfn, u8 hdr_type)
1da177e4
LT		 179{
180 u16 status;
1da177e4
LT		 181
182 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
183 if (!(status & PCI_STATUS_CAP_LIST))
184 return 0;
185
186 switch (hdr_type) {
187 case PCI_HEADER_TYPE_NORMAL:
188 case PCI_HEADER_TYPE_BRIDGE:
d3bac118 189 return PCI_CAPABILITY_LIST;
1da177e4 190 case PCI_HEADER_TYPE_CARDBUS:
d3bac118 191 return PCI_CB_CAPABILITY_LIST;
1da177e4
LT		 192 default:
193 return 0;
194 }
d3bac118
ME		 195
196 return 0;
1da177e4
LT		 197}
198
199/**
200 * pci_find_capability - query for devices' capabilities
201 * @dev: PCI device to query
202 * @cap: capability code
203 *
204 * Tell if a device supports a given PCI capability.
205 * Returns the address of the requested capability structure within the
206 * device's PCI configuration space or 0 in case the device does not
207 * support it. Possible values for @cap:
208 *
209 * %PCI_CAP_ID_PM Power Management
210 * %PCI_CAP_ID_AGP Accelerated Graphics Port
211 * %PCI_CAP_ID_VPD Vital Product Data
212 * %PCI_CAP_ID_SLOTID Slot Identification
213 * %PCI_CAP_ID_MSI Message Signalled Interrupts
214 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
215 * %PCI_CAP_ID_PCIX PCI-X
216 * %PCI_CAP_ID_EXP PCI Express
217 */
218int pci_find_capability(struct pci_dev *dev, int cap)
219{
d3bac118
ME		 220 int pos;
221
222 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
223 if (pos)
224 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
225
226 return pos;
1da177e4
LT		 227}
228
229/**
230 * pci_bus_find_capability - query for devices' capabilities
231 * @bus: the PCI bus to query
232 * @devfn: PCI device to query
233 * @cap: capability code
234 *
235 * Like pci_find_capability() but works for pci devices that do not have a
236 * pci_dev structure set up yet.
237 *
238 * Returns the address of the requested capability structure within the
239 * device's PCI configuration space or 0 in case the device does not
240 * support it.
241 */
242int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
243{
d3bac118 244 int pos;
1da177e4
LT		 245 u8 hdr_type;
246
247 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
248
d3bac118
ME		 249 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
250 if (pos)
251 pos = __pci_find_next_cap(bus, devfn, pos, cap);
252
253 return pos;
1da177e4
LT		 254}
255
256/**
44a9a36f 257 * pci_find_next_ext_capability - Find an extended capability
1da177e4 258 * @dev: PCI device to query
44a9a36f 259 * @start: address at which to start looking (0 to start at beginning of list)
1da177e4
LT		 260 * @cap: capability code
261 *
44a9a36f 262 * Returns the address of the next matching extended capability structure
1da177e4 263 * within the device's PCI configuration space or 0 if the device does
44a9a36f
BH		 264 * not support it. Some capabilities can occur several times, e.g., the
265 * vendor-specific capability, and this provides a way to find them all.
1da177e4 266 */
44a9a36f 267int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
1da177e4
LT		 268{
269 u32 header;
557848c3
ZY		 270 int ttl;
271 int pos = PCI_CFG_SPACE_SIZE;
1da177e4 272
557848c3
ZY		 273 /* minimum 8 bytes per capability */
274 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
275
276 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
1da177e4
LT		 277 return 0;
278
44a9a36f
BH		 279 if (start)
280 pos = start;
281
1da177e4
LT		 282 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
283 return 0;
284
285 /*
286 * If we have no capabilities, this is indicated by cap ID,
287 * cap version and next pointer all being 0.
288 */
289 if (header == 0)
290 return 0;
291
292 while (ttl-- > 0) {
44a9a36f 293 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
1da177e4
LT		 294 return pos;
295
296 pos = PCI_EXT_CAP_NEXT(header);
557848c3 297 if (pos < PCI_CFG_SPACE_SIZE)
1da177e4
LT		 298 break;
299
300 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
301 break;
302 }
303
304 return 0;
305}
44a9a36f
BH		 306EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
307
308/**
309 * pci_find_ext_capability - Find an extended capability
310 * @dev: PCI device to query
311 * @cap: capability code
312 *
313 * Returns the address of the requested extended capability structure
314 * within the device's PCI configuration space or 0 if the device does
315 * not support it. Possible values for @cap:
316 *
317 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
318 * %PCI_EXT_CAP_ID_VC Virtual Channel
319 * %PCI_EXT_CAP_ID_DSN Device Serial Number
320 * %PCI_EXT_CAP_ID_PWR Power Budgeting
321 */
322int pci_find_ext_capability(struct pci_dev *dev, int cap)
323{
324 return pci_find_next_ext_capability(dev, 0, cap);
325}
3a720d72 326EXPORT_SYMBOL_GPL(pci_find_ext_capability);
1da177e4 327
687d5fe3
ME		 328static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
329{
330 int rc, ttl = PCI_FIND_CAP_TTL;
331 u8 cap, mask;
332
333 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
334 mask = HT_3BIT_CAP_MASK;
335 else
336 mask = HT_5BIT_CAP_MASK;
337
338 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
339 PCI_CAP_ID_HT, &ttl);
340 while (pos) {
341 rc = pci_read_config_byte(dev, pos + 3, &cap);
342 if (rc != PCIBIOS_SUCCESSFUL)
343 return 0;
344
345 if ((cap & mask) == ht_cap)
346 return pos;
347
47a4d5be
BG		 348 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
349 pos + PCI_CAP_LIST_NEXT,
687d5fe3
ME		 350 PCI_CAP_ID_HT, &ttl);
351 }
352
353 return 0;
354}
355/**
356 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
357 * @dev: PCI device to query
358 * @pos: Position from which to continue searching
359 * @ht_cap: Hypertransport capability code
360 *
361 * To be used in conjunction with pci_find_ht_capability() to search for
362 * all capabilities matching @ht_cap. @pos should always be a value returned
363 * from pci_find_ht_capability().
364 *
365 * NB. To be 100% safe against broken PCI devices, the caller should take
366 * steps to avoid an infinite loop.
367 */
368int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
369{
370 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
371}
372EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
373
374/**
375 * pci_find_ht_capability - query a device's Hypertransport capabilities
376 * @dev: PCI device to query
377 * @ht_cap: Hypertransport capability code
378 *
379 * Tell if a device supports a given Hypertransport capability.
380 * Returns an address within the device's PCI configuration space
381 * or 0 in case the device does not support the request capability.
382 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
383 * which has a Hypertransport capability matching @ht_cap.
384 */
385int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
386{
387 int pos;
388
389 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
390 if (pos)
391 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
392
393 return pos;
394}
395EXPORT_SYMBOL_GPL(pci_find_ht_capability);
396
1da177e4
LT		 397/**
398 * pci_find_parent_resource - return resource region of parent bus of given region
399 * @dev: PCI device structure contains resources to be searched
400 * @res: child resource record for which parent is sought
401 *
402 * For given resource region of given device, return the resource
403 * region of parent bus the given region is contained in or where
404 * it should be allocated from.
405 */
406struct resource *
407pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
408{
409 const struct pci_bus *bus = dev->bus;
410 int i;
89a74ecc 411 struct resource *best = NULL, *r;
1da177e4 412
89a74ecc 413 pci_bus_for_each_resource(bus, r, i) {
1da177e4
LT		 414 if (!r)
415 continue;
416 if (res->start && !(res->start >= r->start && res->end <= r->end))
417 continue; /* Not contained */
418 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
419 continue; /* Wrong type */
420 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
421 return r; /* Exact match */
8c8def26
LT		 422 /* We can't insert a non-prefetch resource inside a prefetchable parent .. */
423 if (r->flags & IORESOURCE_PREFETCH)
424 continue;
425 /* .. but we can put a prefetchable resource inside a non-prefetchable one */
426 if (!best)
427 best = r;
1da177e4
LT		 428 }
429 return best;
430}
431
064b53db
JL		 432/**
433 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
434 * @dev: PCI device to have its BARs restored
435 *
436 * Restore the BAR values for a given device, so as to make it
437 * accessible by its driver.
438 */
ad668599 439static void
064b53db
JL		 440pci_restore_bars(struct pci_dev *dev)
441{
bc5f5a82 442 int i;
064b53db 443
bc5f5a82 444 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
14add80b 445 pci_update_resource(dev, i);
064b53db
JL		 446}
447
961d9120
RW		 448static struct pci_platform_pm_ops *pci_platform_pm;
449
450int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
451{
eb9d0fe4
RW		 452 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
453 || !ops->sleep_wake || !ops->can_wakeup)
961d9120
RW		 454 return -EINVAL;
455 pci_platform_pm = ops;
456 return 0;
457}
458
459static inline bool platform_pci_power_manageable(struct pci_dev *dev)
460{
461 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
462}
463
464static inline int platform_pci_set_power_state(struct pci_dev *dev,
465 pci_power_t t)
466{
467 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
468}
469
470static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
471{
472 return pci_platform_pm ?
473 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
474}
8f7020d3 475
eb9d0fe4
RW		 476static inline bool platform_pci_can_wakeup(struct pci_dev *dev)
477{
478 return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false;
479}
480
481static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
482{
483 return pci_platform_pm ?
484 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
485}
486
b67ea761
RW		 487static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
488{
489 return pci_platform_pm ?
490 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
491}
492
1da177e4 493/**
44e4e66e
RW		 494 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
495 * given PCI device
496 * @dev: PCI device to handle.
44e4e66e 497 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1da177e4 498 *
44e4e66e
RW		 499 * RETURN VALUE:
500 * -EINVAL if the requested state is invalid.
501 * -EIO if device does not support PCI PM or its PM capabilities register has a
502 * wrong version, or device doesn't support the requested state.
503 * 0 if device already is in the requested state.
504 * 0 if device's power state has been successfully changed.
1da177e4 505 */
f00a20ef 506static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
1da177e4 507{
337001b6 508 u16 pmcsr;
44e4e66e 509 bool need_restore = false;
1da177e4 510
4a865905
RW		 511 /* Check if we're already there */
512 if (dev->current_state == state)
513 return 0;
514
337001b6 515 if (!dev->pm_cap)
cca03dec
AL		 516 return -EIO;
517
44e4e66e
RW		 518 if (state < PCI_D0 || state > PCI_D3hot)
519 return -EINVAL;
520
1da177e4
LT		 521 /* Validate current state:
522 * Can enter D0 from any state, but if we can only go deeper
523 * to sleep if we're already in a low power state
524 */
4a865905 525 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
44e4e66e 526 && dev->current_state > state) {
80ccba11
BH		 527 dev_err(&dev->dev, "invalid power transition "
528 "(from state %d to %d)\n", dev->current_state, state);
1da177e4 529 return -EINVAL;
44e4e66e 530 }
1da177e4 531
1da177e4 532 /* check if this device supports the desired state */
337001b6
RW		 533 if ((state == PCI_D1 && !dev->d1_support)
534 || (state == PCI_D2 && !dev->d2_support))
3fe9d19f 535 return -EIO;
1da177e4 536
337001b6 537 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
064b53db 538
32a36585 539 /* If we're (effectively) in D3, force entire word to 0.
1da177e4
LT		 540 * This doesn't affect PME_Status, disables PME_En, and
541 * sets PowerState to 0.
542 */
32a36585 543 switch (dev->current_state) {
d3535fbb
JL		 544 case PCI_D0:
545 case PCI_D1:
546 case PCI_D2:
547 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
548 pmcsr |= state;
549 break;
f62795f1
RW		 550 case PCI_D3hot:
551 case PCI_D3cold:
32a36585
JL		 552 case PCI_UNKNOWN: /* Boot-up */
553 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
f00a20ef 554 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
44e4e66e 555 need_restore = true;
32a36585 556 /* Fall-through: force to D0 */
32a36585 557 default:
d3535fbb 558 pmcsr = 0;
32a36585 559 break;
1da177e4
LT		 560 }
561
562 /* enter specified state */
337001b6 563 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1da177e4
LT		 564
565 /* Mandatory power management transition delays */
566 /* see PCI PM 1.1 5.6.1 table 18 */
567 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
1ae861e6 568 pci_dev_d3_sleep(dev);
1da177e4 569 else if (state == PCI_D2 || dev->current_state == PCI_D2)
aa8c6c93 570 udelay(PCI_PM_D2_DELAY);
1da177e4 571
e13cdbd7
RW		 572 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
573 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
574 if (dev->current_state != state && printk_ratelimit())
575 dev_info(&dev->dev, "Refused to change power state, "
576 "currently in D%d\n", dev->current_state);
064b53db 577
448bd857
HY		 578 /*
579 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
064b53db
JL		 580 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
581 * from D3hot to D0 _may_ perform an internal reset, thereby
582 * going to "D0 Uninitialized" rather than "D0 Initialized".
583 * For example, at least some versions of the 3c905B and the
584 * 3c556B exhibit this behaviour.
585 *
586 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
587 * devices in a D3hot state at boot. Consequently, we need to
588 * restore at least the BARs so that the device will be
589 * accessible to its driver.
590 */
591 if (need_restore)
592 pci_restore_bars(dev);
593
f00a20ef 594 if (dev->bus->self)
7d715a6c
SL		 595 pcie_aspm_pm_state_change(dev->bus->self);
596
1da177e4
LT		 597 return 0;
598}
599
44e4e66e
RW		 600/**
601 * pci_update_current_state - Read PCI power state of given device from its
602 * PCI PM registers and cache it
603 * @dev: PCI device to handle.
f06fc0b6 604 * @state: State to cache in case the device doesn't have the PM capability
44e4e66e 605 */
73410429 606void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
44e4e66e 607{
337001b6 608 if (dev->pm_cap) {
44e4e66e
RW		 609 u16 pmcsr;
610
448bd857
HY		 611 /*
612 * Configuration space is not accessible for device in
613 * D3cold, so just keep or set D3cold for safety
614 */
615 if (dev->current_state == PCI_D3cold)
616 return;
617 if (state == PCI_D3cold) {
618 dev->current_state = PCI_D3cold;
619 return;
620 }
337001b6 621 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
44e4e66e 622 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
f06fc0b6
RW		 623 } else {
624 dev->current_state = state;
44e4e66e
RW		 625 }
626}
627
db288c9c
RW		 628/**
629 * pci_power_up - Put the given device into D0 forcibly
630 * @dev: PCI device to power up
631 */
632void pci_power_up(struct pci_dev *dev)
633{
634 if (platform_pci_power_manageable(dev))
635 platform_pci_set_power_state(dev, PCI_D0);
636
637 pci_raw_set_power_state(dev, PCI_D0);
638 pci_update_current_state(dev, PCI_D0);
639}
640
0e5dd46b
RW		 641/**
642 * pci_platform_power_transition - Use platform to change device power state
643 * @dev: PCI device to handle.
644 * @state: State to put the device into.
645 */
646static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
647{
648 int error;
649
650 if (platform_pci_power_manageable(dev)) {
651 error = platform_pci_set_power_state(dev, state);
652 if (!error)
653 pci_update_current_state(dev, state);
b51306c6
AH		 654 /* Fall back to PCI_D0 if native PM is not supported */
655 if (!dev->pm_cap)
656 dev->current_state = PCI_D0;
0e5dd46b
RW		 657 } else {
658 error = -ENODEV;
659 /* Fall back to PCI_D0 if native PM is not supported */
b3bad72e
RW		 660 if (!dev->pm_cap)
661 dev->current_state = PCI_D0;
0e5dd46b
RW		 662 }
663
664 return error;
665}
666
667/**
668 * __pci_start_power_transition - Start power transition of a PCI device
669 * @dev: PCI device to handle.
670 * @state: State to put the device into.
671 */
672static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
673{
448bd857 674 if (state == PCI_D0) {
0e5dd46b 675 pci_platform_power_transition(dev, PCI_D0);
448bd857
HY		 676 /*
677 * Mandatory power management transition delays, see
678 * PCI Express Base Specification Revision 2.0 Section
679 * 6.6.1: Conventional Reset. Do not delay for
680 * devices powered on/off by corresponding bridge,
681 * because have already delayed for the bridge.
682 */
683 if (dev->runtime_d3cold) {
684 msleep(dev->d3cold_delay);
685 /*
686 * When powering on a bridge from D3cold, the
687 * whole hierarchy may be powered on into
688 * D0uninitialized state, resume them to give
689 * them a chance to suspend again
690 */
691 pci_wakeup_bus(dev->subordinate);
692 }
693 }
694}
695
696/**
697 * __pci_dev_set_current_state - Set current state of a PCI device
698 * @dev: Device to handle
699 * @data: pointer to state to be set
700 */
701static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
702{
703 pci_power_t state = *(pci_power_t *)data;
704
705 dev->current_state = state;
706 return 0;
707}
708
709/**
710 * __pci_bus_set_current_state - Walk given bus and set current state of devices
711 * @bus: Top bus of the subtree to walk.
712 * @state: state to be set
713 */
714static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
715{
716 if (bus)
717 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
0e5dd46b
RW		 718}
719
720/**
721 * __pci_complete_power_transition - Complete power transition of a PCI device
722 * @dev: PCI device to handle.
723 * @state: State to put the device into.
724 *
725 * This function should not be called directly by device drivers.
726 */
727int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
728{
448bd857
HY		 729 int ret;
730
db288c9c 731 if (state <= PCI_D0)
448bd857
HY		 732 return -EINVAL;
733 ret = pci_platform_power_transition(dev, state);
734 /* Power off the bridge may power off the whole hierarchy */
735 if (!ret && state == PCI_D3cold)
736 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
737 return ret;
0e5dd46b
RW		 738}
739EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
740
44e4e66e
RW		 741/**
742 * pci_set_power_state - Set the power state of a PCI device
743 * @dev: PCI device to handle.
744 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
745 *
877d0310 746 * Transition a device to a new power state, using the platform firmware and/or
44e4e66e
RW		 747 * the device's PCI PM registers.
748 *
749 * RETURN VALUE:
750 * -EINVAL if the requested state is invalid.
751 * -EIO if device does not support PCI PM or its PM capabilities register has a
752 * wrong version, or device doesn't support the requested state.
753 * 0 if device already is in the requested state.
754 * 0 if device's power state has been successfully changed.
755 */
756int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
757{
337001b6 758 int error;
44e4e66e
RW		 759
760 /* bound the state we're entering */
448bd857
HY		 761 if (state > PCI_D3cold)
762 state = PCI_D3cold;
44e4e66e
RW		 763 else if (state < PCI_D0)
764 state = PCI_D0;
765 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
766 /*
767 * If the device or the parent bridge do not support PCI PM,
768 * ignore the request if we're doing anything other than putting
769 * it into D0 (which would only happen on boot).
770 */
771 return 0;
772
db288c9c
RW		 773 /* Check if we're already there */
774 if (dev->current_state == state)
775 return 0;
776
0e5dd46b
RW		 777 __pci_start_power_transition(dev, state);
778
979b1791
AC		 779 /* This device is quirked not to be put into D3, so
780 don't put it in D3 */
448bd857 781 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
979b1791 782 return 0;
44e4e66e 783
448bd857
HY		 784 /*
785 * To put device in D3cold, we put device into D3hot in native
786 * way, then put device into D3cold with platform ops
787 */
788 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
789 PCI_D3hot : state);
44e4e66e 790
0e5dd46b
RW		 791 if (!__pci_complete_power_transition(dev, state))
792 error = 0;
1a680b7c
NC		 793 /*
794 * When aspm_policy is "powersave" this call ensures
795 * that ASPM is configured.
796 */
797 if (!error && dev->bus->self)
798 pcie_aspm_powersave_config_link(dev->bus->self);
44e4e66e
RW		 799
800 return error;
801}
802
1da177e4
LT		 803/**
804 * pci_choose_state - Choose the power state of a PCI device
805 * @dev: PCI device to be suspended
806 * @state: target sleep state for the whole system. This is the value
807 * that is passed to suspend() function.
808 *
809 * Returns PCI power state suitable for given device and given system
810 * message.
811 */
812
813pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
814{
ab826ca4 815 pci_power_t ret;
0f64474b 816
1da177e4
LT		 817 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
818 return PCI_D0;
819
961d9120
RW		 820 ret = platform_pci_choose_state(dev);
821 if (ret != PCI_POWER_ERROR)
822 return ret;
ca078bae
PM		 823
824 switch (state.event) {
825 case PM_EVENT_ON:
826 return PCI_D0;
827 case PM_EVENT_FREEZE:
b887d2e6
DB		 828 case PM_EVENT_PRETHAW:
829 /* REVISIT both freeze and pre-thaw "should" use D0 */
ca078bae 830 case PM_EVENT_SUSPEND:
3a2d5b70 831 case PM_EVENT_HIBERNATE:
ca078bae 832 return PCI_D3hot;
1da177e4 833 default:
80ccba11
BH		 834 dev_info(&dev->dev, "unrecognized suspend event %d\n",
835 state.event);
1da177e4
LT		 836 BUG();
837 }
838 return PCI_D0;
839}
840
841EXPORT_SYMBOL(pci_choose_state);
842
89858517
YZ		 843#define PCI_EXP_SAVE_REGS 7
844
1b6b8ce2 845
34a4876e
YL		 846static struct pci_cap_saved_state *pci_find_saved_cap(
847 struct pci_dev *pci_dev, char cap)
848{
849 struct pci_cap_saved_state *tmp;
850 struct hlist_node *pos;
851
852 hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
853 if (tmp->cap.cap_nr == cap)
854 return tmp;
855 }
856 return NULL;
857}
858
b56a5a23
MT		 859static int pci_save_pcie_state(struct pci_dev *dev)
860{
59875ae4 861 int i = 0;
b56a5a23
MT		 862 struct pci_cap_saved_state *save_state;
863 u16 *cap;
864
59875ae4 865 if (!pci_is_pcie(dev))
b56a5a23
MT		 866 return 0;
867
9f35575d 868 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
b56a5a23 869 if (!save_state) {
e496b617 870 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
b56a5a23
MT		 871 return -ENOMEM;
872 }
63f4898a 873
59875ae4
JL		 874 cap = (u16 *)&save_state->cap.data[0];
875 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
876 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
877 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
878 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
879 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
880 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
881 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
9cb604ed 882
b56a5a23
MT		 883 return 0;
884}
885
886static void pci_restore_pcie_state(struct pci_dev *dev)
887{
59875ae4 888 int i = 0;
b56a5a23
MT		 889 struct pci_cap_saved_state *save_state;
890 u16 *cap;
891
892 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
59875ae4 893 if (!save_state)
9cb604ed
MS		 894 return;
895
59875ae4
JL		 896 cap = (u16 *)&save_state->cap.data[0];
897 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
898 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
899 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
900 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
901 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
902 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
903 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
b56a5a23
MT		 904}
905
cc692a5f
SH		 906
907static int pci_save_pcix_state(struct pci_dev *dev)
908{
63f4898a 909 int pos;
cc692a5f 910 struct pci_cap_saved_state *save_state;
cc692a5f
SH		 911
912 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
913 if (pos <= 0)
914 return 0;
915
f34303de 916 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
cc692a5f 917 if (!save_state) {
e496b617 918 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
cc692a5f
SH		 919 return -ENOMEM;
920 }
cc692a5f 921
24a4742f
AW		 922 pci_read_config_word(dev, pos + PCI_X_CMD,
923 (u16 *)save_state->cap.data);
63f4898a 924
cc692a5f
SH		 925 return 0;
926}
927
928static void pci_restore_pcix_state(struct pci_dev *dev)
929{
930 int i = 0, pos;
931 struct pci_cap_saved_state *save_state;
932 u16 *cap;
933
934 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
935 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
936 if (!save_state || pos <= 0)
937 return;
24a4742f 938 cap = (u16 *)&save_state->cap.data[0];
cc692a5f
SH		 939
940 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
cc692a5f
SH		 941}
942
943
1da177e4
LT		 944/**
945 * pci_save_state - save the PCI configuration space of a device before suspending
946 * @dev: - PCI device that we're dealing with
1da177e4
LT		 947 */
948int
949pci_save_state(struct pci_dev *dev)
950{
951 int i;
952 /* XXX: 100% dword access ok here? */
953 for (i = 0; i < 16; i++)
9e0b5b2c 954 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
aa8c6c93 955 dev->state_saved = true;
b56a5a23
MT		 956 if ((i = pci_save_pcie_state(dev)) != 0)
957 return i;
cc692a5f
SH		 958 if ((i = pci_save_pcix_state(dev)) != 0)
959 return i;
1da177e4
LT		 960 return 0;
961}
962
ebfc5b80
RW		 963static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
964 u32 saved_val, int retry)
965{
966 u32 val;
967
968 pci_read_config_dword(pdev, offset, &val);
969 if (val == saved_val)
970 return;
971
972 for (;;) {
973 dev_dbg(&pdev->dev, "restoring config space at offset "
974 "%#x (was %#x, writing %#x)\n", offset, val, saved_val);
975 pci_write_config_dword(pdev, offset, saved_val);
976 if (retry-- <= 0)
977 return;
978
979 pci_read_config_dword(pdev, offset, &val);
980 if (val == saved_val)
981 return;
982
983 mdelay(1);
984 }
985}
986
a6cb9ee7
RW		 987static void pci_restore_config_space_range(struct pci_dev *pdev,
988 int start, int end, int retry)
ebfc5b80
RW		 989{
990 int index;
991
992 for (index = end; index >= start; index--)
993 pci_restore_config_dword(pdev, 4 * index,
994 pdev->saved_config_space[index],
995 retry);
996}
997
a6cb9ee7
RW		 998static void pci_restore_config_space(struct pci_dev *pdev)
999{
1000 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1001 pci_restore_config_space_range(pdev, 10, 15, 0);
1002 /* Restore BARs before the command register. */
1003 pci_restore_config_space_range(pdev, 4, 9, 10);
1004 pci_restore_config_space_range(pdev, 0, 3, 0);
1005 } else {
1006 pci_restore_config_space_range(pdev, 0, 15, 0);
1007 }
1008}
1009
1da177e4
LT		 1010/**
1011 * pci_restore_state - Restore the saved state of a PCI device
1012 * @dev: - PCI device that we're dealing with
1da177e4 1013 */
1d3c16a8 1014void pci_restore_state(struct pci_dev *dev)
1da177e4 1015{
c82f63e4 1016 if (!dev->state_saved)
1d3c16a8 1017 return;
4b77b0a2 1018
b56a5a23
MT		 1019 /* PCI Express register must be restored first */
1020 pci_restore_pcie_state(dev);
1900ca13 1021 pci_restore_ats_state(dev);
b56a5a23 1022
a6cb9ee7 1023 pci_restore_config_space(dev);
ebfc5b80 1024
cc692a5f 1025 pci_restore_pcix_state(dev);
41017f0c 1026 pci_restore_msi_state(dev);
8c5cdb6a 1027 pci_restore_iov_state(dev);
8fed4b65 1028
4b77b0a2 1029 dev->state_saved = false;
1da177e4
LT		 1030}
1031
ffbdd3f7
AW		 1032struct pci_saved_state {
1033 u32 config_space[16];
1034 struct pci_cap_saved_data cap[0];
1035};
1036
1037/**
1038 * pci_store_saved_state - Allocate and return an opaque struct containing
1039 * the device saved state.
1040 * @dev: PCI device that we're dealing with
1041 *
1042 * Rerturn NULL if no state or error.
1043 */
1044struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1045{
1046 struct pci_saved_state *state;
1047 struct pci_cap_saved_state *tmp;
1048 struct pci_cap_saved_data *cap;
1049 struct hlist_node *pos;
1050 size_t size;
1051
1052 if (!dev->state_saved)
1053 return NULL;
1054
1055 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1056
1057 hlist_for_each_entry(tmp, pos, &dev->saved_cap_space, next)
1058 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1059
1060 state = kzalloc(size, GFP_KERNEL);
1061 if (!state)
1062 return NULL;
1063
1064 memcpy(state->config_space, dev->saved_config_space,
1065 sizeof(state->config_space));
1066
1067 cap = state->cap;
1068 hlist_for_each_entry(tmp, pos, &dev->saved_cap_space, next) {
1069 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1070 memcpy(cap, &tmp->cap, len);
1071 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1072 }
1073 /* Empty cap_save terminates list */
1074
1075 return state;
1076}
1077EXPORT_SYMBOL_GPL(pci_store_saved_state);
1078
1079/**
1080 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1081 * @dev: PCI device that we're dealing with
1082 * @state: Saved state returned from pci_store_saved_state()
1083 */
1084int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state)
1085{
1086 struct pci_cap_saved_data *cap;
1087
1088 dev->state_saved = false;
1089
1090 if (!state)
1091 return 0;
1092
1093 memcpy(dev->saved_config_space, state->config_space,
1094 sizeof(state->config_space));
1095
1096 cap = state->cap;
1097 while (cap->size) {
1098 struct pci_cap_saved_state *tmp;
1099
1100 tmp = pci_find_saved_cap(dev, cap->cap_nr);
1101 if (!tmp || tmp->cap.size != cap->size)
1102 return -EINVAL;
1103
1104 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1105 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1106 sizeof(struct pci_cap_saved_data) + cap->size);
1107 }
1108
1109 dev->state_saved = true;
1110 return 0;
1111}
1112EXPORT_SYMBOL_GPL(pci_load_saved_state);
1113
1114/**
1115 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1116 * and free the memory allocated for it.
1117 * @dev: PCI device that we're dealing with
1118 * @state: Pointer to saved state returned from pci_store_saved_state()
1119 */
1120int pci_load_and_free_saved_state(struct pci_dev *dev,
1121 struct pci_saved_state **state)
1122{
1123 int ret = pci_load_saved_state(dev, *state);
1124 kfree(*state);
1125 *state = NULL;
1126 return ret;
1127}
1128EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1129
38cc1302
HS		 1130static int do_pci_enable_device(struct pci_dev *dev, int bars)
1131{
1132 int err;
1133
1134 err = pci_set_power_state(dev, PCI_D0);
1135 if (err < 0 && err != -EIO)
1136 return err;
1137 err = pcibios_enable_device(dev, bars);
1138 if (err < 0)
1139 return err;
1140 pci_fixup_device(pci_fixup_enable, dev);
1141
1142 return 0;
1143}
1144
1145/**
0b62e13b 1146 * pci_reenable_device - Resume abandoned device
38cc1302
HS		 1147 * @dev: PCI device to be resumed
1148 *
1149 * Note this function is a backend of pci_default_resume and is not supposed
1150 * to be called by normal code, write proper resume handler and use it instead.
1151 */
0b62e13b 1152int pci_reenable_device(struct pci_dev *dev)
38cc1302 1153{
296ccb08 1154 if (pci_is_enabled(dev))
38cc1302
HS		 1155 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1156 return 0;
1157}
1158
b718989d
BH		 1159static int __pci_enable_device_flags(struct pci_dev *dev,
1160 resource_size_t flags)
1da177e4
LT		 1161{
1162 int err;
b718989d 1163 int i, bars = 0;
1da177e4 1164
97c145f7
JB		 1165 /*
1166 * Power state could be unknown at this point, either due to a fresh
1167 * boot or a device removal call. So get the current power state
1168 * so that things like MSI message writing will behave as expected
1169 * (e.g. if the device really is in D0 at enable time).
1170 */
1171 if (dev->pm_cap) {
1172 u16 pmcsr;
1173 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1174 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1175 }
1176
9fb625c3
HS		 1177 if (atomic_add_return(1, &dev->enable_cnt) > 1)
1178 return 0; /* already enabled */
1179
497f16f2
YL		 1180 /* only skip sriov related */
1181 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1182 if (dev->resource[i].flags & flags)
1183 bars |= (1 << i);
1184 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
b718989d
BH		 1185 if (dev->resource[i].flags & flags)
1186 bars |= (1 << i);
1187
38cc1302 1188 err = do_pci_enable_device(dev, bars);
95a62965 1189 if (err < 0)
38cc1302 1190 atomic_dec(&dev->enable_cnt);
9fb625c3 1191 return err;
1da177e4
LT		 1192}
1193
b718989d
BH		 1194/**
1195 * pci_enable_device_io - Initialize a device for use with IO space
1196 * @dev: PCI device to be initialized
1197 *
1198 * Initialize device before it's used by a driver. Ask low-level code
1199 * to enable I/O resources. Wake up the device if it was suspended.
1200 * Beware, this function can fail.
1201 */
1202int pci_enable_device_io(struct pci_dev *dev)
1203{
1204 return __pci_enable_device_flags(dev, IORESOURCE_IO);
1205}
1206
1207/**
1208 * pci_enable_device_mem - Initialize a device for use with Memory space
1209 * @dev: PCI device to be initialized
1210 *
1211 * Initialize device before it's used by a driver. Ask low-level code
1212 * to enable Memory resources. Wake up the device if it was suspended.
1213 * Beware, this function can fail.
1214 */
1215int pci_enable_device_mem(struct pci_dev *dev)
1216{
1217 return __pci_enable_device_flags(dev, IORESOURCE_MEM);
1218}
1219
bae94d02
IPG		 1220/**
1221 * pci_enable_device - Initialize device before it's used by a driver.
1222 * @dev: PCI device to be initialized
1223 *
1224 * Initialize device before it's used by a driver. Ask low-level code
1225 * to enable I/O and memory. Wake up the device if it was suspended.
1226 * Beware, this function can fail.
1227 *
1228 * Note we don't actually enable the device many times if we call
1229 * this function repeatedly (we just increment the count).
1230 */
1231int pci_enable_device(struct pci_dev *dev)
1232{
b718989d 1233 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
bae94d02
IPG		 1234}
1235
9ac7849e
TH		 1236/*
1237 * Managed PCI resources. This manages device on/off, intx/msi/msix
1238 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1239 * there's no need to track it separately. pci_devres is initialized
1240 * when a device is enabled using managed PCI device enable interface.
1241 */
1242struct pci_devres {
7f375f32
TH		 1243 unsigned int enabled:1;
1244 unsigned int pinned:1;
9ac7849e
TH		 1245 unsigned int orig_intx:1;
1246 unsigned int restore_intx:1;
1247 u32 region_mask;
1248};
1249
1250static void pcim_release(struct device *gendev, void *res)
1251{
1252 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
1253 struct pci_devres *this = res;
1254 int i;
1255
1256 if (dev->msi_enabled)
1257 pci_disable_msi(dev);
1258 if (dev->msix_enabled)
1259 pci_disable_msix(dev);
1260
1261 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1262 if (this->region_mask & (1 << i))
1263 pci_release_region(dev, i);
1264
1265 if (this->restore_intx)
1266 pci_intx(dev, this->orig_intx);
1267
7f375f32 1268 if (this->enabled && !this->pinned)
9ac7849e
TH		 1269 pci_disable_device(dev);
1270}
1271
1272static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
1273{
1274 struct pci_devres *dr, *new_dr;
1275
1276 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1277 if (dr)
1278 return dr;
1279
1280 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1281 if (!new_dr)
1282 return NULL;
1283 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1284}
1285
1286static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
1287{
1288 if (pci_is_managed(pdev))
1289 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1290 return NULL;
1291}
1292
1293/**
1294 * pcim_enable_device - Managed pci_enable_device()
1295 * @pdev: PCI device to be initialized
1296 *
1297 * Managed pci_enable_device().
1298 */
1299int pcim_enable_device(struct pci_dev *pdev)
1300{
1301 struct pci_devres *dr;
1302 int rc;
1303
1304 dr = get_pci_dr(pdev);
1305 if (unlikely(!dr))
1306 return -ENOMEM;
b95d58ea
TH		 1307 if (dr->enabled)
1308 return 0;
9ac7849e
TH		 1309
1310 rc = pci_enable_device(pdev);
1311 if (!rc) {
1312 pdev->is_managed = 1;
7f375f32 1313 dr->enabled = 1;
9ac7849e
TH		 1314 }
1315 return rc;
1316}
1317
1318/**
1319 * pcim_pin_device - Pin managed PCI device
1320 * @pdev: PCI device to pin
1321 *
1322 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1323 * driver detach. @pdev must have been enabled with
1324 * pcim_enable_device().
1325 */
1326void pcim_pin_device(struct pci_dev *pdev)
1327{
1328 struct pci_devres *dr;
1329
1330 dr = find_pci_dr(pdev);
7f375f32 1331 WARN_ON(!dr || !dr->enabled);
9ac7849e 1332 if (dr)
7f375f32 1333 dr->pinned = 1;
9ac7849e
TH		 1334}
1335
eca0d467
MG		 1336/*
1337 * pcibios_add_device - provide arch specific hooks when adding device dev
1338 * @dev: the PCI device being added
1339 *
1340 * Permits the platform to provide architecture specific functionality when
1341 * devices are added. This is the default implementation. Architecture
1342 * implementations can override this.
1343 */
1344int __weak pcibios_add_device (struct pci_dev *dev)
1345{
1346 return 0;
1347}
1348
1da177e4
LT		 1349/**
1350 * pcibios_disable_device - disable arch specific PCI resources for device dev
1351 * @dev: the PCI device to disable
1352 *
1353 * Disables architecture specific PCI resources for the device. This
1354 * is the default implementation. Architecture implementations can
1355 * override this.
1356 */
d6d88c83 1357void __weak pcibios_disable_device (struct pci_dev *dev) {}
1da177e4 1358
fa58d305
RW		 1359static void do_pci_disable_device(struct pci_dev *dev)
1360{
1361 u16 pci_command;
1362
1363 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1364 if (pci_command & PCI_COMMAND_MASTER) {
1365 pci_command &= ~PCI_COMMAND_MASTER;
1366 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1367 }
1368
1369 pcibios_disable_device(dev);
1370}
1371
1372/**
1373 * pci_disable_enabled_device - Disable device without updating enable_cnt
1374 * @dev: PCI device to disable
1375 *
1376 * NOTE: This function is a backend of PCI power management routines and is
1377 * not supposed to be called drivers.
1378 */
1379void pci_disable_enabled_device(struct pci_dev *dev)
1380{
296ccb08 1381 if (pci_is_enabled(dev))
fa58d305
RW		 1382 do_pci_disable_device(dev);
1383}
1384
1da177e4
LT		 1385/**
1386 * pci_disable_device - Disable PCI device after use
1387 * @dev: PCI device to be disabled
1388 *
1389 * Signal to the system that the PCI device is not in use by the system
1390 * anymore. This only involves disabling PCI bus-mastering, if active.
bae94d02
IPG		 1391 *
1392 * Note we don't actually disable the device until all callers of
ee6583f6 1393 * pci_enable_device() have called pci_disable_device().
1da177e4
LT		 1394 */
1395void
1396pci_disable_device(struct pci_dev *dev)
1397{
9ac7849e 1398 struct pci_devres *dr;
99dc804d 1399
9ac7849e
TH		 1400 dr = find_pci_dr(dev);
1401 if (dr)
7f375f32 1402 dr->enabled = 0;
9ac7849e 1403
bae94d02
IPG		 1404 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
1405 return;
1406
fa58d305 1407 do_pci_disable_device(dev);
1da177e4 1408
fa58d305 1409 dev->is_busmaster = 0;
1da177e4
LT		 1410}
1411
f7bdd12d
BK		 1412/**
1413 * pcibios_set_pcie_reset_state - set reset state for device dev
45e829ea 1414 * @dev: the PCIe device reset
f7bdd12d
BK		 1415 * @state: Reset state to enter into
1416 *
1417 *
45e829ea 1418 * Sets the PCIe reset state for the device. This is the default
f7bdd12d
BK		 1419 * implementation. Architecture implementations can override this.
1420 */
d6d88c83
BH		 1421int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
1422 enum pcie_reset_state state)
f7bdd12d
BK		 1423{
1424 return -EINVAL;
1425}
1426
1427/**
1428 * pci_set_pcie_reset_state - set reset state for device dev
45e829ea 1429 * @dev: the PCIe device reset
f7bdd12d
BK		 1430 * @state: Reset state to enter into
1431 *
1432 *
1433 * Sets the PCI reset state for the device.
1434 */
1435int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1436{
1437 return pcibios_set_pcie_reset_state(dev, state);
1438}
1439
58ff4633
RW		 1440/**
1441 * pci_check_pme_status - Check if given device has generated PME.
1442 * @dev: Device to check.
1443 *
1444 * Check the PME status of the device and if set, clear it and clear PME enable
1445 * (if set). Return 'true' if PME status and PME enable were both set or
1446 * 'false' otherwise.
1447 */
1448bool pci_check_pme_status(struct pci_dev *dev)
1449{
1450 int pmcsr_pos;
1451 u16 pmcsr;
1452 bool ret = false;
1453
1454 if (!dev->pm_cap)
1455 return false;
1456
1457 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1458 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1459 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1460 return false;
1461
1462 /* Clear PME status. */
1463 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1464 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1465 /* Disable PME to avoid interrupt flood. */
1466 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1467 ret = true;
1468 }
1469
1470 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1471
1472 return ret;
1473}
1474
b67ea761
RW		 1475/**
1476 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1477 * @dev: Device to handle.
379021d5 1478 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
b67ea761
RW		 1479 *
1480 * Check if @dev has generated PME and queue a resume request for it in that
1481 * case.
1482 */
379021d5 1483static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
b67ea761 1484{
379021d5
RW		 1485 if (pme_poll_reset && dev->pme_poll)
1486 dev->pme_poll = false;
1487
c125e96f 1488 if (pci_check_pme_status(dev)) {
c125e96f 1489 pci_wakeup_event(dev);
0f953bf6 1490 pm_request_resume(&dev->dev);
c125e96f 1491 }
b67ea761
RW		 1492 return 0;
1493}
1494
1495/**
1496 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1497 * @bus: Top bus of the subtree to walk.
1498 */
1499void pci_pme_wakeup_bus(struct pci_bus *bus)
1500{
1501 if (bus)
379021d5 1502 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
b67ea761
RW		 1503}
1504
448bd857
HY		 1505/**
1506 * pci_wakeup - Wake up a PCI device
ceaf5b5f 1507 * @pci_dev: Device to handle.
448bd857
HY		 1508 * @ign: ignored parameter
1509 */
1510static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
1511{
1512 pci_wakeup_event(pci_dev);
1513 pm_request_resume(&pci_dev->dev);
1514 return 0;
1515}
1516
1517/**
1518 * pci_wakeup_bus - Walk given bus and wake up devices on it
1519 * @bus: Top bus of the subtree to walk.
1520 */
1521void pci_wakeup_bus(struct pci_bus *bus)
1522{
1523 if (bus)
1524 pci_walk_bus(bus, pci_wakeup, NULL);
1525}
1526
eb9d0fe4
RW		 1527/**
1528 * pci_pme_capable - check the capability of PCI device to generate PME#
1529 * @dev: PCI device to handle.
eb9d0fe4
RW		 1530 * @state: PCI state from which device will issue PME#.
1531 */
e5899e1b 1532bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
eb9d0fe4 1533{
337001b6 1534 if (!dev->pm_cap)
eb9d0fe4
RW		 1535 return false;
1536
337001b6 1537 return !!(dev->pme_support & (1 << state));
eb9d0fe4
RW		 1538}
1539
df17e62e
MG		 1540static void pci_pme_list_scan(struct work_struct *work)
1541{
379021d5 1542 struct pci_pme_device *pme_dev, *n;
df17e62e
MG		 1543
1544 mutex_lock(&pci_pme_list_mutex);
1545 if (!list_empty(&pci_pme_list)) {
379021d5
RW		 1546 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1547 if (pme_dev->dev->pme_poll) {
71a83bd7
ZY		 1548 struct pci_dev *bridge;
1549
1550 bridge = pme_dev->dev->bus->self;
1551 /*
1552 * If bridge is in low power state, the
1553 * configuration space of subordinate devices
1554 * may be not accessible
1555 */
1556 if (bridge && bridge->current_state != PCI_D0)
1557 continue;
379021d5
RW		 1558 pci_pme_wakeup(pme_dev->dev, NULL);
1559 } else {
1560 list_del(&pme_dev->list);
1561 kfree(pme_dev);
1562 }
1563 }
1564 if (!list_empty(&pci_pme_list))
1565 schedule_delayed_work(&pci_pme_work,
1566 msecs_to_jiffies(PME_TIMEOUT));
df17e62e
MG		 1567 }
1568 mutex_unlock(&pci_pme_list_mutex);
1569}
1570
eb9d0fe4
RW		 1571/**
1572 * pci_pme_active - enable or disable PCI device's PME# function
1573 * @dev: PCI device to handle.
eb9d0fe4
RW		 1574 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1575 *
1576 * The caller must verify that the device is capable of generating PME# before
1577 * calling this function with @enable equal to 'true'.
1578 */
5a6c9b60 1579void pci_pme_active(struct pci_dev *dev, bool enable)
eb9d0fe4
RW		 1580{
1581 u16 pmcsr;
1582
337001b6 1583 if (!dev->pm_cap)
eb9d0fe4
RW		 1584 return;
1585
337001b6 1586 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
eb9d0fe4
RW		 1587 /* Clear PME_Status by writing 1 to it and enable PME# */
1588 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1589 if (!enable)
1590 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1591
337001b6 1592 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
eb9d0fe4 1593
6e965e0d
HY		 1594 /*
1595 * PCI (as opposed to PCIe) PME requires that the device have
1596 * its PME# line hooked up correctly. Not all hardware vendors
1597 * do this, so the PME never gets delivered and the device
1598 * remains asleep. The easiest way around this is to
1599 * periodically walk the list of suspended devices and check
1600 * whether any have their PME flag set. The assumption is that
1601 * we'll wake up often enough anyway that this won't be a huge
1602 * hit, and the power savings from the devices will still be a
1603 * win.
1604 *
1605 * Although PCIe uses in-band PME message instead of PME# line
1606 * to report PME, PME does not work for some PCIe devices in
1607 * reality. For example, there are devices that set their PME
1608 * status bits, but don't really bother to send a PME message;
1609 * there are PCI Express Root Ports that don't bother to
1610 * trigger interrupts when they receive PME messages from the
1611 * devices below. So PME poll is used for PCIe devices too.
1612 */
df17e62e 1613
379021d5 1614 if (dev->pme_poll) {
df17e62e
MG		 1615 struct pci_pme_device *pme_dev;
1616 if (enable) {
1617 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1618 GFP_KERNEL);
1619 if (!pme_dev)
1620 goto out;
1621 pme_dev->dev = dev;
1622 mutex_lock(&pci_pme_list_mutex);
1623 list_add(&pme_dev->list, &pci_pme_list);
1624 if (list_is_singular(&pci_pme_list))
1625 schedule_delayed_work(&pci_pme_work,
1626 msecs_to_jiffies(PME_TIMEOUT));
1627 mutex_unlock(&pci_pme_list_mutex);
1628 } else {
1629 mutex_lock(&pci_pme_list_mutex);
1630 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1631 if (pme_dev->dev == dev) {
1632 list_del(&pme_dev->list);
1633 kfree(pme_dev);
1634 break;
1635 }
1636 }
1637 mutex_unlock(&pci_pme_list_mutex);
1638 }
1639 }
1640
1641out:
85b8582d 1642 dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled");
eb9d0fe4
RW		 1643}
1644
1da177e4 1645/**
6cbf8214 1646 * __pci_enable_wake - enable PCI device as wakeup event source
075c1771
DB		 1647 * @dev: PCI device affected
1648 * @state: PCI state from which device will issue wakeup events
6cbf8214 1649 * @runtime: True if the events are to be generated at run time
075c1771
DB		 1650 * @enable: True to enable event generation; false to disable
1651 *
1652 * This enables the device as a wakeup event source, or disables it.
1653 * When such events involves platform-specific hooks, those hooks are
1654 * called automatically by this routine.
1655 *
1656 * Devices with legacy power management (no standard PCI PM capabilities)
eb9d0fe4 1657 * always require such platform hooks.
075c1771 1658 *
eb9d0fe4
RW		 1659 * RETURN VALUE:
1660 * 0 is returned on success
1661 * -EINVAL is returned if device is not supposed to wake up the system
1662 * Error code depending on the platform is returned if both the platform and
1663 * the native mechanism fail to enable the generation of wake-up events
1da177e4 1664 */
6cbf8214
RW		 1665int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1666 bool runtime, bool enable)
1da177e4 1667{
5bcc2fb4 1668 int ret = 0;
075c1771 1669
6cbf8214 1670 if (enable && !runtime && !device_may_wakeup(&dev->dev))
eb9d0fe4 1671 return -EINVAL;
1da177e4 1672
e80bb09d
RW		 1673 /* Don't do the same thing twice in a row for one device. */
1674 if (!!enable == !!dev->wakeup_prepared)
1675 return 0;
1676
eb9d0fe4
RW		 1677 /*
1678 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1679 * Anderson we should be doing PME# wake enable followed by ACPI wake
1680 * enable. To disable wake-up we call the platform first, for symmetry.
075c1771 1681 */
1da177e4 1682
5bcc2fb4
RW		 1683 if (enable) {
1684 int error;
1da177e4 1685
5bcc2fb4
RW		 1686 if (pci_pme_capable(dev, state))
1687 pci_pme_active(dev, true);
1688 else
1689 ret = 1;
6cbf8214
RW		 1690 error = runtime ? platform_pci_run_wake(dev, true) :
1691 platform_pci_sleep_wake(dev, true);
5bcc2fb4
RW		 1692 if (ret)
1693 ret = error;
e80bb09d
RW		 1694 if (!ret)
1695 dev->wakeup_prepared = true;
5bcc2fb4 1696 } else {
6cbf8214
RW		 1697 if (runtime)
1698 platform_pci_run_wake(dev, false);
1699 else
1700 platform_pci_sleep_wake(dev, false);
5bcc2fb4 1701 pci_pme_active(dev, false);
e80bb09d 1702 dev->wakeup_prepared = false;
5bcc2fb4 1703 }
1da177e4 1704
5bcc2fb4 1705 return ret;
eb9d0fe4 1706}
6cbf8214 1707EXPORT_SYMBOL(__pci_enable_wake);
1da177e4 1708
0235c4fc
RW		 1709/**
1710 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1711 * @dev: PCI device to prepare
1712 * @enable: True to enable wake-up event generation; false to disable
1713 *
1714 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1715 * and this function allows them to set that up cleanly - pci_enable_wake()
1716 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1717 * ordering constraints.
1718 *
1719 * This function only returns error code if the device is not capable of
1720 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1721 * enable wake-up power for it.
1722 */
1723int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1724{
1725 return pci_pme_capable(dev, PCI_D3cold) ?
1726 pci_enable_wake(dev, PCI_D3cold, enable) :
1727 pci_enable_wake(dev, PCI_D3hot, enable);
1728}
1729
404cc2d8 1730/**
37139074
JB		 1731 * pci_target_state - find an appropriate low power state for a given PCI dev
1732 * @dev: PCI device
1733 *
1734 * Use underlying platform code to find a supported low power state for @dev.
1735 * If the platform can't manage @dev, return the deepest state from which it
1736 * can generate wake events, based on any available PME info.
404cc2d8 1737 */
e5899e1b 1738pci_power_t pci_target_state(struct pci_dev *dev)
404cc2d8
RW		 1739{
1740 pci_power_t target_state = PCI_D3hot;
404cc2d8
RW		 1741
1742 if (platform_pci_power_manageable(dev)) {
1743 /*
1744 * Call the platform to choose the target state of the device
1745 * and enable wake-up from this state if supported.
1746 */
1747 pci_power_t state = platform_pci_choose_state(dev);
1748
1749 switch (state) {
1750 case PCI_POWER_ERROR:
1751 case PCI_UNKNOWN:
1752 break;
1753 case PCI_D1:
1754 case PCI_D2:
1755 if (pci_no_d1d2(dev))
1756 break;
1757 default:
1758 target_state = state;
404cc2d8 1759 }
d2abdf62
RW		 1760 } else if (!dev->pm_cap) {
1761 target_state = PCI_D0;
404cc2d8
RW		 1762 } else if (device_may_wakeup(&dev->dev)) {
1763 /*
1764 * Find the deepest state from which the device can generate
1765 * wake-up events, make it the target state and enable device
1766 * to generate PME#.
1767 */
337001b6
RW		 1768 if (dev->pme_support) {
1769 while (target_state
1770 && !(dev->pme_support & (1 << target_state)))
1771 target_state--;
404cc2d8
RW		 1772 }
1773 }
1774
e5899e1b
RW		 1775 return target_state;
1776}
1777
1778/**
1779 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1780 * @dev: Device to handle.
1781 *
1782 * Choose the power state appropriate for the device depending on whether
1783 * it can wake up the system and/or is power manageable by the platform
1784 * (PCI_D3hot is the default) and put the device into that state.
1785 */
1786int pci_prepare_to_sleep(struct pci_dev *dev)
1787{
1788 pci_power_t target_state = pci_target_state(dev);
1789 int error;
1790
1791 if (target_state == PCI_POWER_ERROR)
1792 return -EIO;
1793
448bd857
HY		 1794 /* D3cold during system suspend/hibernate is not supported */
1795 if (target_state > PCI_D3hot)
1796 target_state = PCI_D3hot;
1797
8efb8c76 1798 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
c157dfa3 1799
404cc2d8
RW		 1800 error = pci_set_power_state(dev, target_state);
1801
1802 if (error)
1803 pci_enable_wake(dev, target_state, false);
1804
1805 return error;
1806}
1807
1808/**
443bd1c4 1809 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
404cc2d8
RW		 1810 * @dev: Device to handle.
1811 *
88393161 1812 * Disable device's system wake-up capability and put it into D0.
404cc2d8
RW		 1813 */
1814int pci_back_from_sleep(struct pci_dev *dev)
1815{
1816 pci_enable_wake(dev, PCI_D0, false);
1817 return pci_set_power_state(dev, PCI_D0);
1818}
1819
6cbf8214
RW		 1820/**
1821 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1822 * @dev: PCI device being suspended.
1823 *
1824 * Prepare @dev to generate wake-up events at run time and put it into a low
1825 * power state.
1826 */
1827int pci_finish_runtime_suspend(struct pci_dev *dev)
1828{
1829 pci_power_t target_state = pci_target_state(dev);
1830 int error;
1831
1832 if (target_state == PCI_POWER_ERROR)
1833 return -EIO;
1834
448bd857
HY		 1835 dev->runtime_d3cold = target_state == PCI_D3cold;
1836
6cbf8214
RW		 1837 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
1838
1839 error = pci_set_power_state(dev, target_state);
1840
448bd857 1841 if (error) {
6cbf8214 1842 __pci_enable_wake(dev, target_state, true, false);
448bd857
HY		 1843 dev->runtime_d3cold = false;
1844 }
6cbf8214
RW		 1845
1846 return error;
1847}
1848
b67ea761
RW		 1849/**
1850 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1851 * @dev: Device to check.
1852 *
1853 * Return true if the device itself is cabable of generating wake-up events
1854 * (through the platform or using the native PCIe PME) or if the device supports
1855 * PME and one of its upstream bridges can generate wake-up events.
1856 */
1857bool pci_dev_run_wake(struct pci_dev *dev)
1858{
1859 struct pci_bus *bus = dev->bus;
1860
1861 if (device_run_wake(&dev->dev))
1862 return true;
1863
1864 if (!dev->pme_support)
1865 return false;
1866
1867 while (bus->parent) {
1868 struct pci_dev *bridge = bus->self;
1869
1870 if (device_run_wake(&bridge->dev))
1871 return true;
1872
1873 bus = bus->parent;
1874 }
1875
1876 /* We have reached the root bus. */
1877 if (bus->bridge)
1878 return device_run_wake(bus->bridge);
1879
1880 return false;
1881}
1882EXPORT_SYMBOL_GPL(pci_dev_run_wake);
1883
b3c32c4f
HY		 1884void pci_config_pm_runtime_get(struct pci_dev *pdev)
1885{
1886 struct device *dev = &pdev->dev;
1887 struct device *parent = dev->parent;
1888
1889 if (parent)
1890 pm_runtime_get_sync(parent);
1891 pm_runtime_get_noresume(dev);
1892 /*
1893 * pdev->current_state is set to PCI_D3cold during suspending,
1894 * so wait until suspending completes
1895 */
1896 pm_runtime_barrier(dev);
1897 /*
1898 * Only need to resume devices in D3cold, because config
1899 * registers are still accessible for devices suspended but
1900 * not in D3cold.
1901 */
1902 if (pdev->current_state == PCI_D3cold)
1903 pm_runtime_resume(dev);
1904}
1905
1906void pci_config_pm_runtime_put(struct pci_dev *pdev)
1907{
1908 struct device *dev = &pdev->dev;
1909 struct device *parent = dev->parent;
1910
1911 pm_runtime_put(dev);
1912 if (parent)
1913 pm_runtime_put_sync(parent);
1914}
1915
eb9d0fe4
RW		 1916/**
1917 * pci_pm_init - Initialize PM functions of given PCI device
1918 * @dev: PCI device to handle.
1919 */
1920void pci_pm_init(struct pci_dev *dev)
1921{
1922 int pm;
1923 u16 pmc;
1da177e4 1924
bb910a70 1925 pm_runtime_forbid(&dev->dev);
967577b0
HY		 1926 pm_runtime_set_active(&dev->dev);
1927 pm_runtime_enable(&dev->dev);
a1e4d72c 1928 device_enable_async_suspend(&dev->dev);
e80bb09d 1929 dev->wakeup_prepared = false;
bb910a70 1930
337001b6
RW		 1931 dev->pm_cap = 0;
1932
eb9d0fe4
RW		 1933 /* find PCI PM capability in list */
1934 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1935 if (!pm)
50246dd4 1936 return;
eb9d0fe4
RW		 1937 /* Check device's ability to generate PME# */
1938 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
075c1771 1939
eb9d0fe4
RW		 1940 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1941 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1942 pmc & PCI_PM_CAP_VER_MASK);
50246dd4 1943 return;
eb9d0fe4
RW		 1944 }
1945
337001b6 1946 dev->pm_cap = pm;
1ae861e6 1947 dev->d3_delay = PCI_PM_D3_WAIT;
448bd857 1948 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
4f9c1397 1949 dev->d3cold_allowed = true;
337001b6
RW		 1950
1951 dev->d1_support = false;
1952 dev->d2_support = false;
1953 if (!pci_no_d1d2(dev)) {
c9ed77ee 1954 if (pmc & PCI_PM_CAP_D1)
337001b6 1955 dev->d1_support = true;
c9ed77ee 1956 if (pmc & PCI_PM_CAP_D2)
337001b6 1957 dev->d2_support = true;
c9ed77ee
BH		 1958
1959 if (dev->d1_support || dev->d2_support)
1960 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
ec84f126
JB		 1961 dev->d1_support ? " D1" : "",
1962 dev->d2_support ? " D2" : "");
337001b6
RW		 1963 }
1964
1965 pmc &= PCI_PM_CAP_PME_MASK;
1966 if (pmc) {
10c3d71d
BH		 1967 dev_printk(KERN_DEBUG, &dev->dev,
1968 "PME# supported from%s%s%s%s%s\n",
c9ed77ee
BH		 1969 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
1970 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
1971 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
1972 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
1973 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
337001b6 1974 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
379021d5 1975 dev->pme_poll = true;
eb9d0fe4
RW		 1976 /*
1977 * Make device's PM flags reflect the wake-up capability, but
1978 * let the user space enable it to wake up the system as needed.
1979 */
1980 device_set_wakeup_capable(&dev->dev, true);
eb9d0fe4 1981 /* Disable the PME# generation functionality */
337001b6
RW		 1982 pci_pme_active(dev, false);
1983 } else {
1984 dev->pme_support = 0;
eb9d0fe4 1985 }
1da177e4
LT		 1986}
1987
eb9c39d0
JB		 1988/**
1989 * platform_pci_wakeup_init - init platform wakeup if present
1990 * @dev: PCI device
1991 *
1992 * Some devices don't have PCI PM caps but can still generate wakeup
1993 * events through platform methods (like ACPI events). If @dev supports
1994 * platform wakeup events, set the device flag to indicate as much. This
1995 * may be redundant if the device also supports PCI PM caps, but double
1996 * initialization should be safe in that case.
1997 */
1998void platform_pci_wakeup_init(struct pci_dev *dev)
1999{
2000 if (!platform_pci_can_wakeup(dev))
2001 return;
2002
2003 device_set_wakeup_capable(&dev->dev, true);
eb9c39d0
JB		 2004 platform_pci_sleep_wake(dev, false);
2005}
2006
34a4876e
YL		 2007static void pci_add_saved_cap(struct pci_dev *pci_dev,
2008 struct pci_cap_saved_state *new_cap)
2009{
2010 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
2011}
2012
63f4898a
RW		 2013/**
2014 * pci_add_save_buffer - allocate buffer for saving given capability registers
2015 * @dev: the PCI device
2016 * @cap: the capability to allocate the buffer for
2017 * @size: requested size of the buffer
2018 */
2019static int pci_add_cap_save_buffer(
2020 struct pci_dev *dev, char cap, unsigned int size)
2021{
2022 int pos;
2023 struct pci_cap_saved_state *save_state;
2024
2025 pos = pci_find_capability(dev, cap);
2026 if (pos <= 0)
2027 return 0;
2028
2029 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
2030 if (!save_state)
2031 return -ENOMEM;
2032
24a4742f
AW		 2033 save_state->cap.cap_nr = cap;
2034 save_state->cap.size = size;
63f4898a
RW		 2035 pci_add_saved_cap(dev, save_state);
2036
2037 return 0;
2038}
2039
2040/**
2041 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
2042 * @dev: the PCI device
2043 */
2044void pci_allocate_cap_save_buffers(struct pci_dev *dev)
2045{
2046 int error;
2047
89858517
YZ		 2048 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
2049 PCI_EXP_SAVE_REGS * sizeof(u16));
63f4898a
RW		 2050 if (error)
2051 dev_err(&dev->dev,
2052 "unable to preallocate PCI Express save buffer\n");
2053
2054 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
2055 if (error)
2056 dev_err(&dev->dev,
2057 "unable to preallocate PCI-X save buffer\n");
2058}
2059
f796841e
YL		 2060void pci_free_cap_save_buffers(struct pci_dev *dev)
2061{
2062 struct pci_cap_saved_state *tmp;
2063 struct hlist_node *pos, *n;
2064
2065 hlist_for_each_entry_safe(tmp, pos, n, &dev->saved_cap_space, next)
2066 kfree(tmp);
2067}
2068
58c3a727
YZ		 2069/**
2070 * pci_enable_ari - enable ARI forwarding if hardware support it
2071 * @dev: the PCI device
2072 */
2073void pci_enable_ari(struct pci_dev *dev)
2074{
58c3a727 2075 u32 cap;
8113587c 2076 struct pci_dev *bridge;
58c3a727 2077
6748dcc2 2078 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
58c3a727
YZ		 2079 return;
2080
59875ae4 2081 if (!pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI))
58c3a727
YZ		 2082 return;
2083
8113587c 2084 bridge = dev->bus->self;
cb97ae34 2085 if (!bridge)
8113587c
ZY		 2086 return;
2087
59875ae4 2088 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
58c3a727
YZ		 2089 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2090 return;
2091
59875ae4 2092 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_ARI);
8113587c 2093 bridge->ari_enabled = 1;
58c3a727
YZ		 2094}
2095
b48d4425 2096/**
c463b8cb 2097 * pci_enable_ido - enable ID-based Ordering on a device
b48d4425
JB		 2098 * @dev: the PCI device
2099 * @type: which types of IDO to enable
2100 *
2101 * Enable ID-based ordering on @dev. @type can contain the bits
2102 * %PCI_EXP_IDO_REQUEST and/or %PCI_EXP_IDO_COMPLETION to indicate
2103 * which types of transactions are allowed to be re-ordered.
2104 */
2105void pci_enable_ido(struct pci_dev *dev, unsigned long type)
2106{
59875ae4 2107 u16 ctrl = 0;
b48d4425 2108
b48d4425
JB		 2109 if (type & PCI_EXP_IDO_REQUEST)
2110 ctrl |= PCI_EXP_IDO_REQ_EN;
2111 if (type & PCI_EXP_IDO_COMPLETION)
2112 ctrl |= PCI_EXP_IDO_CMP_EN;
59875ae4
JL		 2113 if (ctrl)
2114 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, ctrl);
b48d4425
JB		 2115}
2116EXPORT_SYMBOL(pci_enable_ido);
2117
2118/**
2119 * pci_disable_ido - disable ID-based ordering on a device
2120 * @dev: the PCI device
2121 * @type: which types of IDO to disable
2122 */
2123void pci_disable_ido(struct pci_dev *dev, unsigned long type)
2124{
59875ae4 2125 u16 ctrl = 0;
b48d4425 2126
b48d4425 2127 if (type & PCI_EXP_IDO_REQUEST)
59875ae4 2128 ctrl |= PCI_EXP_IDO_REQ_EN;
b48d4425 2129 if (type & PCI_EXP_IDO_COMPLETION)
59875ae4
JL		 2130 ctrl |= PCI_EXP_IDO_CMP_EN;
2131 if (ctrl)
2132 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, ctrl);
b48d4425
JB		 2133}
2134EXPORT_SYMBOL(pci_disable_ido);
2135
48a92a81
JB		 2136/**
2137 * pci_enable_obff - enable optimized buffer flush/fill
2138 * @dev: PCI device
2139 * @type: type of signaling to use
2140 *
2141 * Try to enable @type OBFF signaling on @dev. It will try using WAKE#
2142 * signaling if possible, falling back to message signaling only if
2143 * WAKE# isn't supported. @type should indicate whether the PCIe link
2144 * be brought out of L0s or L1 to send the message. It should be either
2145 * %PCI_EXP_OBFF_SIGNAL_ALWAYS or %PCI_OBFF_SIGNAL_L0.
2146 *
2147 * If your device can benefit from receiving all messages, even at the
2148 * power cost of bringing the link back up from a low power state, use
2149 * %PCI_EXP_OBFF_SIGNAL_ALWAYS. Otherwise, use %PCI_OBFF_SIGNAL_L0 (the
2150 * preferred type).
2151 *
2152 * RETURNS:
2153 * Zero on success, appropriate error number on failure.
2154 */
2155int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
2156{
48a92a81
JB		 2157 u32 cap;
2158 u16 ctrl;
2159 int ret;
2160
59875ae4 2161 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
48a92a81
JB		 2162 if (!(cap & PCI_EXP_OBFF_MASK))
2163 return -ENOTSUPP; /* no OBFF support at all */
2164
2165 /* Make sure the topology supports OBFF as well */
8291550f 2166 if (dev->bus->self) {
48a92a81
JB		 2167 ret = pci_enable_obff(dev->bus->self, type);
2168 if (ret)
2169 return ret;
2170 }
2171
59875ae4 2172 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &ctrl);
48a92a81
JB		 2173 if (cap & PCI_EXP_OBFF_WAKE)
2174 ctrl |= PCI_EXP_OBFF_WAKE_EN;
2175 else {
2176 switch (type) {
2177 case PCI_EXP_OBFF_SIGNAL_L0:
2178 if (!(ctrl & PCI_EXP_OBFF_WAKE_EN))
2179 ctrl |= PCI_EXP_OBFF_MSGA_EN;
2180 break;
2181 case PCI_EXP_OBFF_SIGNAL_ALWAYS:
2182 ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
2183 ctrl |= PCI_EXP_OBFF_MSGB_EN;
2184 break;
2185 default:
2186 WARN(1, "bad OBFF signal type\n");
2187 return -ENOTSUPP;
2188 }
2189 }
59875ae4 2190 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, ctrl);
48a92a81
JB		 2191
2192 return 0;
2193}
2194EXPORT_SYMBOL(pci_enable_obff);
2195
2196/**
2197 * pci_disable_obff - disable optimized buffer flush/fill
2198 * @dev: PCI device
2199 *
2200 * Disable OBFF on @dev.
2201 */
2202void pci_disable_obff(struct pci_dev *dev)
2203{
59875ae4 2204 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_OBFF_WAKE_EN);
48a92a81
JB		 2205}
2206EXPORT_SYMBOL(pci_disable_obff);
2207
51c2e0a7
JB		 2208/**
2209 * pci_ltr_supported - check whether a device supports LTR
2210 * @dev: PCI device
2211 *
2212 * RETURNS:
2213 * True if @dev supports latency tolerance reporting, false otherwise.
2214 */
c32823f8 2215static bool pci_ltr_supported(struct pci_dev *dev)
51c2e0a7 2216{
51c2e0a7
JB		 2217 u32 cap;
2218
59875ae4 2219 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
51c2e0a7
JB		 2220
2221 return cap & PCI_EXP_DEVCAP2_LTR;
2222}
51c2e0a7
JB		 2223
2224/**
2225 * pci_enable_ltr - enable latency tolerance reporting
2226 * @dev: PCI device
2227 *
2228 * Enable LTR on @dev if possible, which means enabling it first on
2229 * upstream ports.
2230 *
2231 * RETURNS:
2232 * Zero on success, errno on failure.
2233 */
2234int pci_enable_ltr(struct pci_dev *dev)
2235{
51c2e0a7
JB		 2236 int ret;
2237
51c2e0a7
JB		 2238 /* Only primary function can enable/disable LTR */
2239 if (PCI_FUNC(dev->devfn) != 0)
2240 return -EINVAL;
2241
59875ae4
JL		 2242 if (!pci_ltr_supported(dev))
2243 return -ENOTSUPP;
2244
51c2e0a7 2245 /* Enable upstream ports first */
8291550f 2246 if (dev->bus->self) {
51c2e0a7
JB		 2247 ret = pci_enable_ltr(dev->bus->self);
2248 if (ret)
2249 return ret;
2250 }
2251
59875ae4 2252 return pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_LTR_EN);
51c2e0a7
JB		 2253}
2254EXPORT_SYMBOL(pci_enable_ltr);
2255
2256/**
2257 * pci_disable_ltr - disable latency tolerance reporting
2258 * @dev: PCI device
2259 */
2260void pci_disable_ltr(struct pci_dev *dev)
2261{
51c2e0a7
JB		 2262 /* Only primary function can enable/disable LTR */
2263 if (PCI_FUNC(dev->devfn) != 0)
2264 return;
2265
59875ae4
JL		 2266 if (!pci_ltr_supported(dev))
2267 return;
2268
2269 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_LTR_EN);
51c2e0a7
JB		 2270}
2271EXPORT_SYMBOL(pci_disable_ltr);
2272
2273static int __pci_ltr_scale(int *val)
2274{
2275 int scale = 0;
2276
2277 while (*val > 1023) {
2278 *val = (*val + 31) / 32;
2279 scale++;
2280 }
2281 return scale;
2282}
2283
2284/**
2285 * pci_set_ltr - set LTR latency values
2286 * @dev: PCI device
2287 * @snoop_lat_ns: snoop latency in nanoseconds
2288 * @nosnoop_lat_ns: nosnoop latency in nanoseconds
2289 *
2290 * Figure out the scale and set the LTR values accordingly.
2291 */
2292int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns)
2293{
2294 int pos, ret, snoop_scale, nosnoop_scale;
2295 u16 val;
2296
2297 if (!pci_ltr_supported(dev))
2298 return -ENOTSUPP;
2299
2300 snoop_scale = __pci_ltr_scale(&snoop_lat_ns);
2301 nosnoop_scale = __pci_ltr_scale(&nosnoop_lat_ns);
2302
2303 if (snoop_lat_ns > PCI_LTR_VALUE_MASK ||
2304 nosnoop_lat_ns > PCI_LTR_VALUE_MASK)
2305 return -EINVAL;
2306
2307 if ((snoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)) ||
2308 (nosnoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)))
2309 return -EINVAL;
2310
2311 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
2312 if (!pos)
2313 return -ENOTSUPP;
2314
2315 val = (snoop_scale << PCI_LTR_SCALE_SHIFT) | snoop_lat_ns;
2316 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_SNOOP_LAT, val);
2317 if (ret != 4)
2318 return -EIO;
2319
2320 val = (nosnoop_scale << PCI_LTR_SCALE_SHIFT) | nosnoop_lat_ns;
2321 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_NOSNOOP_LAT, val);
2322 if (ret != 4)
2323 return -EIO;
2324
2325 return 0;
2326}
2327EXPORT_SYMBOL(pci_set_ltr);
2328
5d990b62
CW		 2329static int pci_acs_enable;
2330
2331/**
2332 * pci_request_acs - ask for ACS to be enabled if supported
2333 */
2334void pci_request_acs(void)
2335{
2336 pci_acs_enable = 1;
2337}
2338
ae21ee65
AK		 2339/**
2340 * pci_enable_acs - enable ACS if hardware support it
2341 * @dev: the PCI device
2342 */
2343void pci_enable_acs(struct pci_dev *dev)
2344{
2345 int pos;
2346 u16 cap;
2347 u16 ctrl;
2348
5d990b62
CW		 2349 if (!pci_acs_enable)
2350 return;
2351
ae21ee65
AK		 2352 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2353 if (!pos)
2354 return;
2355
2356 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2357 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2358
2359 /* Source Validation */
2360 ctrl |= (cap & PCI_ACS_SV);
2361
2362 /* P2P Request Redirect */
2363 ctrl |= (cap & PCI_ACS_RR);
2364
2365 /* P2P Completion Redirect */
2366 ctrl |= (cap & PCI_ACS_CR);
2367
2368 /* Upstream Forwarding */
2369 ctrl |= (cap & PCI_ACS_UF);
2370
2371 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2372}
2373
ad805758
AW		 2374/**
2375 * pci_acs_enabled - test ACS against required flags for a given device
2376 * @pdev: device to test
2377 * @acs_flags: required PCI ACS flags
2378 *
2379 * Return true if the device supports the provided flags. Automatically
2380 * filters out flags that are not implemented on multifunction devices.
2381 */
2382bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2383{
2384 int pos, ret;
2385 u16 ctrl;
2386
2387 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
2388 if (ret >= 0)
2389 return ret > 0;
2390
2391 if (!pci_is_pcie(pdev))
2392 return false;
2393
2394 /* Filter out flags not applicable to multifunction */
2395 if (pdev->multifunction)
2396 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR |
2397 PCI_ACS_EC | PCI_ACS_DT);
2398
62f87c0e
YW		 2399 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_DOWNSTREAM ||
2400 pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT ||
ad805758
AW		 2401 pdev->multifunction) {
2402 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
2403 if (!pos)
2404 return false;
2405
2406 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
2407 if ((ctrl & acs_flags) != acs_flags)
2408 return false;
2409 }
2410
2411 return true;
2412}
2413
2414/**
2415 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
2416 * @start: starting downstream device
2417 * @end: ending upstream device or NULL to search to the root bus
2418 * @acs_flags: required flags
2419 *
2420 * Walk up a device tree from start to end testing PCI ACS support. If
2421 * any step along the way does not support the required flags, return false.
2422 */
2423bool pci_acs_path_enabled(struct pci_dev *start,
2424 struct pci_dev *end, u16 acs_flags)
2425{
2426 struct pci_dev *pdev, *parent = start;
2427
2428 do {
2429 pdev = parent;
2430
2431 if (!pci_acs_enabled(pdev, acs_flags))
2432 return false;
2433
2434 if (pci_is_root_bus(pdev->bus))
2435 return (end == NULL);
2436
2437 parent = pdev->bus->self;
2438 } while (pdev != end);
2439
2440 return true;
2441}
2442
57c2cf71
BH		 2443/**
2444 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2445 * @dev: the PCI device
2446 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2447 *
2448 * Perform INTx swizzling for a device behind one level of bridge. This is
2449 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
46b952a3
MW		 2450 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2451 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2452 * the PCI Express Base Specification, Revision 2.1)
57c2cf71 2453 */
3df425f3 2454u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
57c2cf71 2455{
46b952a3
MW		 2456 int slot;
2457
2458 if (pci_ari_enabled(dev->bus))
2459 slot = 0;
2460 else
2461 slot = PCI_SLOT(dev->devfn);
2462
2463 return (((pin - 1) + slot) % 4) + 1;
57c2cf71
BH		 2464}
2465
1da177e4
LT		 2466int
2467pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
2468{
2469 u8 pin;
2470
514d207d 2471 pin = dev->pin;
1da177e4
LT		 2472 if (!pin)
2473 return -1;
878f2e50 2474
8784fd4d 2475 while (!pci_is_root_bus(dev->bus)) {
57c2cf71 2476 pin = pci_swizzle_interrupt_pin(dev, pin);
1da177e4
LT		 2477 dev = dev->bus->self;
2478 }
2479 *bridge = dev;
2480 return pin;
2481}
2482
68feac87
BH		 2483/**
2484 * pci_common_swizzle - swizzle INTx all the way to root bridge
2485 * @dev: the PCI device
2486 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2487 *
2488 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2489 * bridges all the way up to a PCI root bus.
2490 */
2491u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
2492{
2493 u8 pin = *pinp;
2494
1eb39487 2495 while (!pci_is_root_bus(dev->bus)) {
68feac87
BH		 2496 pin = pci_swizzle_interrupt_pin(dev, pin);
2497 dev = dev->bus->self;
2498 }
2499 *pinp = pin;
2500 return PCI_SLOT(dev->devfn);
2501}
2502
1da177e4
LT		 2503/**
2504 * pci_release_region - Release a PCI bar
2505 * @pdev: PCI device whose resources were previously reserved by pci_request_region
2506 * @bar: BAR to release
2507 *
2508 * Releases the PCI I/O and memory resources previously reserved by a
2509 * successful call to pci_request_region. Call this function only
2510 * after all use of the PCI regions has ceased.
2511 */
2512void pci_release_region(struct pci_dev *pdev, int bar)
2513{
9ac7849e
TH		 2514 struct pci_devres *dr;
2515
1da177e4
LT		 2516 if (pci_resource_len(pdev, bar) == 0)
2517 return;
2518 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
2519 release_region(pci_resource_start(pdev, bar),
2520 pci_resource_len(pdev, bar));
2521 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
2522 release_mem_region(pci_resource_start(pdev, bar),
2523 pci_resource_len(pdev, bar));
9ac7849e
TH		 2524
2525 dr = find_pci_dr(pdev);
2526 if (dr)
2527 dr->region_mask &= ~(1 << bar);
1da177e4
LT		 2528}
2529
2530/**
f5ddcac4 2531 * __pci_request_region - Reserved PCI I/O and memory resource
1da177e4
LT		 2532 * @pdev: PCI device whose resources are to be reserved
2533 * @bar: BAR to be reserved
2534 * @res_name: Name to be associated with resource.
f5ddcac4 2535 * @exclusive: whether the region access is exclusive or not
1da177e4
LT		 2536 *
2537 * Mark the PCI region associated with PCI device @pdev BR @bar as
2538 * being reserved by owner @res_name. Do not access any
2539 * address inside the PCI regions unless this call returns
2540 * successfully.
2541 *
f5ddcac4
RD		 2542 * If @exclusive is set, then the region is marked so that userspace
2543 * is explicitly not allowed to map the resource via /dev/mem or
2544 * sysfs MMIO access.
2545 *
1da177e4
LT		 2546 * Returns 0 on success, or %EBUSY on error. A warning
2547 * message is also printed on failure.
2548 */
e8de1481
AV		 2549static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
2550 int exclusive)
1da177e4 2551{
9ac7849e
TH		 2552 struct pci_devres *dr;
2553
1da177e4
LT		 2554 if (pci_resource_len(pdev, bar) == 0)
2555 return 0;
2556
2557 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
2558 if (!request_region(pci_resource_start(pdev, bar),
2559 pci_resource_len(pdev, bar), res_name))
2560 goto err_out;
2561 }
2562 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
e8de1481
AV		 2563 if (!__request_mem_region(pci_resource_start(pdev, bar),
2564 pci_resource_len(pdev, bar), res_name,
2565 exclusive))
1da177e4
LT		 2566 goto err_out;
2567 }
9ac7849e
TH		 2568
2569 dr = find_pci_dr(pdev);
2570 if (dr)
2571 dr->region_mask |= 1 << bar;
2572
1da177e4
LT		 2573 return 0;
2574
2575err_out:
c7dabef8 2576 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
096e6f67 2577 &pdev->resource[bar]);
1da177e4
LT		 2578 return -EBUSY;
2579}
2580
e8de1481 2581/**
f5ddcac4 2582 * pci_request_region - Reserve PCI I/O and memory resource
e8de1481
AV		 2583 * @pdev: PCI device whose resources are to be reserved
2584 * @bar: BAR to be reserved
f5ddcac4 2585 * @res_name: Name to be associated with resource
e8de1481 2586 *
f5ddcac4 2587 * Mark the PCI region associated with PCI device @pdev BAR @bar as
e8de1481
AV		 2588 * being reserved by owner @res_name. Do not access any
2589 * address inside the PCI regions unless this call returns
2590 * successfully.
2591 *
2592 * Returns 0 on success, or %EBUSY on error. A warning
2593 * message is also printed on failure.
2594 */
2595int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
2596{
2597 return __pci_request_region(pdev, bar, res_name, 0);
2598}
2599
2600/**
2601 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
2602 * @pdev: PCI device whose resources are to be reserved
2603 * @bar: BAR to be reserved
2604 * @res_name: Name to be associated with resource.
2605 *
2606 * Mark the PCI region associated with PCI device @pdev BR @bar as
2607 * being reserved by owner @res_name. Do not access any
2608 * address inside the PCI regions unless this call returns
2609 * successfully.
2610 *
2611 * Returns 0 on success, or %EBUSY on error. A warning
2612 * message is also printed on failure.
2613 *
2614 * The key difference that _exclusive makes it that userspace is
2615 * explicitly not allowed to map the resource via /dev/mem or
2616 * sysfs.
2617 */
2618int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
2619{
2620 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
2621}
c87deff7
HS		 2622/**
2623 * pci_release_selected_regions - Release selected PCI I/O and memory resources
2624 * @pdev: PCI device whose resources were previously reserved
2625 * @bars: Bitmask of BARs to be released
2626 *
2627 * Release selected PCI I/O and memory resources previously reserved.
2628 * Call this function only after all use of the PCI regions has ceased.
2629 */
2630void pci_release_selected_regions(struct pci_dev *pdev, int bars)
2631{
2632 int i;
2633
2634 for (i = 0; i < 6; i++)
2635 if (bars & (1 << i))
2636 pci_release_region(pdev, i);
2637}
2638
e8de1481
AV		 2639int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
2640 const char *res_name, int excl)
c87deff7
HS		 2641{
2642 int i;
2643
2644 for (i = 0; i < 6; i++)
2645 if (bars & (1 << i))
e8de1481 2646 if (__pci_request_region(pdev, i, res_name, excl))
c87deff7
HS		 2647 goto err_out;
2648 return 0;
2649
2650err_out:
2651 while(--i >= 0)
2652 if (bars & (1 << i))
2653 pci_release_region(pdev, i);
2654
2655 return -EBUSY;
2656}
1da177e4 2657
e8de1481
AV		 2658
2659/**
2660 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2661 * @pdev: PCI device whose resources are to be reserved
2662 * @bars: Bitmask of BARs to be requested
2663 * @res_name: Name to be associated with resource
2664 */
2665int pci_request_selected_regions(struct pci_dev *pdev, int bars,
2666 const char *res_name)
2667{
2668 return __pci_request_selected_regions(pdev, bars, res_name, 0);
2669}
2670
2671int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
2672 int bars, const char *res_name)
2673{
2674 return __pci_request_selected_regions(pdev, bars, res_name,
2675 IORESOURCE_EXCLUSIVE);
2676}
2677
1da177e4
LT		 2678/**
2679 * pci_release_regions - Release reserved PCI I/O and memory resources
2680 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2681 *
2682 * Releases all PCI I/O and memory resources previously reserved by a
2683 * successful call to pci_request_regions. Call this function only
2684 * after all use of the PCI regions has ceased.
2685 */
2686
2687void pci_release_regions(struct pci_dev *pdev)
2688{
c87deff7 2689 pci_release_selected_regions(pdev, (1 << 6) - 1);
1da177e4
LT		 2690}
2691
2692/**
2693 * pci_request_regions - Reserved PCI I/O and memory resources
2694 * @pdev: PCI device whose resources are to be reserved
2695 * @res_name: Name to be associated with resource.
2696 *
2697 * Mark all PCI regions associated with PCI device @pdev as
2698 * being reserved by owner @res_name. Do not access any
2699 * address inside the PCI regions unless this call returns
2700 * successfully.
2701 *
2702 * Returns 0 on success, or %EBUSY on error. A warning
2703 * message is also printed on failure.
2704 */
3c990e92 2705int pci_request_regions(struct pci_dev *pdev, const char *res_name)
1da177e4 2706{
c87deff7 2707 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
1da177e4
LT		 2708}
2709
e8de1481
AV		 2710/**
2711 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2712 * @pdev: PCI device whose resources are to be reserved
2713 * @res_name: Name to be associated with resource.
2714 *
2715 * Mark all PCI regions associated with PCI device @pdev as
2716 * being reserved by owner @res_name. Do not access any
2717 * address inside the PCI regions unless this call returns
2718 * successfully.
2719 *
2720 * pci_request_regions_exclusive() will mark the region so that
2721 * /dev/mem and the sysfs MMIO access will not be allowed.
2722 *
2723 * Returns 0 on success, or %EBUSY on error. A warning
2724 * message is also printed on failure.
2725 */
2726int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
2727{
2728 return pci_request_selected_regions_exclusive(pdev,
2729 ((1 << 6) - 1), res_name);
2730}
2731
6a479079
BH		 2732static void __pci_set_master(struct pci_dev *dev, bool enable)
2733{
2734 u16 old_cmd, cmd;
2735
2736 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
2737 if (enable)
2738 cmd = old_cmd | PCI_COMMAND_MASTER;
2739 else
2740 cmd = old_cmd & ~PCI_COMMAND_MASTER;
2741 if (cmd != old_cmd) {
2742 dev_dbg(&dev->dev, "%s bus mastering\n",
2743 enable ? "enabling" : "disabling");
2744 pci_write_config_word(dev, PCI_COMMAND, cmd);
2745 }
2746 dev->is_busmaster = enable;
2747}
e8de1481 2748
2b6f2c35
MS		 2749/**
2750 * pcibios_setup - process "pci=" kernel boot arguments
2751 * @str: string used to pass in "pci=" kernel boot arguments
2752 *
2753 * Process kernel boot arguments. This is the default implementation.
2754 * Architecture specific implementations can override this as necessary.
2755 */
2756char * __weak __init pcibios_setup(char *str)
2757{
2758 return str;
2759}
2760
96c55900
MS		 2761/**
2762 * pcibios_set_master - enable PCI bus-mastering for device dev
2763 * @dev: the PCI device to enable
2764 *
2765 * Enables PCI bus-mastering for the device. This is the default
2766 * implementation. Architecture specific implementations can override
2767 * this if necessary.
2768 */
2769void __weak pcibios_set_master(struct pci_dev *dev)
2770{
2771 u8 lat;
2772
f676678f
MS		 2773 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
2774 if (pci_is_pcie(dev))
2775 return;
2776
96c55900
MS		 2777 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
2778 if (lat < 16)
2779 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
2780 else if (lat > pcibios_max_latency)
2781 lat = pcibios_max_latency;
2782 else
2783 return;
2784 dev_printk(KERN_DEBUG, &dev->dev, "setting latency timer to %d\n", lat);
2785 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
2786}
2787
1da177e4
LT		 2788/**
2789 * pci_set_master - enables bus-mastering for device dev
2790 * @dev: the PCI device to enable
2791 *
2792 * Enables bus-mastering on the device and calls pcibios_set_master()
2793 * to do the needed arch specific settings.
2794 */
6a479079 2795void pci_set_master(struct pci_dev *dev)
1da177e4 2796{
6a479079 2797 __pci_set_master(dev, true);
1da177e4
LT		 2798 pcibios_set_master(dev);
2799}
2800
6a479079
BH		 2801/**
2802 * pci_clear_master - disables bus-mastering for device dev
2803 * @dev: the PCI device to disable
2804 */
2805void pci_clear_master(struct pci_dev *dev)
2806{
2807 __pci_set_master(dev, false);
2808}
2809
1da177e4 2810/**
edb2d97e
MW		 2811 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2812 * @dev: the PCI device for which MWI is to be enabled
1da177e4 2813 *
edb2d97e
MW		 2814 * Helper function for pci_set_mwi.
2815 * Originally copied from drivers/net/acenic.c.
1da177e4
LT		 2816 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2817 *
2818 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2819 */
15ea76d4 2820int pci_set_cacheline_size(struct pci_dev *dev)
1da177e4
LT		 2821{
2822 u8 cacheline_size;
2823
2824 if (!pci_cache_line_size)
15ea76d4 2825 return -EINVAL;
1da177e4
LT		 2826
2827 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2828 equal to or multiple of the right value. */
2829 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2830 if (cacheline_size >= pci_cache_line_size &&
2831 (cacheline_size % pci_cache_line_size) == 0)
2832 return 0;
2833
2834 /* Write the correct value. */
2835 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
2836 /* Read it back. */
2837 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2838 if (cacheline_size == pci_cache_line_size)
2839 return 0;
2840
80ccba11
BH		 2841 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
2842 "supported\n", pci_cache_line_size << 2);
1da177e4
LT		 2843
2844 return -EINVAL;
2845}
15ea76d4
TH		 2846EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
2847
2848#ifdef PCI_DISABLE_MWI
2849int pci_set_mwi(struct pci_dev *dev)
2850{
2851 return 0;
2852}
2853
2854int pci_try_set_mwi(struct pci_dev *dev)
2855{
2856 return 0;
2857}
2858
2859void pci_clear_mwi(struct pci_dev *dev)
2860{
2861}
2862
2863#else
1da177e4
LT		 2864
2865/**
2866 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2867 * @dev: the PCI device for which MWI is enabled
2868 *
694625c0 2869 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1da177e4
LT		 2870 *
2871 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2872 */
2873int
2874pci_set_mwi(struct pci_dev *dev)
2875{
2876 int rc;
2877 u16 cmd;
2878
edb2d97e 2879 rc = pci_set_cacheline_size(dev);
1da177e4
LT		 2880 if (rc)
2881 return rc;
2882
2883 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2884 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
80ccba11 2885 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
1da177e4
LT		 2886 cmd |= PCI_COMMAND_INVALIDATE;
2887 pci_write_config_word(dev, PCI_COMMAND, cmd);
2888 }
2889
2890 return 0;
2891}
2892
694625c0
RD		 2893/**
2894 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2895 * @dev: the PCI device for which MWI is enabled
2896 *
2897 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2898 * Callers are not required to check the return value.
2899 *
2900 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2901 */
2902int pci_try_set_mwi(struct pci_dev *dev)
2903{
2904 int rc = pci_set_mwi(dev);
2905 return rc;
2906}
2907
1da177e4
LT		 2908/**
2909 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2910 * @dev: the PCI device to disable
2911 *
2912 * Disables PCI Memory-Write-Invalidate transaction on the device
2913 */
2914void
2915pci_clear_mwi(struct pci_dev *dev)
2916{
2917 u16 cmd;
2918
2919 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2920 if (cmd & PCI_COMMAND_INVALIDATE) {
2921 cmd &= ~PCI_COMMAND_INVALIDATE;
2922 pci_write_config_word(dev, PCI_COMMAND, cmd);
2923 }
2924}
edb2d97e 2925#endif /* ! PCI_DISABLE_MWI */
1da177e4 2926
a04ce0ff
BR		 2927/**
2928 * pci_intx - enables/disables PCI INTx for device dev
8f7020d3
RD		 2929 * @pdev: the PCI device to operate on
2930 * @enable: boolean: whether to enable or disable PCI INTx
a04ce0ff
BR		 2931 *
2932 * Enables/disables PCI INTx for device dev
2933 */
2934void
2935pci_intx(struct pci_dev *pdev, int enable)
2936{
2937 u16 pci_command, new;
2938
2939 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
2940
2941 if (enable) {
2942 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
2943 } else {
2944 new = pci_command | PCI_COMMAND_INTX_DISABLE;
2945 }
2946
2947 if (new != pci_command) {
9ac7849e
TH		 2948 struct pci_devres *dr;
2949
2fd9d74b 2950 pci_write_config_word(pdev, PCI_COMMAND, new);
9ac7849e
TH		 2951
2952 dr = find_pci_dr(pdev);
2953 if (dr && !dr->restore_intx) {
2954 dr->restore_intx = 1;
2955 dr->orig_intx = !enable;
2956 }
a04ce0ff
BR		 2957 }
2958}
2959
a2e27787
JK		 2960/**
2961 * pci_intx_mask_supported - probe for INTx masking support
6e9292c5 2962 * @dev: the PCI device to operate on
a2e27787
JK		 2963 *
2964 * Check if the device dev support INTx masking via the config space
2965 * command word.
2966 */
2967bool pci_intx_mask_supported(struct pci_dev *dev)
2968{
2969 bool mask_supported = false;
2970 u16 orig, new;
2971
fbebb9fd
BH		 2972 if (dev->broken_intx_masking)
2973 return false;
2974
a2e27787
JK		 2975 pci_cfg_access_lock(dev);
2976
2977 pci_read_config_word(dev, PCI_COMMAND, &orig);
2978 pci_write_config_word(dev, PCI_COMMAND,
2979 orig ^ PCI_COMMAND_INTX_DISABLE);
2980 pci_read_config_word(dev, PCI_COMMAND, &new);
2981
2982 /*
2983 * There's no way to protect against hardware bugs or detect them
2984 * reliably, but as long as we know what the value should be, let's
2985 * go ahead and check it.
2986 */
2987 if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
2988 dev_err(&dev->dev, "Command register changed from "
2989 "0x%x to 0x%x: driver or hardware bug?\n", orig, new);
2990 } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
2991 mask_supported = true;
2992 pci_write_config_word(dev, PCI_COMMAND, orig);
2993 }
2994
2995 pci_cfg_access_unlock(dev);
2996 return mask_supported;
2997}
2998EXPORT_SYMBOL_GPL(pci_intx_mask_supported);
2999
3000static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
3001{
3002 struct pci_bus *bus = dev->bus;
3003 bool mask_updated = true;
3004 u32 cmd_status_dword;
3005 u16 origcmd, newcmd;
3006 unsigned long flags;
3007 bool irq_pending;
3008
3009 /*
3010 * We do a single dword read to retrieve both command and status.
3011 * Document assumptions that make this possible.
3012 */
3013 BUILD_BUG_ON(PCI_COMMAND % 4);
3014 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
3015
3016 raw_spin_lock_irqsave(&pci_lock, flags);
3017
3018 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
3019
3020 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
3021
3022 /*
3023 * Check interrupt status register to see whether our device
3024 * triggered the interrupt (when masking) or the next IRQ is
3025 * already pending (when unmasking).
3026 */
3027 if (mask != irq_pending) {
3028 mask_updated = false;
3029 goto done;
3030 }
3031
3032 origcmd = cmd_status_dword;
3033 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
3034 if (mask)
3035 newcmd |= PCI_COMMAND_INTX_DISABLE;
3036 if (newcmd != origcmd)
3037 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
3038
3039done:
3040 raw_spin_unlock_irqrestore(&pci_lock, flags);
3041
3042 return mask_updated;
3043}
3044
3045/**
3046 * pci_check_and_mask_intx - mask INTx on pending interrupt
6e9292c5 3047 * @dev: the PCI device to operate on
a2e27787
JK		 3048 *
3049 * Check if the device dev has its INTx line asserted, mask it and
3050 * return true in that case. False is returned if not interrupt was
3051 * pending.
3052 */
3053bool pci_check_and_mask_intx(struct pci_dev *dev)
3054{
3055 return pci_check_and_set_intx_mask(dev, true);
3056}
3057EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
3058
3059/**
3060 * pci_check_and_mask_intx - unmask INTx of no interrupt is pending
6e9292c5 3061 * @dev: the PCI device to operate on
a2e27787
JK		 3062 *
3063 * Check if the device dev has its INTx line asserted, unmask it if not
3064 * and return true. False is returned and the mask remains active if
3065 * there was still an interrupt pending.
3066 */
3067bool pci_check_and_unmask_intx(struct pci_dev *dev)
3068{
3069 return pci_check_and_set_intx_mask(dev, false);
3070}
3071EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
3072
f5f2b131
EB		 3073/**
3074 * pci_msi_off - disables any msi or msix capabilities
8d7d86e9 3075 * @dev: the PCI device to operate on
f5f2b131
EB		 3076 *
3077 * If you want to use msi see pci_enable_msi and friends.
3078 * This is a lower level primitive that allows us to disable
3079 * msi operation at the device level.
3080 */
3081void pci_msi_off(struct pci_dev *dev)
3082{
3083 int pos;
3084 u16 control;
3085
3086 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
3087 if (pos) {
3088 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
3089 control &= ~PCI_MSI_FLAGS_ENABLE;
3090 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
3091 }
3092 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
3093 if (pos) {
3094 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
3095 control &= ~PCI_MSIX_FLAGS_ENABLE;
3096 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
3097 }
3098}
b03214d5 3099EXPORT_SYMBOL_GPL(pci_msi_off);
f5f2b131 3100
4d57cdfa
FT		 3101int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
3102{
3103 return dma_set_max_seg_size(&dev->dev, size);
3104}
3105EXPORT_SYMBOL(pci_set_dma_max_seg_size);
4d57cdfa 3106
59fc67de
FT		 3107int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
3108{
3109 return dma_set_seg_boundary(&dev->dev, mask);
3110}
3111EXPORT_SYMBOL(pci_set_dma_seg_boundary);
59fc67de 3112
8c1c699f 3113static int pcie_flr(struct pci_dev *dev, int probe)
8dd7f803 3114{
8c1c699f 3115 int i;
8dd7f803 3116 u32 cap;
59875ae4 3117 u16 status;
8c1c699f 3118
59875ae4 3119 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
8dd7f803
SY		 3120 if (!(cap & PCI_EXP_DEVCAP_FLR))
3121 return -ENOTTY;
3122
d91cdc74
SY		 3123 if (probe)
3124 return 0;
3125
8dd7f803 3126 /* Wait for Transaction Pending bit clean */
8c1c699f
YZ		 3127 for (i = 0; i < 4; i++) {
3128 if (i)
3129 msleep((1 << (i - 1)) * 100);
5fe5db05 3130
59875ae4 3131 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
8c1c699f
YZ		 3132 if (!(status & PCI_EXP_DEVSTA_TRPND))
3133 goto clear;
3134 }
3135
3136 dev_err(&dev->dev, "transaction is not cleared; "
3137 "proceeding with reset anyway\n");
3138
3139clear:
59875ae4 3140 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
04b55c47 3141
8c1c699f 3142 msleep(100);
8dd7f803 3143
8dd7f803
SY		 3144 return 0;
3145}
d91cdc74 3146
8c1c699f 3147static int pci_af_flr(struct pci_dev *dev, int probe)
1ca88797 3148{
8c1c699f
YZ		 3149 int i;
3150 int pos;
1ca88797 3151 u8 cap;
8c1c699f 3152 u8 status;
1ca88797 3153
8c1c699f
YZ		 3154 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
3155 if (!pos)
1ca88797 3156 return -ENOTTY;
8c1c699f
YZ		 3157
3158 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
1ca88797
SY		 3159 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
3160 return -ENOTTY;
3161
3162 if (probe)
3163 return 0;
3164
1ca88797 3165 /* Wait for Transaction Pending bit clean */
8c1c699f
YZ		 3166 for (i = 0; i < 4; i++) {
3167 if (i)
3168 msleep((1 << (i - 1)) * 100);
3169
3170 pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status);
3171 if (!(status & PCI_AF_STATUS_TP))
3172 goto clear;
3173 }
5fe5db05 3174
8c1c699f
YZ		 3175 dev_err(&dev->dev, "transaction is not cleared; "
3176 "proceeding with reset anyway\n");
5fe5db05 3177
8c1c699f
YZ		 3178clear:
3179 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
1ca88797 3180 msleep(100);
8c1c699f 3181
1ca88797
SY		 3182 return 0;
3183}
3184
83d74e03
RW		 3185/**
3186 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
3187 * @dev: Device to reset.
3188 * @probe: If set, only check if the device can be reset this way.
3189 *
3190 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
3191 * unset, it will be reinitialized internally when going from PCI_D3hot to
3192 * PCI_D0. If that's the case and the device is not in a low-power state
3193 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
3194 *
3195 * NOTE: This causes the caller to sleep for twice the device power transition
3196 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
3197 * by devault (i.e. unless the @dev's d3_delay field has a different value).
3198 * Moreover, only devices in D0 can be reset by this function.
3199 */
f85876ba 3200static int pci_pm_reset(struct pci_dev *dev, int probe)
d91cdc74 3201{
f85876ba
YZ		 3202 u16 csr;
3203
3204 if (!dev->pm_cap)
3205 return -ENOTTY;
d91cdc74 3206
f85876ba
YZ		 3207 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
3208 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
3209 return -ENOTTY;
d91cdc74 3210
f85876ba
YZ		 3211 if (probe)
3212 return 0;
1ca88797 3213
f85876ba
YZ		 3214 if (dev->current_state != PCI_D0)
3215 return -EINVAL;
3216
3217 csr &= ~PCI_PM_CTRL_STATE_MASK;
3218 csr |= PCI_D3hot;
3219 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
1ae861e6 3220 pci_dev_d3_sleep(dev);
f85876ba
YZ		 3221
3222 csr &= ~PCI_PM_CTRL_STATE_MASK;
3223 csr |= PCI_D0;
3224 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
1ae861e6 3225 pci_dev_d3_sleep(dev);
f85876ba
YZ		 3226
3227 return 0;
3228}
3229
c12ff1df
YZ		 3230static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
3231{
3232 u16 ctrl;
3233 struct pci_dev *pdev;
3234
654b75e0 3235 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
c12ff1df
YZ		 3236 return -ENOTTY;
3237
3238 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3239 if (pdev != dev)
3240 return -ENOTTY;
3241
3242 if (probe)
3243 return 0;
3244
3245 pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl);
3246 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
3247 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
3248 msleep(100);
3249
3250 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
3251 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
3252 msleep(100);
3253
3254 return 0;
3255}
3256
977f857c 3257static int __pci_dev_reset(struct pci_dev *dev, int probe)
d91cdc74 3258{
8c1c699f
YZ		 3259 int rc;
3260
3261 might_sleep();
3262
b9c3b266
DC		 3263 rc = pci_dev_specific_reset(dev, probe);
3264 if (rc != -ENOTTY)
3265 goto done;
3266
8c1c699f
YZ		 3267 rc = pcie_flr(dev, probe);
3268 if (rc != -ENOTTY)
3269 goto done;
d91cdc74 3270
8c1c699f 3271 rc = pci_af_flr(dev, probe);
f85876ba
YZ		 3272 if (rc != -ENOTTY)
3273 goto done;
3274
3275 rc = pci_pm_reset(dev, probe);
c12ff1df
YZ		 3276 if (rc != -ENOTTY)
3277 goto done;
3278
3279 rc = pci_parent_bus_reset(dev, probe);
8c1c699f 3280done:
977f857c
KRW		 3281 return rc;
3282}
3283
3284static int pci_dev_reset(struct pci_dev *dev, int probe)
3285{
3286 int rc;
3287
3288 if (!probe) {
3289 pci_cfg_access_lock(dev);
3290 /* block PM suspend, driver probe, etc. */
3291 device_lock(&dev->dev);
3292 }
3293
3294 rc = __pci_dev_reset(dev, probe);
3295
8c1c699f 3296 if (!probe) {
8e9394ce 3297 device_unlock(&dev->dev);
fb51ccbf 3298 pci_cfg_access_unlock(dev);
8c1c699f 3299 }
8c1c699f 3300 return rc;
d91cdc74 3301}
d91cdc74 3302/**
8c1c699f
YZ		 3303 * __pci_reset_function - reset a PCI device function
3304 * @dev: PCI device to reset
d91cdc74
SY		 3305 *
3306 * Some devices allow an individual function to be reset without affecting
3307 * other functions in the same device. The PCI device must be responsive
3308 * to PCI config space in order to use this function.
3309 *
3310 * The device function is presumed to be unused when this function is called.
3311 * Resetting the device will make the contents of PCI configuration space
3312 * random, so any caller of this must be prepared to reinitialise the
3313 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3314 * etc.
3315 *
8c1c699f 3316 * Returns 0 if the device function was successfully reset or negative if the
d91cdc74
SY		 3317 * device doesn't support resetting a single function.
3318 */
8c1c699f 3319int __pci_reset_function(struct pci_dev *dev)
d91cdc74 3320{
8c1c699f 3321 return pci_dev_reset(dev, 0);
d91cdc74 3322}
8c1c699f 3323EXPORT_SYMBOL_GPL(__pci_reset_function);
8dd7f803 3324
6fbf9e7a
KRW		 3325/**
3326 * __pci_reset_function_locked - reset a PCI device function while holding
3327 * the @dev mutex lock.
3328 * @dev: PCI device to reset
3329 *
3330 * Some devices allow an individual function to be reset without affecting
3331 * other functions in the same device. The PCI device must be responsive
3332 * to PCI config space in order to use this function.
3333 *
3334 * The device function is presumed to be unused and the caller is holding
3335 * the device mutex lock when this function is called.
3336 * Resetting the device will make the contents of PCI configuration space
3337 * random, so any caller of this must be prepared to reinitialise the
3338 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3339 * etc.
3340 *
3341 * Returns 0 if the device function was successfully reset or negative if the
3342 * device doesn't support resetting a single function.
3343 */
3344int __pci_reset_function_locked(struct pci_dev *dev)
3345{
977f857c 3346 return __pci_dev_reset(dev, 0);
6fbf9e7a
KRW		 3347}
3348EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
3349
711d5779
MT		 3350/**
3351 * pci_probe_reset_function - check whether the device can be safely reset
3352 * @dev: PCI device to reset
3353 *
3354 * Some devices allow an individual function to be reset without affecting
3355 * other functions in the same device. The PCI device must be responsive
3356 * to PCI config space in order to use this function.
3357 *
3358 * Returns 0 if the device function can be reset or negative if the
3359 * device doesn't support resetting a single function.
3360 */
3361int pci_probe_reset_function(struct pci_dev *dev)
3362{
3363 return pci_dev_reset(dev, 1);
3364}
3365
8dd7f803 3366/**
8c1c699f
YZ		 3367 * pci_reset_function - quiesce and reset a PCI device function
3368 * @dev: PCI device to reset
8dd7f803
SY		 3369 *
3370 * Some devices allow an individual function to be reset without affecting
3371 * other functions in the same device. The PCI device must be responsive
3372 * to PCI config space in order to use this function.
3373 *
3374 * This function does not just reset the PCI portion of a device, but
3375 * clears all the state associated with the device. This function differs
8c1c699f 3376 * from __pci_reset_function in that it saves and restores device state
8dd7f803
SY		 3377 * over the reset.
3378 *
8c1c699f 3379 * Returns 0 if the device function was successfully reset or negative if the
8dd7f803
SY		 3380 * device doesn't support resetting a single function.
3381 */
3382int pci_reset_function(struct pci_dev *dev)
3383{
8c1c699f 3384 int rc;
8dd7f803 3385
8c1c699f
YZ		 3386 rc = pci_dev_reset(dev, 1);
3387 if (rc)
3388 return rc;
8dd7f803 3389
8dd7f803
SY		 3390 pci_save_state(dev);
3391
8c1c699f
YZ		 3392 /*
3393 * both INTx and MSI are disabled after the Interrupt Disable bit
3394 * is set and the Bus Master bit is cleared.
3395 */
8dd7f803
SY		 3396 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
3397
8c1c699f 3398 rc = pci_dev_reset(dev, 0);
8dd7f803
SY		 3399
3400 pci_restore_state(dev);
8dd7f803 3401
8c1c699f 3402 return rc;
8dd7f803
SY		 3403}
3404EXPORT_SYMBOL_GPL(pci_reset_function);
3405
d556ad4b
PO		 3406/**
3407 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
3408 * @dev: PCI device to query
3409 *
3410 * Returns mmrbc: maximum designed memory read count in bytes
3411 * or appropriate error value.
3412 */
3413int pcix_get_max_mmrbc(struct pci_dev *dev)
3414{
7c9e2b1c 3415 int cap;
d556ad4b
PO		 3416 u32 stat;
3417
3418 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3419 if (!cap)
3420 return -EINVAL;
3421
7c9e2b1c 3422 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
d556ad4b
PO		 3423 return -EINVAL;
3424
25daeb55 3425 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
d556ad4b
PO		 3426}
3427EXPORT_SYMBOL(pcix_get_max_mmrbc);
3428
3429/**
3430 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
3431 * @dev: PCI device to query
3432 *
3433 * Returns mmrbc: maximum memory read count in bytes
3434 * or appropriate error value.
3435 */
3436int pcix_get_mmrbc(struct pci_dev *dev)
3437{
7c9e2b1c 3438 int cap;
bdc2bda7 3439 u16 cmd;
d556ad4b
PO		 3440
3441 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3442 if (!cap)
3443 return -EINVAL;
3444
7c9e2b1c
DN		 3445 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3446 return -EINVAL;
d556ad4b 3447
7c9e2b1c 3448 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
d556ad4b
PO		 3449}
3450EXPORT_SYMBOL(pcix_get_mmrbc);
3451
3452/**
3453 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
3454 * @dev: PCI device to query
3455 * @mmrbc: maximum memory read count in bytes
3456 * valid values are 512, 1024, 2048, 4096
3457 *
3458 * If possible sets maximum memory read byte count, some bridges have erratas
3459 * that prevent this.
3460 */
3461int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
3462{
7c9e2b1c 3463 int cap;
bdc2bda7
DN		 3464 u32 stat, v, o;
3465 u16 cmd;
d556ad4b 3466
229f5afd 3467 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
7c9e2b1c 3468 return -EINVAL;
d556ad4b
PO		 3469
3470 v = ffs(mmrbc) - 10;
3471
3472 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3473 if (!cap)
7c9e2b1c 3474 return -EINVAL;
d556ad4b 3475
7c9e2b1c
DN		 3476 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3477 return -EINVAL;
d556ad4b
PO		 3478
3479 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
3480 return -E2BIG;
3481
7c9e2b1c
DN		 3482 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3483 return -EINVAL;
d556ad4b
PO		 3484
3485 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
3486 if (o != v) {
809a3bf9 3487 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
d556ad4b
PO		 3488 return -EIO;
3489
3490 cmd &= ~PCI_X_CMD_MAX_READ;
3491 cmd |= v << 2;
7c9e2b1c
DN		 3492 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
3493 return -EIO;
d556ad4b 3494 }
7c9e2b1c 3495 return 0;
d556ad4b
PO		 3496}
3497EXPORT_SYMBOL(pcix_set_mmrbc);
3498
3499/**
3500 * pcie_get_readrq - get PCI Express read request size
3501 * @dev: PCI device to query
3502 *
3503 * Returns maximum memory read request in bytes
3504 * or appropriate error value.
3505 */
3506int pcie_get_readrq(struct pci_dev *dev)
3507{
d556ad4b
PO		 3508 u16 ctl;
3509
59875ae4 3510 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
d556ad4b 3511
59875ae4 3512 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
d556ad4b
PO		 3513}
3514EXPORT_SYMBOL(pcie_get_readrq);
3515
3516/**
3517 * pcie_set_readrq - set PCI Express maximum memory read request
3518 * @dev: PCI device to query
42e61f4a 3519 * @rq: maximum memory read count in bytes
d556ad4b
PO		 3520 * valid values are 128, 256, 512, 1024, 2048, 4096
3521 *
c9b378c7 3522 * If possible sets maximum memory read request in bytes
d556ad4b
PO		 3523 */
3524int pcie_set_readrq(struct pci_dev *dev, int rq)
3525{
59875ae4 3526 u16 v;
d556ad4b 3527
229f5afd 3528 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
59875ae4 3529 return -EINVAL;
d556ad4b 3530
a1c473aa
BH		 3531 /*
3532 * If using the "performance" PCIe config, we clamp the
3533 * read rq size to the max packet size to prevent the
3534 * host bridge generating requests larger than we can
3535 * cope with
3536 */
3537 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
3538 int mps = pcie_get_mps(dev);
3539
3540 if (mps < 0)
3541 return mps;
3542 if (mps < rq)
3543 rq = mps;
3544 }
3545
3546 v = (ffs(rq) - 8) << 12;
d556ad4b 3547
59875ae4
JL		 3548 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
3549 PCI_EXP_DEVCTL_READRQ, v);
d556ad4b
PO		 3550}
3551EXPORT_SYMBOL(pcie_set_readrq);
3552
b03e7495
JM		 3553/**
3554 * pcie_get_mps - get PCI Express maximum payload size
3555 * @dev: PCI device to query
3556 *
3557 * Returns maximum payload size in bytes
3558 * or appropriate error value.
3559 */
3560int pcie_get_mps(struct pci_dev *dev)
3561{
b03e7495
JM		 3562 u16 ctl;
3563
59875ae4 3564 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
b03e7495 3565
59875ae4 3566 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
b03e7495
JM		 3567}
3568
3569/**
3570 * pcie_set_mps - set PCI Express maximum payload size
3571 * @dev: PCI device to query
47c08f31 3572 * @mps: maximum payload size in bytes
b03e7495
JM		 3573 * valid values are 128, 256, 512, 1024, 2048, 4096
3574 *
3575 * If possible sets maximum payload size
3576 */
3577int pcie_set_mps(struct pci_dev *dev, int mps)
3578{
59875ae4 3579 u16 v;
b03e7495
JM		 3580
3581 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
59875ae4 3582 return -EINVAL;
b03e7495
JM		 3583
3584 v = ffs(mps) - 8;
3585 if (v > dev->pcie_mpss)
59875ae4 3586 return -EINVAL;
b03e7495
JM		 3587 v <<= 5;
3588
59875ae4
JL		 3589 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
3590 PCI_EXP_DEVCTL_PAYLOAD, v);
b03e7495
JM		 3591}
3592
c87deff7
HS		 3593/**
3594 * pci_select_bars - Make BAR mask from the type of resource
f95d882d 3595 * @dev: the PCI device for which BAR mask is made
c87deff7
HS		 3596 * @flags: resource type mask to be selected
3597 *
3598 * This helper routine makes bar mask from the type of resource.
3599 */
3600int pci_select_bars(struct pci_dev *dev, unsigned long flags)
3601{
3602 int i, bars = 0;
3603 for (i = 0; i < PCI_NUM_RESOURCES; i++)
3604 if (pci_resource_flags(dev, i) & flags)
3605 bars |= (1 << i);
3606 return bars;
3607}
3608
613e7ed6
YZ		 3609/**
3610 * pci_resource_bar - get position of the BAR associated with a resource
3611 * @dev: the PCI device
3612 * @resno: the resource number
3613 * @type: the BAR type to be filled in
3614 *
3615 * Returns BAR position in config space, or 0 if the BAR is invalid.
3616 */
3617int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
3618{
d1b054da
YZ		 3619 int reg;
3620
613e7ed6
YZ		 3621 if (resno < PCI_ROM_RESOURCE) {
3622 *type = pci_bar_unknown;
3623 return PCI_BASE_ADDRESS_0 + 4 * resno;
3624 } else if (resno == PCI_ROM_RESOURCE) {
3625 *type = pci_bar_mem32;
3626 return dev->rom_base_reg;
d1b054da
YZ		 3627 } else if (resno < PCI_BRIDGE_RESOURCES) {
3628 /* device specific resource */
3629 reg = pci_iov_resource_bar(dev, resno, type);
3630 if (reg)
3631 return reg;
613e7ed6
YZ		 3632 }
3633
865df576 3634 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
613e7ed6
YZ		 3635 return 0;
3636}
3637
95a8b6ef
MT		 3638/* Some architectures require additional programming to enable VGA */
3639static arch_set_vga_state_t arch_set_vga_state;
3640
3641void __init pci_register_set_vga_state(arch_set_vga_state_t func)
3642{
3643 arch_set_vga_state = func; /* NULL disables */
3644}
3645
3646static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
7ad35cf2 3647 unsigned int command_bits, u32 flags)
95a8b6ef
MT		 3648{
3649 if (arch_set_vga_state)
3650 return arch_set_vga_state(dev, decode, command_bits,
7ad35cf2 3651 flags);
95a8b6ef
MT		 3652 return 0;
3653}
3654
deb2d2ec
BH		 3655/**
3656 * pci_set_vga_state - set VGA decode state on device and parents if requested
19eea630
RD		 3657 * @dev: the PCI device
3658 * @decode: true = enable decoding, false = disable decoding
3659 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
3f37d622 3660 * @flags: traverse ancestors and change bridges
3448a19d 3661 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
deb2d2ec
BH		 3662 */
3663int pci_set_vga_state(struct pci_dev *dev, bool decode,
3448a19d 3664 unsigned int command_bits, u32 flags)
deb2d2ec
BH		 3665{
3666 struct pci_bus *bus;
3667 struct pci_dev *bridge;
3668 u16 cmd;
95a8b6ef 3669 int rc;
deb2d2ec 3670
3448a19d 3671 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) & (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
deb2d2ec 3672
95a8b6ef 3673 /* ARCH specific VGA enables */
3448a19d 3674 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
95a8b6ef
MT		 3675 if (rc)
3676 return rc;
3677
3448a19d
DA		 3678 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
3679 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3680 if (decode == true)
3681 cmd |= command_bits;
3682 else
3683 cmd &= ~command_bits;
3684 pci_write_config_word(dev, PCI_COMMAND, cmd);
3685 }
deb2d2ec 3686
3448a19d 3687 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
deb2d2ec
BH		 3688 return 0;
3689
3690 bus = dev->bus;
3691 while (bus) {
3692 bridge = bus->self;
3693 if (bridge) {
3694 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
3695 &cmd);
3696 if (decode == true)
3697 cmd |= PCI_BRIDGE_CTL_VGA;
3698 else
3699 cmd &= ~PCI_BRIDGE_CTL_VGA;
3700 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
3701 cmd);
3702 }
3703 bus = bus->parent;
3704 }
3705 return 0;
3706}
3707
32a9a682
YS		 3708#define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
3709static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
e9d1e492 3710static DEFINE_SPINLOCK(resource_alignment_lock);
32a9a682
YS		 3711
3712/**
3713 * pci_specified_resource_alignment - get resource alignment specified by user.
3714 * @dev: the PCI device to get
3715 *
3716 * RETURNS: Resource alignment if it is specified.
3717 * Zero if it is not specified.
3718 */
3719resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
3720{
3721 int seg, bus, slot, func, align_order, count;
3722 resource_size_t align = 0;
3723 char *p;
3724
3725 spin_lock(&resource_alignment_lock);
3726 p = resource_alignment_param;
3727 while (*p) {
3728 count = 0;
3729 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
3730 p[count] == '@') {
3731 p += count + 1;
3732 } else {
3733 align_order = -1;
3734 }
3735 if (sscanf(p, "%x:%x:%x.%x%n",
3736 &seg, &bus, &slot, &func, &count) != 4) {
3737 seg = 0;
3738 if (sscanf(p, "%x:%x.%x%n",
3739 &bus, &slot, &func, &count) != 3) {
3740 /* Invalid format */
3741 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
3742 p);
3743 break;
3744 }
3745 }
3746 p += count;
3747 if (seg == pci_domain_nr(dev->bus) &&
3748 bus == dev->bus->number &&
3749 slot == PCI_SLOT(dev->devfn) &&
3750 func == PCI_FUNC(dev->devfn)) {
3751 if (align_order == -1) {
3752 align = PAGE_SIZE;
3753 } else {
3754 align = 1 << align_order;
3755 }
3756 /* Found */
3757 break;
3758 }
3759 if (*p != ';' && *p != ',') {
3760 /* End of param or invalid format */
3761 break;
3762 }
3763 p++;
3764 }
3765 spin_unlock(&resource_alignment_lock);
3766 return align;
3767}
3768
3769/**
3770 * pci_is_reassigndev - check if specified PCI is target device to reassign
3771 * @dev: the PCI device to check
3772 *
3773 * RETURNS: non-zero for PCI device is a target device to reassign,
3774 * or zero is not.
3775 */
3776int pci_is_reassigndev(struct pci_dev *dev)
3777{
3778 return (pci_specified_resource_alignment(dev) != 0);
3779}
3780
2069ecfb
YL		 3781/*
3782 * This function disables memory decoding and releases memory resources
3783 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
3784 * It also rounds up size to specified alignment.
3785 * Later on, the kernel will assign page-aligned memory resource back
3786 * to the device.
3787 */
3788void pci_reassigndev_resource_alignment(struct pci_dev *dev)
3789{
3790 int i;
3791 struct resource *r;
3792 resource_size_t align, size;
3793 u16 command;
3794
3795 if (!pci_is_reassigndev(dev))
3796 return;
3797
3798 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
3799 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
3800 dev_warn(&dev->dev,
3801 "Can't reassign resources to host bridge.\n");
3802 return;
3803 }
3804
3805 dev_info(&dev->dev,
3806 "Disabling memory decoding and releasing memory resources.\n");
3807 pci_read_config_word(dev, PCI_COMMAND, &command);
3808 command &= ~PCI_COMMAND_MEMORY;
3809 pci_write_config_word(dev, PCI_COMMAND, command);
3810
3811 align = pci_specified_resource_alignment(dev);
3812 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
3813 r = &dev->resource[i];
3814 if (!(r->flags & IORESOURCE_MEM))
3815 continue;
3816 size = resource_size(r);
3817 if (size < align) {
3818 size = align;
3819 dev_info(&dev->dev,
3820 "Rounding up size of resource #%d to %#llx.\n",
3821 i, (unsigned long long)size);
3822 }
3823 r->end = size - 1;
3824 r->start = 0;
3825 }
3826 /* Need to disable bridge's resource window,
3827 * to enable the kernel to reassign new resource
3828 * window later on.
3829 */
3830 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
3831 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
3832 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
3833 r = &dev->resource[i];
3834 if (!(r->flags & IORESOURCE_MEM))
3835 continue;
3836 r->end = resource_size(r) - 1;
3837 r->start = 0;
3838 }
3839 pci_disable_bridge_window(dev);
3840 }
3841}
3842
32a9a682
YS		 3843ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
3844{
3845 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
3846 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
3847 spin_lock(&resource_alignment_lock);
3848 strncpy(resource_alignment_param, buf, count);
3849 resource_alignment_param[count] = '\0';
3850 spin_unlock(&resource_alignment_lock);
3851 return count;
3852}
3853
3854ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
3855{
3856 size_t count;
3857 spin_lock(&resource_alignment_lock);
3858 count = snprintf(buf, size, "%s", resource_alignment_param);
3859 spin_unlock(&resource_alignment_lock);
3860 return count;
3861}
3862
3863static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
3864{
3865 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
3866}
3867
3868static ssize_t pci_resource_alignment_store(struct bus_type *bus,
3869 const char *buf, size_t count)
3870{
3871 return pci_set_resource_alignment_param(buf, count);
3872}
3873
3874BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
3875 pci_resource_alignment_store);
3876
3877static int __init pci_resource_alignment_sysfs_init(void)
3878{
3879 return bus_create_file(&pci_bus_type,
3880 &bus_attr_resource_alignment);
3881}
3882
3883late_initcall(pci_resource_alignment_sysfs_init);
3884
15856ad5 3885static void pci_no_domains(void)
32a2eea7
JG		 3886{
3887#ifdef CONFIG_PCI_DOMAINS
3888 pci_domains_supported = 0;
3889#endif
3890}
3891
0ef5f8f6 3892/**
642c92da 3893 * pci_ext_cfg_avail - can we access extended PCI config space?
0ef5f8f6
AP		 3894 *
3895 * Returns 1 if we can access PCI extended config space (offsets
3896 * greater than 0xff). This is the default implementation. Architecture
3897 * implementations can override this.
3898 */
642c92da 3899int __weak pci_ext_cfg_avail(void)
0ef5f8f6
AP		 3900{
3901 return 1;
3902}
3903
2d1c8618
BH		 3904void __weak pci_fixup_cardbus(struct pci_bus *bus)
3905{
3906}
3907EXPORT_SYMBOL(pci_fixup_cardbus);
3908
ad04d31e 3909static int __init pci_setup(char *str)
1da177e4
LT		 3910{
3911 while (str) {
3912 char *k = strchr(str, ',');
3913 if (k)
3914 *k++ = 0;
3915 if (*str && (str = pcibios_setup(str)) && *str) {
309e57df
MW		 3916 if (!strcmp(str, "nomsi")) {
3917 pci_no_msi();
7f785763
RD		 3918 } else if (!strcmp(str, "noaer")) {
3919 pci_no_aer();
b55438fd
YL		 3920 } else if (!strncmp(str, "realloc=", 8)) {
3921 pci_realloc_get_opt(str + 8);
f483d392 3922 } else if (!strncmp(str, "realloc", 7)) {
b55438fd 3923 pci_realloc_get_opt("on");
32a2eea7
JG		 3924 } else if (!strcmp(str, "nodomains")) {
3925 pci_no_domains();
6748dcc2
RW		 3926 } else if (!strncmp(str, "noari", 5)) {
3927 pcie_ari_disabled = true;
4516a618
AN		 3928 } else if (!strncmp(str, "cbiosize=", 9)) {
3929 pci_cardbus_io_size = memparse(str + 9, &str);
3930 } else if (!strncmp(str, "cbmemsize=", 10)) {
3931 pci_cardbus_mem_size = memparse(str + 10, &str);
32a9a682
YS		 3932 } else if (!strncmp(str, "resource_alignment=", 19)) {
3933 pci_set_resource_alignment_param(str + 19,
3934 strlen(str + 19));
43c16408
AP		 3935 } else if (!strncmp(str, "ecrc=", 5)) {
3936 pcie_ecrc_get_policy(str + 5);
28760489
EB		 3937 } else if (!strncmp(str, "hpiosize=", 9)) {
3938 pci_hotplug_io_size = memparse(str + 9, &str);
3939 } else if (!strncmp(str, "hpmemsize=", 10)) {
3940 pci_hotplug_mem_size = memparse(str + 10, &str);
5f39e670
JM		 3941 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
3942 pcie_bus_config = PCIE_BUS_TUNE_OFF;
b03e7495
JM		 3943 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
3944 pcie_bus_config = PCIE_BUS_SAFE;
3945 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
3946 pcie_bus_config = PCIE_BUS_PERFORMANCE;
5f39e670
JM		 3947 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
3948 pcie_bus_config = PCIE_BUS_PEER2PEER;
284f5f9d
BH		 3949 } else if (!strncmp(str, "pcie_scan_all", 13)) {
3950 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
309e57df
MW		 3951 } else {
3952 printk(KERN_ERR "PCI: Unknown option `%s'\n",
3953 str);
3954 }
1da177e4
LT		 3955 }
3956 str = k;
3957 }
0637a70a 3958 return 0;
1da177e4 3959}
0637a70a 3960early_param("pci", pci_setup);
1da177e4 3961
0b62e13b 3962EXPORT_SYMBOL(pci_reenable_device);
b718989d
BH		 3963EXPORT_SYMBOL(pci_enable_device_io);
3964EXPORT_SYMBOL(pci_enable_device_mem);
1da177e4 3965EXPORT_SYMBOL(pci_enable_device);
9ac7849e
TH		 3966EXPORT_SYMBOL(pcim_enable_device);
3967EXPORT_SYMBOL(pcim_pin_device);
1da177e4 3968EXPORT_SYMBOL(pci_disable_device);
1da177e4
LT		 3969EXPORT_SYMBOL(pci_find_capability);
3970EXPORT_SYMBOL(pci_bus_find_capability);
3971EXPORT_SYMBOL(pci_release_regions);
3972EXPORT_SYMBOL(pci_request_regions);
e8de1481 3973EXPORT_SYMBOL(pci_request_regions_exclusive);
1da177e4
LT		 3974EXPORT_SYMBOL(pci_release_region);
3975EXPORT_SYMBOL(pci_request_region);
e8de1481 3976EXPORT_SYMBOL(pci_request_region_exclusive);
c87deff7
HS		 3977EXPORT_SYMBOL(pci_release_selected_regions);
3978EXPORT_SYMBOL(pci_request_selected_regions);
e8de1481 3979EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
1da177e4 3980EXPORT_SYMBOL(pci_set_master);
6a479079 3981EXPORT_SYMBOL(pci_clear_master);
1da177e4 3982EXPORT_SYMBOL(pci_set_mwi);
694625c0 3983EXPORT_SYMBOL(pci_try_set_mwi);
1da177e4 3984EXPORT_SYMBOL(pci_clear_mwi);
a04ce0ff 3985EXPORT_SYMBOL_GPL(pci_intx);
1da177e4
LT		 3986EXPORT_SYMBOL(pci_assign_resource);
3987EXPORT_SYMBOL(pci_find_parent_resource);
c87deff7 3988EXPORT_SYMBOL(pci_select_bars);
1da177e4
LT		 3989
3990EXPORT_SYMBOL(pci_set_power_state);
3991EXPORT_SYMBOL(pci_save_state);
3992EXPORT_SYMBOL(pci_restore_state);
e5899e1b 3993EXPORT_SYMBOL(pci_pme_capable);
5a6c9b60 3994EXPORT_SYMBOL(pci_pme_active);
0235c4fc 3995EXPORT_SYMBOL(pci_wake_from_d3);
e5899e1b 3996EXPORT_SYMBOL(pci_target_state);
404cc2d8
RW		 3997EXPORT_SYMBOL(pci_prepare_to_sleep);
3998EXPORT_SYMBOL(pci_back_from_sleep);
f7bdd12d 3999EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
kernel source for telekom puls (alcatel/mediatek)