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PCI: Add pci_find_ht_capability() for finding Hypertransport capabilities
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / pci / pci.c
CommitLineData
1da177e4
LT		 1/*
2 * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $
3 *
4 * PCI Bus Services, see include/linux/pci.h for further explanation.
5 *
6 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * David Mosberger-Tang
8 *
9 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 */
11
12#include <linux/kernel.h>
13#include <linux/delay.h>
14#include <linux/init.h>
15#include <linux/pci.h>
16#include <linux/module.h>
17#include <linux/spinlock.h>
4e57b681 18#include <linux/string.h>
1da177e4 19#include <asm/dma.h> /* isa_dma_bridge_buggy */
bc56b9e0 20#include "pci.h"
1da177e4 21
ffadcc2f 22unsigned int pci_pm_d3_delay = 10;
1da177e4
LT		 23
24/**
25 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
26 * @bus: pointer to PCI bus structure to search
27 *
28 * Given a PCI bus, returns the highest PCI bus number present in the set
29 * including the given PCI bus and its list of child PCI buses.
30 */
31unsigned char __devinit
32pci_bus_max_busnr(struct pci_bus* bus)
33{
34 struct list_head *tmp;
35 unsigned char max, n;
36
b82db5ce 37 max = bus->subordinate;
1da177e4
LT		 38 list_for_each(tmp, &bus->children) {
39 n = pci_bus_max_busnr(pci_bus_b(tmp));
40 if(n > max)
41 max = n;
42 }
43 return max;
44}
b82db5ce 45EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
1da177e4 46
b82db5ce 47#if 0
1da177e4
LT		 48/**
49 * pci_max_busnr - returns maximum PCI bus number
50 *
51 * Returns the highest PCI bus number present in the system global list of
52 * PCI buses.
53 */
54unsigned char __devinit
55pci_max_busnr(void)
56{
57 struct pci_bus *bus = NULL;
58 unsigned char max, n;
59
60 max = 0;
61 while ((bus = pci_find_next_bus(bus)) != NULL) {
62 n = pci_bus_max_busnr(bus);
63 if(n > max)
64 max = n;
65 }
66 return max;
67}
68
54c762fe
AB		 69#endif /* 0 */
70
687d5fe3
ME		 71#define PCI_FIND_CAP_TTL 48
72
73static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
74 u8 pos, int cap, int *ttl)
24a4e377
RD		 75{
76 u8 id;
24a4e377 77
687d5fe3 78 while ((*ttl)--) {
24a4e377
RD		 79 pci_bus_read_config_byte(bus, devfn, pos, &pos);
80 if (pos < 0x40)
81 break;
82 pos &= ~3;
83 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
84 &id);
85 if (id == 0xff)
86 break;
87 if (id == cap)
88 return pos;
89 pos += PCI_CAP_LIST_NEXT;
90 }
91 return 0;
92}
93
687d5fe3
ME		 94static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
95 u8 pos, int cap)
96{
97 int ttl = PCI_FIND_CAP_TTL;
98
99 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
100}
101
24a4e377
RD		 102int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
103{
104 return __pci_find_next_cap(dev->bus, dev->devfn,
105 pos + PCI_CAP_LIST_NEXT, cap);
106}
107EXPORT_SYMBOL_GPL(pci_find_next_capability);
108
d3bac118
ME		 109static int __pci_bus_find_cap_start(struct pci_bus *bus,
110 unsigned int devfn, u8 hdr_type)
1da177e4
LT		 111{
112 u16 status;
1da177e4
LT		 113
114 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
115 if (!(status & PCI_STATUS_CAP_LIST))
116 return 0;
117
118 switch (hdr_type) {
119 case PCI_HEADER_TYPE_NORMAL:
120 case PCI_HEADER_TYPE_BRIDGE:
d3bac118 121 return PCI_CAPABILITY_LIST;
1da177e4 122 case PCI_HEADER_TYPE_CARDBUS:
d3bac118 123 return PCI_CB_CAPABILITY_LIST;
1da177e4
LT		 124 default:
125 return 0;
126 }
d3bac118
ME		 127
128 return 0;
1da177e4
LT		 129}
130
131/**
132 * pci_find_capability - query for devices' capabilities
133 * @dev: PCI device to query
134 * @cap: capability code
135 *
136 * Tell if a device supports a given PCI capability.
137 * Returns the address of the requested capability structure within the
138 * device's PCI configuration space or 0 in case the device does not
139 * support it. Possible values for @cap:
140 *
141 * %PCI_CAP_ID_PM Power Management
142 * %PCI_CAP_ID_AGP Accelerated Graphics Port
143 * %PCI_CAP_ID_VPD Vital Product Data
144 * %PCI_CAP_ID_SLOTID Slot Identification
145 * %PCI_CAP_ID_MSI Message Signalled Interrupts
146 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
147 * %PCI_CAP_ID_PCIX PCI-X
148 * %PCI_CAP_ID_EXP PCI Express
149 */
150int pci_find_capability(struct pci_dev *dev, int cap)
151{
d3bac118
ME		 152 int pos;
153
154 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
155 if (pos)
156 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
157
158 return pos;
1da177e4
LT		 159}
160
161/**
162 * pci_bus_find_capability - query for devices' capabilities
163 * @bus: the PCI bus to query
164 * @devfn: PCI device to query
165 * @cap: capability code
166 *
167 * Like pci_find_capability() but works for pci devices that do not have a
168 * pci_dev structure set up yet.
169 *
170 * Returns the address of the requested capability structure within the
171 * device's PCI configuration space or 0 in case the device does not
172 * support it.
173 */
174int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
175{
d3bac118 176 int pos;
1da177e4
LT		 177 u8 hdr_type;
178
179 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
180
d3bac118
ME		 181 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
182 if (pos)
183 pos = __pci_find_next_cap(bus, devfn, pos, cap);
184
185 return pos;
1da177e4
LT		 186}
187
188/**
189 * pci_find_ext_capability - Find an extended capability
190 * @dev: PCI device to query
191 * @cap: capability code
192 *
193 * Returns the address of the requested extended capability structure
194 * within the device's PCI configuration space or 0 if the device does
195 * not support it. Possible values for @cap:
196 *
197 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
198 * %PCI_EXT_CAP_ID_VC Virtual Channel
199 * %PCI_EXT_CAP_ID_DSN Device Serial Number
200 * %PCI_EXT_CAP_ID_PWR Power Budgeting
201 */
202int pci_find_ext_capability(struct pci_dev *dev, int cap)
203{
204 u32 header;
205 int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */
206 int pos = 0x100;
207
208 if (dev->cfg_size <= 256)
209 return 0;
210
211 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
212 return 0;
213
214 /*
215 * If we have no capabilities, this is indicated by cap ID,
216 * cap version and next pointer all being 0.
217 */
218 if (header == 0)
219 return 0;
220
221 while (ttl-- > 0) {
222 if (PCI_EXT_CAP_ID(header) == cap)
223 return pos;
224
225 pos = PCI_EXT_CAP_NEXT(header);
226 if (pos < 0x100)
227 break;
228
229 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
230 break;
231 }
232
233 return 0;
234}
3a720d72 235EXPORT_SYMBOL_GPL(pci_find_ext_capability);
1da177e4 236
687d5fe3
ME		 237static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
238{
239 int rc, ttl = PCI_FIND_CAP_TTL;
240 u8 cap, mask;
241
242 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
243 mask = HT_3BIT_CAP_MASK;
244 else
245 mask = HT_5BIT_CAP_MASK;
246
247 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
248 PCI_CAP_ID_HT, &ttl);
249 while (pos) {
250 rc = pci_read_config_byte(dev, pos + 3, &cap);
251 if (rc != PCIBIOS_SUCCESSFUL)
252 return 0;
253
254 if ((cap & mask) == ht_cap)
255 return pos;
256
257 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
258 PCI_CAP_ID_HT, &ttl);
259 }
260
261 return 0;
262}
263/**
264 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
265 * @dev: PCI device to query
266 * @pos: Position from which to continue searching
267 * @ht_cap: Hypertransport capability code
268 *
269 * To be used in conjunction with pci_find_ht_capability() to search for
270 * all capabilities matching @ht_cap. @pos should always be a value returned
271 * from pci_find_ht_capability().
272 *
273 * NB. To be 100% safe against broken PCI devices, the caller should take
274 * steps to avoid an infinite loop.
275 */
276int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
277{
278 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
279}
280EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
281
282/**
283 * pci_find_ht_capability - query a device's Hypertransport capabilities
284 * @dev: PCI device to query
285 * @ht_cap: Hypertransport capability code
286 *
287 * Tell if a device supports a given Hypertransport capability.
288 * Returns an address within the device's PCI configuration space
289 * or 0 in case the device does not support the request capability.
290 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
291 * which has a Hypertransport capability matching @ht_cap.
292 */
293int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
294{
295 int pos;
296
297 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
298 if (pos)
299 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
300
301 return pos;
302}
303EXPORT_SYMBOL_GPL(pci_find_ht_capability);
304
1da177e4
LT		 305/**
306 * pci_find_parent_resource - return resource region of parent bus of given region
307 * @dev: PCI device structure contains resources to be searched
308 * @res: child resource record for which parent is sought
309 *
310 * For given resource region of given device, return the resource
311 * region of parent bus the given region is contained in or where
312 * it should be allocated from.
313 */
314struct resource *
315pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
316{
317 const struct pci_bus *bus = dev->bus;
318 int i;
319 struct resource *best = NULL;
320
321 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
322 struct resource *r = bus->resource[i];
323 if (!r)
324 continue;
325 if (res->start && !(res->start >= r->start && res->end <= r->end))
326 continue; /* Not contained */
327 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
328 continue; /* Wrong type */
329 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
330 return r; /* Exact match */
331 if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
332 best = r; /* Approximating prefetchable by non-prefetchable */
333 }
334 return best;
335}
336
064b53db
JL		 337/**
338 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
339 * @dev: PCI device to have its BARs restored
340 *
341 * Restore the BAR values for a given device, so as to make it
342 * accessible by its driver.
343 */
344void
345pci_restore_bars(struct pci_dev *dev)
346{
347 int i, numres;
348
349 switch (dev->hdr_type) {
350 case PCI_HEADER_TYPE_NORMAL:
351 numres = 6;
352 break;
353 case PCI_HEADER_TYPE_BRIDGE:
354 numres = 2;
355 break;
356 case PCI_HEADER_TYPE_CARDBUS:
357 numres = 1;
358 break;
359 default:
360 /* Should never get here, but just in case... */
361 return;
362 }
363
364 for (i = 0; i < numres; i ++)
365 pci_update_resource(dev, &dev->resource[i], i);
366}
367
8f7020d3
RD		 368int (*platform_pci_set_power_state)(struct pci_dev *dev, pci_power_t t);
369
1da177e4
LT		 370/**
371 * pci_set_power_state - Set the power state of a PCI device
372 * @dev: PCI device to be suspended
373 * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering
374 *
375 * Transition a device to a new power state, using the Power Management
376 * Capabilities in the device's config space.
377 *
378 * RETURN VALUE:
379 * -EINVAL if trying to enter a lower state than we're already in.
380 * 0 if we're already in the requested state.
381 * -EIO if device does not support PCI PM.
382 * 0 if we can successfully change the power state.
383 */
1da177e4
LT		 384int
385pci_set_power_state(struct pci_dev *dev, pci_power_t state)
386{
064b53db 387 int pm, need_restore = 0;
1da177e4
LT		 388 u16 pmcsr, pmc;
389
390 /* bound the state we're entering */
391 if (state > PCI_D3hot)
392 state = PCI_D3hot;
393
394 /* Validate current state:
395 * Can enter D0 from any state, but if we can only go deeper
396 * to sleep if we're already in a low power state
397 */
02669492
AM		 398 if (state != PCI_D0 && dev->current_state > state) {
399 printk(KERN_ERR "%s(): %s: state=%d, current state=%d\n",
400 __FUNCTION__, pci_name(dev), state, dev->current_state);
1da177e4 401 return -EINVAL;
02669492 402 } else if (dev->current_state == state)
1da177e4
LT		 403 return 0; /* we're already there */
404
ffadcc2f
KCA		 405 /*
406 * If the device or the parent bridge can't support PCI PM, ignore
407 * the request if we're doing anything besides putting it into D0
408 * (which would only happen on boot).
409 */
410 if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
411 return 0;
412
1da177e4
LT		 413 /* find PCI PM capability in list */
414 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
415
416 /* abort if the device doesn't support PM capabilities */
417 if (!pm)
418 return -EIO;
419
420 pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc);
3fe9d19f 421 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1da177e4
LT		 422 printk(KERN_DEBUG
423 "PCI: %s has unsupported PM cap regs version (%u)\n",
424 pci_name(dev), pmc & PCI_PM_CAP_VER_MASK);
425 return -EIO;
426 }
427
428 /* check if this device supports the desired state */
3fe9d19f
DR		 429 if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1))
430 return -EIO;
431 else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2))
432 return -EIO;
1da177e4 433
064b53db
JL		 434 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
435
32a36585 436 /* If we're (effectively) in D3, force entire word to 0.
1da177e4
LT		 437 * This doesn't affect PME_Status, disables PME_En, and
438 * sets PowerState to 0.
439 */
32a36585 440 switch (dev->current_state) {
d3535fbb
JL		 441 case PCI_D0:
442 case PCI_D1:
443 case PCI_D2:
444 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
445 pmcsr |= state;
446 break;
32a36585
JL		 447 case PCI_UNKNOWN: /* Boot-up */
448 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
449 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
064b53db 450 need_restore = 1;
32a36585 451 /* Fall-through: force to D0 */
32a36585 452 default:
d3535fbb 453 pmcsr = 0;
32a36585 454 break;
1da177e4
LT		 455 }
456
457 /* enter specified state */
458 pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr);
459
460 /* Mandatory power management transition delays */
461 /* see PCI PM 1.1 5.6.1 table 18 */
462 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
ffadcc2f 463 msleep(pci_pm_d3_delay);
1da177e4
LT		 464 else if (state == PCI_D2 || dev->current_state == PCI_D2)
465 udelay(200);
1da177e4 466
b913100d
DSL		 467 /*
468 * Give firmware a chance to be called, such as ACPI _PRx, _PSx
d6e05edc 469 * Firmware method after native method ?
b913100d
DSL		 470 */
471 if (platform_pci_set_power_state)
472 platform_pci_set_power_state(dev, state);
473
474 dev->current_state = state;
064b53db
JL		 475
476 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
477 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
478 * from D3hot to D0 _may_ perform an internal reset, thereby
479 * going to "D0 Uninitialized" rather than "D0 Initialized".
480 * For example, at least some versions of the 3c905B and the
481 * 3c556B exhibit this behaviour.
482 *
483 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
484 * devices in a D3hot state at boot. Consequently, we need to
485 * restore at least the BARs so that the device will be
486 * accessible to its driver.
487 */
488 if (need_restore)
489 pci_restore_bars(dev);
490
1da177e4
LT		 491 return 0;
492}
493
f165b10f 494int (*platform_pci_choose_state)(struct pci_dev *dev, pm_message_t state);
0f64474b 495
1da177e4
LT		 496/**
497 * pci_choose_state - Choose the power state of a PCI device
498 * @dev: PCI device to be suspended
499 * @state: target sleep state for the whole system. This is the value
500 * that is passed to suspend() function.
501 *
502 * Returns PCI power state suitable for given device and given system
503 * message.
504 */
505
506pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
507{
0f64474b
DSL		 508 int ret;
509
1da177e4
LT		 510 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
511 return PCI_D0;
512
0f64474b
DSL		 513 if (platform_pci_choose_state) {
514 ret = platform_pci_choose_state(dev, state);
515 if (ret >= 0)
ca078bae 516 state.event = ret;
0f64474b 517 }
ca078bae
PM		 518
519 switch (state.event) {
520 case PM_EVENT_ON:
521 return PCI_D0;
522 case PM_EVENT_FREEZE:
b887d2e6
DB		 523 case PM_EVENT_PRETHAW:
524 /* REVISIT both freeze and pre-thaw "should" use D0 */
ca078bae
PM		 525 case PM_EVENT_SUSPEND:
526 return PCI_D3hot;
1da177e4 527 default:
b887d2e6 528 printk("Unrecognized suspend event %d\n", state.event);
1da177e4
LT		 529 BUG();
530 }
531 return PCI_D0;
532}
533
534EXPORT_SYMBOL(pci_choose_state);
535
b56a5a23
MT		 536static int pci_save_pcie_state(struct pci_dev *dev)
537{
538 int pos, i = 0;
539 struct pci_cap_saved_state *save_state;
540 u16 *cap;
541
542 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
543 if (pos <= 0)
544 return 0;
545
546 save_state = kzalloc(sizeof(*save_state) + sizeof(u16) * 4, GFP_KERNEL);
547 if (!save_state) {
548 dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n");
549 return -ENOMEM;
550 }
551 cap = (u16 *)&save_state->data[0];
552
553 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
554 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
555 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
556 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
557 pci_add_saved_cap(dev, save_state);
558 return 0;
559}
560
561static void pci_restore_pcie_state(struct pci_dev *dev)
562{
563 int i = 0, pos;
564 struct pci_cap_saved_state *save_state;
565 u16 *cap;
566
567 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
568 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
569 if (!save_state || pos <= 0)
570 return;
571 cap = (u16 *)&save_state->data[0];
572
573 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
574 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
575 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
576 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
577 pci_remove_saved_cap(save_state);
578 kfree(save_state);
579}
580
cc692a5f
SH		 581
582static int pci_save_pcix_state(struct pci_dev *dev)
583{
584 int pos, i = 0;
585 struct pci_cap_saved_state *save_state;
586 u16 *cap;
587
588 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
589 if (pos <= 0)
590 return 0;
591
592 save_state = kzalloc(sizeof(*save_state) + sizeof(u16), GFP_KERNEL);
593 if (!save_state) {
594 dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n");
595 return -ENOMEM;
596 }
597 cap = (u16 *)&save_state->data[0];
598
599 pci_read_config_word(dev, pos + PCI_X_CMD, &cap[i++]);
600 pci_add_saved_cap(dev, save_state);
601 return 0;
602}
603
604static void pci_restore_pcix_state(struct pci_dev *dev)
605{
606 int i = 0, pos;
607 struct pci_cap_saved_state *save_state;
608 u16 *cap;
609
610 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
611 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
612 if (!save_state || pos <= 0)
613 return;
614 cap = (u16 *)&save_state->data[0];
615
616 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
617 pci_remove_saved_cap(save_state);
618 kfree(save_state);
619}
620
621
1da177e4
LT		 622/**
623 * pci_save_state - save the PCI configuration space of a device before suspending
624 * @dev: - PCI device that we're dealing with
1da177e4
LT		 625 */
626int
627pci_save_state(struct pci_dev *dev)
628{
629 int i;
630 /* XXX: 100% dword access ok here? */
631 for (i = 0; i < 16; i++)
632 pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]);
41017f0c
SL		 633 if ((i = pci_save_msi_state(dev)) != 0)
634 return i;
635 if ((i = pci_save_msix_state(dev)) != 0)
636 return i;
b56a5a23
MT		 637 if ((i = pci_save_pcie_state(dev)) != 0)
638 return i;
cc692a5f
SH		 639 if ((i = pci_save_pcix_state(dev)) != 0)
640 return i;
1da177e4
LT		 641 return 0;
642}
643
644/**
645 * pci_restore_state - Restore the saved state of a PCI device
646 * @dev: - PCI device that we're dealing with
1da177e4
LT		 647 */
648int
649pci_restore_state(struct pci_dev *dev)
650{
651 int i;
04d9c1a1 652 int val;
1da177e4 653
b56a5a23
MT		 654 /* PCI Express register must be restored first */
655 pci_restore_pcie_state(dev);
656
8b8c8d28
YL		 657 /*
658 * The Base Address register should be programmed before the command
659 * register(s)
660 */
661 for (i = 15; i >= 0; i--) {
04d9c1a1
DJ		 662 pci_read_config_dword(dev, i * 4, &val);
663 if (val != dev->saved_config_space[i]) {
664 printk(KERN_DEBUG "PM: Writing back config space on "
665 "device %s at offset %x (was %x, writing %x)\n",
666 pci_name(dev), i,
667 val, (int)dev->saved_config_space[i]);
668 pci_write_config_dword(dev,i * 4,
669 dev->saved_config_space[i]);
670 }
671 }
cc692a5f 672 pci_restore_pcix_state(dev);
41017f0c
SL		 673 pci_restore_msi_state(dev);
674 pci_restore_msix_state(dev);
1da177e4
LT		 675 return 0;
676}
677
678/**
679 * pci_enable_device_bars - Initialize some of a device for use
680 * @dev: PCI device to be initialized
681 * @bars: bitmask of BAR's that must be configured
682 *
683 * Initialize device before it's used by a driver. Ask low-level code
684 * to enable selected I/O and memory resources. Wake up the device if it
685 * was suspended. Beware, this function can fail.
686 */
687
688int
689pci_enable_device_bars(struct pci_dev *dev, int bars)
690{
691 int err;
692
95a62965 693 err = pci_set_power_state(dev, PCI_D0);
11f3859b 694 if (err < 0 && err != -EIO)
95a62965
GKH		 695 return err;
696 err = pcibios_enable_device(dev, bars);
697 if (err < 0)
1da177e4
LT		 698 return err;
699 return 0;
700}
701
702/**
bae94d02 703 * __pci_enable_device - Initialize device before it's used by a driver.
1da177e4
LT		 704 * @dev: PCI device to be initialized
705 *
706 * Initialize device before it's used by a driver. Ask low-level code
707 * to enable I/O and memory. Wake up the device if it was suspended.
708 * Beware, this function can fail.
bae94d02
IPG		 709 *
710 * Note this function is a backend and is not supposed to be called by
711 * normal code, use pci_enable_device() instead.
1da177e4
LT		 712 */
713int
bae94d02 714__pci_enable_device(struct pci_dev *dev)
1da177e4 715{
a1e022b3
KA		 716 int err;
717
a1e022b3 718 err = pci_enable_device_bars(dev, (1 << PCI_NUM_RESOURCES) - 1);
b64c05e7 719 if (err)
1da177e4
LT		 720 return err;
721 pci_fixup_device(pci_fixup_enable, dev);
722 return 0;
723}
724
bae94d02
IPG		 725/**
726 * pci_enable_device - Initialize device before it's used by a driver.
727 * @dev: PCI device to be initialized
728 *
729 * Initialize device before it's used by a driver. Ask low-level code
730 * to enable I/O and memory. Wake up the device if it was suspended.
731 * Beware, this function can fail.
732 *
733 * Note we don't actually enable the device many times if we call
734 * this function repeatedly (we just increment the count).
735 */
736int pci_enable_device(struct pci_dev *dev)
737{
738 int result;
739 if (atomic_add_return(1, &dev->enable_cnt) > 1)
740 return 0; /* already enabled */
741 result = __pci_enable_device(dev);
742 if (result < 0)
743 atomic_dec(&dev->enable_cnt);
744 return result;
745}
746
1da177e4
LT		 747/**
748 * pcibios_disable_device - disable arch specific PCI resources for device dev
749 * @dev: the PCI device to disable
750 *
751 * Disables architecture specific PCI resources for the device. This
752 * is the default implementation. Architecture implementations can
753 * override this.
754 */
755void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
756
757/**
758 * pci_disable_device - Disable PCI device after use
759 * @dev: PCI device to be disabled
760 *
761 * Signal to the system that the PCI device is not in use by the system
762 * anymore. This only involves disabling PCI bus-mastering, if active.
bae94d02
IPG		 763 *
764 * Note we don't actually disable the device until all callers of
765 * pci_device_enable() have called pci_device_disable().
1da177e4
LT		 766 */
767void
768pci_disable_device(struct pci_dev *dev)
769{
770 u16 pci_command;
99dc804d 771
bae94d02
IPG		 772 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
773 return;
774
99dc804d
SL		 775 if (dev->msi_enabled)
776 disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI),
777 PCI_CAP_ID_MSI);
778 if (dev->msix_enabled)
779 disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI),
780 PCI_CAP_ID_MSIX);
781
1da177e4
LT		 782 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
783 if (pci_command & PCI_COMMAND_MASTER) {
784 pci_command &= ~PCI_COMMAND_MASTER;
785 pci_write_config_word(dev, PCI_COMMAND, pci_command);
786 }
ceb43744 787 dev->is_busmaster = 0;
1da177e4
LT		 788
789 pcibios_disable_device(dev);
790}
791
792/**
793 * pci_enable_wake - enable device to generate PME# when suspended
794 * @dev: - PCI device to operate on
795 * @state: - Current state of device.
796 * @enable: - Flag to enable or disable generation
797 *
798 * Set the bits in the device's PM Capabilities to generate PME# when
799 * the system is suspended.
800 *
801 * -EIO is returned if device doesn't have PM Capabilities.
802 * -EINVAL is returned if device supports it, but can't generate wake events.
803 * 0 if operation is successful.
804 *
805 */
806int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable)
807{
808 int pm;
809 u16 value;
810
811 /* find PCI PM capability in list */
812 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
813
814 /* If device doesn't support PM Capabilities, but request is to disable
815 * wake events, it's a nop; otherwise fail */
816 if (!pm)
817 return enable ? -EIO : 0;
818
819 /* Check device's ability to generate PME# */
820 pci_read_config_word(dev,pm+PCI_PM_PMC,&value);
821
822 value &= PCI_PM_CAP_PME_MASK;
823 value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
824
825 /* Check if it can generate PME# from requested state. */
826 if (!value || !(value & (1 << state)))
827 return enable ? -EINVAL : 0;
828
829 pci_read_config_word(dev, pm + PCI_PM_CTRL, &value);
830
831 /* Clear PME_Status by writing 1 to it and enable PME# */
832 value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
833
834 if (!enable)
835 value &= ~PCI_PM_CTRL_PME_ENABLE;
836
837 pci_write_config_word(dev, pm + PCI_PM_CTRL, value);
838
839 return 0;
840}
841
842int
843pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
844{
845 u8 pin;
846
514d207d 847 pin = dev->pin;
1da177e4
LT		 848 if (!pin)
849 return -1;
850 pin--;
851 while (dev->bus->self) {
852 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
853 dev = dev->bus->self;
854 }
855 *bridge = dev;
856 return pin;
857}
858
859/**
860 * pci_release_region - Release a PCI bar
861 * @pdev: PCI device whose resources were previously reserved by pci_request_region
862 * @bar: BAR to release
863 *
864 * Releases the PCI I/O and memory resources previously reserved by a
865 * successful call to pci_request_region. Call this function only
866 * after all use of the PCI regions has ceased.
867 */
868void pci_release_region(struct pci_dev *pdev, int bar)
869{
870 if (pci_resource_len(pdev, bar) == 0)
871 return;
872 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
873 release_region(pci_resource_start(pdev, bar),
874 pci_resource_len(pdev, bar));
875 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
876 release_mem_region(pci_resource_start(pdev, bar),
877 pci_resource_len(pdev, bar));
878}
879
880/**
881 * pci_request_region - Reserved PCI I/O and memory resource
882 * @pdev: PCI device whose resources are to be reserved
883 * @bar: BAR to be reserved
884 * @res_name: Name to be associated with resource.
885 *
886 * Mark the PCI region associated with PCI device @pdev BR @bar as
887 * being reserved by owner @res_name. Do not access any
888 * address inside the PCI regions unless this call returns
889 * successfully.
890 *
891 * Returns 0 on success, or %EBUSY on error. A warning
892 * message is also printed on failure.
893 */
3c990e92 894int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
1da177e4
LT		 895{
896 if (pci_resource_len(pdev, bar) == 0)
897 return 0;
898
899 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
900 if (!request_region(pci_resource_start(pdev, bar),
901 pci_resource_len(pdev, bar), res_name))
902 goto err_out;
903 }
904 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
905 if (!request_mem_region(pci_resource_start(pdev, bar),
906 pci_resource_len(pdev, bar), res_name))
907 goto err_out;
908 }
909
910 return 0;
911
912err_out:
1396a8c3
GKH		 913 printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%llx@%llx "
914 "for device %s\n",
1da177e4
LT		 915 pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem",
916 bar + 1, /* PCI BAR # */
1396a8c3
GKH		 917 (unsigned long long)pci_resource_len(pdev, bar),
918 (unsigned long long)pci_resource_start(pdev, bar),
1da177e4
LT		 919 pci_name(pdev));
920 return -EBUSY;
921}
922
923
924/**
925 * pci_release_regions - Release reserved PCI I/O and memory resources
926 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
927 *
928 * Releases all PCI I/O and memory resources previously reserved by a
929 * successful call to pci_request_regions. Call this function only
930 * after all use of the PCI regions has ceased.
931 */
932
933void pci_release_regions(struct pci_dev *pdev)
934{
935 int i;
936
937 for (i = 0; i < 6; i++)
938 pci_release_region(pdev, i);
939}
940
941/**
942 * pci_request_regions - Reserved PCI I/O and memory resources
943 * @pdev: PCI device whose resources are to be reserved
944 * @res_name: Name to be associated with resource.
945 *
946 * Mark all PCI regions associated with PCI device @pdev as
947 * being reserved by owner @res_name. Do not access any
948 * address inside the PCI regions unless this call returns
949 * successfully.
950 *
951 * Returns 0 on success, or %EBUSY on error. A warning
952 * message is also printed on failure.
953 */
3c990e92 954int pci_request_regions(struct pci_dev *pdev, const char *res_name)
1da177e4
LT		 955{
956 int i;
957
958 for (i = 0; i < 6; i++)
959 if(pci_request_region(pdev, i, res_name))
960 goto err_out;
961 return 0;
962
963err_out:
964 while(--i >= 0)
965 pci_release_region(pdev, i);
966
967 return -EBUSY;
968}
969
970/**
971 * pci_set_master - enables bus-mastering for device dev
972 * @dev: the PCI device to enable
973 *
974 * Enables bus-mastering on the device and calls pcibios_set_master()
975 * to do the needed arch specific settings.
976 */
977void
978pci_set_master(struct pci_dev *dev)
979{
980 u16 cmd;
981
982 pci_read_config_word(dev, PCI_COMMAND, &cmd);
983 if (! (cmd & PCI_COMMAND_MASTER)) {
984 pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev));
985 cmd |= PCI_COMMAND_MASTER;
986 pci_write_config_word(dev, PCI_COMMAND, cmd);
987 }
988 dev->is_busmaster = 1;
989 pcibios_set_master(dev);
990}
991
edb2d97e
MW		 992#ifdef PCI_DISABLE_MWI
993int pci_set_mwi(struct pci_dev *dev)
994{
995 return 0;
996}
997
998void pci_clear_mwi(struct pci_dev *dev)
999{
1000}
1001
1002#else
ebf5a248
MW		 1003
1004#ifndef PCI_CACHE_LINE_BYTES
1005#define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
1006#endif
1007
1da177e4 1008/* This can be overridden by arch code. */
ebf5a248
MW		 1009/* Don't forget this is measured in 32-bit words, not bytes */
1010u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4;
1da177e4
LT		 1011
1012/**
edb2d97e
MW		 1013 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
1014 * @dev: the PCI device for which MWI is to be enabled
1da177e4 1015 *
edb2d97e
MW		 1016 * Helper function for pci_set_mwi.
1017 * Originally copied from drivers/net/acenic.c.
1da177e4
LT		 1018 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
1019 *
1020 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1021 */
1022static int
edb2d97e 1023pci_set_cacheline_size(struct pci_dev *dev)
1da177e4
LT		 1024{
1025 u8 cacheline_size;
1026
1027 if (!pci_cache_line_size)
1028 return -EINVAL; /* The system doesn't support MWI. */
1029
1030 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
1031 equal to or multiple of the right value. */
1032 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1033 if (cacheline_size >= pci_cache_line_size &&
1034 (cacheline_size % pci_cache_line_size) == 0)
1035 return 0;
1036
1037 /* Write the correct value. */
1038 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
1039 /* Read it back. */
1040 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1041 if (cacheline_size == pci_cache_line_size)
1042 return 0;
1043
1044 printk(KERN_DEBUG "PCI: cache line size of %d is not supported "
1045 "by device %s\n", pci_cache_line_size << 2, pci_name(dev));
1046
1047 return -EINVAL;
1048}
1da177e4
LT		 1049
1050/**
1051 * pci_set_mwi - enables memory-write-invalidate PCI transaction
1052 * @dev: the PCI device for which MWI is enabled
1053 *
1054 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND,
1055 * and then calls @pcibios_set_mwi to do the needed arch specific
1056 * operations or a generic mwi-prep function.
1057 *
1058 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1059 */
1060int
1061pci_set_mwi(struct pci_dev *dev)
1062{
1063 int rc;
1064 u16 cmd;
1065
edb2d97e 1066 rc = pci_set_cacheline_size(dev);
1da177e4
LT		 1067 if (rc)
1068 return rc;
1069
1070 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1071 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
1072 pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n", pci_name(dev));
1073 cmd |= PCI_COMMAND_INVALIDATE;
1074 pci_write_config_word(dev, PCI_COMMAND, cmd);
1075 }
1076
1077 return 0;
1078}
1079
1080/**
1081 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
1082 * @dev: the PCI device to disable
1083 *
1084 * Disables PCI Memory-Write-Invalidate transaction on the device
1085 */
1086void
1087pci_clear_mwi(struct pci_dev *dev)
1088{
1089 u16 cmd;
1090
1091 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1092 if (cmd & PCI_COMMAND_INVALIDATE) {
1093 cmd &= ~PCI_COMMAND_INVALIDATE;
1094 pci_write_config_word(dev, PCI_COMMAND, cmd);
1095 }
1096}
edb2d97e 1097#endif /* ! PCI_DISABLE_MWI */
1da177e4 1098
a04ce0ff
BR		 1099/**
1100 * pci_intx - enables/disables PCI INTx for device dev
8f7020d3
RD		 1101 * @pdev: the PCI device to operate on
1102 * @enable: boolean: whether to enable or disable PCI INTx
a04ce0ff
BR		 1103 *
1104 * Enables/disables PCI INTx for device dev
1105 */
1106void
1107pci_intx(struct pci_dev *pdev, int enable)
1108{
1109 u16 pci_command, new;
1110
1111 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
1112
1113 if (enable) {
1114 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
1115 } else {
1116 new = pci_command | PCI_COMMAND_INTX_DISABLE;
1117 }
1118
1119 if (new != pci_command) {
2fd9d74b 1120 pci_write_config_word(pdev, PCI_COMMAND, new);
a04ce0ff
BR		 1121 }
1122}
1123
1da177e4
LT		 1124#ifndef HAVE_ARCH_PCI_SET_DMA_MASK
1125/*
1126 * These can be overridden by arch-specific implementations
1127 */
1128int
1129pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1130{
1131 if (!pci_dma_supported(dev, mask))
1132 return -EIO;
1133
1134 dev->dma_mask = mask;
1135
1136 return 0;
1137}
1138
1da177e4
LT		 1139int
1140pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1141{
1142 if (!pci_dma_supported(dev, mask))
1143 return -EIO;
1144
1145 dev->dev.coherent_dma_mask = mask;
1146
1147 return 0;
1148}
1149#endif
1150
1151static int __devinit pci_init(void)
1152{
1153 struct pci_dev *dev = NULL;
1154
1155 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1156 pci_fixup_device(pci_fixup_final, dev);
1157 }
1158 return 0;
1159}
1160
1161static int __devinit pci_setup(char *str)
1162{
1163 while (str) {
1164 char *k = strchr(str, ',');
1165 if (k)
1166 *k++ = 0;
1167 if (*str && (str = pcibios_setup(str)) && *str) {
309e57df
MW		 1168 if (!strcmp(str, "nomsi")) {
1169 pci_no_msi();
1170 } else {
1171 printk(KERN_ERR "PCI: Unknown option `%s'\n",
1172 str);
1173 }
1da177e4
LT		 1174 }
1175 str = k;
1176 }
0637a70a 1177 return 0;
1da177e4 1178}
0637a70a 1179early_param("pci", pci_setup);
1da177e4
LT		 1180
1181device_initcall(pci_init);
1da177e4
LT		 1182
1183#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
1184/* FIXME: Some boxes have multiple ISA bridges! */
1185struct pci_dev *isa_bridge;
1186EXPORT_SYMBOL(isa_bridge);
1187#endif
1188
064b53db 1189EXPORT_SYMBOL_GPL(pci_restore_bars);
1da177e4
LT		 1190EXPORT_SYMBOL(pci_enable_device_bars);
1191EXPORT_SYMBOL(pci_enable_device);
1192EXPORT_SYMBOL(pci_disable_device);
1da177e4
LT		 1193EXPORT_SYMBOL(pci_find_capability);
1194EXPORT_SYMBOL(pci_bus_find_capability);
1195EXPORT_SYMBOL(pci_release_regions);
1196EXPORT_SYMBOL(pci_request_regions);
1197EXPORT_SYMBOL(pci_release_region);
1198EXPORT_SYMBOL(pci_request_region);
1199EXPORT_SYMBOL(pci_set_master);
1200EXPORT_SYMBOL(pci_set_mwi);
1201EXPORT_SYMBOL(pci_clear_mwi);
a04ce0ff 1202EXPORT_SYMBOL_GPL(pci_intx);
1da177e4 1203EXPORT_SYMBOL(pci_set_dma_mask);
1da177e4
LT		 1204EXPORT_SYMBOL(pci_set_consistent_dma_mask);
1205EXPORT_SYMBOL(pci_assign_resource);
1206EXPORT_SYMBOL(pci_find_parent_resource);
1207
1208EXPORT_SYMBOL(pci_set_power_state);
1209EXPORT_SYMBOL(pci_save_state);
1210EXPORT_SYMBOL(pci_restore_state);
1211EXPORT_SYMBOL(pci_enable_wake);
1212
1213/* Quirk info */
1214
1215EXPORT_SYMBOL(isa_dma_bridge_buggy);
1216EXPORT_SYMBOL(pci_pci_problems);
kernel source for telekom puls (alcatel/mediatek)