Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * PCI Bus Services, see include/linux/pci.h for further explanation. |
3 | * | |
4 | * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, | |
5 | * David Mosberger-Tang | |
6 | * | |
7 | * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> | |
8 | */ | |
9 | ||
10 | #include <linux/kernel.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/pci.h> | |
075c1771 | 14 | #include <linux/pm.h> |
1da177e4 LT |
15 | #include <linux/module.h> |
16 | #include <linux/spinlock.h> | |
4e57b681 | 17 | #include <linux/string.h> |
229f5afd | 18 | #include <linux/log2.h> |
7d715a6c | 19 | #include <linux/pci-aspm.h> |
c300bd2f | 20 | #include <linux/pm_wakeup.h> |
8dd7f803 | 21 | #include <linux/interrupt.h> |
32a9a682 | 22 | #include <linux/device.h> |
b67ea761 | 23 | #include <linux/pm_runtime.h> |
32a9a682 | 24 | #include <asm/setup.h> |
bc56b9e0 | 25 | #include "pci.h" |
1da177e4 | 26 | |
00240c38 AS |
27 | const char *pci_power_names[] = { |
28 | "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown", | |
29 | }; | |
30 | EXPORT_SYMBOL_GPL(pci_power_names); | |
31 | ||
93177a74 RW |
32 | int isa_dma_bridge_buggy; |
33 | EXPORT_SYMBOL(isa_dma_bridge_buggy); | |
34 | ||
35 | int pci_pci_problems; | |
36 | EXPORT_SYMBOL(pci_pci_problems); | |
37 | ||
1ae861e6 RW |
38 | unsigned int pci_pm_d3_delay; |
39 | ||
40 | static void pci_dev_d3_sleep(struct pci_dev *dev) | |
41 | { | |
42 | unsigned int delay = dev->d3_delay; | |
43 | ||
44 | if (delay < pci_pm_d3_delay) | |
45 | delay = pci_pm_d3_delay; | |
46 | ||
47 | msleep(delay); | |
48 | } | |
1da177e4 | 49 | |
32a2eea7 JG |
50 | #ifdef CONFIG_PCI_DOMAINS |
51 | int pci_domains_supported = 1; | |
52 | #endif | |
53 | ||
4516a618 AN |
54 | #define DEFAULT_CARDBUS_IO_SIZE (256) |
55 | #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024) | |
56 | /* pci=cbmemsize=nnM,cbiosize=nn can override this */ | |
57 | unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; | |
58 | unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; | |
59 | ||
28760489 EB |
60 | #define DEFAULT_HOTPLUG_IO_SIZE (256) |
61 | #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024) | |
62 | /* pci=hpmemsize=nnM,hpiosize=nn can override this */ | |
63 | unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE; | |
64 | unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE; | |
65 | ||
ac1aa47b JB |
66 | /* |
67 | * The default CLS is used if arch didn't set CLS explicitly and not | |
68 | * all pci devices agree on the same value. Arch can override either | |
69 | * the dfl or actual value as it sees fit. Don't forget this is | |
70 | * measured in 32-bit words, not bytes. | |
71 | */ | |
98e724c7 | 72 | u8 pci_dfl_cache_line_size __devinitdata = L1_CACHE_BYTES >> 2; |
ac1aa47b JB |
73 | u8 pci_cache_line_size; |
74 | ||
1da177e4 LT |
75 | /** |
76 | * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children | |
77 | * @bus: pointer to PCI bus structure to search | |
78 | * | |
79 | * Given a PCI bus, returns the highest PCI bus number present in the set | |
80 | * including the given PCI bus and its list of child PCI buses. | |
81 | */ | |
96bde06a | 82 | unsigned char pci_bus_max_busnr(struct pci_bus* bus) |
1da177e4 LT |
83 | { |
84 | struct list_head *tmp; | |
85 | unsigned char max, n; | |
86 | ||
b82db5ce | 87 | max = bus->subordinate; |
1da177e4 LT |
88 | list_for_each(tmp, &bus->children) { |
89 | n = pci_bus_max_busnr(pci_bus_b(tmp)); | |
90 | if(n > max) | |
91 | max = n; | |
92 | } | |
93 | return max; | |
94 | } | |
b82db5ce | 95 | EXPORT_SYMBOL_GPL(pci_bus_max_busnr); |
1da177e4 | 96 | |
1684f5dd AM |
97 | #ifdef CONFIG_HAS_IOMEM |
98 | void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar) | |
99 | { | |
100 | /* | |
101 | * Make sure the BAR is actually a memory resource, not an IO resource | |
102 | */ | |
103 | if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { | |
104 | WARN_ON(1); | |
105 | return NULL; | |
106 | } | |
107 | return ioremap_nocache(pci_resource_start(pdev, bar), | |
108 | pci_resource_len(pdev, bar)); | |
109 | } | |
110 | EXPORT_SYMBOL_GPL(pci_ioremap_bar); | |
111 | #endif | |
112 | ||
b82db5ce | 113 | #if 0 |
1da177e4 LT |
114 | /** |
115 | * pci_max_busnr - returns maximum PCI bus number | |
116 | * | |
117 | * Returns the highest PCI bus number present in the system global list of | |
118 | * PCI buses. | |
119 | */ | |
120 | unsigned char __devinit | |
121 | pci_max_busnr(void) | |
122 | { | |
123 | struct pci_bus *bus = NULL; | |
124 | unsigned char max, n; | |
125 | ||
126 | max = 0; | |
127 | while ((bus = pci_find_next_bus(bus)) != NULL) { | |
128 | n = pci_bus_max_busnr(bus); | |
129 | if(n > max) | |
130 | max = n; | |
131 | } | |
132 | return max; | |
133 | } | |
134 | ||
54c762fe AB |
135 | #endif /* 0 */ |
136 | ||
687d5fe3 ME |
137 | #define PCI_FIND_CAP_TTL 48 |
138 | ||
139 | static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, | |
140 | u8 pos, int cap, int *ttl) | |
24a4e377 RD |
141 | { |
142 | u8 id; | |
24a4e377 | 143 | |
687d5fe3 | 144 | while ((*ttl)--) { |
24a4e377 RD |
145 | pci_bus_read_config_byte(bus, devfn, pos, &pos); |
146 | if (pos < 0x40) | |
147 | break; | |
148 | pos &= ~3; | |
149 | pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, | |
150 | &id); | |
151 | if (id == 0xff) | |
152 | break; | |
153 | if (id == cap) | |
154 | return pos; | |
155 | pos += PCI_CAP_LIST_NEXT; | |
156 | } | |
157 | return 0; | |
158 | } | |
159 | ||
687d5fe3 ME |
160 | static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, |
161 | u8 pos, int cap) | |
162 | { | |
163 | int ttl = PCI_FIND_CAP_TTL; | |
164 | ||
165 | return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); | |
166 | } | |
167 | ||
24a4e377 RD |
168 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) |
169 | { | |
170 | return __pci_find_next_cap(dev->bus, dev->devfn, | |
171 | pos + PCI_CAP_LIST_NEXT, cap); | |
172 | } | |
173 | EXPORT_SYMBOL_GPL(pci_find_next_capability); | |
174 | ||
d3bac118 ME |
175 | static int __pci_bus_find_cap_start(struct pci_bus *bus, |
176 | unsigned int devfn, u8 hdr_type) | |
1da177e4 LT |
177 | { |
178 | u16 status; | |
1da177e4 LT |
179 | |
180 | pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); | |
181 | if (!(status & PCI_STATUS_CAP_LIST)) | |
182 | return 0; | |
183 | ||
184 | switch (hdr_type) { | |
185 | case PCI_HEADER_TYPE_NORMAL: | |
186 | case PCI_HEADER_TYPE_BRIDGE: | |
d3bac118 | 187 | return PCI_CAPABILITY_LIST; |
1da177e4 | 188 | case PCI_HEADER_TYPE_CARDBUS: |
d3bac118 | 189 | return PCI_CB_CAPABILITY_LIST; |
1da177e4 LT |
190 | default: |
191 | return 0; | |
192 | } | |
d3bac118 ME |
193 | |
194 | return 0; | |
1da177e4 LT |
195 | } |
196 | ||
197 | /** | |
198 | * pci_find_capability - query for devices' capabilities | |
199 | * @dev: PCI device to query | |
200 | * @cap: capability code | |
201 | * | |
202 | * Tell if a device supports a given PCI capability. | |
203 | * Returns the address of the requested capability structure within the | |
204 | * device's PCI configuration space or 0 in case the device does not | |
205 | * support it. Possible values for @cap: | |
206 | * | |
207 | * %PCI_CAP_ID_PM Power Management | |
208 | * %PCI_CAP_ID_AGP Accelerated Graphics Port | |
209 | * %PCI_CAP_ID_VPD Vital Product Data | |
210 | * %PCI_CAP_ID_SLOTID Slot Identification | |
211 | * %PCI_CAP_ID_MSI Message Signalled Interrupts | |
212 | * %PCI_CAP_ID_CHSWP CompactPCI HotSwap | |
213 | * %PCI_CAP_ID_PCIX PCI-X | |
214 | * %PCI_CAP_ID_EXP PCI Express | |
215 | */ | |
216 | int pci_find_capability(struct pci_dev *dev, int cap) | |
217 | { | |
d3bac118 ME |
218 | int pos; |
219 | ||
220 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
221 | if (pos) | |
222 | pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); | |
223 | ||
224 | return pos; | |
1da177e4 LT |
225 | } |
226 | ||
227 | /** | |
228 | * pci_bus_find_capability - query for devices' capabilities | |
229 | * @bus: the PCI bus to query | |
230 | * @devfn: PCI device to query | |
231 | * @cap: capability code | |
232 | * | |
233 | * Like pci_find_capability() but works for pci devices that do not have a | |
234 | * pci_dev structure set up yet. | |
235 | * | |
236 | * Returns the address of the requested capability structure within the | |
237 | * device's PCI configuration space or 0 in case the device does not | |
238 | * support it. | |
239 | */ | |
240 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) | |
241 | { | |
d3bac118 | 242 | int pos; |
1da177e4 LT |
243 | u8 hdr_type; |
244 | ||
245 | pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); | |
246 | ||
d3bac118 ME |
247 | pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f); |
248 | if (pos) | |
249 | pos = __pci_find_next_cap(bus, devfn, pos, cap); | |
250 | ||
251 | return pos; | |
1da177e4 LT |
252 | } |
253 | ||
254 | /** | |
255 | * pci_find_ext_capability - Find an extended capability | |
256 | * @dev: PCI device to query | |
257 | * @cap: capability code | |
258 | * | |
259 | * Returns the address of the requested extended capability structure | |
260 | * within the device's PCI configuration space or 0 if the device does | |
261 | * not support it. Possible values for @cap: | |
262 | * | |
263 | * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting | |
264 | * %PCI_EXT_CAP_ID_VC Virtual Channel | |
265 | * %PCI_EXT_CAP_ID_DSN Device Serial Number | |
266 | * %PCI_EXT_CAP_ID_PWR Power Budgeting | |
267 | */ | |
268 | int pci_find_ext_capability(struct pci_dev *dev, int cap) | |
269 | { | |
270 | u32 header; | |
557848c3 ZY |
271 | int ttl; |
272 | int pos = PCI_CFG_SPACE_SIZE; | |
1da177e4 | 273 | |
557848c3 ZY |
274 | /* minimum 8 bytes per capability */ |
275 | ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; | |
276 | ||
277 | if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) | |
1da177e4 LT |
278 | return 0; |
279 | ||
280 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
281 | return 0; | |
282 | ||
283 | /* | |
284 | * If we have no capabilities, this is indicated by cap ID, | |
285 | * cap version and next pointer all being 0. | |
286 | */ | |
287 | if (header == 0) | |
288 | return 0; | |
289 | ||
290 | while (ttl-- > 0) { | |
291 | if (PCI_EXT_CAP_ID(header) == cap) | |
292 | return pos; | |
293 | ||
294 | pos = PCI_EXT_CAP_NEXT(header); | |
557848c3 | 295 | if (pos < PCI_CFG_SPACE_SIZE) |
1da177e4 LT |
296 | break; |
297 | ||
298 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
299 | break; | |
300 | } | |
301 | ||
302 | return 0; | |
303 | } | |
3a720d72 | 304 | EXPORT_SYMBOL_GPL(pci_find_ext_capability); |
1da177e4 | 305 | |
cf4c43dd JB |
306 | /** |
307 | * pci_bus_find_ext_capability - find an extended capability | |
308 | * @bus: the PCI bus to query | |
309 | * @devfn: PCI device to query | |
310 | * @cap: capability code | |
311 | * | |
312 | * Like pci_find_ext_capability() but works for pci devices that do not have a | |
313 | * pci_dev structure set up yet. | |
314 | * | |
315 | * Returns the address of the requested capability structure within the | |
316 | * device's PCI configuration space or 0 in case the device does not | |
317 | * support it. | |
318 | */ | |
319 | int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn, | |
320 | int cap) | |
321 | { | |
322 | u32 header; | |
323 | int ttl; | |
324 | int pos = PCI_CFG_SPACE_SIZE; | |
325 | ||
326 | /* minimum 8 bytes per capability */ | |
327 | ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; | |
328 | ||
329 | if (!pci_bus_read_config_dword(bus, devfn, pos, &header)) | |
330 | return 0; | |
331 | if (header == 0xffffffff || header == 0) | |
332 | return 0; | |
333 | ||
334 | while (ttl-- > 0) { | |
335 | if (PCI_EXT_CAP_ID(header) == cap) | |
336 | return pos; | |
337 | ||
338 | pos = PCI_EXT_CAP_NEXT(header); | |
339 | if (pos < PCI_CFG_SPACE_SIZE) | |
340 | break; | |
341 | ||
342 | if (!pci_bus_read_config_dword(bus, devfn, pos, &header)) | |
343 | break; | |
344 | } | |
345 | ||
346 | return 0; | |
347 | } | |
348 | ||
687d5fe3 ME |
349 | static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) |
350 | { | |
351 | int rc, ttl = PCI_FIND_CAP_TTL; | |
352 | u8 cap, mask; | |
353 | ||
354 | if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) | |
355 | mask = HT_3BIT_CAP_MASK; | |
356 | else | |
357 | mask = HT_5BIT_CAP_MASK; | |
358 | ||
359 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, | |
360 | PCI_CAP_ID_HT, &ttl); | |
361 | while (pos) { | |
362 | rc = pci_read_config_byte(dev, pos + 3, &cap); | |
363 | if (rc != PCIBIOS_SUCCESSFUL) | |
364 | return 0; | |
365 | ||
366 | if ((cap & mask) == ht_cap) | |
367 | return pos; | |
368 | ||
47a4d5be BG |
369 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, |
370 | pos + PCI_CAP_LIST_NEXT, | |
687d5fe3 ME |
371 | PCI_CAP_ID_HT, &ttl); |
372 | } | |
373 | ||
374 | return 0; | |
375 | } | |
376 | /** | |
377 | * pci_find_next_ht_capability - query a device's Hypertransport capabilities | |
378 | * @dev: PCI device to query | |
379 | * @pos: Position from which to continue searching | |
380 | * @ht_cap: Hypertransport capability code | |
381 | * | |
382 | * To be used in conjunction with pci_find_ht_capability() to search for | |
383 | * all capabilities matching @ht_cap. @pos should always be a value returned | |
384 | * from pci_find_ht_capability(). | |
385 | * | |
386 | * NB. To be 100% safe against broken PCI devices, the caller should take | |
387 | * steps to avoid an infinite loop. | |
388 | */ | |
389 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap) | |
390 | { | |
391 | return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); | |
392 | } | |
393 | EXPORT_SYMBOL_GPL(pci_find_next_ht_capability); | |
394 | ||
395 | /** | |
396 | * pci_find_ht_capability - query a device's Hypertransport capabilities | |
397 | * @dev: PCI device to query | |
398 | * @ht_cap: Hypertransport capability code | |
399 | * | |
400 | * Tell if a device supports a given Hypertransport capability. | |
401 | * Returns an address within the device's PCI configuration space | |
402 | * or 0 in case the device does not support the request capability. | |
403 | * The address points to the PCI capability, of type PCI_CAP_ID_HT, | |
404 | * which has a Hypertransport capability matching @ht_cap. | |
405 | */ | |
406 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap) | |
407 | { | |
408 | int pos; | |
409 | ||
410 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
411 | if (pos) | |
412 | pos = __pci_find_next_ht_cap(dev, pos, ht_cap); | |
413 | ||
414 | return pos; | |
415 | } | |
416 | EXPORT_SYMBOL_GPL(pci_find_ht_capability); | |
417 | ||
1da177e4 LT |
418 | /** |
419 | * pci_find_parent_resource - return resource region of parent bus of given region | |
420 | * @dev: PCI device structure contains resources to be searched | |
421 | * @res: child resource record for which parent is sought | |
422 | * | |
423 | * For given resource region of given device, return the resource | |
424 | * region of parent bus the given region is contained in or where | |
425 | * it should be allocated from. | |
426 | */ | |
427 | struct resource * | |
428 | pci_find_parent_resource(const struct pci_dev *dev, struct resource *res) | |
429 | { | |
430 | const struct pci_bus *bus = dev->bus; | |
431 | int i; | |
89a74ecc | 432 | struct resource *best = NULL, *r; |
1da177e4 | 433 | |
89a74ecc | 434 | pci_bus_for_each_resource(bus, r, i) { |
1da177e4 LT |
435 | if (!r) |
436 | continue; | |
437 | if (res->start && !(res->start >= r->start && res->end <= r->end)) | |
438 | continue; /* Not contained */ | |
439 | if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM)) | |
440 | continue; /* Wrong type */ | |
441 | if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) | |
442 | return r; /* Exact match */ | |
8c8def26 LT |
443 | /* We can't insert a non-prefetch resource inside a prefetchable parent .. */ |
444 | if (r->flags & IORESOURCE_PREFETCH) | |
445 | continue; | |
446 | /* .. but we can put a prefetchable resource inside a non-prefetchable one */ | |
447 | if (!best) | |
448 | best = r; | |
1da177e4 LT |
449 | } |
450 | return best; | |
451 | } | |
452 | ||
064b53db JL |
453 | /** |
454 | * pci_restore_bars - restore a devices BAR values (e.g. after wake-up) | |
455 | * @dev: PCI device to have its BARs restored | |
456 | * | |
457 | * Restore the BAR values for a given device, so as to make it | |
458 | * accessible by its driver. | |
459 | */ | |
ad668599 | 460 | static void |
064b53db JL |
461 | pci_restore_bars(struct pci_dev *dev) |
462 | { | |
bc5f5a82 | 463 | int i; |
064b53db | 464 | |
bc5f5a82 | 465 | for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) |
14add80b | 466 | pci_update_resource(dev, i); |
064b53db JL |
467 | } |
468 | ||
961d9120 RW |
469 | static struct pci_platform_pm_ops *pci_platform_pm; |
470 | ||
471 | int pci_set_platform_pm(struct pci_platform_pm_ops *ops) | |
472 | { | |
eb9d0fe4 RW |
473 | if (!ops->is_manageable || !ops->set_state || !ops->choose_state |
474 | || !ops->sleep_wake || !ops->can_wakeup) | |
961d9120 RW |
475 | return -EINVAL; |
476 | pci_platform_pm = ops; | |
477 | return 0; | |
478 | } | |
479 | ||
480 | static inline bool platform_pci_power_manageable(struct pci_dev *dev) | |
481 | { | |
482 | return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false; | |
483 | } | |
484 | ||
485 | static inline int platform_pci_set_power_state(struct pci_dev *dev, | |
486 | pci_power_t t) | |
487 | { | |
488 | return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS; | |
489 | } | |
490 | ||
491 | static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev) | |
492 | { | |
493 | return pci_platform_pm ? | |
494 | pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR; | |
495 | } | |
8f7020d3 | 496 | |
eb9d0fe4 RW |
497 | static inline bool platform_pci_can_wakeup(struct pci_dev *dev) |
498 | { | |
499 | return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false; | |
500 | } | |
501 | ||
502 | static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable) | |
503 | { | |
504 | return pci_platform_pm ? | |
505 | pci_platform_pm->sleep_wake(dev, enable) : -ENODEV; | |
506 | } | |
507 | ||
b67ea761 RW |
508 | static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable) |
509 | { | |
510 | return pci_platform_pm ? | |
511 | pci_platform_pm->run_wake(dev, enable) : -ENODEV; | |
512 | } | |
513 | ||
1da177e4 | 514 | /** |
44e4e66e RW |
515 | * pci_raw_set_power_state - Use PCI PM registers to set the power state of |
516 | * given PCI device | |
517 | * @dev: PCI device to handle. | |
44e4e66e | 518 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. |
1da177e4 | 519 | * |
44e4e66e RW |
520 | * RETURN VALUE: |
521 | * -EINVAL if the requested state is invalid. | |
522 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
523 | * wrong version, or device doesn't support the requested state. | |
524 | * 0 if device already is in the requested state. | |
525 | * 0 if device's power state has been successfully changed. | |
1da177e4 | 526 | */ |
f00a20ef | 527 | static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) |
1da177e4 | 528 | { |
337001b6 | 529 | u16 pmcsr; |
44e4e66e | 530 | bool need_restore = false; |
1da177e4 | 531 | |
4a865905 RW |
532 | /* Check if we're already there */ |
533 | if (dev->current_state == state) | |
534 | return 0; | |
535 | ||
337001b6 | 536 | if (!dev->pm_cap) |
cca03dec AL |
537 | return -EIO; |
538 | ||
44e4e66e RW |
539 | if (state < PCI_D0 || state > PCI_D3hot) |
540 | return -EINVAL; | |
541 | ||
1da177e4 LT |
542 | /* Validate current state: |
543 | * Can enter D0 from any state, but if we can only go deeper | |
544 | * to sleep if we're already in a low power state | |
545 | */ | |
4a865905 | 546 | if (state != PCI_D0 && dev->current_state <= PCI_D3cold |
44e4e66e | 547 | && dev->current_state > state) { |
80ccba11 BH |
548 | dev_err(&dev->dev, "invalid power transition " |
549 | "(from state %d to %d)\n", dev->current_state, state); | |
1da177e4 | 550 | return -EINVAL; |
44e4e66e | 551 | } |
1da177e4 | 552 | |
1da177e4 | 553 | /* check if this device supports the desired state */ |
337001b6 RW |
554 | if ((state == PCI_D1 && !dev->d1_support) |
555 | || (state == PCI_D2 && !dev->d2_support)) | |
3fe9d19f | 556 | return -EIO; |
1da177e4 | 557 | |
337001b6 | 558 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
064b53db | 559 | |
32a36585 | 560 | /* If we're (effectively) in D3, force entire word to 0. |
1da177e4 LT |
561 | * This doesn't affect PME_Status, disables PME_En, and |
562 | * sets PowerState to 0. | |
563 | */ | |
32a36585 | 564 | switch (dev->current_state) { |
d3535fbb JL |
565 | case PCI_D0: |
566 | case PCI_D1: | |
567 | case PCI_D2: | |
568 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
569 | pmcsr |= state; | |
570 | break; | |
f62795f1 RW |
571 | case PCI_D3hot: |
572 | case PCI_D3cold: | |
32a36585 JL |
573 | case PCI_UNKNOWN: /* Boot-up */ |
574 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot | |
f00a20ef | 575 | && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) |
44e4e66e | 576 | need_restore = true; |
32a36585 | 577 | /* Fall-through: force to D0 */ |
32a36585 | 578 | default: |
d3535fbb | 579 | pmcsr = 0; |
32a36585 | 580 | break; |
1da177e4 LT |
581 | } |
582 | ||
583 | /* enter specified state */ | |
337001b6 | 584 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
1da177e4 LT |
585 | |
586 | /* Mandatory power management transition delays */ | |
587 | /* see PCI PM 1.1 5.6.1 table 18 */ | |
588 | if (state == PCI_D3hot || dev->current_state == PCI_D3hot) | |
1ae861e6 | 589 | pci_dev_d3_sleep(dev); |
1da177e4 | 590 | else if (state == PCI_D2 || dev->current_state == PCI_D2) |
aa8c6c93 | 591 | udelay(PCI_PM_D2_DELAY); |
1da177e4 | 592 | |
e13cdbd7 RW |
593 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
594 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); | |
595 | if (dev->current_state != state && printk_ratelimit()) | |
596 | dev_info(&dev->dev, "Refused to change power state, " | |
597 | "currently in D%d\n", dev->current_state); | |
064b53db JL |
598 | |
599 | /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT | |
600 | * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning | |
601 | * from D3hot to D0 _may_ perform an internal reset, thereby | |
602 | * going to "D0 Uninitialized" rather than "D0 Initialized". | |
603 | * For example, at least some versions of the 3c905B and the | |
604 | * 3c556B exhibit this behaviour. | |
605 | * | |
606 | * At least some laptop BIOSen (e.g. the Thinkpad T21) leave | |
607 | * devices in a D3hot state at boot. Consequently, we need to | |
608 | * restore at least the BARs so that the device will be | |
609 | * accessible to its driver. | |
610 | */ | |
611 | if (need_restore) | |
612 | pci_restore_bars(dev); | |
613 | ||
f00a20ef | 614 | if (dev->bus->self) |
7d715a6c SL |
615 | pcie_aspm_pm_state_change(dev->bus->self); |
616 | ||
1da177e4 LT |
617 | return 0; |
618 | } | |
619 | ||
44e4e66e RW |
620 | /** |
621 | * pci_update_current_state - Read PCI power state of given device from its | |
622 | * PCI PM registers and cache it | |
623 | * @dev: PCI device to handle. | |
f06fc0b6 | 624 | * @state: State to cache in case the device doesn't have the PM capability |
44e4e66e | 625 | */ |
73410429 | 626 | void pci_update_current_state(struct pci_dev *dev, pci_power_t state) |
44e4e66e | 627 | { |
337001b6 | 628 | if (dev->pm_cap) { |
44e4e66e RW |
629 | u16 pmcsr; |
630 | ||
337001b6 | 631 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
44e4e66e | 632 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); |
f06fc0b6 RW |
633 | } else { |
634 | dev->current_state = state; | |
44e4e66e RW |
635 | } |
636 | } | |
637 | ||
0e5dd46b RW |
638 | /** |
639 | * pci_platform_power_transition - Use platform to change device power state | |
640 | * @dev: PCI device to handle. | |
641 | * @state: State to put the device into. | |
642 | */ | |
643 | static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state) | |
644 | { | |
645 | int error; | |
646 | ||
647 | if (platform_pci_power_manageable(dev)) { | |
648 | error = platform_pci_set_power_state(dev, state); | |
649 | if (!error) | |
650 | pci_update_current_state(dev, state); | |
651 | } else { | |
652 | error = -ENODEV; | |
653 | /* Fall back to PCI_D0 if native PM is not supported */ | |
b3bad72e RW |
654 | if (!dev->pm_cap) |
655 | dev->current_state = PCI_D0; | |
0e5dd46b RW |
656 | } |
657 | ||
658 | return error; | |
659 | } | |
660 | ||
661 | /** | |
662 | * __pci_start_power_transition - Start power transition of a PCI device | |
663 | * @dev: PCI device to handle. | |
664 | * @state: State to put the device into. | |
665 | */ | |
666 | static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state) | |
667 | { | |
668 | if (state == PCI_D0) | |
669 | pci_platform_power_transition(dev, PCI_D0); | |
670 | } | |
671 | ||
672 | /** | |
673 | * __pci_complete_power_transition - Complete power transition of a PCI device | |
674 | * @dev: PCI device to handle. | |
675 | * @state: State to put the device into. | |
676 | * | |
677 | * This function should not be called directly by device drivers. | |
678 | */ | |
679 | int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state) | |
680 | { | |
681 | return state > PCI_D0 ? | |
682 | pci_platform_power_transition(dev, state) : -EINVAL; | |
683 | } | |
684 | EXPORT_SYMBOL_GPL(__pci_complete_power_transition); | |
685 | ||
44e4e66e RW |
686 | /** |
687 | * pci_set_power_state - Set the power state of a PCI device | |
688 | * @dev: PCI device to handle. | |
689 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. | |
690 | * | |
877d0310 | 691 | * Transition a device to a new power state, using the platform firmware and/or |
44e4e66e RW |
692 | * the device's PCI PM registers. |
693 | * | |
694 | * RETURN VALUE: | |
695 | * -EINVAL if the requested state is invalid. | |
696 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
697 | * wrong version, or device doesn't support the requested state. | |
698 | * 0 if device already is in the requested state. | |
699 | * 0 if device's power state has been successfully changed. | |
700 | */ | |
701 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state) | |
702 | { | |
337001b6 | 703 | int error; |
44e4e66e RW |
704 | |
705 | /* bound the state we're entering */ | |
706 | if (state > PCI_D3hot) | |
707 | state = PCI_D3hot; | |
708 | else if (state < PCI_D0) | |
709 | state = PCI_D0; | |
710 | else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) | |
711 | /* | |
712 | * If the device or the parent bridge do not support PCI PM, | |
713 | * ignore the request if we're doing anything other than putting | |
714 | * it into D0 (which would only happen on boot). | |
715 | */ | |
716 | return 0; | |
717 | ||
4a865905 RW |
718 | /* Check if we're already there */ |
719 | if (dev->current_state == state) | |
720 | return 0; | |
721 | ||
0e5dd46b RW |
722 | __pci_start_power_transition(dev, state); |
723 | ||
979b1791 AC |
724 | /* This device is quirked not to be put into D3, so |
725 | don't put it in D3 */ | |
726 | if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) | |
727 | return 0; | |
44e4e66e | 728 | |
f00a20ef | 729 | error = pci_raw_set_power_state(dev, state); |
44e4e66e | 730 | |
0e5dd46b RW |
731 | if (!__pci_complete_power_transition(dev, state)) |
732 | error = 0; | |
44e4e66e RW |
733 | |
734 | return error; | |
735 | } | |
736 | ||
1da177e4 LT |
737 | /** |
738 | * pci_choose_state - Choose the power state of a PCI device | |
739 | * @dev: PCI device to be suspended | |
740 | * @state: target sleep state for the whole system. This is the value | |
741 | * that is passed to suspend() function. | |
742 | * | |
743 | * Returns PCI power state suitable for given device and given system | |
744 | * message. | |
745 | */ | |
746 | ||
747 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) | |
748 | { | |
ab826ca4 | 749 | pci_power_t ret; |
0f64474b | 750 | |
1da177e4 LT |
751 | if (!pci_find_capability(dev, PCI_CAP_ID_PM)) |
752 | return PCI_D0; | |
753 | ||
961d9120 RW |
754 | ret = platform_pci_choose_state(dev); |
755 | if (ret != PCI_POWER_ERROR) | |
756 | return ret; | |
ca078bae PM |
757 | |
758 | switch (state.event) { | |
759 | case PM_EVENT_ON: | |
760 | return PCI_D0; | |
761 | case PM_EVENT_FREEZE: | |
b887d2e6 DB |
762 | case PM_EVENT_PRETHAW: |
763 | /* REVISIT both freeze and pre-thaw "should" use D0 */ | |
ca078bae | 764 | case PM_EVENT_SUSPEND: |
3a2d5b70 | 765 | case PM_EVENT_HIBERNATE: |
ca078bae | 766 | return PCI_D3hot; |
1da177e4 | 767 | default: |
80ccba11 BH |
768 | dev_info(&dev->dev, "unrecognized suspend event %d\n", |
769 | state.event); | |
1da177e4 LT |
770 | BUG(); |
771 | } | |
772 | return PCI_D0; | |
773 | } | |
774 | ||
775 | EXPORT_SYMBOL(pci_choose_state); | |
776 | ||
89858517 YZ |
777 | #define PCI_EXP_SAVE_REGS 7 |
778 | ||
1b6b8ce2 YZ |
779 | #define pcie_cap_has_devctl(type, flags) 1 |
780 | #define pcie_cap_has_lnkctl(type, flags) \ | |
781 | ((flags & PCI_EXP_FLAGS_VERS) > 1 || \ | |
782 | (type == PCI_EXP_TYPE_ROOT_PORT || \ | |
783 | type == PCI_EXP_TYPE_ENDPOINT || \ | |
784 | type == PCI_EXP_TYPE_LEG_END)) | |
785 | #define pcie_cap_has_sltctl(type, flags) \ | |
786 | ((flags & PCI_EXP_FLAGS_VERS) > 1 || \ | |
787 | ((type == PCI_EXP_TYPE_ROOT_PORT) || \ | |
788 | (type == PCI_EXP_TYPE_DOWNSTREAM && \ | |
789 | (flags & PCI_EXP_FLAGS_SLOT)))) | |
790 | #define pcie_cap_has_rtctl(type, flags) \ | |
791 | ((flags & PCI_EXP_FLAGS_VERS) > 1 || \ | |
792 | (type == PCI_EXP_TYPE_ROOT_PORT || \ | |
793 | type == PCI_EXP_TYPE_RC_EC)) | |
794 | #define pcie_cap_has_devctl2(type, flags) \ | |
795 | ((flags & PCI_EXP_FLAGS_VERS) > 1) | |
796 | #define pcie_cap_has_lnkctl2(type, flags) \ | |
797 | ((flags & PCI_EXP_FLAGS_VERS) > 1) | |
798 | #define pcie_cap_has_sltctl2(type, flags) \ | |
799 | ((flags & PCI_EXP_FLAGS_VERS) > 1) | |
800 | ||
b56a5a23 MT |
801 | static int pci_save_pcie_state(struct pci_dev *dev) |
802 | { | |
803 | int pos, i = 0; | |
804 | struct pci_cap_saved_state *save_state; | |
805 | u16 *cap; | |
1b6b8ce2 | 806 | u16 flags; |
b56a5a23 | 807 | |
06a1cbaf KK |
808 | pos = pci_pcie_cap(dev); |
809 | if (!pos) | |
b56a5a23 MT |
810 | return 0; |
811 | ||
9f35575d | 812 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); |
b56a5a23 | 813 | if (!save_state) { |
e496b617 | 814 | dev_err(&dev->dev, "buffer not found in %s\n", __func__); |
b56a5a23 MT |
815 | return -ENOMEM; |
816 | } | |
817 | cap = (u16 *)&save_state->data[0]; | |
818 | ||
1b6b8ce2 YZ |
819 | pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags); |
820 | ||
821 | if (pcie_cap_has_devctl(dev->pcie_type, flags)) | |
822 | pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]); | |
823 | if (pcie_cap_has_lnkctl(dev->pcie_type, flags)) | |
824 | pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]); | |
825 | if (pcie_cap_has_sltctl(dev->pcie_type, flags)) | |
826 | pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]); | |
827 | if (pcie_cap_has_rtctl(dev->pcie_type, flags)) | |
828 | pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]); | |
829 | if (pcie_cap_has_devctl2(dev->pcie_type, flags)) | |
830 | pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]); | |
831 | if (pcie_cap_has_lnkctl2(dev->pcie_type, flags)) | |
832 | pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]); | |
833 | if (pcie_cap_has_sltctl2(dev->pcie_type, flags)) | |
834 | pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]); | |
63f4898a | 835 | |
b56a5a23 MT |
836 | return 0; |
837 | } | |
838 | ||
839 | static void pci_restore_pcie_state(struct pci_dev *dev) | |
840 | { | |
841 | int i = 0, pos; | |
842 | struct pci_cap_saved_state *save_state; | |
843 | u16 *cap; | |
1b6b8ce2 | 844 | u16 flags; |
b56a5a23 MT |
845 | |
846 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); | |
847 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
848 | if (!save_state || pos <= 0) | |
849 | return; | |
850 | cap = (u16 *)&save_state->data[0]; | |
851 | ||
1b6b8ce2 YZ |
852 | pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags); |
853 | ||
854 | if (pcie_cap_has_devctl(dev->pcie_type, flags)) | |
855 | pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]); | |
856 | if (pcie_cap_has_lnkctl(dev->pcie_type, flags)) | |
857 | pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]); | |
858 | if (pcie_cap_has_sltctl(dev->pcie_type, flags)) | |
859 | pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]); | |
860 | if (pcie_cap_has_rtctl(dev->pcie_type, flags)) | |
861 | pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]); | |
862 | if (pcie_cap_has_devctl2(dev->pcie_type, flags)) | |
863 | pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]); | |
864 | if (pcie_cap_has_lnkctl2(dev->pcie_type, flags)) | |
865 | pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]); | |
866 | if (pcie_cap_has_sltctl2(dev->pcie_type, flags)) | |
867 | pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]); | |
b56a5a23 MT |
868 | } |
869 | ||
cc692a5f SH |
870 | |
871 | static int pci_save_pcix_state(struct pci_dev *dev) | |
872 | { | |
63f4898a | 873 | int pos; |
cc692a5f | 874 | struct pci_cap_saved_state *save_state; |
cc692a5f SH |
875 | |
876 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
877 | if (pos <= 0) | |
878 | return 0; | |
879 | ||
f34303de | 880 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); |
cc692a5f | 881 | if (!save_state) { |
e496b617 | 882 | dev_err(&dev->dev, "buffer not found in %s\n", __func__); |
cc692a5f SH |
883 | return -ENOMEM; |
884 | } | |
cc692a5f | 885 | |
63f4898a RW |
886 | pci_read_config_word(dev, pos + PCI_X_CMD, (u16 *)save_state->data); |
887 | ||
cc692a5f SH |
888 | return 0; |
889 | } | |
890 | ||
891 | static void pci_restore_pcix_state(struct pci_dev *dev) | |
892 | { | |
893 | int i = 0, pos; | |
894 | struct pci_cap_saved_state *save_state; | |
895 | u16 *cap; | |
896 | ||
897 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); | |
898 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
899 | if (!save_state || pos <= 0) | |
900 | return; | |
901 | cap = (u16 *)&save_state->data[0]; | |
902 | ||
903 | pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); | |
cc692a5f SH |
904 | } |
905 | ||
906 | ||
1da177e4 LT |
907 | /** |
908 | * pci_save_state - save the PCI configuration space of a device before suspending | |
909 | * @dev: - PCI device that we're dealing with | |
1da177e4 LT |
910 | */ |
911 | int | |
912 | pci_save_state(struct pci_dev *dev) | |
913 | { | |
914 | int i; | |
915 | /* XXX: 100% dword access ok here? */ | |
916 | for (i = 0; i < 16; i++) | |
9e0b5b2c | 917 | pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]); |
aa8c6c93 | 918 | dev->state_saved = true; |
b56a5a23 MT |
919 | if ((i = pci_save_pcie_state(dev)) != 0) |
920 | return i; | |
cc692a5f SH |
921 | if ((i = pci_save_pcix_state(dev)) != 0) |
922 | return i; | |
1da177e4 LT |
923 | return 0; |
924 | } | |
925 | ||
926 | /** | |
927 | * pci_restore_state - Restore the saved state of a PCI device | |
928 | * @dev: - PCI device that we're dealing with | |
1da177e4 LT |
929 | */ |
930 | int | |
931 | pci_restore_state(struct pci_dev *dev) | |
932 | { | |
933 | int i; | |
b4482a4b | 934 | u32 val; |
1da177e4 | 935 | |
c82f63e4 AD |
936 | if (!dev->state_saved) |
937 | return 0; | |
4b77b0a2 | 938 | |
b56a5a23 MT |
939 | /* PCI Express register must be restored first */ |
940 | pci_restore_pcie_state(dev); | |
941 | ||
8b8c8d28 YL |
942 | /* |
943 | * The Base Address register should be programmed before the command | |
944 | * register(s) | |
945 | */ | |
946 | for (i = 15; i >= 0; i--) { | |
04d9c1a1 DJ |
947 | pci_read_config_dword(dev, i * 4, &val); |
948 | if (val != dev->saved_config_space[i]) { | |
80ccba11 BH |
949 | dev_printk(KERN_DEBUG, &dev->dev, "restoring config " |
950 | "space at offset %#x (was %#x, writing %#x)\n", | |
951 | i, val, (int)dev->saved_config_space[i]); | |
04d9c1a1 DJ |
952 | pci_write_config_dword(dev,i * 4, |
953 | dev->saved_config_space[i]); | |
954 | } | |
955 | } | |
cc692a5f | 956 | pci_restore_pcix_state(dev); |
41017f0c | 957 | pci_restore_msi_state(dev); |
8c5cdb6a | 958 | pci_restore_iov_state(dev); |
8fed4b65 | 959 | |
4b77b0a2 RW |
960 | dev->state_saved = false; |
961 | ||
1da177e4 LT |
962 | return 0; |
963 | } | |
964 | ||
38cc1302 HS |
965 | static int do_pci_enable_device(struct pci_dev *dev, int bars) |
966 | { | |
967 | int err; | |
968 | ||
969 | err = pci_set_power_state(dev, PCI_D0); | |
970 | if (err < 0 && err != -EIO) | |
971 | return err; | |
972 | err = pcibios_enable_device(dev, bars); | |
973 | if (err < 0) | |
974 | return err; | |
975 | pci_fixup_device(pci_fixup_enable, dev); | |
976 | ||
977 | return 0; | |
978 | } | |
979 | ||
980 | /** | |
0b62e13b | 981 | * pci_reenable_device - Resume abandoned device |
38cc1302 HS |
982 | * @dev: PCI device to be resumed |
983 | * | |
984 | * Note this function is a backend of pci_default_resume and is not supposed | |
985 | * to be called by normal code, write proper resume handler and use it instead. | |
986 | */ | |
0b62e13b | 987 | int pci_reenable_device(struct pci_dev *dev) |
38cc1302 | 988 | { |
296ccb08 | 989 | if (pci_is_enabled(dev)) |
38cc1302 HS |
990 | return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); |
991 | return 0; | |
992 | } | |
993 | ||
b718989d BH |
994 | static int __pci_enable_device_flags(struct pci_dev *dev, |
995 | resource_size_t flags) | |
1da177e4 LT |
996 | { |
997 | int err; | |
b718989d | 998 | int i, bars = 0; |
1da177e4 | 999 | |
9fb625c3 HS |
1000 | if (atomic_add_return(1, &dev->enable_cnt) > 1) |
1001 | return 0; /* already enabled */ | |
1002 | ||
b718989d BH |
1003 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) |
1004 | if (dev->resource[i].flags & flags) | |
1005 | bars |= (1 << i); | |
1006 | ||
38cc1302 | 1007 | err = do_pci_enable_device(dev, bars); |
95a62965 | 1008 | if (err < 0) |
38cc1302 | 1009 | atomic_dec(&dev->enable_cnt); |
9fb625c3 | 1010 | return err; |
1da177e4 LT |
1011 | } |
1012 | ||
b718989d BH |
1013 | /** |
1014 | * pci_enable_device_io - Initialize a device for use with IO space | |
1015 | * @dev: PCI device to be initialized | |
1016 | * | |
1017 | * Initialize device before it's used by a driver. Ask low-level code | |
1018 | * to enable I/O resources. Wake up the device if it was suspended. | |
1019 | * Beware, this function can fail. | |
1020 | */ | |
1021 | int pci_enable_device_io(struct pci_dev *dev) | |
1022 | { | |
1023 | return __pci_enable_device_flags(dev, IORESOURCE_IO); | |
1024 | } | |
1025 | ||
1026 | /** | |
1027 | * pci_enable_device_mem - Initialize a device for use with Memory space | |
1028 | * @dev: PCI device to be initialized | |
1029 | * | |
1030 | * Initialize device before it's used by a driver. Ask low-level code | |
1031 | * to enable Memory resources. Wake up the device if it was suspended. | |
1032 | * Beware, this function can fail. | |
1033 | */ | |
1034 | int pci_enable_device_mem(struct pci_dev *dev) | |
1035 | { | |
1036 | return __pci_enable_device_flags(dev, IORESOURCE_MEM); | |
1037 | } | |
1038 | ||
bae94d02 IPG |
1039 | /** |
1040 | * pci_enable_device - Initialize device before it's used by a driver. | |
1041 | * @dev: PCI device to be initialized | |
1042 | * | |
1043 | * Initialize device before it's used by a driver. Ask low-level code | |
1044 | * to enable I/O and memory. Wake up the device if it was suspended. | |
1045 | * Beware, this function can fail. | |
1046 | * | |
1047 | * Note we don't actually enable the device many times if we call | |
1048 | * this function repeatedly (we just increment the count). | |
1049 | */ | |
1050 | int pci_enable_device(struct pci_dev *dev) | |
1051 | { | |
b718989d | 1052 | return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); |
bae94d02 IPG |
1053 | } |
1054 | ||
9ac7849e TH |
1055 | /* |
1056 | * Managed PCI resources. This manages device on/off, intx/msi/msix | |
1057 | * on/off and BAR regions. pci_dev itself records msi/msix status, so | |
1058 | * there's no need to track it separately. pci_devres is initialized | |
1059 | * when a device is enabled using managed PCI device enable interface. | |
1060 | */ | |
1061 | struct pci_devres { | |
7f375f32 TH |
1062 | unsigned int enabled:1; |
1063 | unsigned int pinned:1; | |
9ac7849e TH |
1064 | unsigned int orig_intx:1; |
1065 | unsigned int restore_intx:1; | |
1066 | u32 region_mask; | |
1067 | }; | |
1068 | ||
1069 | static void pcim_release(struct device *gendev, void *res) | |
1070 | { | |
1071 | struct pci_dev *dev = container_of(gendev, struct pci_dev, dev); | |
1072 | struct pci_devres *this = res; | |
1073 | int i; | |
1074 | ||
1075 | if (dev->msi_enabled) | |
1076 | pci_disable_msi(dev); | |
1077 | if (dev->msix_enabled) | |
1078 | pci_disable_msix(dev); | |
1079 | ||
1080 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) | |
1081 | if (this->region_mask & (1 << i)) | |
1082 | pci_release_region(dev, i); | |
1083 | ||
1084 | if (this->restore_intx) | |
1085 | pci_intx(dev, this->orig_intx); | |
1086 | ||
7f375f32 | 1087 | if (this->enabled && !this->pinned) |
9ac7849e TH |
1088 | pci_disable_device(dev); |
1089 | } | |
1090 | ||
1091 | static struct pci_devres * get_pci_dr(struct pci_dev *pdev) | |
1092 | { | |
1093 | struct pci_devres *dr, *new_dr; | |
1094 | ||
1095 | dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
1096 | if (dr) | |
1097 | return dr; | |
1098 | ||
1099 | new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL); | |
1100 | if (!new_dr) | |
1101 | return NULL; | |
1102 | return devres_get(&pdev->dev, new_dr, NULL, NULL); | |
1103 | } | |
1104 | ||
1105 | static struct pci_devres * find_pci_dr(struct pci_dev *pdev) | |
1106 | { | |
1107 | if (pci_is_managed(pdev)) | |
1108 | return devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
1109 | return NULL; | |
1110 | } | |
1111 | ||
1112 | /** | |
1113 | * pcim_enable_device - Managed pci_enable_device() | |
1114 | * @pdev: PCI device to be initialized | |
1115 | * | |
1116 | * Managed pci_enable_device(). | |
1117 | */ | |
1118 | int pcim_enable_device(struct pci_dev *pdev) | |
1119 | { | |
1120 | struct pci_devres *dr; | |
1121 | int rc; | |
1122 | ||
1123 | dr = get_pci_dr(pdev); | |
1124 | if (unlikely(!dr)) | |
1125 | return -ENOMEM; | |
b95d58ea TH |
1126 | if (dr->enabled) |
1127 | return 0; | |
9ac7849e TH |
1128 | |
1129 | rc = pci_enable_device(pdev); | |
1130 | if (!rc) { | |
1131 | pdev->is_managed = 1; | |
7f375f32 | 1132 | dr->enabled = 1; |
9ac7849e TH |
1133 | } |
1134 | return rc; | |
1135 | } | |
1136 | ||
1137 | /** | |
1138 | * pcim_pin_device - Pin managed PCI device | |
1139 | * @pdev: PCI device to pin | |
1140 | * | |
1141 | * Pin managed PCI device @pdev. Pinned device won't be disabled on | |
1142 | * driver detach. @pdev must have been enabled with | |
1143 | * pcim_enable_device(). | |
1144 | */ | |
1145 | void pcim_pin_device(struct pci_dev *pdev) | |
1146 | { | |
1147 | struct pci_devres *dr; | |
1148 | ||
1149 | dr = find_pci_dr(pdev); | |
7f375f32 | 1150 | WARN_ON(!dr || !dr->enabled); |
9ac7849e | 1151 | if (dr) |
7f375f32 | 1152 | dr->pinned = 1; |
9ac7849e TH |
1153 | } |
1154 | ||
1da177e4 LT |
1155 | /** |
1156 | * pcibios_disable_device - disable arch specific PCI resources for device dev | |
1157 | * @dev: the PCI device to disable | |
1158 | * | |
1159 | * Disables architecture specific PCI resources for the device. This | |
1160 | * is the default implementation. Architecture implementations can | |
1161 | * override this. | |
1162 | */ | |
1163 | void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {} | |
1164 | ||
fa58d305 RW |
1165 | static void do_pci_disable_device(struct pci_dev *dev) |
1166 | { | |
1167 | u16 pci_command; | |
1168 | ||
1169 | pci_read_config_word(dev, PCI_COMMAND, &pci_command); | |
1170 | if (pci_command & PCI_COMMAND_MASTER) { | |
1171 | pci_command &= ~PCI_COMMAND_MASTER; | |
1172 | pci_write_config_word(dev, PCI_COMMAND, pci_command); | |
1173 | } | |
1174 | ||
1175 | pcibios_disable_device(dev); | |
1176 | } | |
1177 | ||
1178 | /** | |
1179 | * pci_disable_enabled_device - Disable device without updating enable_cnt | |
1180 | * @dev: PCI device to disable | |
1181 | * | |
1182 | * NOTE: This function is a backend of PCI power management routines and is | |
1183 | * not supposed to be called drivers. | |
1184 | */ | |
1185 | void pci_disable_enabled_device(struct pci_dev *dev) | |
1186 | { | |
296ccb08 | 1187 | if (pci_is_enabled(dev)) |
fa58d305 RW |
1188 | do_pci_disable_device(dev); |
1189 | } | |
1190 | ||
1da177e4 LT |
1191 | /** |
1192 | * pci_disable_device - Disable PCI device after use | |
1193 | * @dev: PCI device to be disabled | |
1194 | * | |
1195 | * Signal to the system that the PCI device is not in use by the system | |
1196 | * anymore. This only involves disabling PCI bus-mastering, if active. | |
bae94d02 IPG |
1197 | * |
1198 | * Note we don't actually disable the device until all callers of | |
1199 | * pci_device_enable() have called pci_device_disable(). | |
1da177e4 LT |
1200 | */ |
1201 | void | |
1202 | pci_disable_device(struct pci_dev *dev) | |
1203 | { | |
9ac7849e | 1204 | struct pci_devres *dr; |
99dc804d | 1205 | |
9ac7849e TH |
1206 | dr = find_pci_dr(dev); |
1207 | if (dr) | |
7f375f32 | 1208 | dr->enabled = 0; |
9ac7849e | 1209 | |
bae94d02 IPG |
1210 | if (atomic_sub_return(1, &dev->enable_cnt) != 0) |
1211 | return; | |
1212 | ||
fa58d305 | 1213 | do_pci_disable_device(dev); |
1da177e4 | 1214 | |
fa58d305 | 1215 | dev->is_busmaster = 0; |
1da177e4 LT |
1216 | } |
1217 | ||
f7bdd12d BK |
1218 | /** |
1219 | * pcibios_set_pcie_reset_state - set reset state for device dev | |
45e829ea | 1220 | * @dev: the PCIe device reset |
f7bdd12d BK |
1221 | * @state: Reset state to enter into |
1222 | * | |
1223 | * | |
45e829ea | 1224 | * Sets the PCIe reset state for the device. This is the default |
f7bdd12d BK |
1225 | * implementation. Architecture implementations can override this. |
1226 | */ | |
1227 | int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev, | |
1228 | enum pcie_reset_state state) | |
1229 | { | |
1230 | return -EINVAL; | |
1231 | } | |
1232 | ||
1233 | /** | |
1234 | * pci_set_pcie_reset_state - set reset state for device dev | |
45e829ea | 1235 | * @dev: the PCIe device reset |
f7bdd12d BK |
1236 | * @state: Reset state to enter into |
1237 | * | |
1238 | * | |
1239 | * Sets the PCI reset state for the device. | |
1240 | */ | |
1241 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) | |
1242 | { | |
1243 | return pcibios_set_pcie_reset_state(dev, state); | |
1244 | } | |
1245 | ||
58ff4633 RW |
1246 | /** |
1247 | * pci_check_pme_status - Check if given device has generated PME. | |
1248 | * @dev: Device to check. | |
1249 | * | |
1250 | * Check the PME status of the device and if set, clear it and clear PME enable | |
1251 | * (if set). Return 'true' if PME status and PME enable were both set or | |
1252 | * 'false' otherwise. | |
1253 | */ | |
1254 | bool pci_check_pme_status(struct pci_dev *dev) | |
1255 | { | |
1256 | int pmcsr_pos; | |
1257 | u16 pmcsr; | |
1258 | bool ret = false; | |
1259 | ||
1260 | if (!dev->pm_cap) | |
1261 | return false; | |
1262 | ||
1263 | pmcsr_pos = dev->pm_cap + PCI_PM_CTRL; | |
1264 | pci_read_config_word(dev, pmcsr_pos, &pmcsr); | |
1265 | if (!(pmcsr & PCI_PM_CTRL_PME_STATUS)) | |
1266 | return false; | |
1267 | ||
1268 | /* Clear PME status. */ | |
1269 | pmcsr |= PCI_PM_CTRL_PME_STATUS; | |
1270 | if (pmcsr & PCI_PM_CTRL_PME_ENABLE) { | |
1271 | /* Disable PME to avoid interrupt flood. */ | |
1272 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
1273 | ret = true; | |
1274 | } | |
1275 | ||
1276 | pci_write_config_word(dev, pmcsr_pos, pmcsr); | |
1277 | ||
1278 | return ret; | |
1279 | } | |
1280 | ||
b67ea761 RW |
1281 | /** |
1282 | * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set. | |
1283 | * @dev: Device to handle. | |
1284 | * @ign: Ignored. | |
1285 | * | |
1286 | * Check if @dev has generated PME and queue a resume request for it in that | |
1287 | * case. | |
1288 | */ | |
1289 | static int pci_pme_wakeup(struct pci_dev *dev, void *ign) | |
1290 | { | |
1291 | if (pci_check_pme_status(dev)) | |
1292 | pm_request_resume(&dev->dev); | |
1293 | return 0; | |
1294 | } | |
1295 | ||
1296 | /** | |
1297 | * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary. | |
1298 | * @bus: Top bus of the subtree to walk. | |
1299 | */ | |
1300 | void pci_pme_wakeup_bus(struct pci_bus *bus) | |
1301 | { | |
1302 | if (bus) | |
1303 | pci_walk_bus(bus, pci_pme_wakeup, NULL); | |
1304 | } | |
1305 | ||
eb9d0fe4 RW |
1306 | /** |
1307 | * pci_pme_capable - check the capability of PCI device to generate PME# | |
1308 | * @dev: PCI device to handle. | |
eb9d0fe4 RW |
1309 | * @state: PCI state from which device will issue PME#. |
1310 | */ | |
e5899e1b | 1311 | bool pci_pme_capable(struct pci_dev *dev, pci_power_t state) |
eb9d0fe4 | 1312 | { |
337001b6 | 1313 | if (!dev->pm_cap) |
eb9d0fe4 RW |
1314 | return false; |
1315 | ||
337001b6 | 1316 | return !!(dev->pme_support & (1 << state)); |
eb9d0fe4 RW |
1317 | } |
1318 | ||
1319 | /** | |
1320 | * pci_pme_active - enable or disable PCI device's PME# function | |
1321 | * @dev: PCI device to handle. | |
eb9d0fe4 RW |
1322 | * @enable: 'true' to enable PME# generation; 'false' to disable it. |
1323 | * | |
1324 | * The caller must verify that the device is capable of generating PME# before | |
1325 | * calling this function with @enable equal to 'true'. | |
1326 | */ | |
5a6c9b60 | 1327 | void pci_pme_active(struct pci_dev *dev, bool enable) |
eb9d0fe4 RW |
1328 | { |
1329 | u16 pmcsr; | |
1330 | ||
337001b6 | 1331 | if (!dev->pm_cap) |
eb9d0fe4 RW |
1332 | return; |
1333 | ||
337001b6 | 1334 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
eb9d0fe4 RW |
1335 | /* Clear PME_Status by writing 1 to it and enable PME# */ |
1336 | pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; | |
1337 | if (!enable) | |
1338 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
1339 | ||
337001b6 | 1340 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
eb9d0fe4 | 1341 | |
10c3d71d | 1342 | dev_printk(KERN_DEBUG, &dev->dev, "PME# %s\n", |
eb9d0fe4 RW |
1343 | enable ? "enabled" : "disabled"); |
1344 | } | |
1345 | ||
1da177e4 | 1346 | /** |
6cbf8214 | 1347 | * __pci_enable_wake - enable PCI device as wakeup event source |
075c1771 DB |
1348 | * @dev: PCI device affected |
1349 | * @state: PCI state from which device will issue wakeup events | |
6cbf8214 | 1350 | * @runtime: True if the events are to be generated at run time |
075c1771 DB |
1351 | * @enable: True to enable event generation; false to disable |
1352 | * | |
1353 | * This enables the device as a wakeup event source, or disables it. | |
1354 | * When such events involves platform-specific hooks, those hooks are | |
1355 | * called automatically by this routine. | |
1356 | * | |
1357 | * Devices with legacy power management (no standard PCI PM capabilities) | |
eb9d0fe4 | 1358 | * always require such platform hooks. |
075c1771 | 1359 | * |
eb9d0fe4 RW |
1360 | * RETURN VALUE: |
1361 | * 0 is returned on success | |
1362 | * -EINVAL is returned if device is not supposed to wake up the system | |
1363 | * Error code depending on the platform is returned if both the platform and | |
1364 | * the native mechanism fail to enable the generation of wake-up events | |
1da177e4 | 1365 | */ |
6cbf8214 RW |
1366 | int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, |
1367 | bool runtime, bool enable) | |
1da177e4 | 1368 | { |
5bcc2fb4 | 1369 | int ret = 0; |
075c1771 | 1370 | |
6cbf8214 | 1371 | if (enable && !runtime && !device_may_wakeup(&dev->dev)) |
eb9d0fe4 | 1372 | return -EINVAL; |
1da177e4 | 1373 | |
e80bb09d RW |
1374 | /* Don't do the same thing twice in a row for one device. */ |
1375 | if (!!enable == !!dev->wakeup_prepared) | |
1376 | return 0; | |
1377 | ||
eb9d0fe4 RW |
1378 | /* |
1379 | * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don | |
1380 | * Anderson we should be doing PME# wake enable followed by ACPI wake | |
1381 | * enable. To disable wake-up we call the platform first, for symmetry. | |
075c1771 | 1382 | */ |
1da177e4 | 1383 | |
5bcc2fb4 RW |
1384 | if (enable) { |
1385 | int error; | |
1da177e4 | 1386 | |
5bcc2fb4 RW |
1387 | if (pci_pme_capable(dev, state)) |
1388 | pci_pme_active(dev, true); | |
1389 | else | |
1390 | ret = 1; | |
6cbf8214 RW |
1391 | error = runtime ? platform_pci_run_wake(dev, true) : |
1392 | platform_pci_sleep_wake(dev, true); | |
5bcc2fb4 RW |
1393 | if (ret) |
1394 | ret = error; | |
e80bb09d RW |
1395 | if (!ret) |
1396 | dev->wakeup_prepared = true; | |
5bcc2fb4 | 1397 | } else { |
6cbf8214 RW |
1398 | if (runtime) |
1399 | platform_pci_run_wake(dev, false); | |
1400 | else | |
1401 | platform_pci_sleep_wake(dev, false); | |
5bcc2fb4 | 1402 | pci_pme_active(dev, false); |
e80bb09d | 1403 | dev->wakeup_prepared = false; |
5bcc2fb4 | 1404 | } |
1da177e4 | 1405 | |
5bcc2fb4 | 1406 | return ret; |
eb9d0fe4 | 1407 | } |
6cbf8214 | 1408 | EXPORT_SYMBOL(__pci_enable_wake); |
1da177e4 | 1409 | |
0235c4fc RW |
1410 | /** |
1411 | * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold | |
1412 | * @dev: PCI device to prepare | |
1413 | * @enable: True to enable wake-up event generation; false to disable | |
1414 | * | |
1415 | * Many drivers want the device to wake up the system from D3_hot or D3_cold | |
1416 | * and this function allows them to set that up cleanly - pci_enable_wake() | |
1417 | * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI | |
1418 | * ordering constraints. | |
1419 | * | |
1420 | * This function only returns error code if the device is not capable of | |
1421 | * generating PME# from both D3_hot and D3_cold, and the platform is unable to | |
1422 | * enable wake-up power for it. | |
1423 | */ | |
1424 | int pci_wake_from_d3(struct pci_dev *dev, bool enable) | |
1425 | { | |
1426 | return pci_pme_capable(dev, PCI_D3cold) ? | |
1427 | pci_enable_wake(dev, PCI_D3cold, enable) : | |
1428 | pci_enable_wake(dev, PCI_D3hot, enable); | |
1429 | } | |
1430 | ||
404cc2d8 | 1431 | /** |
37139074 JB |
1432 | * pci_target_state - find an appropriate low power state for a given PCI dev |
1433 | * @dev: PCI device | |
1434 | * | |
1435 | * Use underlying platform code to find a supported low power state for @dev. | |
1436 | * If the platform can't manage @dev, return the deepest state from which it | |
1437 | * can generate wake events, based on any available PME info. | |
404cc2d8 | 1438 | */ |
e5899e1b | 1439 | pci_power_t pci_target_state(struct pci_dev *dev) |
404cc2d8 RW |
1440 | { |
1441 | pci_power_t target_state = PCI_D3hot; | |
404cc2d8 RW |
1442 | |
1443 | if (platform_pci_power_manageable(dev)) { | |
1444 | /* | |
1445 | * Call the platform to choose the target state of the device | |
1446 | * and enable wake-up from this state if supported. | |
1447 | */ | |
1448 | pci_power_t state = platform_pci_choose_state(dev); | |
1449 | ||
1450 | switch (state) { | |
1451 | case PCI_POWER_ERROR: | |
1452 | case PCI_UNKNOWN: | |
1453 | break; | |
1454 | case PCI_D1: | |
1455 | case PCI_D2: | |
1456 | if (pci_no_d1d2(dev)) | |
1457 | break; | |
1458 | default: | |
1459 | target_state = state; | |
404cc2d8 | 1460 | } |
d2abdf62 RW |
1461 | } else if (!dev->pm_cap) { |
1462 | target_state = PCI_D0; | |
404cc2d8 RW |
1463 | } else if (device_may_wakeup(&dev->dev)) { |
1464 | /* | |
1465 | * Find the deepest state from which the device can generate | |
1466 | * wake-up events, make it the target state and enable device | |
1467 | * to generate PME#. | |
1468 | */ | |
337001b6 RW |
1469 | if (dev->pme_support) { |
1470 | while (target_state | |
1471 | && !(dev->pme_support & (1 << target_state))) | |
1472 | target_state--; | |
404cc2d8 RW |
1473 | } |
1474 | } | |
1475 | ||
e5899e1b RW |
1476 | return target_state; |
1477 | } | |
1478 | ||
1479 | /** | |
1480 | * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state | |
1481 | * @dev: Device to handle. | |
1482 | * | |
1483 | * Choose the power state appropriate for the device depending on whether | |
1484 | * it can wake up the system and/or is power manageable by the platform | |
1485 | * (PCI_D3hot is the default) and put the device into that state. | |
1486 | */ | |
1487 | int pci_prepare_to_sleep(struct pci_dev *dev) | |
1488 | { | |
1489 | pci_power_t target_state = pci_target_state(dev); | |
1490 | int error; | |
1491 | ||
1492 | if (target_state == PCI_POWER_ERROR) | |
1493 | return -EIO; | |
1494 | ||
8efb8c76 | 1495 | pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev)); |
c157dfa3 | 1496 | |
404cc2d8 RW |
1497 | error = pci_set_power_state(dev, target_state); |
1498 | ||
1499 | if (error) | |
1500 | pci_enable_wake(dev, target_state, false); | |
1501 | ||
1502 | return error; | |
1503 | } | |
1504 | ||
1505 | /** | |
443bd1c4 | 1506 | * pci_back_from_sleep - turn PCI device on during system-wide transition into working state |
404cc2d8 RW |
1507 | * @dev: Device to handle. |
1508 | * | |
1509 | * Disable device's sytem wake-up capability and put it into D0. | |
1510 | */ | |
1511 | int pci_back_from_sleep(struct pci_dev *dev) | |
1512 | { | |
1513 | pci_enable_wake(dev, PCI_D0, false); | |
1514 | return pci_set_power_state(dev, PCI_D0); | |
1515 | } | |
1516 | ||
6cbf8214 RW |
1517 | /** |
1518 | * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend. | |
1519 | * @dev: PCI device being suspended. | |
1520 | * | |
1521 | * Prepare @dev to generate wake-up events at run time and put it into a low | |
1522 | * power state. | |
1523 | */ | |
1524 | int pci_finish_runtime_suspend(struct pci_dev *dev) | |
1525 | { | |
1526 | pci_power_t target_state = pci_target_state(dev); | |
1527 | int error; | |
1528 | ||
1529 | if (target_state == PCI_POWER_ERROR) | |
1530 | return -EIO; | |
1531 | ||
1532 | __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev)); | |
1533 | ||
1534 | error = pci_set_power_state(dev, target_state); | |
1535 | ||
1536 | if (error) | |
1537 | __pci_enable_wake(dev, target_state, true, false); | |
1538 | ||
1539 | return error; | |
1540 | } | |
1541 | ||
b67ea761 RW |
1542 | /** |
1543 | * pci_dev_run_wake - Check if device can generate run-time wake-up events. | |
1544 | * @dev: Device to check. | |
1545 | * | |
1546 | * Return true if the device itself is cabable of generating wake-up events | |
1547 | * (through the platform or using the native PCIe PME) or if the device supports | |
1548 | * PME and one of its upstream bridges can generate wake-up events. | |
1549 | */ | |
1550 | bool pci_dev_run_wake(struct pci_dev *dev) | |
1551 | { | |
1552 | struct pci_bus *bus = dev->bus; | |
1553 | ||
1554 | if (device_run_wake(&dev->dev)) | |
1555 | return true; | |
1556 | ||
1557 | if (!dev->pme_support) | |
1558 | return false; | |
1559 | ||
1560 | while (bus->parent) { | |
1561 | struct pci_dev *bridge = bus->self; | |
1562 | ||
1563 | if (device_run_wake(&bridge->dev)) | |
1564 | return true; | |
1565 | ||
1566 | bus = bus->parent; | |
1567 | } | |
1568 | ||
1569 | /* We have reached the root bus. */ | |
1570 | if (bus->bridge) | |
1571 | return device_run_wake(bus->bridge); | |
1572 | ||
1573 | return false; | |
1574 | } | |
1575 | EXPORT_SYMBOL_GPL(pci_dev_run_wake); | |
1576 | ||
eb9d0fe4 RW |
1577 | /** |
1578 | * pci_pm_init - Initialize PM functions of given PCI device | |
1579 | * @dev: PCI device to handle. | |
1580 | */ | |
1581 | void pci_pm_init(struct pci_dev *dev) | |
1582 | { | |
1583 | int pm; | |
1584 | u16 pmc; | |
1da177e4 | 1585 | |
bb910a70 | 1586 | pm_runtime_forbid(&dev->dev); |
a1e4d72c | 1587 | device_enable_async_suspend(&dev->dev); |
e80bb09d | 1588 | dev->wakeup_prepared = false; |
bb910a70 | 1589 | |
337001b6 RW |
1590 | dev->pm_cap = 0; |
1591 | ||
eb9d0fe4 RW |
1592 | /* find PCI PM capability in list */ |
1593 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
1594 | if (!pm) | |
50246dd4 | 1595 | return; |
eb9d0fe4 RW |
1596 | /* Check device's ability to generate PME# */ |
1597 | pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); | |
075c1771 | 1598 | |
eb9d0fe4 RW |
1599 | if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { |
1600 | dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n", | |
1601 | pmc & PCI_PM_CAP_VER_MASK); | |
50246dd4 | 1602 | return; |
eb9d0fe4 RW |
1603 | } |
1604 | ||
337001b6 | 1605 | dev->pm_cap = pm; |
1ae861e6 | 1606 | dev->d3_delay = PCI_PM_D3_WAIT; |
337001b6 RW |
1607 | |
1608 | dev->d1_support = false; | |
1609 | dev->d2_support = false; | |
1610 | if (!pci_no_d1d2(dev)) { | |
c9ed77ee | 1611 | if (pmc & PCI_PM_CAP_D1) |
337001b6 | 1612 | dev->d1_support = true; |
c9ed77ee | 1613 | if (pmc & PCI_PM_CAP_D2) |
337001b6 | 1614 | dev->d2_support = true; |
c9ed77ee BH |
1615 | |
1616 | if (dev->d1_support || dev->d2_support) | |
1617 | dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n", | |
ec84f126 JB |
1618 | dev->d1_support ? " D1" : "", |
1619 | dev->d2_support ? " D2" : ""); | |
337001b6 RW |
1620 | } |
1621 | ||
1622 | pmc &= PCI_PM_CAP_PME_MASK; | |
1623 | if (pmc) { | |
10c3d71d BH |
1624 | dev_printk(KERN_DEBUG, &dev->dev, |
1625 | "PME# supported from%s%s%s%s%s\n", | |
c9ed77ee BH |
1626 | (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "", |
1627 | (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "", | |
1628 | (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "", | |
1629 | (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "", | |
1630 | (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : ""); | |
337001b6 | 1631 | dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT; |
eb9d0fe4 RW |
1632 | /* |
1633 | * Make device's PM flags reflect the wake-up capability, but | |
1634 | * let the user space enable it to wake up the system as needed. | |
1635 | */ | |
1636 | device_set_wakeup_capable(&dev->dev, true); | |
1637 | device_set_wakeup_enable(&dev->dev, false); | |
1638 | /* Disable the PME# generation functionality */ | |
337001b6 RW |
1639 | pci_pme_active(dev, false); |
1640 | } else { | |
1641 | dev->pme_support = 0; | |
eb9d0fe4 | 1642 | } |
1da177e4 LT |
1643 | } |
1644 | ||
eb9c39d0 JB |
1645 | /** |
1646 | * platform_pci_wakeup_init - init platform wakeup if present | |
1647 | * @dev: PCI device | |
1648 | * | |
1649 | * Some devices don't have PCI PM caps but can still generate wakeup | |
1650 | * events through platform methods (like ACPI events). If @dev supports | |
1651 | * platform wakeup events, set the device flag to indicate as much. This | |
1652 | * may be redundant if the device also supports PCI PM caps, but double | |
1653 | * initialization should be safe in that case. | |
1654 | */ | |
1655 | void platform_pci_wakeup_init(struct pci_dev *dev) | |
1656 | { | |
1657 | if (!platform_pci_can_wakeup(dev)) | |
1658 | return; | |
1659 | ||
1660 | device_set_wakeup_capable(&dev->dev, true); | |
1661 | device_set_wakeup_enable(&dev->dev, false); | |
1662 | platform_pci_sleep_wake(dev, false); | |
1663 | } | |
1664 | ||
63f4898a RW |
1665 | /** |
1666 | * pci_add_save_buffer - allocate buffer for saving given capability registers | |
1667 | * @dev: the PCI device | |
1668 | * @cap: the capability to allocate the buffer for | |
1669 | * @size: requested size of the buffer | |
1670 | */ | |
1671 | static int pci_add_cap_save_buffer( | |
1672 | struct pci_dev *dev, char cap, unsigned int size) | |
1673 | { | |
1674 | int pos; | |
1675 | struct pci_cap_saved_state *save_state; | |
1676 | ||
1677 | pos = pci_find_capability(dev, cap); | |
1678 | if (pos <= 0) | |
1679 | return 0; | |
1680 | ||
1681 | save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL); | |
1682 | if (!save_state) | |
1683 | return -ENOMEM; | |
1684 | ||
1685 | save_state->cap_nr = cap; | |
1686 | pci_add_saved_cap(dev, save_state); | |
1687 | ||
1688 | return 0; | |
1689 | } | |
1690 | ||
1691 | /** | |
1692 | * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities | |
1693 | * @dev: the PCI device | |
1694 | */ | |
1695 | void pci_allocate_cap_save_buffers(struct pci_dev *dev) | |
1696 | { | |
1697 | int error; | |
1698 | ||
89858517 YZ |
1699 | error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP, |
1700 | PCI_EXP_SAVE_REGS * sizeof(u16)); | |
63f4898a RW |
1701 | if (error) |
1702 | dev_err(&dev->dev, | |
1703 | "unable to preallocate PCI Express save buffer\n"); | |
1704 | ||
1705 | error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16)); | |
1706 | if (error) | |
1707 | dev_err(&dev->dev, | |
1708 | "unable to preallocate PCI-X save buffer\n"); | |
1709 | } | |
1710 | ||
58c3a727 YZ |
1711 | /** |
1712 | * pci_enable_ari - enable ARI forwarding if hardware support it | |
1713 | * @dev: the PCI device | |
1714 | */ | |
1715 | void pci_enable_ari(struct pci_dev *dev) | |
1716 | { | |
1717 | int pos; | |
1718 | u32 cap; | |
1719 | u16 ctrl; | |
8113587c | 1720 | struct pci_dev *bridge; |
58c3a727 | 1721 | |
5f4d91a1 | 1722 | if (!pci_is_pcie(dev) || dev->devfn) |
58c3a727 YZ |
1723 | return; |
1724 | ||
8113587c ZY |
1725 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); |
1726 | if (!pos) | |
58c3a727 YZ |
1727 | return; |
1728 | ||
8113587c | 1729 | bridge = dev->bus->self; |
5f4d91a1 | 1730 | if (!bridge || !pci_is_pcie(bridge)) |
8113587c ZY |
1731 | return; |
1732 | ||
06a1cbaf | 1733 | pos = pci_pcie_cap(bridge); |
58c3a727 YZ |
1734 | if (!pos) |
1735 | return; | |
1736 | ||
8113587c | 1737 | pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap); |
58c3a727 YZ |
1738 | if (!(cap & PCI_EXP_DEVCAP2_ARI)) |
1739 | return; | |
1740 | ||
8113587c | 1741 | pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl); |
58c3a727 | 1742 | ctrl |= PCI_EXP_DEVCTL2_ARI; |
8113587c | 1743 | pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl); |
58c3a727 | 1744 | |
8113587c | 1745 | bridge->ari_enabled = 1; |
58c3a727 YZ |
1746 | } |
1747 | ||
5d990b62 CW |
1748 | static int pci_acs_enable; |
1749 | ||
1750 | /** | |
1751 | * pci_request_acs - ask for ACS to be enabled if supported | |
1752 | */ | |
1753 | void pci_request_acs(void) | |
1754 | { | |
1755 | pci_acs_enable = 1; | |
1756 | } | |
1757 | ||
ae21ee65 AK |
1758 | /** |
1759 | * pci_enable_acs - enable ACS if hardware support it | |
1760 | * @dev: the PCI device | |
1761 | */ | |
1762 | void pci_enable_acs(struct pci_dev *dev) | |
1763 | { | |
1764 | int pos; | |
1765 | u16 cap; | |
1766 | u16 ctrl; | |
1767 | ||
5d990b62 CW |
1768 | if (!pci_acs_enable) |
1769 | return; | |
1770 | ||
5f4d91a1 | 1771 | if (!pci_is_pcie(dev)) |
ae21ee65 AK |
1772 | return; |
1773 | ||
1774 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); | |
1775 | if (!pos) | |
1776 | return; | |
1777 | ||
1778 | pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap); | |
1779 | pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl); | |
1780 | ||
1781 | /* Source Validation */ | |
1782 | ctrl |= (cap & PCI_ACS_SV); | |
1783 | ||
1784 | /* P2P Request Redirect */ | |
1785 | ctrl |= (cap & PCI_ACS_RR); | |
1786 | ||
1787 | /* P2P Completion Redirect */ | |
1788 | ctrl |= (cap & PCI_ACS_CR); | |
1789 | ||
1790 | /* Upstream Forwarding */ | |
1791 | ctrl |= (cap & PCI_ACS_UF); | |
1792 | ||
1793 | pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl); | |
1794 | } | |
1795 | ||
57c2cf71 BH |
1796 | /** |
1797 | * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge | |
1798 | * @dev: the PCI device | |
1799 | * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD) | |
1800 | * | |
1801 | * Perform INTx swizzling for a device behind one level of bridge. This is | |
1802 | * required by section 9.1 of the PCI-to-PCI bridge specification for devices | |
46b952a3 MW |
1803 | * behind bridges on add-in cards. For devices with ARI enabled, the slot |
1804 | * number is always 0 (see the Implementation Note in section 2.2.8.1 of | |
1805 | * the PCI Express Base Specification, Revision 2.1) | |
57c2cf71 BH |
1806 | */ |
1807 | u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin) | |
1808 | { | |
46b952a3 MW |
1809 | int slot; |
1810 | ||
1811 | if (pci_ari_enabled(dev->bus)) | |
1812 | slot = 0; | |
1813 | else | |
1814 | slot = PCI_SLOT(dev->devfn); | |
1815 | ||
1816 | return (((pin - 1) + slot) % 4) + 1; | |
57c2cf71 BH |
1817 | } |
1818 | ||
1da177e4 LT |
1819 | int |
1820 | pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) | |
1821 | { | |
1822 | u8 pin; | |
1823 | ||
514d207d | 1824 | pin = dev->pin; |
1da177e4 LT |
1825 | if (!pin) |
1826 | return -1; | |
878f2e50 | 1827 | |
8784fd4d | 1828 | while (!pci_is_root_bus(dev->bus)) { |
57c2cf71 | 1829 | pin = pci_swizzle_interrupt_pin(dev, pin); |
1da177e4 LT |
1830 | dev = dev->bus->self; |
1831 | } | |
1832 | *bridge = dev; | |
1833 | return pin; | |
1834 | } | |
1835 | ||
68feac87 BH |
1836 | /** |
1837 | * pci_common_swizzle - swizzle INTx all the way to root bridge | |
1838 | * @dev: the PCI device | |
1839 | * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD) | |
1840 | * | |
1841 | * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI | |
1842 | * bridges all the way up to a PCI root bus. | |
1843 | */ | |
1844 | u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp) | |
1845 | { | |
1846 | u8 pin = *pinp; | |
1847 | ||
1eb39487 | 1848 | while (!pci_is_root_bus(dev->bus)) { |
68feac87 BH |
1849 | pin = pci_swizzle_interrupt_pin(dev, pin); |
1850 | dev = dev->bus->self; | |
1851 | } | |
1852 | *pinp = pin; | |
1853 | return PCI_SLOT(dev->devfn); | |
1854 | } | |
1855 | ||
1da177e4 LT |
1856 | /** |
1857 | * pci_release_region - Release a PCI bar | |
1858 | * @pdev: PCI device whose resources were previously reserved by pci_request_region | |
1859 | * @bar: BAR to release | |
1860 | * | |
1861 | * Releases the PCI I/O and memory resources previously reserved by a | |
1862 | * successful call to pci_request_region. Call this function only | |
1863 | * after all use of the PCI regions has ceased. | |
1864 | */ | |
1865 | void pci_release_region(struct pci_dev *pdev, int bar) | |
1866 | { | |
9ac7849e TH |
1867 | struct pci_devres *dr; |
1868 | ||
1da177e4 LT |
1869 | if (pci_resource_len(pdev, bar) == 0) |
1870 | return; | |
1871 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) | |
1872 | release_region(pci_resource_start(pdev, bar), | |
1873 | pci_resource_len(pdev, bar)); | |
1874 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) | |
1875 | release_mem_region(pci_resource_start(pdev, bar), | |
1876 | pci_resource_len(pdev, bar)); | |
9ac7849e TH |
1877 | |
1878 | dr = find_pci_dr(pdev); | |
1879 | if (dr) | |
1880 | dr->region_mask &= ~(1 << bar); | |
1da177e4 LT |
1881 | } |
1882 | ||
1883 | /** | |
f5ddcac4 | 1884 | * __pci_request_region - Reserved PCI I/O and memory resource |
1da177e4 LT |
1885 | * @pdev: PCI device whose resources are to be reserved |
1886 | * @bar: BAR to be reserved | |
1887 | * @res_name: Name to be associated with resource. | |
f5ddcac4 | 1888 | * @exclusive: whether the region access is exclusive or not |
1da177e4 LT |
1889 | * |
1890 | * Mark the PCI region associated with PCI device @pdev BR @bar as | |
1891 | * being reserved by owner @res_name. Do not access any | |
1892 | * address inside the PCI regions unless this call returns | |
1893 | * successfully. | |
1894 | * | |
f5ddcac4 RD |
1895 | * If @exclusive is set, then the region is marked so that userspace |
1896 | * is explicitly not allowed to map the resource via /dev/mem or | |
1897 | * sysfs MMIO access. | |
1898 | * | |
1da177e4 LT |
1899 | * Returns 0 on success, or %EBUSY on error. A warning |
1900 | * message is also printed on failure. | |
1901 | */ | |
e8de1481 AV |
1902 | static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name, |
1903 | int exclusive) | |
1da177e4 | 1904 | { |
9ac7849e TH |
1905 | struct pci_devres *dr; |
1906 | ||
1da177e4 LT |
1907 | if (pci_resource_len(pdev, bar) == 0) |
1908 | return 0; | |
1909 | ||
1910 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { | |
1911 | if (!request_region(pci_resource_start(pdev, bar), | |
1912 | pci_resource_len(pdev, bar), res_name)) | |
1913 | goto err_out; | |
1914 | } | |
1915 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { | |
e8de1481 AV |
1916 | if (!__request_mem_region(pci_resource_start(pdev, bar), |
1917 | pci_resource_len(pdev, bar), res_name, | |
1918 | exclusive)) | |
1da177e4 LT |
1919 | goto err_out; |
1920 | } | |
9ac7849e TH |
1921 | |
1922 | dr = find_pci_dr(pdev); | |
1923 | if (dr) | |
1924 | dr->region_mask |= 1 << bar; | |
1925 | ||
1da177e4 LT |
1926 | return 0; |
1927 | ||
1928 | err_out: | |
c7dabef8 | 1929 | dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar, |
096e6f67 | 1930 | &pdev->resource[bar]); |
1da177e4 LT |
1931 | return -EBUSY; |
1932 | } | |
1933 | ||
e8de1481 | 1934 | /** |
f5ddcac4 | 1935 | * pci_request_region - Reserve PCI I/O and memory resource |
e8de1481 AV |
1936 | * @pdev: PCI device whose resources are to be reserved |
1937 | * @bar: BAR to be reserved | |
f5ddcac4 | 1938 | * @res_name: Name to be associated with resource |
e8de1481 | 1939 | * |
f5ddcac4 | 1940 | * Mark the PCI region associated with PCI device @pdev BAR @bar as |
e8de1481 AV |
1941 | * being reserved by owner @res_name. Do not access any |
1942 | * address inside the PCI regions unless this call returns | |
1943 | * successfully. | |
1944 | * | |
1945 | * Returns 0 on success, or %EBUSY on error. A warning | |
1946 | * message is also printed on failure. | |
1947 | */ | |
1948 | int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) | |
1949 | { | |
1950 | return __pci_request_region(pdev, bar, res_name, 0); | |
1951 | } | |
1952 | ||
1953 | /** | |
1954 | * pci_request_region_exclusive - Reserved PCI I/O and memory resource | |
1955 | * @pdev: PCI device whose resources are to be reserved | |
1956 | * @bar: BAR to be reserved | |
1957 | * @res_name: Name to be associated with resource. | |
1958 | * | |
1959 | * Mark the PCI region associated with PCI device @pdev BR @bar as | |
1960 | * being reserved by owner @res_name. Do not access any | |
1961 | * address inside the PCI regions unless this call returns | |
1962 | * successfully. | |
1963 | * | |
1964 | * Returns 0 on success, or %EBUSY on error. A warning | |
1965 | * message is also printed on failure. | |
1966 | * | |
1967 | * The key difference that _exclusive makes it that userspace is | |
1968 | * explicitly not allowed to map the resource via /dev/mem or | |
1969 | * sysfs. | |
1970 | */ | |
1971 | int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name) | |
1972 | { | |
1973 | return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE); | |
1974 | } | |
c87deff7 HS |
1975 | /** |
1976 | * pci_release_selected_regions - Release selected PCI I/O and memory resources | |
1977 | * @pdev: PCI device whose resources were previously reserved | |
1978 | * @bars: Bitmask of BARs to be released | |
1979 | * | |
1980 | * Release selected PCI I/O and memory resources previously reserved. | |
1981 | * Call this function only after all use of the PCI regions has ceased. | |
1982 | */ | |
1983 | void pci_release_selected_regions(struct pci_dev *pdev, int bars) | |
1984 | { | |
1985 | int i; | |
1986 | ||
1987 | for (i = 0; i < 6; i++) | |
1988 | if (bars & (1 << i)) | |
1989 | pci_release_region(pdev, i); | |
1990 | } | |
1991 | ||
e8de1481 AV |
1992 | int __pci_request_selected_regions(struct pci_dev *pdev, int bars, |
1993 | const char *res_name, int excl) | |
c87deff7 HS |
1994 | { |
1995 | int i; | |
1996 | ||
1997 | for (i = 0; i < 6; i++) | |
1998 | if (bars & (1 << i)) | |
e8de1481 | 1999 | if (__pci_request_region(pdev, i, res_name, excl)) |
c87deff7 HS |
2000 | goto err_out; |
2001 | return 0; | |
2002 | ||
2003 | err_out: | |
2004 | while(--i >= 0) | |
2005 | if (bars & (1 << i)) | |
2006 | pci_release_region(pdev, i); | |
2007 | ||
2008 | return -EBUSY; | |
2009 | } | |
1da177e4 | 2010 | |
e8de1481 AV |
2011 | |
2012 | /** | |
2013 | * pci_request_selected_regions - Reserve selected PCI I/O and memory resources | |
2014 | * @pdev: PCI device whose resources are to be reserved | |
2015 | * @bars: Bitmask of BARs to be requested | |
2016 | * @res_name: Name to be associated with resource | |
2017 | */ | |
2018 | int pci_request_selected_regions(struct pci_dev *pdev, int bars, | |
2019 | const char *res_name) | |
2020 | { | |
2021 | return __pci_request_selected_regions(pdev, bars, res_name, 0); | |
2022 | } | |
2023 | ||
2024 | int pci_request_selected_regions_exclusive(struct pci_dev *pdev, | |
2025 | int bars, const char *res_name) | |
2026 | { | |
2027 | return __pci_request_selected_regions(pdev, bars, res_name, | |
2028 | IORESOURCE_EXCLUSIVE); | |
2029 | } | |
2030 | ||
1da177e4 LT |
2031 | /** |
2032 | * pci_release_regions - Release reserved PCI I/O and memory resources | |
2033 | * @pdev: PCI device whose resources were previously reserved by pci_request_regions | |
2034 | * | |
2035 | * Releases all PCI I/O and memory resources previously reserved by a | |
2036 | * successful call to pci_request_regions. Call this function only | |
2037 | * after all use of the PCI regions has ceased. | |
2038 | */ | |
2039 | ||
2040 | void pci_release_regions(struct pci_dev *pdev) | |
2041 | { | |
c87deff7 | 2042 | pci_release_selected_regions(pdev, (1 << 6) - 1); |
1da177e4 LT |
2043 | } |
2044 | ||
2045 | /** | |
2046 | * pci_request_regions - Reserved PCI I/O and memory resources | |
2047 | * @pdev: PCI device whose resources are to be reserved | |
2048 | * @res_name: Name to be associated with resource. | |
2049 | * | |
2050 | * Mark all PCI regions associated with PCI device @pdev as | |
2051 | * being reserved by owner @res_name. Do not access any | |
2052 | * address inside the PCI regions unless this call returns | |
2053 | * successfully. | |
2054 | * | |
2055 | * Returns 0 on success, or %EBUSY on error. A warning | |
2056 | * message is also printed on failure. | |
2057 | */ | |
3c990e92 | 2058 | int pci_request_regions(struct pci_dev *pdev, const char *res_name) |
1da177e4 | 2059 | { |
c87deff7 | 2060 | return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name); |
1da177e4 LT |
2061 | } |
2062 | ||
e8de1481 AV |
2063 | /** |
2064 | * pci_request_regions_exclusive - Reserved PCI I/O and memory resources | |
2065 | * @pdev: PCI device whose resources are to be reserved | |
2066 | * @res_name: Name to be associated with resource. | |
2067 | * | |
2068 | * Mark all PCI regions associated with PCI device @pdev as | |
2069 | * being reserved by owner @res_name. Do not access any | |
2070 | * address inside the PCI regions unless this call returns | |
2071 | * successfully. | |
2072 | * | |
2073 | * pci_request_regions_exclusive() will mark the region so that | |
2074 | * /dev/mem and the sysfs MMIO access will not be allowed. | |
2075 | * | |
2076 | * Returns 0 on success, or %EBUSY on error. A warning | |
2077 | * message is also printed on failure. | |
2078 | */ | |
2079 | int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name) | |
2080 | { | |
2081 | return pci_request_selected_regions_exclusive(pdev, | |
2082 | ((1 << 6) - 1), res_name); | |
2083 | } | |
2084 | ||
6a479079 BH |
2085 | static void __pci_set_master(struct pci_dev *dev, bool enable) |
2086 | { | |
2087 | u16 old_cmd, cmd; | |
2088 | ||
2089 | pci_read_config_word(dev, PCI_COMMAND, &old_cmd); | |
2090 | if (enable) | |
2091 | cmd = old_cmd | PCI_COMMAND_MASTER; | |
2092 | else | |
2093 | cmd = old_cmd & ~PCI_COMMAND_MASTER; | |
2094 | if (cmd != old_cmd) { | |
2095 | dev_dbg(&dev->dev, "%s bus mastering\n", | |
2096 | enable ? "enabling" : "disabling"); | |
2097 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
2098 | } | |
2099 | dev->is_busmaster = enable; | |
2100 | } | |
e8de1481 | 2101 | |
1da177e4 LT |
2102 | /** |
2103 | * pci_set_master - enables bus-mastering for device dev | |
2104 | * @dev: the PCI device to enable | |
2105 | * | |
2106 | * Enables bus-mastering on the device and calls pcibios_set_master() | |
2107 | * to do the needed arch specific settings. | |
2108 | */ | |
6a479079 | 2109 | void pci_set_master(struct pci_dev *dev) |
1da177e4 | 2110 | { |
6a479079 | 2111 | __pci_set_master(dev, true); |
1da177e4 LT |
2112 | pcibios_set_master(dev); |
2113 | } | |
2114 | ||
6a479079 BH |
2115 | /** |
2116 | * pci_clear_master - disables bus-mastering for device dev | |
2117 | * @dev: the PCI device to disable | |
2118 | */ | |
2119 | void pci_clear_master(struct pci_dev *dev) | |
2120 | { | |
2121 | __pci_set_master(dev, false); | |
2122 | } | |
2123 | ||
1da177e4 | 2124 | /** |
edb2d97e MW |
2125 | * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed |
2126 | * @dev: the PCI device for which MWI is to be enabled | |
1da177e4 | 2127 | * |
edb2d97e MW |
2128 | * Helper function for pci_set_mwi. |
2129 | * Originally copied from drivers/net/acenic.c. | |
1da177e4 LT |
2130 | * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. |
2131 | * | |
2132 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
2133 | */ | |
15ea76d4 | 2134 | int pci_set_cacheline_size(struct pci_dev *dev) |
1da177e4 LT |
2135 | { |
2136 | u8 cacheline_size; | |
2137 | ||
2138 | if (!pci_cache_line_size) | |
15ea76d4 | 2139 | return -EINVAL; |
1da177e4 LT |
2140 | |
2141 | /* Validate current setting: the PCI_CACHE_LINE_SIZE must be | |
2142 | equal to or multiple of the right value. */ | |
2143 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
2144 | if (cacheline_size >= pci_cache_line_size && | |
2145 | (cacheline_size % pci_cache_line_size) == 0) | |
2146 | return 0; | |
2147 | ||
2148 | /* Write the correct value. */ | |
2149 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); | |
2150 | /* Read it back. */ | |
2151 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
2152 | if (cacheline_size == pci_cache_line_size) | |
2153 | return 0; | |
2154 | ||
80ccba11 BH |
2155 | dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not " |
2156 | "supported\n", pci_cache_line_size << 2); | |
1da177e4 LT |
2157 | |
2158 | return -EINVAL; | |
2159 | } | |
15ea76d4 TH |
2160 | EXPORT_SYMBOL_GPL(pci_set_cacheline_size); |
2161 | ||
2162 | #ifdef PCI_DISABLE_MWI | |
2163 | int pci_set_mwi(struct pci_dev *dev) | |
2164 | { | |
2165 | return 0; | |
2166 | } | |
2167 | ||
2168 | int pci_try_set_mwi(struct pci_dev *dev) | |
2169 | { | |
2170 | return 0; | |
2171 | } | |
2172 | ||
2173 | void pci_clear_mwi(struct pci_dev *dev) | |
2174 | { | |
2175 | } | |
2176 | ||
2177 | #else | |
1da177e4 LT |
2178 | |
2179 | /** | |
2180 | * pci_set_mwi - enables memory-write-invalidate PCI transaction | |
2181 | * @dev: the PCI device for which MWI is enabled | |
2182 | * | |
694625c0 | 2183 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. |
1da177e4 LT |
2184 | * |
2185 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
2186 | */ | |
2187 | int | |
2188 | pci_set_mwi(struct pci_dev *dev) | |
2189 | { | |
2190 | int rc; | |
2191 | u16 cmd; | |
2192 | ||
edb2d97e | 2193 | rc = pci_set_cacheline_size(dev); |
1da177e4 LT |
2194 | if (rc) |
2195 | return rc; | |
2196 | ||
2197 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
2198 | if (! (cmd & PCI_COMMAND_INVALIDATE)) { | |
80ccba11 | 2199 | dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n"); |
1da177e4 LT |
2200 | cmd |= PCI_COMMAND_INVALIDATE; |
2201 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
2202 | } | |
2203 | ||
2204 | return 0; | |
2205 | } | |
2206 | ||
694625c0 RD |
2207 | /** |
2208 | * pci_try_set_mwi - enables memory-write-invalidate PCI transaction | |
2209 | * @dev: the PCI device for which MWI is enabled | |
2210 | * | |
2211 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. | |
2212 | * Callers are not required to check the return value. | |
2213 | * | |
2214 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
2215 | */ | |
2216 | int pci_try_set_mwi(struct pci_dev *dev) | |
2217 | { | |
2218 | int rc = pci_set_mwi(dev); | |
2219 | return rc; | |
2220 | } | |
2221 | ||
1da177e4 LT |
2222 | /** |
2223 | * pci_clear_mwi - disables Memory-Write-Invalidate for device dev | |
2224 | * @dev: the PCI device to disable | |
2225 | * | |
2226 | * Disables PCI Memory-Write-Invalidate transaction on the device | |
2227 | */ | |
2228 | void | |
2229 | pci_clear_mwi(struct pci_dev *dev) | |
2230 | { | |
2231 | u16 cmd; | |
2232 | ||
2233 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
2234 | if (cmd & PCI_COMMAND_INVALIDATE) { | |
2235 | cmd &= ~PCI_COMMAND_INVALIDATE; | |
2236 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
2237 | } | |
2238 | } | |
edb2d97e | 2239 | #endif /* ! PCI_DISABLE_MWI */ |
1da177e4 | 2240 | |
a04ce0ff BR |
2241 | /** |
2242 | * pci_intx - enables/disables PCI INTx for device dev | |
8f7020d3 RD |
2243 | * @pdev: the PCI device to operate on |
2244 | * @enable: boolean: whether to enable or disable PCI INTx | |
a04ce0ff BR |
2245 | * |
2246 | * Enables/disables PCI INTx for device dev | |
2247 | */ | |
2248 | void | |
2249 | pci_intx(struct pci_dev *pdev, int enable) | |
2250 | { | |
2251 | u16 pci_command, new; | |
2252 | ||
2253 | pci_read_config_word(pdev, PCI_COMMAND, &pci_command); | |
2254 | ||
2255 | if (enable) { | |
2256 | new = pci_command & ~PCI_COMMAND_INTX_DISABLE; | |
2257 | } else { | |
2258 | new = pci_command | PCI_COMMAND_INTX_DISABLE; | |
2259 | } | |
2260 | ||
2261 | if (new != pci_command) { | |
9ac7849e TH |
2262 | struct pci_devres *dr; |
2263 | ||
2fd9d74b | 2264 | pci_write_config_word(pdev, PCI_COMMAND, new); |
9ac7849e TH |
2265 | |
2266 | dr = find_pci_dr(pdev); | |
2267 | if (dr && !dr->restore_intx) { | |
2268 | dr->restore_intx = 1; | |
2269 | dr->orig_intx = !enable; | |
2270 | } | |
a04ce0ff BR |
2271 | } |
2272 | } | |
2273 | ||
f5f2b131 EB |
2274 | /** |
2275 | * pci_msi_off - disables any msi or msix capabilities | |
8d7d86e9 | 2276 | * @dev: the PCI device to operate on |
f5f2b131 EB |
2277 | * |
2278 | * If you want to use msi see pci_enable_msi and friends. | |
2279 | * This is a lower level primitive that allows us to disable | |
2280 | * msi operation at the device level. | |
2281 | */ | |
2282 | void pci_msi_off(struct pci_dev *dev) | |
2283 | { | |
2284 | int pos; | |
2285 | u16 control; | |
2286 | ||
2287 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
2288 | if (pos) { | |
2289 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
2290 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
2291 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
2292 | } | |
2293 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
2294 | if (pos) { | |
2295 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
2296 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
2297 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
2298 | } | |
2299 | } | |
2300 | ||
4d57cdfa FT |
2301 | #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE |
2302 | int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size) | |
2303 | { | |
2304 | return dma_set_max_seg_size(&dev->dev, size); | |
2305 | } | |
2306 | EXPORT_SYMBOL(pci_set_dma_max_seg_size); | |
2307 | #endif | |
2308 | ||
59fc67de FT |
2309 | #ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY |
2310 | int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask) | |
2311 | { | |
2312 | return dma_set_seg_boundary(&dev->dev, mask); | |
2313 | } | |
2314 | EXPORT_SYMBOL(pci_set_dma_seg_boundary); | |
2315 | #endif | |
2316 | ||
8c1c699f | 2317 | static int pcie_flr(struct pci_dev *dev, int probe) |
8dd7f803 | 2318 | { |
8c1c699f YZ |
2319 | int i; |
2320 | int pos; | |
8dd7f803 | 2321 | u32 cap; |
04b55c47 | 2322 | u16 status, control; |
8dd7f803 | 2323 | |
06a1cbaf | 2324 | pos = pci_pcie_cap(dev); |
8c1c699f | 2325 | if (!pos) |
8dd7f803 | 2326 | return -ENOTTY; |
8c1c699f YZ |
2327 | |
2328 | pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap); | |
8dd7f803 SY |
2329 | if (!(cap & PCI_EXP_DEVCAP_FLR)) |
2330 | return -ENOTTY; | |
2331 | ||
d91cdc74 SY |
2332 | if (probe) |
2333 | return 0; | |
2334 | ||
8dd7f803 | 2335 | /* Wait for Transaction Pending bit clean */ |
8c1c699f YZ |
2336 | for (i = 0; i < 4; i++) { |
2337 | if (i) | |
2338 | msleep((1 << (i - 1)) * 100); | |
5fe5db05 | 2339 | |
8c1c699f YZ |
2340 | pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status); |
2341 | if (!(status & PCI_EXP_DEVSTA_TRPND)) | |
2342 | goto clear; | |
2343 | } | |
2344 | ||
2345 | dev_err(&dev->dev, "transaction is not cleared; " | |
2346 | "proceeding with reset anyway\n"); | |
2347 | ||
2348 | clear: | |
04b55c47 SR |
2349 | pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &control); |
2350 | control |= PCI_EXP_DEVCTL_BCR_FLR; | |
2351 | pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, control); | |
2352 | ||
8c1c699f | 2353 | msleep(100); |
8dd7f803 | 2354 | |
8dd7f803 SY |
2355 | return 0; |
2356 | } | |
d91cdc74 | 2357 | |
8c1c699f | 2358 | static int pci_af_flr(struct pci_dev *dev, int probe) |
1ca88797 | 2359 | { |
8c1c699f YZ |
2360 | int i; |
2361 | int pos; | |
1ca88797 | 2362 | u8 cap; |
8c1c699f | 2363 | u8 status; |
1ca88797 | 2364 | |
8c1c699f YZ |
2365 | pos = pci_find_capability(dev, PCI_CAP_ID_AF); |
2366 | if (!pos) | |
1ca88797 | 2367 | return -ENOTTY; |
8c1c699f YZ |
2368 | |
2369 | pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap); | |
1ca88797 SY |
2370 | if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) |
2371 | return -ENOTTY; | |
2372 | ||
2373 | if (probe) | |
2374 | return 0; | |
2375 | ||
1ca88797 | 2376 | /* Wait for Transaction Pending bit clean */ |
8c1c699f YZ |
2377 | for (i = 0; i < 4; i++) { |
2378 | if (i) | |
2379 | msleep((1 << (i - 1)) * 100); | |
2380 | ||
2381 | pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status); | |
2382 | if (!(status & PCI_AF_STATUS_TP)) | |
2383 | goto clear; | |
2384 | } | |
5fe5db05 | 2385 | |
8c1c699f YZ |
2386 | dev_err(&dev->dev, "transaction is not cleared; " |
2387 | "proceeding with reset anyway\n"); | |
5fe5db05 | 2388 | |
8c1c699f YZ |
2389 | clear: |
2390 | pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); | |
1ca88797 | 2391 | msleep(100); |
8c1c699f | 2392 | |
1ca88797 SY |
2393 | return 0; |
2394 | } | |
2395 | ||
f85876ba | 2396 | static int pci_pm_reset(struct pci_dev *dev, int probe) |
d91cdc74 | 2397 | { |
f85876ba YZ |
2398 | u16 csr; |
2399 | ||
2400 | if (!dev->pm_cap) | |
2401 | return -ENOTTY; | |
d91cdc74 | 2402 | |
f85876ba YZ |
2403 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr); |
2404 | if (csr & PCI_PM_CTRL_NO_SOFT_RESET) | |
2405 | return -ENOTTY; | |
d91cdc74 | 2406 | |
f85876ba YZ |
2407 | if (probe) |
2408 | return 0; | |
1ca88797 | 2409 | |
f85876ba YZ |
2410 | if (dev->current_state != PCI_D0) |
2411 | return -EINVAL; | |
2412 | ||
2413 | csr &= ~PCI_PM_CTRL_STATE_MASK; | |
2414 | csr |= PCI_D3hot; | |
2415 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); | |
1ae861e6 | 2416 | pci_dev_d3_sleep(dev); |
f85876ba YZ |
2417 | |
2418 | csr &= ~PCI_PM_CTRL_STATE_MASK; | |
2419 | csr |= PCI_D0; | |
2420 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); | |
1ae861e6 | 2421 | pci_dev_d3_sleep(dev); |
f85876ba YZ |
2422 | |
2423 | return 0; | |
2424 | } | |
2425 | ||
c12ff1df YZ |
2426 | static int pci_parent_bus_reset(struct pci_dev *dev, int probe) |
2427 | { | |
2428 | u16 ctrl; | |
2429 | struct pci_dev *pdev; | |
2430 | ||
654b75e0 | 2431 | if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self) |
c12ff1df YZ |
2432 | return -ENOTTY; |
2433 | ||
2434 | list_for_each_entry(pdev, &dev->bus->devices, bus_list) | |
2435 | if (pdev != dev) | |
2436 | return -ENOTTY; | |
2437 | ||
2438 | if (probe) | |
2439 | return 0; | |
2440 | ||
2441 | pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl); | |
2442 | ctrl |= PCI_BRIDGE_CTL_BUS_RESET; | |
2443 | pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl); | |
2444 | msleep(100); | |
2445 | ||
2446 | ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; | |
2447 | pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl); | |
2448 | msleep(100); | |
2449 | ||
2450 | return 0; | |
2451 | } | |
2452 | ||
8c1c699f | 2453 | static int pci_dev_reset(struct pci_dev *dev, int probe) |
d91cdc74 | 2454 | { |
8c1c699f YZ |
2455 | int rc; |
2456 | ||
2457 | might_sleep(); | |
2458 | ||
2459 | if (!probe) { | |
2460 | pci_block_user_cfg_access(dev); | |
2461 | /* block PM suspend, driver probe, etc. */ | |
8e9394ce | 2462 | device_lock(&dev->dev); |
8c1c699f | 2463 | } |
d91cdc74 | 2464 | |
b9c3b266 DC |
2465 | rc = pci_dev_specific_reset(dev, probe); |
2466 | if (rc != -ENOTTY) | |
2467 | goto done; | |
2468 | ||
8c1c699f YZ |
2469 | rc = pcie_flr(dev, probe); |
2470 | if (rc != -ENOTTY) | |
2471 | goto done; | |
d91cdc74 | 2472 | |
8c1c699f | 2473 | rc = pci_af_flr(dev, probe); |
f85876ba YZ |
2474 | if (rc != -ENOTTY) |
2475 | goto done; | |
2476 | ||
2477 | rc = pci_pm_reset(dev, probe); | |
c12ff1df YZ |
2478 | if (rc != -ENOTTY) |
2479 | goto done; | |
2480 | ||
2481 | rc = pci_parent_bus_reset(dev, probe); | |
8c1c699f YZ |
2482 | done: |
2483 | if (!probe) { | |
8e9394ce | 2484 | device_unlock(&dev->dev); |
8c1c699f YZ |
2485 | pci_unblock_user_cfg_access(dev); |
2486 | } | |
1ca88797 | 2487 | |
8c1c699f | 2488 | return rc; |
d91cdc74 SY |
2489 | } |
2490 | ||
2491 | /** | |
8c1c699f YZ |
2492 | * __pci_reset_function - reset a PCI device function |
2493 | * @dev: PCI device to reset | |
d91cdc74 SY |
2494 | * |
2495 | * Some devices allow an individual function to be reset without affecting | |
2496 | * other functions in the same device. The PCI device must be responsive | |
2497 | * to PCI config space in order to use this function. | |
2498 | * | |
2499 | * The device function is presumed to be unused when this function is called. | |
2500 | * Resetting the device will make the contents of PCI configuration space | |
2501 | * random, so any caller of this must be prepared to reinitialise the | |
2502 | * device including MSI, bus mastering, BARs, decoding IO and memory spaces, | |
2503 | * etc. | |
2504 | * | |
8c1c699f | 2505 | * Returns 0 if the device function was successfully reset or negative if the |
d91cdc74 SY |
2506 | * device doesn't support resetting a single function. |
2507 | */ | |
8c1c699f | 2508 | int __pci_reset_function(struct pci_dev *dev) |
d91cdc74 | 2509 | { |
8c1c699f | 2510 | return pci_dev_reset(dev, 0); |
d91cdc74 | 2511 | } |
8c1c699f | 2512 | EXPORT_SYMBOL_GPL(__pci_reset_function); |
8dd7f803 | 2513 | |
711d5779 MT |
2514 | /** |
2515 | * pci_probe_reset_function - check whether the device can be safely reset | |
2516 | * @dev: PCI device to reset | |
2517 | * | |
2518 | * Some devices allow an individual function to be reset without affecting | |
2519 | * other functions in the same device. The PCI device must be responsive | |
2520 | * to PCI config space in order to use this function. | |
2521 | * | |
2522 | * Returns 0 if the device function can be reset or negative if the | |
2523 | * device doesn't support resetting a single function. | |
2524 | */ | |
2525 | int pci_probe_reset_function(struct pci_dev *dev) | |
2526 | { | |
2527 | return pci_dev_reset(dev, 1); | |
2528 | } | |
2529 | ||
8dd7f803 | 2530 | /** |
8c1c699f YZ |
2531 | * pci_reset_function - quiesce and reset a PCI device function |
2532 | * @dev: PCI device to reset | |
8dd7f803 SY |
2533 | * |
2534 | * Some devices allow an individual function to be reset without affecting | |
2535 | * other functions in the same device. The PCI device must be responsive | |
2536 | * to PCI config space in order to use this function. | |
2537 | * | |
2538 | * This function does not just reset the PCI portion of a device, but | |
2539 | * clears all the state associated with the device. This function differs | |
8c1c699f | 2540 | * from __pci_reset_function in that it saves and restores device state |
8dd7f803 SY |
2541 | * over the reset. |
2542 | * | |
8c1c699f | 2543 | * Returns 0 if the device function was successfully reset or negative if the |
8dd7f803 SY |
2544 | * device doesn't support resetting a single function. |
2545 | */ | |
2546 | int pci_reset_function(struct pci_dev *dev) | |
2547 | { | |
8c1c699f | 2548 | int rc; |
8dd7f803 | 2549 | |
8c1c699f YZ |
2550 | rc = pci_dev_reset(dev, 1); |
2551 | if (rc) | |
2552 | return rc; | |
8dd7f803 | 2553 | |
8dd7f803 SY |
2554 | pci_save_state(dev); |
2555 | ||
8c1c699f YZ |
2556 | /* |
2557 | * both INTx and MSI are disabled after the Interrupt Disable bit | |
2558 | * is set and the Bus Master bit is cleared. | |
2559 | */ | |
8dd7f803 SY |
2560 | pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE); |
2561 | ||
8c1c699f | 2562 | rc = pci_dev_reset(dev, 0); |
8dd7f803 SY |
2563 | |
2564 | pci_restore_state(dev); | |
8dd7f803 | 2565 | |
8c1c699f | 2566 | return rc; |
8dd7f803 SY |
2567 | } |
2568 | EXPORT_SYMBOL_GPL(pci_reset_function); | |
2569 | ||
d556ad4b PO |
2570 | /** |
2571 | * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count | |
2572 | * @dev: PCI device to query | |
2573 | * | |
2574 | * Returns mmrbc: maximum designed memory read count in bytes | |
2575 | * or appropriate error value. | |
2576 | */ | |
2577 | int pcix_get_max_mmrbc(struct pci_dev *dev) | |
2578 | { | |
7c9e2b1c | 2579 | int cap; |
d556ad4b PO |
2580 | u32 stat; |
2581 | ||
2582 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
2583 | if (!cap) | |
2584 | return -EINVAL; | |
2585 | ||
7c9e2b1c | 2586 | if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) |
d556ad4b PO |
2587 | return -EINVAL; |
2588 | ||
25daeb55 | 2589 | return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21); |
d556ad4b PO |
2590 | } |
2591 | EXPORT_SYMBOL(pcix_get_max_mmrbc); | |
2592 | ||
2593 | /** | |
2594 | * pcix_get_mmrbc - get PCI-X maximum memory read byte count | |
2595 | * @dev: PCI device to query | |
2596 | * | |
2597 | * Returns mmrbc: maximum memory read count in bytes | |
2598 | * or appropriate error value. | |
2599 | */ | |
2600 | int pcix_get_mmrbc(struct pci_dev *dev) | |
2601 | { | |
7c9e2b1c | 2602 | int cap; |
bdc2bda7 | 2603 | u16 cmd; |
d556ad4b PO |
2604 | |
2605 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
2606 | if (!cap) | |
2607 | return -EINVAL; | |
2608 | ||
7c9e2b1c DN |
2609 | if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) |
2610 | return -EINVAL; | |
d556ad4b | 2611 | |
7c9e2b1c | 2612 | return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); |
d556ad4b PO |
2613 | } |
2614 | EXPORT_SYMBOL(pcix_get_mmrbc); | |
2615 | ||
2616 | /** | |
2617 | * pcix_set_mmrbc - set PCI-X maximum memory read byte count | |
2618 | * @dev: PCI device to query | |
2619 | * @mmrbc: maximum memory read count in bytes | |
2620 | * valid values are 512, 1024, 2048, 4096 | |
2621 | * | |
2622 | * If possible sets maximum memory read byte count, some bridges have erratas | |
2623 | * that prevent this. | |
2624 | */ | |
2625 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) | |
2626 | { | |
7c9e2b1c | 2627 | int cap; |
bdc2bda7 DN |
2628 | u32 stat, v, o; |
2629 | u16 cmd; | |
d556ad4b | 2630 | |
229f5afd | 2631 | if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc)) |
7c9e2b1c | 2632 | return -EINVAL; |
d556ad4b PO |
2633 | |
2634 | v = ffs(mmrbc) - 10; | |
2635 | ||
2636 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
2637 | if (!cap) | |
7c9e2b1c | 2638 | return -EINVAL; |
d556ad4b | 2639 | |
7c9e2b1c DN |
2640 | if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) |
2641 | return -EINVAL; | |
d556ad4b PO |
2642 | |
2643 | if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21) | |
2644 | return -E2BIG; | |
2645 | ||
7c9e2b1c DN |
2646 | if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) |
2647 | return -EINVAL; | |
d556ad4b PO |
2648 | |
2649 | o = (cmd & PCI_X_CMD_MAX_READ) >> 2; | |
2650 | if (o != v) { | |
2651 | if (v > o && dev->bus && | |
2652 | (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) | |
2653 | return -EIO; | |
2654 | ||
2655 | cmd &= ~PCI_X_CMD_MAX_READ; | |
2656 | cmd |= v << 2; | |
7c9e2b1c DN |
2657 | if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd)) |
2658 | return -EIO; | |
d556ad4b | 2659 | } |
7c9e2b1c | 2660 | return 0; |
d556ad4b PO |
2661 | } |
2662 | EXPORT_SYMBOL(pcix_set_mmrbc); | |
2663 | ||
2664 | /** | |
2665 | * pcie_get_readrq - get PCI Express read request size | |
2666 | * @dev: PCI device to query | |
2667 | * | |
2668 | * Returns maximum memory read request in bytes | |
2669 | * or appropriate error value. | |
2670 | */ | |
2671 | int pcie_get_readrq(struct pci_dev *dev) | |
2672 | { | |
2673 | int ret, cap; | |
2674 | u16 ctl; | |
2675 | ||
06a1cbaf | 2676 | cap = pci_pcie_cap(dev); |
d556ad4b PO |
2677 | if (!cap) |
2678 | return -EINVAL; | |
2679 | ||
2680 | ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); | |
2681 | if (!ret) | |
2682 | ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12); | |
2683 | ||
2684 | return ret; | |
2685 | } | |
2686 | EXPORT_SYMBOL(pcie_get_readrq); | |
2687 | ||
2688 | /** | |
2689 | * pcie_set_readrq - set PCI Express maximum memory read request | |
2690 | * @dev: PCI device to query | |
42e61f4a | 2691 | * @rq: maximum memory read count in bytes |
d556ad4b PO |
2692 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
2693 | * | |
2694 | * If possible sets maximum read byte count | |
2695 | */ | |
2696 | int pcie_set_readrq(struct pci_dev *dev, int rq) | |
2697 | { | |
2698 | int cap, err = -EINVAL; | |
2699 | u16 ctl, v; | |
2700 | ||
229f5afd | 2701 | if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) |
d556ad4b PO |
2702 | goto out; |
2703 | ||
2704 | v = (ffs(rq) - 8) << 12; | |
2705 | ||
06a1cbaf | 2706 | cap = pci_pcie_cap(dev); |
d556ad4b PO |
2707 | if (!cap) |
2708 | goto out; | |
2709 | ||
2710 | err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); | |
2711 | if (err) | |
2712 | goto out; | |
2713 | ||
2714 | if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) { | |
2715 | ctl &= ~PCI_EXP_DEVCTL_READRQ; | |
2716 | ctl |= v; | |
2717 | err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl); | |
2718 | } | |
2719 | ||
2720 | out: | |
2721 | return err; | |
2722 | } | |
2723 | EXPORT_SYMBOL(pcie_set_readrq); | |
2724 | ||
c87deff7 HS |
2725 | /** |
2726 | * pci_select_bars - Make BAR mask from the type of resource | |
f95d882d | 2727 | * @dev: the PCI device for which BAR mask is made |
c87deff7 HS |
2728 | * @flags: resource type mask to be selected |
2729 | * | |
2730 | * This helper routine makes bar mask from the type of resource. | |
2731 | */ | |
2732 | int pci_select_bars(struct pci_dev *dev, unsigned long flags) | |
2733 | { | |
2734 | int i, bars = 0; | |
2735 | for (i = 0; i < PCI_NUM_RESOURCES; i++) | |
2736 | if (pci_resource_flags(dev, i) & flags) | |
2737 | bars |= (1 << i); | |
2738 | return bars; | |
2739 | } | |
2740 | ||
613e7ed6 YZ |
2741 | /** |
2742 | * pci_resource_bar - get position of the BAR associated with a resource | |
2743 | * @dev: the PCI device | |
2744 | * @resno: the resource number | |
2745 | * @type: the BAR type to be filled in | |
2746 | * | |
2747 | * Returns BAR position in config space, or 0 if the BAR is invalid. | |
2748 | */ | |
2749 | int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type) | |
2750 | { | |
d1b054da YZ |
2751 | int reg; |
2752 | ||
613e7ed6 YZ |
2753 | if (resno < PCI_ROM_RESOURCE) { |
2754 | *type = pci_bar_unknown; | |
2755 | return PCI_BASE_ADDRESS_0 + 4 * resno; | |
2756 | } else if (resno == PCI_ROM_RESOURCE) { | |
2757 | *type = pci_bar_mem32; | |
2758 | return dev->rom_base_reg; | |
d1b054da YZ |
2759 | } else if (resno < PCI_BRIDGE_RESOURCES) { |
2760 | /* device specific resource */ | |
2761 | reg = pci_iov_resource_bar(dev, resno, type); | |
2762 | if (reg) | |
2763 | return reg; | |
613e7ed6 YZ |
2764 | } |
2765 | ||
865df576 | 2766 | dev_err(&dev->dev, "BAR %d: invalid resource\n", resno); |
613e7ed6 YZ |
2767 | return 0; |
2768 | } | |
2769 | ||
95a8b6ef MT |
2770 | /* Some architectures require additional programming to enable VGA */ |
2771 | static arch_set_vga_state_t arch_set_vga_state; | |
2772 | ||
2773 | void __init pci_register_set_vga_state(arch_set_vga_state_t func) | |
2774 | { | |
2775 | arch_set_vga_state = func; /* NULL disables */ | |
2776 | } | |
2777 | ||
2778 | static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode, | |
2779 | unsigned int command_bits, bool change_bridge) | |
2780 | { | |
2781 | if (arch_set_vga_state) | |
2782 | return arch_set_vga_state(dev, decode, command_bits, | |
2783 | change_bridge); | |
2784 | return 0; | |
2785 | } | |
2786 | ||
deb2d2ec BH |
2787 | /** |
2788 | * pci_set_vga_state - set VGA decode state on device and parents if requested | |
19eea630 RD |
2789 | * @dev: the PCI device |
2790 | * @decode: true = enable decoding, false = disable decoding | |
2791 | * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY | |
2792 | * @change_bridge: traverse ancestors and change bridges | |
deb2d2ec BH |
2793 | */ |
2794 | int pci_set_vga_state(struct pci_dev *dev, bool decode, | |
2795 | unsigned int command_bits, bool change_bridge) | |
2796 | { | |
2797 | struct pci_bus *bus; | |
2798 | struct pci_dev *bridge; | |
2799 | u16 cmd; | |
95a8b6ef | 2800 | int rc; |
deb2d2ec BH |
2801 | |
2802 | WARN_ON(command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)); | |
2803 | ||
95a8b6ef MT |
2804 | /* ARCH specific VGA enables */ |
2805 | rc = pci_set_vga_state_arch(dev, decode, command_bits, change_bridge); | |
2806 | if (rc) | |
2807 | return rc; | |
2808 | ||
deb2d2ec BH |
2809 | pci_read_config_word(dev, PCI_COMMAND, &cmd); |
2810 | if (decode == true) | |
2811 | cmd |= command_bits; | |
2812 | else | |
2813 | cmd &= ~command_bits; | |
2814 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
2815 | ||
2816 | if (change_bridge == false) | |
2817 | return 0; | |
2818 | ||
2819 | bus = dev->bus; | |
2820 | while (bus) { | |
2821 | bridge = bus->self; | |
2822 | if (bridge) { | |
2823 | pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, | |
2824 | &cmd); | |
2825 | if (decode == true) | |
2826 | cmd |= PCI_BRIDGE_CTL_VGA; | |
2827 | else | |
2828 | cmd &= ~PCI_BRIDGE_CTL_VGA; | |
2829 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, | |
2830 | cmd); | |
2831 | } | |
2832 | bus = bus->parent; | |
2833 | } | |
2834 | return 0; | |
2835 | } | |
2836 | ||
32a9a682 YS |
2837 | #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE |
2838 | static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0}; | |
e9d1e492 | 2839 | static DEFINE_SPINLOCK(resource_alignment_lock); |
32a9a682 YS |
2840 | |
2841 | /** | |
2842 | * pci_specified_resource_alignment - get resource alignment specified by user. | |
2843 | * @dev: the PCI device to get | |
2844 | * | |
2845 | * RETURNS: Resource alignment if it is specified. | |
2846 | * Zero if it is not specified. | |
2847 | */ | |
2848 | resource_size_t pci_specified_resource_alignment(struct pci_dev *dev) | |
2849 | { | |
2850 | int seg, bus, slot, func, align_order, count; | |
2851 | resource_size_t align = 0; | |
2852 | char *p; | |
2853 | ||
2854 | spin_lock(&resource_alignment_lock); | |
2855 | p = resource_alignment_param; | |
2856 | while (*p) { | |
2857 | count = 0; | |
2858 | if (sscanf(p, "%d%n", &align_order, &count) == 1 && | |
2859 | p[count] == '@') { | |
2860 | p += count + 1; | |
2861 | } else { | |
2862 | align_order = -1; | |
2863 | } | |
2864 | if (sscanf(p, "%x:%x:%x.%x%n", | |
2865 | &seg, &bus, &slot, &func, &count) != 4) { | |
2866 | seg = 0; | |
2867 | if (sscanf(p, "%x:%x.%x%n", | |
2868 | &bus, &slot, &func, &count) != 3) { | |
2869 | /* Invalid format */ | |
2870 | printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n", | |
2871 | p); | |
2872 | break; | |
2873 | } | |
2874 | } | |
2875 | p += count; | |
2876 | if (seg == pci_domain_nr(dev->bus) && | |
2877 | bus == dev->bus->number && | |
2878 | slot == PCI_SLOT(dev->devfn) && | |
2879 | func == PCI_FUNC(dev->devfn)) { | |
2880 | if (align_order == -1) { | |
2881 | align = PAGE_SIZE; | |
2882 | } else { | |
2883 | align = 1 << align_order; | |
2884 | } | |
2885 | /* Found */ | |
2886 | break; | |
2887 | } | |
2888 | if (*p != ';' && *p != ',') { | |
2889 | /* End of param or invalid format */ | |
2890 | break; | |
2891 | } | |
2892 | p++; | |
2893 | } | |
2894 | spin_unlock(&resource_alignment_lock); | |
2895 | return align; | |
2896 | } | |
2897 | ||
2898 | /** | |
2899 | * pci_is_reassigndev - check if specified PCI is target device to reassign | |
2900 | * @dev: the PCI device to check | |
2901 | * | |
2902 | * RETURNS: non-zero for PCI device is a target device to reassign, | |
2903 | * or zero is not. | |
2904 | */ | |
2905 | int pci_is_reassigndev(struct pci_dev *dev) | |
2906 | { | |
2907 | return (pci_specified_resource_alignment(dev) != 0); | |
2908 | } | |
2909 | ||
2910 | ssize_t pci_set_resource_alignment_param(const char *buf, size_t count) | |
2911 | { | |
2912 | if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1) | |
2913 | count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1; | |
2914 | spin_lock(&resource_alignment_lock); | |
2915 | strncpy(resource_alignment_param, buf, count); | |
2916 | resource_alignment_param[count] = '\0'; | |
2917 | spin_unlock(&resource_alignment_lock); | |
2918 | return count; | |
2919 | } | |
2920 | ||
2921 | ssize_t pci_get_resource_alignment_param(char *buf, size_t size) | |
2922 | { | |
2923 | size_t count; | |
2924 | spin_lock(&resource_alignment_lock); | |
2925 | count = snprintf(buf, size, "%s", resource_alignment_param); | |
2926 | spin_unlock(&resource_alignment_lock); | |
2927 | return count; | |
2928 | } | |
2929 | ||
2930 | static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf) | |
2931 | { | |
2932 | return pci_get_resource_alignment_param(buf, PAGE_SIZE); | |
2933 | } | |
2934 | ||
2935 | static ssize_t pci_resource_alignment_store(struct bus_type *bus, | |
2936 | const char *buf, size_t count) | |
2937 | { | |
2938 | return pci_set_resource_alignment_param(buf, count); | |
2939 | } | |
2940 | ||
2941 | BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show, | |
2942 | pci_resource_alignment_store); | |
2943 | ||
2944 | static int __init pci_resource_alignment_sysfs_init(void) | |
2945 | { | |
2946 | return bus_create_file(&pci_bus_type, | |
2947 | &bus_attr_resource_alignment); | |
2948 | } | |
2949 | ||
2950 | late_initcall(pci_resource_alignment_sysfs_init); | |
2951 | ||
32a2eea7 JG |
2952 | static void __devinit pci_no_domains(void) |
2953 | { | |
2954 | #ifdef CONFIG_PCI_DOMAINS | |
2955 | pci_domains_supported = 0; | |
2956 | #endif | |
2957 | } | |
2958 | ||
0ef5f8f6 AP |
2959 | /** |
2960 | * pci_ext_cfg_enabled - can we access extended PCI config space? | |
2961 | * @dev: The PCI device of the root bridge. | |
2962 | * | |
2963 | * Returns 1 if we can access PCI extended config space (offsets | |
2964 | * greater than 0xff). This is the default implementation. Architecture | |
2965 | * implementations can override this. | |
2966 | */ | |
2967 | int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev) | |
2968 | { | |
2969 | return 1; | |
2970 | } | |
2971 | ||
2d1c8618 BH |
2972 | void __weak pci_fixup_cardbus(struct pci_bus *bus) |
2973 | { | |
2974 | } | |
2975 | EXPORT_SYMBOL(pci_fixup_cardbus); | |
2976 | ||
ad04d31e | 2977 | static int __init pci_setup(char *str) |
1da177e4 LT |
2978 | { |
2979 | while (str) { | |
2980 | char *k = strchr(str, ','); | |
2981 | if (k) | |
2982 | *k++ = 0; | |
2983 | if (*str && (str = pcibios_setup(str)) && *str) { | |
309e57df MW |
2984 | if (!strcmp(str, "nomsi")) { |
2985 | pci_no_msi(); | |
7f785763 RD |
2986 | } else if (!strcmp(str, "noaer")) { |
2987 | pci_no_aer(); | |
32a2eea7 JG |
2988 | } else if (!strcmp(str, "nodomains")) { |
2989 | pci_no_domains(); | |
4516a618 AN |
2990 | } else if (!strncmp(str, "cbiosize=", 9)) { |
2991 | pci_cardbus_io_size = memparse(str + 9, &str); | |
2992 | } else if (!strncmp(str, "cbmemsize=", 10)) { | |
2993 | pci_cardbus_mem_size = memparse(str + 10, &str); | |
32a9a682 YS |
2994 | } else if (!strncmp(str, "resource_alignment=", 19)) { |
2995 | pci_set_resource_alignment_param(str + 19, | |
2996 | strlen(str + 19)); | |
43c16408 AP |
2997 | } else if (!strncmp(str, "ecrc=", 5)) { |
2998 | pcie_ecrc_get_policy(str + 5); | |
28760489 EB |
2999 | } else if (!strncmp(str, "hpiosize=", 9)) { |
3000 | pci_hotplug_io_size = memparse(str + 9, &str); | |
3001 | } else if (!strncmp(str, "hpmemsize=", 10)) { | |
3002 | pci_hotplug_mem_size = memparse(str + 10, &str); | |
309e57df MW |
3003 | } else { |
3004 | printk(KERN_ERR "PCI: Unknown option `%s'\n", | |
3005 | str); | |
3006 | } | |
1da177e4 LT |
3007 | } |
3008 | str = k; | |
3009 | } | |
0637a70a | 3010 | return 0; |
1da177e4 | 3011 | } |
0637a70a | 3012 | early_param("pci", pci_setup); |
1da177e4 | 3013 | |
0b62e13b | 3014 | EXPORT_SYMBOL(pci_reenable_device); |
b718989d BH |
3015 | EXPORT_SYMBOL(pci_enable_device_io); |
3016 | EXPORT_SYMBOL(pci_enable_device_mem); | |
1da177e4 | 3017 | EXPORT_SYMBOL(pci_enable_device); |
9ac7849e TH |
3018 | EXPORT_SYMBOL(pcim_enable_device); |
3019 | EXPORT_SYMBOL(pcim_pin_device); | |
1da177e4 | 3020 | EXPORT_SYMBOL(pci_disable_device); |
1da177e4 LT |
3021 | EXPORT_SYMBOL(pci_find_capability); |
3022 | EXPORT_SYMBOL(pci_bus_find_capability); | |
3023 | EXPORT_SYMBOL(pci_release_regions); | |
3024 | EXPORT_SYMBOL(pci_request_regions); | |
e8de1481 | 3025 | EXPORT_SYMBOL(pci_request_regions_exclusive); |
1da177e4 LT |
3026 | EXPORT_SYMBOL(pci_release_region); |
3027 | EXPORT_SYMBOL(pci_request_region); | |
e8de1481 | 3028 | EXPORT_SYMBOL(pci_request_region_exclusive); |
c87deff7 HS |
3029 | EXPORT_SYMBOL(pci_release_selected_regions); |
3030 | EXPORT_SYMBOL(pci_request_selected_regions); | |
e8de1481 | 3031 | EXPORT_SYMBOL(pci_request_selected_regions_exclusive); |
1da177e4 | 3032 | EXPORT_SYMBOL(pci_set_master); |
6a479079 | 3033 | EXPORT_SYMBOL(pci_clear_master); |
1da177e4 | 3034 | EXPORT_SYMBOL(pci_set_mwi); |
694625c0 | 3035 | EXPORT_SYMBOL(pci_try_set_mwi); |
1da177e4 | 3036 | EXPORT_SYMBOL(pci_clear_mwi); |
a04ce0ff | 3037 | EXPORT_SYMBOL_GPL(pci_intx); |
1da177e4 LT |
3038 | EXPORT_SYMBOL(pci_assign_resource); |
3039 | EXPORT_SYMBOL(pci_find_parent_resource); | |
c87deff7 | 3040 | EXPORT_SYMBOL(pci_select_bars); |
1da177e4 LT |
3041 | |
3042 | EXPORT_SYMBOL(pci_set_power_state); | |
3043 | EXPORT_SYMBOL(pci_save_state); | |
3044 | EXPORT_SYMBOL(pci_restore_state); | |
e5899e1b | 3045 | EXPORT_SYMBOL(pci_pme_capable); |
5a6c9b60 | 3046 | EXPORT_SYMBOL(pci_pme_active); |
0235c4fc | 3047 | EXPORT_SYMBOL(pci_wake_from_d3); |
e5899e1b | 3048 | EXPORT_SYMBOL(pci_target_state); |
404cc2d8 RW |
3049 | EXPORT_SYMBOL(pci_prepare_to_sleep); |
3050 | EXPORT_SYMBOL(pci_back_from_sleep); | |
f7bdd12d | 3051 | EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state); |