Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/init.h> | |
1da177e4 | 14 | #include <linux/ioport.h> |
1da177e4 LT |
15 | #include <linux/pci.h> |
16 | #include <linux/proc_fs.h> | |
3b7d1921 | 17 | #include <linux/msi.h> |
4fdadebc | 18 | #include <linux/smp.h> |
1da177e4 LT |
19 | |
20 | #include <asm/errno.h> | |
21 | #include <asm/io.h> | |
1da177e4 LT |
22 | |
23 | #include "pci.h" | |
24 | #include "msi.h" | |
25 | ||
1da177e4 | 26 | static int pci_msi_enable = 1; |
1da177e4 | 27 | |
6a9e7f20 AB |
28 | /* Arch hooks */ |
29 | ||
11df1f05 ME |
30 | #ifndef arch_msi_check_device |
31 | int arch_msi_check_device(struct pci_dev *dev, int nvec, int type) | |
6a9e7f20 AB |
32 | { |
33 | return 0; | |
34 | } | |
11df1f05 | 35 | #endif |
6a9e7f20 | 36 | |
11df1f05 ME |
37 | #ifndef arch_setup_msi_irqs |
38 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) | |
6a9e7f20 AB |
39 | { |
40 | struct msi_desc *entry; | |
41 | int ret; | |
42 | ||
1c8d7b0a MW |
43 | /* |
44 | * If an architecture wants to support multiple MSI, it needs to | |
45 | * override arch_setup_msi_irqs() | |
46 | */ | |
47 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
48 | return 1; | |
49 | ||
6a9e7f20 AB |
50 | list_for_each_entry(entry, &dev->msi_list, list) { |
51 | ret = arch_setup_msi_irq(dev, entry); | |
b5fbf533 | 52 | if (ret < 0) |
6a9e7f20 | 53 | return ret; |
b5fbf533 ME |
54 | if (ret > 0) |
55 | return -ENOSPC; | |
6a9e7f20 AB |
56 | } |
57 | ||
58 | return 0; | |
59 | } | |
11df1f05 | 60 | #endif |
6a9e7f20 | 61 | |
11df1f05 ME |
62 | #ifndef arch_teardown_msi_irqs |
63 | void arch_teardown_msi_irqs(struct pci_dev *dev) | |
6a9e7f20 AB |
64 | { |
65 | struct msi_desc *entry; | |
66 | ||
67 | list_for_each_entry(entry, &dev->msi_list, list) { | |
1c8d7b0a MW |
68 | int i, nvec; |
69 | if (entry->irq == 0) | |
70 | continue; | |
71 | nvec = 1 << entry->msi_attrib.multiple; | |
72 | for (i = 0; i < nvec; i++) | |
73 | arch_teardown_msi_irq(entry->irq + i); | |
6a9e7f20 AB |
74 | } |
75 | } | |
11df1f05 | 76 | #endif |
6a9e7f20 | 77 | |
110828c9 | 78 | static void msi_set_enable(struct pci_dev *dev, int pos, int enable) |
b1cbf4e4 | 79 | { |
b1cbf4e4 EB |
80 | u16 control; |
81 | ||
110828c9 | 82 | BUG_ON(!pos); |
b1cbf4e4 | 83 | |
110828c9 MW |
84 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); |
85 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
86 | if (enable) | |
87 | control |= PCI_MSI_FLAGS_ENABLE; | |
88 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
5ca5c02f HS |
89 | } |
90 | ||
b1cbf4e4 EB |
91 | static void msix_set_enable(struct pci_dev *dev, int enable) |
92 | { | |
93 | int pos; | |
94 | u16 control; | |
95 | ||
96 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
97 | if (pos) { | |
98 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
99 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
100 | if (enable) | |
101 | control |= PCI_MSIX_FLAGS_ENABLE; | |
102 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
103 | } | |
104 | } | |
105 | ||
bffac3c5 MW |
106 | static inline __attribute_const__ u32 msi_mask(unsigned x) |
107 | { | |
0b49ec37 MW |
108 | /* Don't shift by >= width of type */ |
109 | if (x >= 5) | |
110 | return 0xffffffff; | |
111 | return (1 << (1 << x)) - 1; | |
bffac3c5 MW |
112 | } |
113 | ||
f2440d9a | 114 | static inline __attribute_const__ u32 msi_capable_mask(u16 control) |
988cbb15 | 115 | { |
f2440d9a MW |
116 | return msi_mask((control >> 1) & 7); |
117 | } | |
988cbb15 | 118 | |
f2440d9a MW |
119 | static inline __attribute_const__ u32 msi_enabled_mask(u16 control) |
120 | { | |
121 | return msi_mask((control >> 4) & 7); | |
988cbb15 MW |
122 | } |
123 | ||
ce6fce42 MW |
124 | /* |
125 | * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to | |
126 | * mask all MSI interrupts by clearing the MSI enable bit does not work | |
127 | * reliably as devices without an INTx disable bit will then generate a | |
128 | * level IRQ which will never be cleared. | |
ce6fce42 | 129 | */ |
f2440d9a | 130 | static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
1da177e4 | 131 | { |
f2440d9a | 132 | u32 mask_bits = desc->masked; |
1da177e4 | 133 | |
f2440d9a MW |
134 | if (!desc->msi_attrib.maskbit) |
135 | return; | |
136 | ||
137 | mask_bits &= ~mask; | |
138 | mask_bits |= flag; | |
139 | pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits); | |
140 | desc->masked = mask_bits; | |
141 | } | |
142 | ||
143 | /* | |
144 | * This internal function does not flush PCI writes to the device. | |
145 | * All users must ensure that they read from the device before either | |
146 | * assuming that the device state is up to date, or returning out of this | |
147 | * file. This saves a few milliseconds when initialising devices with lots | |
148 | * of MSI-X interrupts. | |
149 | */ | |
150 | static void msix_mask_irq(struct msi_desc *desc, u32 flag) | |
151 | { | |
152 | u32 mask_bits = desc->masked; | |
153 | unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
2c21fd4b | 154 | PCI_MSIX_ENTRY_VECTOR_CTRL; |
f2440d9a MW |
155 | mask_bits &= ~1; |
156 | mask_bits |= flag; | |
157 | writel(mask_bits, desc->mask_base + offset); | |
158 | desc->masked = mask_bits; | |
159 | } | |
24d27553 | 160 | |
f2440d9a MW |
161 | static void msi_set_mask_bit(unsigned irq, u32 flag) |
162 | { | |
163 | struct msi_desc *desc = get_irq_msi(irq); | |
24d27553 | 164 | |
f2440d9a MW |
165 | if (desc->msi_attrib.is_msix) { |
166 | msix_mask_irq(desc, flag); | |
167 | readl(desc->mask_base); /* Flush write to device */ | |
168 | } else { | |
1c8d7b0a MW |
169 | unsigned offset = irq - desc->dev->irq; |
170 | msi_mask_irq(desc, 1 << offset, flag << offset); | |
1da177e4 | 171 | } |
f2440d9a MW |
172 | } |
173 | ||
174 | void mask_msi_irq(unsigned int irq) | |
175 | { | |
176 | msi_set_mask_bit(irq, 1); | |
177 | } | |
178 | ||
179 | void unmask_msi_irq(unsigned int irq) | |
180 | { | |
181 | msi_set_mask_bit(irq, 0); | |
1da177e4 LT |
182 | } |
183 | ||
3145e941 | 184 | void read_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg) |
1da177e4 | 185 | { |
3145e941 | 186 | struct msi_desc *entry = get_irq_desc_msi(desc); |
24d27553 MW |
187 | if (entry->msi_attrib.is_msix) { |
188 | void __iomem *base = entry->mask_base + | |
189 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
190 | ||
2c21fd4b HS |
191 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR); |
192 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
193 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA); | |
24d27553 | 194 | } else { |
0366f8f7 EB |
195 | struct pci_dev *dev = entry->dev; |
196 | int pos = entry->msi_attrib.pos; | |
197 | u16 data; | |
198 | ||
199 | pci_read_config_dword(dev, msi_lower_address_reg(pos), | |
200 | &msg->address_lo); | |
201 | if (entry->msi_attrib.is_64) { | |
202 | pci_read_config_dword(dev, msi_upper_address_reg(pos), | |
203 | &msg->address_hi); | |
204 | pci_read_config_word(dev, msi_data_reg(pos, 1), &data); | |
205 | } else { | |
206 | msg->address_hi = 0; | |
cbf5d9e6 | 207 | pci_read_config_word(dev, msi_data_reg(pos, 0), &data); |
0366f8f7 EB |
208 | } |
209 | msg->data = data; | |
0366f8f7 EB |
210 | } |
211 | } | |
1da177e4 | 212 | |
3145e941 | 213 | void read_msi_msg(unsigned int irq, struct msi_msg *msg) |
0366f8f7 | 214 | { |
3145e941 YL |
215 | struct irq_desc *desc = irq_to_desc(irq); |
216 | ||
217 | read_msi_msg_desc(desc, msg); | |
218 | } | |
219 | ||
220 | void write_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg) | |
221 | { | |
222 | struct msi_desc *entry = get_irq_desc_msi(desc); | |
24d27553 MW |
223 | if (entry->msi_attrib.is_msix) { |
224 | void __iomem *base; | |
225 | base = entry->mask_base + | |
226 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
227 | ||
2c21fd4b HS |
228 | writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); |
229 | writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
230 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA); | |
24d27553 | 231 | } else { |
0366f8f7 EB |
232 | struct pci_dev *dev = entry->dev; |
233 | int pos = entry->msi_attrib.pos; | |
1c8d7b0a MW |
234 | u16 msgctl; |
235 | ||
236 | pci_read_config_word(dev, msi_control_reg(pos), &msgctl); | |
237 | msgctl &= ~PCI_MSI_FLAGS_QSIZE; | |
238 | msgctl |= entry->msi_attrib.multiple << 4; | |
239 | pci_write_config_word(dev, msi_control_reg(pos), msgctl); | |
0366f8f7 EB |
240 | |
241 | pci_write_config_dword(dev, msi_lower_address_reg(pos), | |
242 | msg->address_lo); | |
243 | if (entry->msi_attrib.is_64) { | |
244 | pci_write_config_dword(dev, msi_upper_address_reg(pos), | |
245 | msg->address_hi); | |
246 | pci_write_config_word(dev, msi_data_reg(pos, 1), | |
247 | msg->data); | |
248 | } else { | |
249 | pci_write_config_word(dev, msi_data_reg(pos, 0), | |
250 | msg->data); | |
251 | } | |
1da177e4 | 252 | } |
392ee1e6 | 253 | entry->msg = *msg; |
1da177e4 | 254 | } |
0366f8f7 | 255 | |
3145e941 YL |
256 | void write_msi_msg(unsigned int irq, struct msi_msg *msg) |
257 | { | |
258 | struct irq_desc *desc = irq_to_desc(irq); | |
259 | ||
260 | write_msi_msg_desc(desc, msg); | |
261 | } | |
262 | ||
032de8e2 | 263 | static int msi_free_irqs(struct pci_dev* dev); |
c54c1879 | 264 | |
379f5327 | 265 | static struct msi_desc *alloc_msi_entry(struct pci_dev *dev) |
1da177e4 | 266 | { |
379f5327 MW |
267 | struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL); |
268 | if (!desc) | |
1da177e4 LT |
269 | return NULL; |
270 | ||
379f5327 MW |
271 | INIT_LIST_HEAD(&desc->list); |
272 | desc->dev = dev; | |
1da177e4 | 273 | |
379f5327 | 274 | return desc; |
1da177e4 LT |
275 | } |
276 | ||
ba698ad4 DM |
277 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
278 | { | |
279 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) | |
280 | pci_intx(dev, enable); | |
281 | } | |
282 | ||
8fed4b65 | 283 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 284 | { |
392ee1e6 | 285 | int pos; |
41017f0c | 286 | u16 control; |
392ee1e6 | 287 | struct msi_desc *entry; |
41017f0c | 288 | |
b1cbf4e4 EB |
289 | if (!dev->msi_enabled) |
290 | return; | |
291 | ||
392ee1e6 EB |
292 | entry = get_irq_msi(dev->irq); |
293 | pos = entry->msi_attrib.pos; | |
41017f0c | 294 | |
ba698ad4 | 295 | pci_intx_for_msi(dev, 0); |
110828c9 | 296 | msi_set_enable(dev, pos, 0); |
392ee1e6 | 297 | write_msi_msg(dev->irq, &entry->msg); |
392ee1e6 EB |
298 | |
299 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
f2440d9a | 300 | msi_mask_irq(entry, msi_capable_mask(control), entry->masked); |
abad2ec9 | 301 | control &= ~PCI_MSI_FLAGS_QSIZE; |
1c8d7b0a | 302 | control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; |
41017f0c | 303 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
304 | } |
305 | ||
306 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 307 | { |
41017f0c | 308 | int pos; |
41017f0c | 309 | struct msi_desc *entry; |
392ee1e6 | 310 | u16 control; |
41017f0c | 311 | |
ded86d8d EB |
312 | if (!dev->msix_enabled) |
313 | return; | |
f598282f MW |
314 | BUG_ON(list_empty(&dev->msi_list)); |
315 | entry = list_entry(dev->msi_list.next, struct msi_desc, list); | |
316 | pos = entry->msi_attrib.pos; | |
317 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
ded86d8d | 318 | |
41017f0c | 319 | /* route the table */ |
ba698ad4 | 320 | pci_intx_for_msi(dev, 0); |
f598282f MW |
321 | control |= PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL; |
322 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
41017f0c | 323 | |
4aa9bc95 ME |
324 | list_for_each_entry(entry, &dev->msi_list, list) { |
325 | write_msi_msg(entry->irq, &entry->msg); | |
f2440d9a | 326 | msix_mask_irq(entry, entry->masked); |
41017f0c | 327 | } |
41017f0c | 328 | |
392ee1e6 | 329 | control &= ~PCI_MSIX_FLAGS_MASKALL; |
392ee1e6 | 330 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); |
41017f0c | 331 | } |
8fed4b65 ME |
332 | |
333 | void pci_restore_msi_state(struct pci_dev *dev) | |
334 | { | |
335 | __pci_restore_msi_state(dev); | |
336 | __pci_restore_msix_state(dev); | |
337 | } | |
94688cf2 | 338 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
41017f0c | 339 | |
1da177e4 LT |
340 | /** |
341 | * msi_capability_init - configure device's MSI capability structure | |
342 | * @dev: pointer to the pci_dev data structure of MSI device function | |
1c8d7b0a | 343 | * @nvec: number of interrupts to allocate |
1da177e4 | 344 | * |
1c8d7b0a MW |
345 | * Setup the MSI capability structure of the device with the requested |
346 | * number of interrupts. A return value of zero indicates the successful | |
347 | * setup of an entry with the new MSI irq. A negative return value indicates | |
348 | * an error, and a positive return value indicates the number of interrupts | |
349 | * which could have been allocated. | |
350 | */ | |
351 | static int msi_capability_init(struct pci_dev *dev, int nvec) | |
1da177e4 LT |
352 | { |
353 | struct msi_desc *entry; | |
7fe3730d | 354 | int pos, ret; |
1da177e4 | 355 | u16 control; |
f2440d9a | 356 | unsigned mask; |
1da177e4 LT |
357 | |
358 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
110828c9 MW |
359 | msi_set_enable(dev, pos, 0); /* Disable MSI during set up */ |
360 | ||
1da177e4 LT |
361 | pci_read_config_word(dev, msi_control_reg(pos), &control); |
362 | /* MSI Entry Initialization */ | |
379f5327 | 363 | entry = alloc_msi_entry(dev); |
f7feaca7 EB |
364 | if (!entry) |
365 | return -ENOMEM; | |
1ce03373 | 366 | |
24d27553 | 367 | entry->msi_attrib.is_msix = 0; |
0366f8f7 | 368 | entry->msi_attrib.is_64 = is_64bit_address(control); |
1da177e4 LT |
369 | entry->msi_attrib.entry_nr = 0; |
370 | entry->msi_attrib.maskbit = is_mask_bit_support(control); | |
1ce03373 | 371 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ |
0366f8f7 | 372 | entry->msi_attrib.pos = pos; |
f2440d9a | 373 | |
67b5db65 | 374 | entry->mask_pos = msi_mask_reg(pos, entry->msi_attrib.is_64); |
f2440d9a MW |
375 | /* All MSIs are unmasked by default, Mask them all */ |
376 | if (entry->msi_attrib.maskbit) | |
377 | pci_read_config_dword(dev, entry->mask_pos, &entry->masked); | |
378 | mask = msi_capable_mask(control); | |
379 | msi_mask_irq(entry, mask, mask); | |
380 | ||
0dd11f9b | 381 | list_add_tail(&entry->list, &dev->msi_list); |
9c831334 | 382 | |
1da177e4 | 383 | /* Configure MSI capability structure */ |
1c8d7b0a | 384 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); |
7fe3730d | 385 | if (ret) { |
7ba1930d | 386 | msi_mask_irq(entry, mask, ~mask); |
032de8e2 | 387 | msi_free_irqs(dev); |
7fe3730d | 388 | return ret; |
fd58e55f | 389 | } |
f7feaca7 | 390 | |
1da177e4 | 391 | /* Set MSI enabled bits */ |
ba698ad4 | 392 | pci_intx_for_msi(dev, 0); |
110828c9 | 393 | msi_set_enable(dev, pos, 1); |
b1cbf4e4 | 394 | dev->msi_enabled = 1; |
1da177e4 | 395 | |
7fe3730d | 396 | dev->irq = entry->irq; |
1da177e4 LT |
397 | return 0; |
398 | } | |
399 | ||
400 | /** | |
401 | * msix_capability_init - configure device's MSI-X capability | |
402 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
403 | * @entries: pointer to an array of struct msix_entry entries |
404 | * @nvec: number of @entries | |
1da177e4 | 405 | * |
eaae4b3a | 406 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
407 | * single MSI-X irq. A return of zero indicates the successful setup of |
408 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
409 | **/ |
410 | static int msix_capability_init(struct pci_dev *dev, | |
411 | struct msix_entry *entries, int nvec) | |
412 | { | |
4aa9bc95 | 413 | struct msi_desc *entry; |
9c831334 | 414 | int pos, i, j, nr_entries, ret; |
a0454b40 GG |
415 | unsigned long phys_addr; |
416 | u32 table_offset; | |
1da177e4 LT |
417 | u16 control; |
418 | u8 bir; | |
419 | void __iomem *base; | |
420 | ||
421 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
f598282f MW |
422 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); |
423 | ||
424 | /* Ensure MSI-X is disabled while it is set up */ | |
425 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
426 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
427 | ||
1da177e4 | 428 | /* Request & Map MSI-X table region */ |
1da177e4 | 429 | nr_entries = multi_msix_capable(control); |
a0454b40 GG |
430 | |
431 | pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); | |
1da177e4 | 432 | bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); |
a0454b40 GG |
433 | table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; |
434 | phys_addr = pci_resource_start (dev, bir) + table_offset; | |
1da177e4 LT |
435 | base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); |
436 | if (base == NULL) | |
437 | return -ENOMEM; | |
438 | ||
1da177e4 | 439 | for (i = 0; i < nvec; i++) { |
379f5327 | 440 | entry = alloc_msi_entry(dev); |
0d073489 HS |
441 | if (!entry) { |
442 | if (!i) | |
443 | iounmap(base); | |
444 | else | |
445 | msi_free_irqs(dev); | |
446 | /* No enough memory. Don't try again */ | |
447 | return -ENOMEM; | |
448 | } | |
1da177e4 LT |
449 | |
450 | j = entries[i].entry; | |
24d27553 | 451 | entry->msi_attrib.is_msix = 1; |
0366f8f7 | 452 | entry->msi_attrib.is_64 = 1; |
1da177e4 | 453 | entry->msi_attrib.entry_nr = j; |
1ce03373 | 454 | entry->msi_attrib.default_irq = dev->irq; |
0366f8f7 | 455 | entry->msi_attrib.pos = pos; |
1da177e4 | 456 | entry->mask_base = base; |
f7feaca7 | 457 | |
0dd11f9b | 458 | list_add_tail(&entry->list, &dev->msi_list); |
1da177e4 | 459 | } |
9c831334 ME |
460 | |
461 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); | |
b5fbf533 ME |
462 | if (ret < 0) { |
463 | /* If we had some success report the number of irqs | |
464 | * we succeeded in setting up. */ | |
9c831334 ME |
465 | int avail = 0; |
466 | list_for_each_entry(entry, &dev->msi_list, list) { | |
467 | if (entry->irq != 0) { | |
468 | avail++; | |
9c831334 | 469 | } |
1da177e4 | 470 | } |
9c831334 | 471 | |
b5fbf533 ME |
472 | if (avail != 0) |
473 | ret = avail; | |
474 | } | |
032de8e2 | 475 | |
b5fbf533 ME |
476 | if (ret) { |
477 | msi_free_irqs(dev); | |
478 | return ret; | |
1da177e4 | 479 | } |
9c831334 | 480 | |
f598282f MW |
481 | /* |
482 | * Some devices require MSI-X to be enabled before we can touch the | |
483 | * MSI-X registers. We need to mask all the vectors to prevent | |
484 | * interrupts coming in before they're fully set up. | |
485 | */ | |
486 | control |= PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE; | |
487 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
488 | ||
9c831334 ME |
489 | i = 0; |
490 | list_for_each_entry(entry, &dev->msi_list, list) { | |
491 | entries[i].vector = entry->irq; | |
492 | set_irq_msi(entry->irq, entry); | |
f598282f MW |
493 | j = entries[i].entry; |
494 | entry->masked = readl(base + j * PCI_MSIX_ENTRY_SIZE + | |
2c21fd4b | 495 | PCI_MSIX_ENTRY_VECTOR_CTRL); |
f598282f | 496 | msix_mask_irq(entry, 1); |
9c831334 ME |
497 | i++; |
498 | } | |
f598282f MW |
499 | |
500 | /* Set MSI-X enabled bits and unmask the function */ | |
ba698ad4 | 501 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 502 | dev->msix_enabled = 1; |
1da177e4 | 503 | |
f598282f MW |
504 | control &= ~PCI_MSIX_FLAGS_MASKALL; |
505 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
8d181018 | 506 | |
1da177e4 LT |
507 | return 0; |
508 | } | |
509 | ||
24334a12 | 510 | /** |
17bbc12a | 511 | * pci_msi_check_device - check whether MSI may be enabled on a device |
24334a12 | 512 | * @dev: pointer to the pci_dev data structure of MSI device function |
c9953a73 | 513 | * @nvec: how many MSIs have been requested ? |
b1e2303d | 514 | * @type: are we checking for MSI or MSI-X ? |
24334a12 | 515 | * |
0306ebfa | 516 | * Look at global flags, the device itself, and its parent busses |
17bbc12a ME |
517 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
518 | * supported return 0, else return an error code. | |
24334a12 | 519 | **/ |
c9953a73 | 520 | static int pci_msi_check_device(struct pci_dev* dev, int nvec, int type) |
24334a12 BG |
521 | { |
522 | struct pci_bus *bus; | |
c9953a73 | 523 | int ret; |
24334a12 | 524 | |
0306ebfa | 525 | /* MSI must be globally enabled and supported by the device */ |
24334a12 BG |
526 | if (!pci_msi_enable || !dev || dev->no_msi) |
527 | return -EINVAL; | |
528 | ||
314e77b3 ME |
529 | /* |
530 | * You can't ask to have 0 or less MSIs configured. | |
531 | * a) it's stupid .. | |
532 | * b) the list manipulation code assumes nvec >= 1. | |
533 | */ | |
534 | if (nvec < 1) | |
535 | return -ERANGE; | |
536 | ||
0306ebfa BG |
537 | /* Any bridge which does NOT route MSI transactions from it's |
538 | * secondary bus to it's primary bus must set NO_MSI flag on | |
539 | * the secondary pci_bus. | |
540 | * We expect only arch-specific PCI host bus controller driver | |
541 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
542 | */ | |
24334a12 BG |
543 | for (bus = dev->bus; bus; bus = bus->parent) |
544 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
545 | return -EINVAL; | |
546 | ||
c9953a73 ME |
547 | ret = arch_msi_check_device(dev, nvec, type); |
548 | if (ret) | |
549 | return ret; | |
550 | ||
b1e2303d ME |
551 | if (!pci_find_capability(dev, type)) |
552 | return -EINVAL; | |
553 | ||
24334a12 BG |
554 | return 0; |
555 | } | |
556 | ||
1da177e4 | 557 | /** |
1c8d7b0a MW |
558 | * pci_enable_msi_block - configure device's MSI capability structure |
559 | * @dev: device to configure | |
560 | * @nvec: number of interrupts to configure | |
1da177e4 | 561 | * |
1c8d7b0a MW |
562 | * Allocate IRQs for a device with the MSI capability. |
563 | * This function returns a negative errno if an error occurs. If it | |
564 | * is unable to allocate the number of interrupts requested, it returns | |
565 | * the number of interrupts it might be able to allocate. If it successfully | |
566 | * allocates at least the number of interrupts requested, it returns 0 and | |
567 | * updates the @dev's irq member to the lowest new interrupt number; the | |
568 | * other interrupt numbers allocated to this device are consecutive. | |
569 | */ | |
570 | int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec) | |
1da177e4 | 571 | { |
1c8d7b0a MW |
572 | int status, pos, maxvec; |
573 | u16 msgctl; | |
574 | ||
575 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
576 | if (!pos) | |
577 | return -EINVAL; | |
578 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); | |
579 | maxvec = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); | |
580 | if (nvec > maxvec) | |
581 | return maxvec; | |
1da177e4 | 582 | |
1c8d7b0a | 583 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI); |
c9953a73 ME |
584 | if (status) |
585 | return status; | |
1da177e4 | 586 | |
ded86d8d | 587 | WARN_ON(!!dev->msi_enabled); |
1da177e4 | 588 | |
1c8d7b0a | 589 | /* Check whether driver already requested MSI-X irqs */ |
b1cbf4e4 | 590 | if (dev->msix_enabled) { |
80ccba11 BH |
591 | dev_info(&dev->dev, "can't enable MSI " |
592 | "(MSI-X already enabled)\n"); | |
b1cbf4e4 | 593 | return -EINVAL; |
1da177e4 | 594 | } |
1c8d7b0a MW |
595 | |
596 | status = msi_capability_init(dev, nvec); | |
1da177e4 LT |
597 | return status; |
598 | } | |
1c8d7b0a | 599 | EXPORT_SYMBOL(pci_enable_msi_block); |
1da177e4 | 600 | |
f2440d9a | 601 | void pci_msi_shutdown(struct pci_dev *dev) |
1da177e4 | 602 | { |
f2440d9a MW |
603 | struct msi_desc *desc; |
604 | u32 mask; | |
605 | u16 ctrl; | |
110828c9 | 606 | unsigned pos; |
1da177e4 | 607 | |
128bc5fc | 608 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
609 | return; |
610 | ||
110828c9 MW |
611 | BUG_ON(list_empty(&dev->msi_list)); |
612 | desc = list_first_entry(&dev->msi_list, struct msi_desc, list); | |
613 | pos = desc->msi_attrib.pos; | |
614 | ||
615 | msi_set_enable(dev, pos, 0); | |
ba698ad4 | 616 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 617 | dev->msi_enabled = 0; |
7bd007e4 | 618 | |
110828c9 | 619 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &ctrl); |
f2440d9a MW |
620 | mask = msi_capable_mask(ctrl); |
621 | msi_mask_irq(desc, mask, ~mask); | |
e387b9ee ME |
622 | |
623 | /* Restore dev->irq to its default pin-assertion irq */ | |
f2440d9a | 624 | dev->irq = desc->msi_attrib.default_irq; |
d52877c7 | 625 | } |
24d27553 | 626 | |
d52877c7 YL |
627 | void pci_disable_msi(struct pci_dev* dev) |
628 | { | |
629 | struct msi_desc *entry; | |
630 | ||
631 | if (!pci_msi_enable || !dev || !dev->msi_enabled) | |
632 | return; | |
633 | ||
634 | pci_msi_shutdown(dev); | |
635 | ||
636 | entry = list_entry(dev->msi_list.next, struct msi_desc, list); | |
379f5327 | 637 | if (entry->msi_attrib.is_msix) |
d52877c7 YL |
638 | return; |
639 | ||
640 | msi_free_irqs(dev); | |
1da177e4 | 641 | } |
4cc086fa | 642 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 643 | |
032de8e2 | 644 | static int msi_free_irqs(struct pci_dev* dev) |
1da177e4 | 645 | { |
032de8e2 | 646 | struct msi_desc *entry, *tmp; |
7ede9c1f | 647 | |
b3b7cc7b | 648 | list_for_each_entry(entry, &dev->msi_list, list) { |
1c8d7b0a MW |
649 | int i, nvec; |
650 | if (!entry->irq) | |
651 | continue; | |
652 | nvec = 1 << entry->msi_attrib.multiple; | |
653 | for (i = 0; i < nvec; i++) | |
654 | BUG_ON(irq_has_action(entry->irq + i)); | |
b3b7cc7b | 655 | } |
1da177e4 | 656 | |
032de8e2 | 657 | arch_teardown_msi_irqs(dev); |
1da177e4 | 658 | |
032de8e2 | 659 | list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) { |
24d27553 | 660 | if (entry->msi_attrib.is_msix) { |
2af5066f | 661 | msix_mask_irq(entry, 1); |
78b7611c EB |
662 | if (list_is_last(&entry->list, &dev->msi_list)) |
663 | iounmap(entry->mask_base); | |
032de8e2 ME |
664 | } |
665 | list_del(&entry->list); | |
666 | kfree(entry); | |
1da177e4 LT |
667 | } |
668 | ||
669 | return 0; | |
670 | } | |
671 | ||
a52e2e35 RW |
672 | /** |
673 | * pci_msix_table_size - return the number of device's MSI-X table entries | |
674 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
675 | */ | |
676 | int pci_msix_table_size(struct pci_dev *dev) | |
677 | { | |
678 | int pos; | |
679 | u16 control; | |
680 | ||
681 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
682 | if (!pos) | |
683 | return 0; | |
684 | ||
685 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
686 | return multi_msix_capable(control); | |
687 | } | |
688 | ||
1da177e4 LT |
689 | /** |
690 | * pci_enable_msix - configure device's MSI-X capability structure | |
691 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 692 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 693 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
694 | * |
695 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 696 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
697 | * MSI-X mode enabled on its hardware device function. A return of zero |
698 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 699 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 700 | * Or a return of > 0 indicates that driver request is exceeding the number |
57fbf52c MT |
701 | * of irqs or MSI-X vectors available. Driver should use the returned value to |
702 | * re-send its request. | |
1da177e4 LT |
703 | **/ |
704 | int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec) | |
705 | { | |
a52e2e35 | 706 | int status, nr_entries; |
ded86d8d | 707 | int i, j; |
1da177e4 | 708 | |
c9953a73 | 709 | if (!entries) |
1da177e4 LT |
710 | return -EINVAL; |
711 | ||
c9953a73 ME |
712 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX); |
713 | if (status) | |
714 | return status; | |
715 | ||
a52e2e35 | 716 | nr_entries = pci_msix_table_size(dev); |
1da177e4 | 717 | if (nvec > nr_entries) |
57fbf52c | 718 | return nr_entries; |
1da177e4 LT |
719 | |
720 | /* Check for any invalid entries */ | |
721 | for (i = 0; i < nvec; i++) { | |
722 | if (entries[i].entry >= nr_entries) | |
723 | return -EINVAL; /* invalid entry */ | |
724 | for (j = i + 1; j < nvec; j++) { | |
725 | if (entries[i].entry == entries[j].entry) | |
726 | return -EINVAL; /* duplicate entry */ | |
727 | } | |
728 | } | |
ded86d8d | 729 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 730 | |
1ce03373 | 731 | /* Check whether driver already requested for MSI irq */ |
b1cbf4e4 | 732 | if (dev->msi_enabled) { |
80ccba11 BH |
733 | dev_info(&dev->dev, "can't enable MSI-X " |
734 | "(MSI IRQ already assigned)\n"); | |
1da177e4 LT |
735 | return -EINVAL; |
736 | } | |
1da177e4 | 737 | status = msix_capability_init(dev, entries, nvec); |
1da177e4 LT |
738 | return status; |
739 | } | |
4cc086fa | 740 | EXPORT_SYMBOL(pci_enable_msix); |
1da177e4 | 741 | |
fc4afc7b | 742 | static void msix_free_all_irqs(struct pci_dev *dev) |
1da177e4 | 743 | { |
032de8e2 | 744 | msi_free_irqs(dev); |
fc4afc7b ME |
745 | } |
746 | ||
d52877c7 | 747 | void pci_msix_shutdown(struct pci_dev* dev) |
fc4afc7b | 748 | { |
128bc5fc | 749 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
750 | return; |
751 | ||
b1cbf4e4 | 752 | msix_set_enable(dev, 0); |
ba698ad4 | 753 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 754 | dev->msix_enabled = 0; |
d52877c7 YL |
755 | } |
756 | void pci_disable_msix(struct pci_dev* dev) | |
757 | { | |
758 | if (!pci_msi_enable || !dev || !dev->msix_enabled) | |
759 | return; | |
760 | ||
761 | pci_msix_shutdown(dev); | |
7bd007e4 | 762 | |
fc4afc7b | 763 | msix_free_all_irqs(dev); |
1da177e4 | 764 | } |
4cc086fa | 765 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 LT |
766 | |
767 | /** | |
1ce03373 | 768 | * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state |
1da177e4 LT |
769 | * @dev: pointer to the pci_dev data structure of MSI(X) device function |
770 | * | |
eaae4b3a | 771 | * Being called during hotplug remove, from which the device function |
1ce03373 | 772 | * is hot-removed. All previous assigned MSI/MSI-X irqs, if |
1da177e4 LT |
773 | * allocated for this device function, are reclaimed to unused state, |
774 | * which may be used later on. | |
775 | **/ | |
776 | void msi_remove_pci_irq_vectors(struct pci_dev* dev) | |
777 | { | |
1da177e4 LT |
778 | if (!pci_msi_enable || !dev) |
779 | return; | |
780 | ||
032de8e2 ME |
781 | if (dev->msi_enabled) |
782 | msi_free_irqs(dev); | |
1da177e4 | 783 | |
fc4afc7b ME |
784 | if (dev->msix_enabled) |
785 | msix_free_all_irqs(dev); | |
1da177e4 LT |
786 | } |
787 | ||
309e57df MW |
788 | void pci_no_msi(void) |
789 | { | |
790 | pci_msi_enable = 0; | |
791 | } | |
c9953a73 | 792 | |
07ae95f9 AP |
793 | /** |
794 | * pci_msi_enabled - is MSI enabled? | |
795 | * | |
796 | * Returns true if MSI has not been disabled by the command-line option | |
797 | * pci=nomsi. | |
798 | **/ | |
799 | int pci_msi_enabled(void) | |
d389fec6 | 800 | { |
07ae95f9 | 801 | return pci_msi_enable; |
d389fec6 | 802 | } |
07ae95f9 | 803 | EXPORT_SYMBOL(pci_msi_enabled); |
d389fec6 | 804 | |
07ae95f9 | 805 | void pci_msi_init_pci_dev(struct pci_dev *dev) |
d389fec6 | 806 | { |
07ae95f9 | 807 | INIT_LIST_HEAD(&dev->msi_list); |
d389fec6 | 808 | } |