Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/init.h> | |
1da177e4 | 14 | #include <linux/ioport.h> |
1da177e4 LT |
15 | #include <linux/pci.h> |
16 | #include <linux/proc_fs.h> | |
3b7d1921 | 17 | #include <linux/msi.h> |
4fdadebc | 18 | #include <linux/smp.h> |
1da177e4 LT |
19 | |
20 | #include <asm/errno.h> | |
21 | #include <asm/io.h> | |
1da177e4 LT |
22 | |
23 | #include "pci.h" | |
24 | #include "msi.h" | |
25 | ||
1da177e4 | 26 | static int pci_msi_enable = 1; |
1da177e4 | 27 | |
6a9e7f20 AB |
28 | /* Arch hooks */ |
29 | ||
11df1f05 ME |
30 | #ifndef arch_msi_check_device |
31 | int arch_msi_check_device(struct pci_dev *dev, int nvec, int type) | |
6a9e7f20 AB |
32 | { |
33 | return 0; | |
34 | } | |
11df1f05 | 35 | #endif |
6a9e7f20 | 36 | |
11df1f05 ME |
37 | #ifndef arch_setup_msi_irqs |
38 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) | |
6a9e7f20 AB |
39 | { |
40 | struct msi_desc *entry; | |
41 | int ret; | |
42 | ||
1c8d7b0a MW |
43 | /* |
44 | * If an architecture wants to support multiple MSI, it needs to | |
45 | * override arch_setup_msi_irqs() | |
46 | */ | |
47 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
48 | return 1; | |
49 | ||
6a9e7f20 AB |
50 | list_for_each_entry(entry, &dev->msi_list, list) { |
51 | ret = arch_setup_msi_irq(dev, entry); | |
b5fbf533 | 52 | if (ret < 0) |
6a9e7f20 | 53 | return ret; |
b5fbf533 ME |
54 | if (ret > 0) |
55 | return -ENOSPC; | |
6a9e7f20 AB |
56 | } |
57 | ||
58 | return 0; | |
59 | } | |
11df1f05 | 60 | #endif |
6a9e7f20 | 61 | |
11df1f05 ME |
62 | #ifndef arch_teardown_msi_irqs |
63 | void arch_teardown_msi_irqs(struct pci_dev *dev) | |
6a9e7f20 AB |
64 | { |
65 | struct msi_desc *entry; | |
66 | ||
67 | list_for_each_entry(entry, &dev->msi_list, list) { | |
1c8d7b0a MW |
68 | int i, nvec; |
69 | if (entry->irq == 0) | |
70 | continue; | |
71 | nvec = 1 << entry->msi_attrib.multiple; | |
72 | for (i = 0; i < nvec; i++) | |
73 | arch_teardown_msi_irq(entry->irq + i); | |
6a9e7f20 AB |
74 | } |
75 | } | |
11df1f05 | 76 | #endif |
6a9e7f20 | 77 | |
110828c9 | 78 | static void msi_set_enable(struct pci_dev *dev, int pos, int enable) |
b1cbf4e4 | 79 | { |
b1cbf4e4 EB |
80 | u16 control; |
81 | ||
110828c9 | 82 | BUG_ON(!pos); |
b1cbf4e4 | 83 | |
110828c9 MW |
84 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); |
85 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
86 | if (enable) | |
87 | control |= PCI_MSI_FLAGS_ENABLE; | |
88 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
5ca5c02f HS |
89 | } |
90 | ||
b1cbf4e4 EB |
91 | static void msix_set_enable(struct pci_dev *dev, int enable) |
92 | { | |
93 | int pos; | |
94 | u16 control; | |
95 | ||
96 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
97 | if (pos) { | |
98 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
99 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
100 | if (enable) | |
101 | control |= PCI_MSIX_FLAGS_ENABLE; | |
102 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
103 | } | |
104 | } | |
105 | ||
bffac3c5 MW |
106 | static inline __attribute_const__ u32 msi_mask(unsigned x) |
107 | { | |
0b49ec37 MW |
108 | /* Don't shift by >= width of type */ |
109 | if (x >= 5) | |
110 | return 0xffffffff; | |
111 | return (1 << (1 << x)) - 1; | |
bffac3c5 MW |
112 | } |
113 | ||
f2440d9a | 114 | static inline __attribute_const__ u32 msi_capable_mask(u16 control) |
988cbb15 | 115 | { |
f2440d9a MW |
116 | return msi_mask((control >> 1) & 7); |
117 | } | |
988cbb15 | 118 | |
f2440d9a MW |
119 | static inline __attribute_const__ u32 msi_enabled_mask(u16 control) |
120 | { | |
121 | return msi_mask((control >> 4) & 7); | |
988cbb15 MW |
122 | } |
123 | ||
ce6fce42 MW |
124 | /* |
125 | * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to | |
126 | * mask all MSI interrupts by clearing the MSI enable bit does not work | |
127 | * reliably as devices without an INTx disable bit will then generate a | |
128 | * level IRQ which will never be cleared. | |
ce6fce42 | 129 | */ |
12abb8ba | 130 | static u32 __msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
1da177e4 | 131 | { |
f2440d9a | 132 | u32 mask_bits = desc->masked; |
1da177e4 | 133 | |
f2440d9a | 134 | if (!desc->msi_attrib.maskbit) |
12abb8ba | 135 | return 0; |
f2440d9a MW |
136 | |
137 | mask_bits &= ~mask; | |
138 | mask_bits |= flag; | |
139 | pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits); | |
12abb8ba HS |
140 | |
141 | return mask_bits; | |
142 | } | |
143 | ||
144 | static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) | |
145 | { | |
146 | desc->masked = __msi_mask_irq(desc, mask, flag); | |
f2440d9a MW |
147 | } |
148 | ||
149 | /* | |
150 | * This internal function does not flush PCI writes to the device. | |
151 | * All users must ensure that they read from the device before either | |
152 | * assuming that the device state is up to date, or returning out of this | |
153 | * file. This saves a few milliseconds when initialising devices with lots | |
154 | * of MSI-X interrupts. | |
155 | */ | |
12abb8ba | 156 | static u32 __msix_mask_irq(struct msi_desc *desc, u32 flag) |
f2440d9a MW |
157 | { |
158 | u32 mask_bits = desc->masked; | |
159 | unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
2c21fd4b | 160 | PCI_MSIX_ENTRY_VECTOR_CTRL; |
f2440d9a MW |
161 | mask_bits &= ~1; |
162 | mask_bits |= flag; | |
163 | writel(mask_bits, desc->mask_base + offset); | |
12abb8ba HS |
164 | |
165 | return mask_bits; | |
166 | } | |
167 | ||
168 | static void msix_mask_irq(struct msi_desc *desc, u32 flag) | |
169 | { | |
170 | desc->masked = __msix_mask_irq(desc, flag); | |
f2440d9a | 171 | } |
24d27553 | 172 | |
f2440d9a MW |
173 | static void msi_set_mask_bit(unsigned irq, u32 flag) |
174 | { | |
175 | struct msi_desc *desc = get_irq_msi(irq); | |
24d27553 | 176 | |
f2440d9a MW |
177 | if (desc->msi_attrib.is_msix) { |
178 | msix_mask_irq(desc, flag); | |
179 | readl(desc->mask_base); /* Flush write to device */ | |
180 | } else { | |
1c8d7b0a MW |
181 | unsigned offset = irq - desc->dev->irq; |
182 | msi_mask_irq(desc, 1 << offset, flag << offset); | |
1da177e4 | 183 | } |
f2440d9a MW |
184 | } |
185 | ||
186 | void mask_msi_irq(unsigned int irq) | |
187 | { | |
188 | msi_set_mask_bit(irq, 1); | |
189 | } | |
190 | ||
191 | void unmask_msi_irq(unsigned int irq) | |
192 | { | |
193 | msi_set_mask_bit(irq, 0); | |
1da177e4 LT |
194 | } |
195 | ||
3145e941 | 196 | void read_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg) |
1da177e4 | 197 | { |
3145e941 | 198 | struct msi_desc *entry = get_irq_desc_msi(desc); |
24d27553 MW |
199 | if (entry->msi_attrib.is_msix) { |
200 | void __iomem *base = entry->mask_base + | |
201 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
202 | ||
2c21fd4b HS |
203 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR); |
204 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
205 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA); | |
24d27553 | 206 | } else { |
0366f8f7 EB |
207 | struct pci_dev *dev = entry->dev; |
208 | int pos = entry->msi_attrib.pos; | |
209 | u16 data; | |
210 | ||
211 | pci_read_config_dword(dev, msi_lower_address_reg(pos), | |
212 | &msg->address_lo); | |
213 | if (entry->msi_attrib.is_64) { | |
214 | pci_read_config_dword(dev, msi_upper_address_reg(pos), | |
215 | &msg->address_hi); | |
216 | pci_read_config_word(dev, msi_data_reg(pos, 1), &data); | |
217 | } else { | |
218 | msg->address_hi = 0; | |
cbf5d9e6 | 219 | pci_read_config_word(dev, msi_data_reg(pos, 0), &data); |
0366f8f7 EB |
220 | } |
221 | msg->data = data; | |
0366f8f7 EB |
222 | } |
223 | } | |
1da177e4 | 224 | |
3145e941 | 225 | void read_msi_msg(unsigned int irq, struct msi_msg *msg) |
0366f8f7 | 226 | { |
3145e941 YL |
227 | struct irq_desc *desc = irq_to_desc(irq); |
228 | ||
229 | read_msi_msg_desc(desc, msg); | |
230 | } | |
231 | ||
232 | void write_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg) | |
233 | { | |
234 | struct msi_desc *entry = get_irq_desc_msi(desc); | |
24d27553 MW |
235 | if (entry->msi_attrib.is_msix) { |
236 | void __iomem *base; | |
237 | base = entry->mask_base + | |
238 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
239 | ||
2c21fd4b HS |
240 | writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); |
241 | writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
242 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA); | |
24d27553 | 243 | } else { |
0366f8f7 EB |
244 | struct pci_dev *dev = entry->dev; |
245 | int pos = entry->msi_attrib.pos; | |
1c8d7b0a MW |
246 | u16 msgctl; |
247 | ||
248 | pci_read_config_word(dev, msi_control_reg(pos), &msgctl); | |
249 | msgctl &= ~PCI_MSI_FLAGS_QSIZE; | |
250 | msgctl |= entry->msi_attrib.multiple << 4; | |
251 | pci_write_config_word(dev, msi_control_reg(pos), msgctl); | |
0366f8f7 EB |
252 | |
253 | pci_write_config_dword(dev, msi_lower_address_reg(pos), | |
254 | msg->address_lo); | |
255 | if (entry->msi_attrib.is_64) { | |
256 | pci_write_config_dword(dev, msi_upper_address_reg(pos), | |
257 | msg->address_hi); | |
258 | pci_write_config_word(dev, msi_data_reg(pos, 1), | |
259 | msg->data); | |
260 | } else { | |
261 | pci_write_config_word(dev, msi_data_reg(pos, 0), | |
262 | msg->data); | |
263 | } | |
1da177e4 | 264 | } |
392ee1e6 | 265 | entry->msg = *msg; |
1da177e4 | 266 | } |
0366f8f7 | 267 | |
3145e941 YL |
268 | void write_msi_msg(unsigned int irq, struct msi_msg *msg) |
269 | { | |
270 | struct irq_desc *desc = irq_to_desc(irq); | |
271 | ||
272 | write_msi_msg_desc(desc, msg); | |
273 | } | |
274 | ||
f56e4481 HS |
275 | static void free_msi_irqs(struct pci_dev *dev) |
276 | { | |
277 | struct msi_desc *entry, *tmp; | |
278 | ||
279 | list_for_each_entry(entry, &dev->msi_list, list) { | |
280 | int i, nvec; | |
281 | if (!entry->irq) | |
282 | continue; | |
283 | nvec = 1 << entry->msi_attrib.multiple; | |
284 | for (i = 0; i < nvec; i++) | |
285 | BUG_ON(irq_has_action(entry->irq + i)); | |
286 | } | |
287 | ||
288 | arch_teardown_msi_irqs(dev); | |
289 | ||
290 | list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) { | |
291 | if (entry->msi_attrib.is_msix) { | |
292 | if (list_is_last(&entry->list, &dev->msi_list)) | |
293 | iounmap(entry->mask_base); | |
294 | } | |
295 | list_del(&entry->list); | |
296 | kfree(entry); | |
297 | } | |
298 | } | |
c54c1879 | 299 | |
379f5327 | 300 | static struct msi_desc *alloc_msi_entry(struct pci_dev *dev) |
1da177e4 | 301 | { |
379f5327 MW |
302 | struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL); |
303 | if (!desc) | |
1da177e4 LT |
304 | return NULL; |
305 | ||
379f5327 MW |
306 | INIT_LIST_HEAD(&desc->list); |
307 | desc->dev = dev; | |
1da177e4 | 308 | |
379f5327 | 309 | return desc; |
1da177e4 LT |
310 | } |
311 | ||
ba698ad4 DM |
312 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
313 | { | |
314 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) | |
315 | pci_intx(dev, enable); | |
316 | } | |
317 | ||
8fed4b65 | 318 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 319 | { |
392ee1e6 | 320 | int pos; |
41017f0c | 321 | u16 control; |
392ee1e6 | 322 | struct msi_desc *entry; |
41017f0c | 323 | |
b1cbf4e4 EB |
324 | if (!dev->msi_enabled) |
325 | return; | |
326 | ||
392ee1e6 EB |
327 | entry = get_irq_msi(dev->irq); |
328 | pos = entry->msi_attrib.pos; | |
41017f0c | 329 | |
ba698ad4 | 330 | pci_intx_for_msi(dev, 0); |
110828c9 | 331 | msi_set_enable(dev, pos, 0); |
392ee1e6 | 332 | write_msi_msg(dev->irq, &entry->msg); |
392ee1e6 EB |
333 | |
334 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
f2440d9a | 335 | msi_mask_irq(entry, msi_capable_mask(control), entry->masked); |
abad2ec9 | 336 | control &= ~PCI_MSI_FLAGS_QSIZE; |
1c8d7b0a | 337 | control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; |
41017f0c | 338 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
339 | } |
340 | ||
341 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 342 | { |
41017f0c | 343 | int pos; |
41017f0c | 344 | struct msi_desc *entry; |
392ee1e6 | 345 | u16 control; |
41017f0c | 346 | |
ded86d8d EB |
347 | if (!dev->msix_enabled) |
348 | return; | |
f598282f | 349 | BUG_ON(list_empty(&dev->msi_list)); |
9cc8d548 | 350 | entry = list_first_entry(&dev->msi_list, struct msi_desc, list); |
f598282f MW |
351 | pos = entry->msi_attrib.pos; |
352 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
ded86d8d | 353 | |
41017f0c | 354 | /* route the table */ |
ba698ad4 | 355 | pci_intx_for_msi(dev, 0); |
f598282f MW |
356 | control |= PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL; |
357 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
41017f0c | 358 | |
4aa9bc95 ME |
359 | list_for_each_entry(entry, &dev->msi_list, list) { |
360 | write_msi_msg(entry->irq, &entry->msg); | |
f2440d9a | 361 | msix_mask_irq(entry, entry->masked); |
41017f0c | 362 | } |
41017f0c | 363 | |
392ee1e6 | 364 | control &= ~PCI_MSIX_FLAGS_MASKALL; |
392ee1e6 | 365 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); |
41017f0c | 366 | } |
8fed4b65 ME |
367 | |
368 | void pci_restore_msi_state(struct pci_dev *dev) | |
369 | { | |
370 | __pci_restore_msi_state(dev); | |
371 | __pci_restore_msix_state(dev); | |
372 | } | |
94688cf2 | 373 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
41017f0c | 374 | |
1da177e4 LT |
375 | /** |
376 | * msi_capability_init - configure device's MSI capability structure | |
377 | * @dev: pointer to the pci_dev data structure of MSI device function | |
1c8d7b0a | 378 | * @nvec: number of interrupts to allocate |
1da177e4 | 379 | * |
1c8d7b0a MW |
380 | * Setup the MSI capability structure of the device with the requested |
381 | * number of interrupts. A return value of zero indicates the successful | |
382 | * setup of an entry with the new MSI irq. A negative return value indicates | |
383 | * an error, and a positive return value indicates the number of interrupts | |
384 | * which could have been allocated. | |
385 | */ | |
386 | static int msi_capability_init(struct pci_dev *dev, int nvec) | |
1da177e4 LT |
387 | { |
388 | struct msi_desc *entry; | |
7fe3730d | 389 | int pos, ret; |
1da177e4 | 390 | u16 control; |
f2440d9a | 391 | unsigned mask; |
1da177e4 LT |
392 | |
393 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
110828c9 MW |
394 | msi_set_enable(dev, pos, 0); /* Disable MSI during set up */ |
395 | ||
1da177e4 LT |
396 | pci_read_config_word(dev, msi_control_reg(pos), &control); |
397 | /* MSI Entry Initialization */ | |
379f5327 | 398 | entry = alloc_msi_entry(dev); |
f7feaca7 EB |
399 | if (!entry) |
400 | return -ENOMEM; | |
1ce03373 | 401 | |
24d27553 | 402 | entry->msi_attrib.is_msix = 0; |
0366f8f7 | 403 | entry->msi_attrib.is_64 = is_64bit_address(control); |
1da177e4 LT |
404 | entry->msi_attrib.entry_nr = 0; |
405 | entry->msi_attrib.maskbit = is_mask_bit_support(control); | |
1ce03373 | 406 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ |
0366f8f7 | 407 | entry->msi_attrib.pos = pos; |
f2440d9a | 408 | |
67b5db65 | 409 | entry->mask_pos = msi_mask_reg(pos, entry->msi_attrib.is_64); |
f2440d9a MW |
410 | /* All MSIs are unmasked by default, Mask them all */ |
411 | if (entry->msi_attrib.maskbit) | |
412 | pci_read_config_dword(dev, entry->mask_pos, &entry->masked); | |
413 | mask = msi_capable_mask(control); | |
414 | msi_mask_irq(entry, mask, mask); | |
415 | ||
0dd11f9b | 416 | list_add_tail(&entry->list, &dev->msi_list); |
9c831334 | 417 | |
1da177e4 | 418 | /* Configure MSI capability structure */ |
1c8d7b0a | 419 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); |
7fe3730d | 420 | if (ret) { |
7ba1930d | 421 | msi_mask_irq(entry, mask, ~mask); |
f56e4481 | 422 | free_msi_irqs(dev); |
7fe3730d | 423 | return ret; |
fd58e55f | 424 | } |
f7feaca7 | 425 | |
1da177e4 | 426 | /* Set MSI enabled bits */ |
ba698ad4 | 427 | pci_intx_for_msi(dev, 0); |
110828c9 | 428 | msi_set_enable(dev, pos, 1); |
b1cbf4e4 | 429 | dev->msi_enabled = 1; |
1da177e4 | 430 | |
7fe3730d | 431 | dev->irq = entry->irq; |
1da177e4 LT |
432 | return 0; |
433 | } | |
434 | ||
5a05a9d8 HS |
435 | static void __iomem *msix_map_region(struct pci_dev *dev, unsigned pos, |
436 | unsigned nr_entries) | |
437 | { | |
438 | unsigned long phys_addr; | |
439 | u32 table_offset; | |
440 | u8 bir; | |
441 | ||
442 | pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); | |
443 | bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); | |
444 | table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; | |
445 | phys_addr = pci_resource_start(dev, bir) + table_offset; | |
446 | ||
447 | return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); | |
448 | } | |
449 | ||
75cb3426 HS |
450 | static void msix_program_entries(struct pci_dev *dev, |
451 | struct msix_entry *entries) | |
452 | { | |
453 | struct msi_desc *entry; | |
454 | int i = 0; | |
455 | ||
456 | list_for_each_entry(entry, &dev->msi_list, list) { | |
457 | int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE + | |
458 | PCI_MSIX_ENTRY_VECTOR_CTRL; | |
459 | ||
460 | entries[i].vector = entry->irq; | |
461 | set_irq_msi(entry->irq, entry); | |
462 | entry->masked = readl(entry->mask_base + offset); | |
463 | msix_mask_irq(entry, 1); | |
464 | i++; | |
465 | } | |
466 | } | |
467 | ||
1da177e4 LT |
468 | /** |
469 | * msix_capability_init - configure device's MSI-X capability | |
470 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
471 | * @entries: pointer to an array of struct msix_entry entries |
472 | * @nvec: number of @entries | |
1da177e4 | 473 | * |
eaae4b3a | 474 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
475 | * single MSI-X irq. A return of zero indicates the successful setup of |
476 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
477 | **/ |
478 | static int msix_capability_init(struct pci_dev *dev, | |
479 | struct msix_entry *entries, int nvec) | |
480 | { | |
4aa9bc95 | 481 | struct msi_desc *entry; |
5a05a9d8 HS |
482 | int pos, i, j, ret; |
483 | u16 control; | |
1da177e4 LT |
484 | void __iomem *base; |
485 | ||
486 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
f598282f MW |
487 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); |
488 | ||
489 | /* Ensure MSI-X is disabled while it is set up */ | |
490 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
491 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
492 | ||
1da177e4 | 493 | /* Request & Map MSI-X table region */ |
5a05a9d8 HS |
494 | base = msix_map_region(dev, pos, multi_msix_capable(control)); |
495 | if (!base) | |
1da177e4 LT |
496 | return -ENOMEM; |
497 | ||
1da177e4 | 498 | for (i = 0; i < nvec; i++) { |
379f5327 | 499 | entry = alloc_msi_entry(dev); |
0d073489 HS |
500 | if (!entry) { |
501 | if (!i) | |
502 | iounmap(base); | |
503 | else | |
f56e4481 | 504 | free_msi_irqs(dev); |
0d073489 HS |
505 | /* No enough memory. Don't try again */ |
506 | return -ENOMEM; | |
507 | } | |
1da177e4 LT |
508 | |
509 | j = entries[i].entry; | |
24d27553 | 510 | entry->msi_attrib.is_msix = 1; |
0366f8f7 | 511 | entry->msi_attrib.is_64 = 1; |
1da177e4 | 512 | entry->msi_attrib.entry_nr = j; |
1ce03373 | 513 | entry->msi_attrib.default_irq = dev->irq; |
0366f8f7 | 514 | entry->msi_attrib.pos = pos; |
1da177e4 | 515 | entry->mask_base = base; |
f7feaca7 | 516 | |
0dd11f9b | 517 | list_add_tail(&entry->list, &dev->msi_list); |
1da177e4 | 518 | } |
9c831334 ME |
519 | |
520 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); | |
583871d4 HS |
521 | if (ret) |
522 | goto error; | |
9c831334 | 523 | |
f598282f MW |
524 | /* |
525 | * Some devices require MSI-X to be enabled before we can touch the | |
526 | * MSI-X registers. We need to mask all the vectors to prevent | |
527 | * interrupts coming in before they're fully set up. | |
528 | */ | |
529 | control |= PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE; | |
530 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
531 | ||
75cb3426 | 532 | msix_program_entries(dev, entries); |
f598282f MW |
533 | |
534 | /* Set MSI-X enabled bits and unmask the function */ | |
ba698ad4 | 535 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 536 | dev->msix_enabled = 1; |
1da177e4 | 537 | |
f598282f MW |
538 | control &= ~PCI_MSIX_FLAGS_MASKALL; |
539 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
8d181018 | 540 | |
1da177e4 | 541 | return 0; |
583871d4 HS |
542 | |
543 | error: | |
544 | if (ret < 0) { | |
545 | /* | |
546 | * If we had some success, report the number of irqs | |
547 | * we succeeded in setting up. | |
548 | */ | |
549 | int avail = 0; | |
550 | ||
551 | list_for_each_entry(entry, &dev->msi_list, list) { | |
552 | if (entry->irq != 0) | |
553 | avail++; | |
554 | } | |
555 | if (avail != 0) | |
556 | ret = avail; | |
557 | } | |
558 | ||
559 | free_msi_irqs(dev); | |
560 | ||
561 | return ret; | |
1da177e4 LT |
562 | } |
563 | ||
24334a12 | 564 | /** |
17bbc12a | 565 | * pci_msi_check_device - check whether MSI may be enabled on a device |
24334a12 | 566 | * @dev: pointer to the pci_dev data structure of MSI device function |
c9953a73 | 567 | * @nvec: how many MSIs have been requested ? |
b1e2303d | 568 | * @type: are we checking for MSI or MSI-X ? |
24334a12 | 569 | * |
0306ebfa | 570 | * Look at global flags, the device itself, and its parent busses |
17bbc12a ME |
571 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
572 | * supported return 0, else return an error code. | |
24334a12 | 573 | **/ |
c9953a73 | 574 | static int pci_msi_check_device(struct pci_dev* dev, int nvec, int type) |
24334a12 BG |
575 | { |
576 | struct pci_bus *bus; | |
c9953a73 | 577 | int ret; |
24334a12 | 578 | |
0306ebfa | 579 | /* MSI must be globally enabled and supported by the device */ |
24334a12 BG |
580 | if (!pci_msi_enable || !dev || dev->no_msi) |
581 | return -EINVAL; | |
582 | ||
314e77b3 ME |
583 | /* |
584 | * You can't ask to have 0 or less MSIs configured. | |
585 | * a) it's stupid .. | |
586 | * b) the list manipulation code assumes nvec >= 1. | |
587 | */ | |
588 | if (nvec < 1) | |
589 | return -ERANGE; | |
590 | ||
0306ebfa BG |
591 | /* Any bridge which does NOT route MSI transactions from it's |
592 | * secondary bus to it's primary bus must set NO_MSI flag on | |
593 | * the secondary pci_bus. | |
594 | * We expect only arch-specific PCI host bus controller driver | |
595 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
596 | */ | |
24334a12 BG |
597 | for (bus = dev->bus; bus; bus = bus->parent) |
598 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
599 | return -EINVAL; | |
600 | ||
c9953a73 ME |
601 | ret = arch_msi_check_device(dev, nvec, type); |
602 | if (ret) | |
603 | return ret; | |
604 | ||
b1e2303d ME |
605 | if (!pci_find_capability(dev, type)) |
606 | return -EINVAL; | |
607 | ||
24334a12 BG |
608 | return 0; |
609 | } | |
610 | ||
1da177e4 | 611 | /** |
1c8d7b0a MW |
612 | * pci_enable_msi_block - configure device's MSI capability structure |
613 | * @dev: device to configure | |
614 | * @nvec: number of interrupts to configure | |
1da177e4 | 615 | * |
1c8d7b0a MW |
616 | * Allocate IRQs for a device with the MSI capability. |
617 | * This function returns a negative errno if an error occurs. If it | |
618 | * is unable to allocate the number of interrupts requested, it returns | |
619 | * the number of interrupts it might be able to allocate. If it successfully | |
620 | * allocates at least the number of interrupts requested, it returns 0 and | |
621 | * updates the @dev's irq member to the lowest new interrupt number; the | |
622 | * other interrupt numbers allocated to this device are consecutive. | |
623 | */ | |
624 | int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec) | |
1da177e4 | 625 | { |
1c8d7b0a MW |
626 | int status, pos, maxvec; |
627 | u16 msgctl; | |
628 | ||
629 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
630 | if (!pos) | |
631 | return -EINVAL; | |
632 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); | |
633 | maxvec = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); | |
634 | if (nvec > maxvec) | |
635 | return maxvec; | |
1da177e4 | 636 | |
1c8d7b0a | 637 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI); |
c9953a73 ME |
638 | if (status) |
639 | return status; | |
1da177e4 | 640 | |
ded86d8d | 641 | WARN_ON(!!dev->msi_enabled); |
1da177e4 | 642 | |
1c8d7b0a | 643 | /* Check whether driver already requested MSI-X irqs */ |
b1cbf4e4 | 644 | if (dev->msix_enabled) { |
80ccba11 BH |
645 | dev_info(&dev->dev, "can't enable MSI " |
646 | "(MSI-X already enabled)\n"); | |
b1cbf4e4 | 647 | return -EINVAL; |
1da177e4 | 648 | } |
1c8d7b0a MW |
649 | |
650 | status = msi_capability_init(dev, nvec); | |
1da177e4 LT |
651 | return status; |
652 | } | |
1c8d7b0a | 653 | EXPORT_SYMBOL(pci_enable_msi_block); |
1da177e4 | 654 | |
f2440d9a | 655 | void pci_msi_shutdown(struct pci_dev *dev) |
1da177e4 | 656 | { |
f2440d9a MW |
657 | struct msi_desc *desc; |
658 | u32 mask; | |
659 | u16 ctrl; | |
110828c9 | 660 | unsigned pos; |
1da177e4 | 661 | |
128bc5fc | 662 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
663 | return; |
664 | ||
110828c9 MW |
665 | BUG_ON(list_empty(&dev->msi_list)); |
666 | desc = list_first_entry(&dev->msi_list, struct msi_desc, list); | |
667 | pos = desc->msi_attrib.pos; | |
668 | ||
669 | msi_set_enable(dev, pos, 0); | |
ba698ad4 | 670 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 671 | dev->msi_enabled = 0; |
7bd007e4 | 672 | |
12abb8ba | 673 | /* Return the device with MSI unmasked as initial states */ |
110828c9 | 674 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &ctrl); |
f2440d9a | 675 | mask = msi_capable_mask(ctrl); |
12abb8ba HS |
676 | /* Keep cached state to be restored */ |
677 | __msi_mask_irq(desc, mask, ~mask); | |
e387b9ee ME |
678 | |
679 | /* Restore dev->irq to its default pin-assertion irq */ | |
f2440d9a | 680 | dev->irq = desc->msi_attrib.default_irq; |
d52877c7 | 681 | } |
24d27553 | 682 | |
d52877c7 YL |
683 | void pci_disable_msi(struct pci_dev* dev) |
684 | { | |
d52877c7 YL |
685 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
686 | return; | |
687 | ||
688 | pci_msi_shutdown(dev); | |
f56e4481 | 689 | free_msi_irqs(dev); |
1da177e4 | 690 | } |
4cc086fa | 691 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 692 | |
a52e2e35 RW |
693 | /** |
694 | * pci_msix_table_size - return the number of device's MSI-X table entries | |
695 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
696 | */ | |
697 | int pci_msix_table_size(struct pci_dev *dev) | |
698 | { | |
699 | int pos; | |
700 | u16 control; | |
701 | ||
702 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
703 | if (!pos) | |
704 | return 0; | |
705 | ||
706 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
707 | return multi_msix_capable(control); | |
708 | } | |
709 | ||
1da177e4 LT |
710 | /** |
711 | * pci_enable_msix - configure device's MSI-X capability structure | |
712 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 713 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 714 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
715 | * |
716 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 717 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
718 | * MSI-X mode enabled on its hardware device function. A return of zero |
719 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 720 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 721 | * Or a return of > 0 indicates that driver request is exceeding the number |
57fbf52c MT |
722 | * of irqs or MSI-X vectors available. Driver should use the returned value to |
723 | * re-send its request. | |
1da177e4 LT |
724 | **/ |
725 | int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec) | |
726 | { | |
a52e2e35 | 727 | int status, nr_entries; |
ded86d8d | 728 | int i, j; |
1da177e4 | 729 | |
c9953a73 | 730 | if (!entries) |
1da177e4 LT |
731 | return -EINVAL; |
732 | ||
c9953a73 ME |
733 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX); |
734 | if (status) | |
735 | return status; | |
736 | ||
a52e2e35 | 737 | nr_entries = pci_msix_table_size(dev); |
1da177e4 | 738 | if (nvec > nr_entries) |
57fbf52c | 739 | return nr_entries; |
1da177e4 LT |
740 | |
741 | /* Check for any invalid entries */ | |
742 | for (i = 0; i < nvec; i++) { | |
743 | if (entries[i].entry >= nr_entries) | |
744 | return -EINVAL; /* invalid entry */ | |
745 | for (j = i + 1; j < nvec; j++) { | |
746 | if (entries[i].entry == entries[j].entry) | |
747 | return -EINVAL; /* duplicate entry */ | |
748 | } | |
749 | } | |
ded86d8d | 750 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 751 | |
1ce03373 | 752 | /* Check whether driver already requested for MSI irq */ |
b1cbf4e4 | 753 | if (dev->msi_enabled) { |
80ccba11 BH |
754 | dev_info(&dev->dev, "can't enable MSI-X " |
755 | "(MSI IRQ already assigned)\n"); | |
1da177e4 LT |
756 | return -EINVAL; |
757 | } | |
1da177e4 | 758 | status = msix_capability_init(dev, entries, nvec); |
1da177e4 LT |
759 | return status; |
760 | } | |
4cc086fa | 761 | EXPORT_SYMBOL(pci_enable_msix); |
1da177e4 | 762 | |
d52877c7 | 763 | void pci_msix_shutdown(struct pci_dev* dev) |
fc4afc7b | 764 | { |
12abb8ba HS |
765 | struct msi_desc *entry; |
766 | ||
128bc5fc | 767 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
768 | return; |
769 | ||
12abb8ba HS |
770 | /* Return the device with MSI-X masked as initial states */ |
771 | list_for_each_entry(entry, &dev->msi_list, list) { | |
772 | /* Keep cached states to be restored */ | |
773 | __msix_mask_irq(entry, 1); | |
774 | } | |
775 | ||
b1cbf4e4 | 776 | msix_set_enable(dev, 0); |
ba698ad4 | 777 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 778 | dev->msix_enabled = 0; |
d52877c7 | 779 | } |
c901851f | 780 | |
d52877c7 YL |
781 | void pci_disable_msix(struct pci_dev* dev) |
782 | { | |
783 | if (!pci_msi_enable || !dev || !dev->msix_enabled) | |
784 | return; | |
785 | ||
786 | pci_msix_shutdown(dev); | |
f56e4481 | 787 | free_msi_irqs(dev); |
1da177e4 | 788 | } |
4cc086fa | 789 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 LT |
790 | |
791 | /** | |
1ce03373 | 792 | * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state |
1da177e4 LT |
793 | * @dev: pointer to the pci_dev data structure of MSI(X) device function |
794 | * | |
eaae4b3a | 795 | * Being called during hotplug remove, from which the device function |
1ce03373 | 796 | * is hot-removed. All previous assigned MSI/MSI-X irqs, if |
1da177e4 LT |
797 | * allocated for this device function, are reclaimed to unused state, |
798 | * which may be used later on. | |
799 | **/ | |
800 | void msi_remove_pci_irq_vectors(struct pci_dev* dev) | |
801 | { | |
1da177e4 LT |
802 | if (!pci_msi_enable || !dev) |
803 | return; | |
804 | ||
f56e4481 HS |
805 | if (dev->msi_enabled || dev->msix_enabled) |
806 | free_msi_irqs(dev); | |
1da177e4 LT |
807 | } |
808 | ||
309e57df MW |
809 | void pci_no_msi(void) |
810 | { | |
811 | pci_msi_enable = 0; | |
812 | } | |
c9953a73 | 813 | |
07ae95f9 AP |
814 | /** |
815 | * pci_msi_enabled - is MSI enabled? | |
816 | * | |
817 | * Returns true if MSI has not been disabled by the command-line option | |
818 | * pci=nomsi. | |
819 | **/ | |
820 | int pci_msi_enabled(void) | |
d389fec6 | 821 | { |
07ae95f9 | 822 | return pci_msi_enable; |
d389fec6 | 823 | } |
07ae95f9 | 824 | EXPORT_SYMBOL(pci_msi_enabled); |
d389fec6 | 825 | |
07ae95f9 | 826 | void pci_msi_init_pci_dev(struct pci_dev *dev) |
d389fec6 | 827 | { |
07ae95f9 | 828 | INIT_LIST_HEAD(&dev->msi_list); |
d389fec6 | 829 | } |