Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/init.h> | |
1da177e4 | 14 | #include <linux/ioport.h> |
1da177e4 LT |
15 | #include <linux/pci.h> |
16 | #include <linux/proc_fs.h> | |
3b7d1921 | 17 | #include <linux/msi.h> |
4fdadebc | 18 | #include <linux/smp.h> |
1da177e4 LT |
19 | |
20 | #include <asm/errno.h> | |
21 | #include <asm/io.h> | |
1da177e4 LT |
22 | |
23 | #include "pci.h" | |
24 | #include "msi.h" | |
25 | ||
1da177e4 | 26 | static int pci_msi_enable = 1; |
1da177e4 | 27 | |
6a9e7f20 AB |
28 | /* Arch hooks */ |
29 | ||
11df1f05 ME |
30 | #ifndef arch_msi_check_device |
31 | int arch_msi_check_device(struct pci_dev *dev, int nvec, int type) | |
6a9e7f20 AB |
32 | { |
33 | return 0; | |
34 | } | |
11df1f05 | 35 | #endif |
6a9e7f20 | 36 | |
11df1f05 ME |
37 | #ifndef arch_setup_msi_irqs |
38 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) | |
6a9e7f20 AB |
39 | { |
40 | struct msi_desc *entry; | |
41 | int ret; | |
42 | ||
1c8d7b0a MW |
43 | /* |
44 | * If an architecture wants to support multiple MSI, it needs to | |
45 | * override arch_setup_msi_irqs() | |
46 | */ | |
47 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
48 | return 1; | |
49 | ||
6a9e7f20 AB |
50 | list_for_each_entry(entry, &dev->msi_list, list) { |
51 | ret = arch_setup_msi_irq(dev, entry); | |
b5fbf533 | 52 | if (ret < 0) |
6a9e7f20 | 53 | return ret; |
b5fbf533 ME |
54 | if (ret > 0) |
55 | return -ENOSPC; | |
6a9e7f20 AB |
56 | } |
57 | ||
58 | return 0; | |
59 | } | |
11df1f05 | 60 | #endif |
6a9e7f20 | 61 | |
11df1f05 ME |
62 | #ifndef arch_teardown_msi_irqs |
63 | void arch_teardown_msi_irqs(struct pci_dev *dev) | |
6a9e7f20 AB |
64 | { |
65 | struct msi_desc *entry; | |
66 | ||
67 | list_for_each_entry(entry, &dev->msi_list, list) { | |
1c8d7b0a MW |
68 | int i, nvec; |
69 | if (entry->irq == 0) | |
70 | continue; | |
71 | nvec = 1 << entry->msi_attrib.multiple; | |
72 | for (i = 0; i < nvec; i++) | |
73 | arch_teardown_msi_irq(entry->irq + i); | |
6a9e7f20 AB |
74 | } |
75 | } | |
11df1f05 | 76 | #endif |
6a9e7f20 | 77 | |
110828c9 | 78 | static void msi_set_enable(struct pci_dev *dev, int pos, int enable) |
b1cbf4e4 | 79 | { |
b1cbf4e4 EB |
80 | u16 control; |
81 | ||
110828c9 | 82 | BUG_ON(!pos); |
b1cbf4e4 | 83 | |
110828c9 MW |
84 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); |
85 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
86 | if (enable) | |
87 | control |= PCI_MSI_FLAGS_ENABLE; | |
88 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
5ca5c02f HS |
89 | } |
90 | ||
b1cbf4e4 EB |
91 | static void msix_set_enable(struct pci_dev *dev, int enable) |
92 | { | |
93 | int pos; | |
94 | u16 control; | |
95 | ||
96 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
97 | if (pos) { | |
98 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
99 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
100 | if (enable) | |
101 | control |= PCI_MSIX_FLAGS_ENABLE; | |
102 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
103 | } | |
104 | } | |
105 | ||
bffac3c5 MW |
106 | static inline __attribute_const__ u32 msi_mask(unsigned x) |
107 | { | |
0b49ec37 MW |
108 | /* Don't shift by >= width of type */ |
109 | if (x >= 5) | |
110 | return 0xffffffff; | |
111 | return (1 << (1 << x)) - 1; | |
bffac3c5 MW |
112 | } |
113 | ||
f2440d9a | 114 | static inline __attribute_const__ u32 msi_capable_mask(u16 control) |
988cbb15 | 115 | { |
f2440d9a MW |
116 | return msi_mask((control >> 1) & 7); |
117 | } | |
988cbb15 | 118 | |
f2440d9a MW |
119 | static inline __attribute_const__ u32 msi_enabled_mask(u16 control) |
120 | { | |
121 | return msi_mask((control >> 4) & 7); | |
988cbb15 MW |
122 | } |
123 | ||
ce6fce42 MW |
124 | /* |
125 | * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to | |
126 | * mask all MSI interrupts by clearing the MSI enable bit does not work | |
127 | * reliably as devices without an INTx disable bit will then generate a | |
128 | * level IRQ which will never be cleared. | |
ce6fce42 | 129 | */ |
f2440d9a | 130 | static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
1da177e4 | 131 | { |
f2440d9a | 132 | u32 mask_bits = desc->masked; |
1da177e4 | 133 | |
f2440d9a MW |
134 | if (!desc->msi_attrib.maskbit) |
135 | return; | |
136 | ||
137 | mask_bits &= ~mask; | |
138 | mask_bits |= flag; | |
139 | pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits); | |
140 | desc->masked = mask_bits; | |
141 | } | |
142 | ||
143 | /* | |
144 | * This internal function does not flush PCI writes to the device. | |
145 | * All users must ensure that they read from the device before either | |
146 | * assuming that the device state is up to date, or returning out of this | |
147 | * file. This saves a few milliseconds when initialising devices with lots | |
148 | * of MSI-X interrupts. | |
149 | */ | |
150 | static void msix_mask_irq(struct msi_desc *desc, u32 flag) | |
151 | { | |
152 | u32 mask_bits = desc->masked; | |
153 | unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
154 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; | |
155 | mask_bits &= ~1; | |
156 | mask_bits |= flag; | |
157 | writel(mask_bits, desc->mask_base + offset); | |
158 | desc->masked = mask_bits; | |
159 | } | |
24d27553 | 160 | |
f2440d9a MW |
161 | static void msi_set_mask_bit(unsigned irq, u32 flag) |
162 | { | |
163 | struct msi_desc *desc = get_irq_msi(irq); | |
24d27553 | 164 | |
f2440d9a MW |
165 | if (desc->msi_attrib.is_msix) { |
166 | msix_mask_irq(desc, flag); | |
167 | readl(desc->mask_base); /* Flush write to device */ | |
168 | } else { | |
1c8d7b0a MW |
169 | unsigned offset = irq - desc->dev->irq; |
170 | msi_mask_irq(desc, 1 << offset, flag << offset); | |
1da177e4 | 171 | } |
f2440d9a MW |
172 | } |
173 | ||
174 | void mask_msi_irq(unsigned int irq) | |
175 | { | |
176 | msi_set_mask_bit(irq, 1); | |
177 | } | |
178 | ||
179 | void unmask_msi_irq(unsigned int irq) | |
180 | { | |
181 | msi_set_mask_bit(irq, 0); | |
1da177e4 LT |
182 | } |
183 | ||
3145e941 | 184 | void read_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg) |
1da177e4 | 185 | { |
3145e941 | 186 | struct msi_desc *entry = get_irq_desc_msi(desc); |
24d27553 MW |
187 | if (entry->msi_attrib.is_msix) { |
188 | void __iomem *base = entry->mask_base + | |
189 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
190 | ||
191 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); | |
192 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); | |
193 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET); | |
194 | } else { | |
0366f8f7 EB |
195 | struct pci_dev *dev = entry->dev; |
196 | int pos = entry->msi_attrib.pos; | |
197 | u16 data; | |
198 | ||
199 | pci_read_config_dword(dev, msi_lower_address_reg(pos), | |
200 | &msg->address_lo); | |
201 | if (entry->msi_attrib.is_64) { | |
202 | pci_read_config_dword(dev, msi_upper_address_reg(pos), | |
203 | &msg->address_hi); | |
204 | pci_read_config_word(dev, msi_data_reg(pos, 1), &data); | |
205 | } else { | |
206 | msg->address_hi = 0; | |
cbf5d9e6 | 207 | pci_read_config_word(dev, msi_data_reg(pos, 0), &data); |
0366f8f7 EB |
208 | } |
209 | msg->data = data; | |
0366f8f7 EB |
210 | } |
211 | } | |
1da177e4 | 212 | |
3145e941 | 213 | void read_msi_msg(unsigned int irq, struct msi_msg *msg) |
0366f8f7 | 214 | { |
3145e941 YL |
215 | struct irq_desc *desc = irq_to_desc(irq); |
216 | ||
217 | read_msi_msg_desc(desc, msg); | |
218 | } | |
219 | ||
220 | void write_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg) | |
221 | { | |
222 | struct msi_desc *entry = get_irq_desc_msi(desc); | |
24d27553 MW |
223 | if (entry->msi_attrib.is_msix) { |
224 | void __iomem *base; | |
225 | base = entry->mask_base + | |
226 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
227 | ||
228 | writel(msg->address_lo, | |
229 | base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); | |
230 | writel(msg->address_hi, | |
231 | base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); | |
232 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET); | |
233 | } else { | |
0366f8f7 EB |
234 | struct pci_dev *dev = entry->dev; |
235 | int pos = entry->msi_attrib.pos; | |
1c8d7b0a MW |
236 | u16 msgctl; |
237 | ||
238 | pci_read_config_word(dev, msi_control_reg(pos), &msgctl); | |
239 | msgctl &= ~PCI_MSI_FLAGS_QSIZE; | |
240 | msgctl |= entry->msi_attrib.multiple << 4; | |
241 | pci_write_config_word(dev, msi_control_reg(pos), msgctl); | |
0366f8f7 EB |
242 | |
243 | pci_write_config_dword(dev, msi_lower_address_reg(pos), | |
244 | msg->address_lo); | |
245 | if (entry->msi_attrib.is_64) { | |
246 | pci_write_config_dword(dev, msi_upper_address_reg(pos), | |
247 | msg->address_hi); | |
248 | pci_write_config_word(dev, msi_data_reg(pos, 1), | |
249 | msg->data); | |
250 | } else { | |
251 | pci_write_config_word(dev, msi_data_reg(pos, 0), | |
252 | msg->data); | |
253 | } | |
1da177e4 | 254 | } |
392ee1e6 | 255 | entry->msg = *msg; |
1da177e4 | 256 | } |
0366f8f7 | 257 | |
3145e941 YL |
258 | void write_msi_msg(unsigned int irq, struct msi_msg *msg) |
259 | { | |
260 | struct irq_desc *desc = irq_to_desc(irq); | |
261 | ||
262 | write_msi_msg_desc(desc, msg); | |
263 | } | |
264 | ||
032de8e2 | 265 | static int msi_free_irqs(struct pci_dev* dev); |
c54c1879 | 266 | |
379f5327 | 267 | static struct msi_desc *alloc_msi_entry(struct pci_dev *dev) |
1da177e4 | 268 | { |
379f5327 MW |
269 | struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL); |
270 | if (!desc) | |
1da177e4 LT |
271 | return NULL; |
272 | ||
379f5327 MW |
273 | INIT_LIST_HEAD(&desc->list); |
274 | desc->dev = dev; | |
1da177e4 | 275 | |
379f5327 | 276 | return desc; |
1da177e4 LT |
277 | } |
278 | ||
ba698ad4 DM |
279 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
280 | { | |
281 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) | |
282 | pci_intx(dev, enable); | |
283 | } | |
284 | ||
8fed4b65 | 285 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 286 | { |
392ee1e6 | 287 | int pos; |
41017f0c | 288 | u16 control; |
392ee1e6 | 289 | struct msi_desc *entry; |
41017f0c | 290 | |
b1cbf4e4 EB |
291 | if (!dev->msi_enabled) |
292 | return; | |
293 | ||
392ee1e6 EB |
294 | entry = get_irq_msi(dev->irq); |
295 | pos = entry->msi_attrib.pos; | |
41017f0c | 296 | |
ba698ad4 | 297 | pci_intx_for_msi(dev, 0); |
110828c9 | 298 | msi_set_enable(dev, pos, 0); |
392ee1e6 | 299 | write_msi_msg(dev->irq, &entry->msg); |
392ee1e6 EB |
300 | |
301 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
f2440d9a | 302 | msi_mask_irq(entry, msi_capable_mask(control), entry->masked); |
abad2ec9 | 303 | control &= ~PCI_MSI_FLAGS_QSIZE; |
1c8d7b0a | 304 | control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; |
41017f0c | 305 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
306 | } |
307 | ||
308 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 309 | { |
41017f0c | 310 | int pos; |
41017f0c | 311 | struct msi_desc *entry; |
392ee1e6 | 312 | u16 control; |
41017f0c | 313 | |
ded86d8d EB |
314 | if (!dev->msix_enabled) |
315 | return; | |
316 | ||
41017f0c | 317 | /* route the table */ |
ba698ad4 | 318 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 319 | msix_set_enable(dev, 0); |
41017f0c | 320 | |
4aa9bc95 ME |
321 | list_for_each_entry(entry, &dev->msi_list, list) { |
322 | write_msi_msg(entry->irq, &entry->msg); | |
f2440d9a | 323 | msix_mask_irq(entry, entry->masked); |
41017f0c | 324 | } |
41017f0c | 325 | |
314e77b3 ME |
326 | BUG_ON(list_empty(&dev->msi_list)); |
327 | entry = list_entry(dev->msi_list.next, struct msi_desc, list); | |
4aa9bc95 | 328 | pos = entry->msi_attrib.pos; |
392ee1e6 EB |
329 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); |
330 | control &= ~PCI_MSIX_FLAGS_MASKALL; | |
331 | control |= PCI_MSIX_FLAGS_ENABLE; | |
332 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
41017f0c | 333 | } |
8fed4b65 ME |
334 | |
335 | void pci_restore_msi_state(struct pci_dev *dev) | |
336 | { | |
337 | __pci_restore_msi_state(dev); | |
338 | __pci_restore_msix_state(dev); | |
339 | } | |
94688cf2 | 340 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
41017f0c | 341 | |
1da177e4 LT |
342 | /** |
343 | * msi_capability_init - configure device's MSI capability structure | |
344 | * @dev: pointer to the pci_dev data structure of MSI device function | |
1c8d7b0a | 345 | * @nvec: number of interrupts to allocate |
1da177e4 | 346 | * |
1c8d7b0a MW |
347 | * Setup the MSI capability structure of the device with the requested |
348 | * number of interrupts. A return value of zero indicates the successful | |
349 | * setup of an entry with the new MSI irq. A negative return value indicates | |
350 | * an error, and a positive return value indicates the number of interrupts | |
351 | * which could have been allocated. | |
352 | */ | |
353 | static int msi_capability_init(struct pci_dev *dev, int nvec) | |
1da177e4 LT |
354 | { |
355 | struct msi_desc *entry; | |
7fe3730d | 356 | int pos, ret; |
1da177e4 | 357 | u16 control; |
f2440d9a | 358 | unsigned mask; |
1da177e4 LT |
359 | |
360 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
110828c9 MW |
361 | msi_set_enable(dev, pos, 0); /* Disable MSI during set up */ |
362 | ||
1da177e4 LT |
363 | pci_read_config_word(dev, msi_control_reg(pos), &control); |
364 | /* MSI Entry Initialization */ | |
379f5327 | 365 | entry = alloc_msi_entry(dev); |
f7feaca7 EB |
366 | if (!entry) |
367 | return -ENOMEM; | |
1ce03373 | 368 | |
24d27553 | 369 | entry->msi_attrib.is_msix = 0; |
0366f8f7 | 370 | entry->msi_attrib.is_64 = is_64bit_address(control); |
1da177e4 LT |
371 | entry->msi_attrib.entry_nr = 0; |
372 | entry->msi_attrib.maskbit = is_mask_bit_support(control); | |
1ce03373 | 373 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ |
0366f8f7 | 374 | entry->msi_attrib.pos = pos; |
f2440d9a | 375 | |
67b5db65 | 376 | entry->mask_pos = msi_mask_reg(pos, entry->msi_attrib.is_64); |
f2440d9a MW |
377 | /* All MSIs are unmasked by default, Mask them all */ |
378 | if (entry->msi_attrib.maskbit) | |
379 | pci_read_config_dword(dev, entry->mask_pos, &entry->masked); | |
380 | mask = msi_capable_mask(control); | |
381 | msi_mask_irq(entry, mask, mask); | |
382 | ||
0dd11f9b | 383 | list_add_tail(&entry->list, &dev->msi_list); |
9c831334 | 384 | |
1da177e4 | 385 | /* Configure MSI capability structure */ |
1c8d7b0a | 386 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); |
7fe3730d | 387 | if (ret) { |
032de8e2 | 388 | msi_free_irqs(dev); |
7fe3730d | 389 | return ret; |
fd58e55f | 390 | } |
f7feaca7 | 391 | |
1da177e4 | 392 | /* Set MSI enabled bits */ |
ba698ad4 | 393 | pci_intx_for_msi(dev, 0); |
110828c9 | 394 | msi_set_enable(dev, pos, 1); |
b1cbf4e4 | 395 | dev->msi_enabled = 1; |
1da177e4 | 396 | |
7fe3730d | 397 | dev->irq = entry->irq; |
1da177e4 LT |
398 | return 0; |
399 | } | |
400 | ||
401 | /** | |
402 | * msix_capability_init - configure device's MSI-X capability | |
403 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
404 | * @entries: pointer to an array of struct msix_entry entries |
405 | * @nvec: number of @entries | |
1da177e4 | 406 | * |
eaae4b3a | 407 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
408 | * single MSI-X irq. A return of zero indicates the successful setup of |
409 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
410 | **/ |
411 | static int msix_capability_init(struct pci_dev *dev, | |
412 | struct msix_entry *entries, int nvec) | |
413 | { | |
4aa9bc95 | 414 | struct msi_desc *entry; |
9c831334 | 415 | int pos, i, j, nr_entries, ret; |
a0454b40 GG |
416 | unsigned long phys_addr; |
417 | u32 table_offset; | |
1da177e4 LT |
418 | u16 control; |
419 | u8 bir; | |
420 | void __iomem *base; | |
421 | ||
b1cbf4e4 EB |
422 | msix_set_enable(dev, 0);/* Ensure msix is disabled as I set it up */ |
423 | ||
1da177e4 LT |
424 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
425 | /* Request & Map MSI-X table region */ | |
426 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
427 | nr_entries = multi_msix_capable(control); | |
a0454b40 GG |
428 | |
429 | pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); | |
1da177e4 | 430 | bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); |
a0454b40 GG |
431 | table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; |
432 | phys_addr = pci_resource_start (dev, bir) + table_offset; | |
1da177e4 LT |
433 | base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); |
434 | if (base == NULL) | |
435 | return -ENOMEM; | |
436 | ||
437 | /* MSI-X Table Initialization */ | |
438 | for (i = 0; i < nvec; i++) { | |
379f5327 | 439 | entry = alloc_msi_entry(dev); |
f7feaca7 | 440 | if (!entry) |
1da177e4 | 441 | break; |
1da177e4 LT |
442 | |
443 | j = entries[i].entry; | |
24d27553 | 444 | entry->msi_attrib.is_msix = 1; |
0366f8f7 | 445 | entry->msi_attrib.is_64 = 1; |
1da177e4 | 446 | entry->msi_attrib.entry_nr = j; |
1ce03373 | 447 | entry->msi_attrib.default_irq = dev->irq; |
0366f8f7 | 448 | entry->msi_attrib.pos = pos; |
1da177e4 | 449 | entry->mask_base = base; |
f2440d9a | 450 | msix_mask_irq(entry, 1); |
f7feaca7 | 451 | |
0dd11f9b | 452 | list_add_tail(&entry->list, &dev->msi_list); |
1da177e4 | 453 | } |
9c831334 ME |
454 | |
455 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); | |
b5fbf533 ME |
456 | if (ret < 0) { |
457 | /* If we had some success report the number of irqs | |
458 | * we succeeded in setting up. */ | |
9c831334 ME |
459 | int avail = 0; |
460 | list_for_each_entry(entry, &dev->msi_list, list) { | |
461 | if (entry->irq != 0) { | |
462 | avail++; | |
9c831334 | 463 | } |
1da177e4 | 464 | } |
9c831334 | 465 | |
b5fbf533 ME |
466 | if (avail != 0) |
467 | ret = avail; | |
468 | } | |
032de8e2 | 469 | |
b5fbf533 ME |
470 | if (ret) { |
471 | msi_free_irqs(dev); | |
472 | return ret; | |
1da177e4 | 473 | } |
9c831334 ME |
474 | |
475 | i = 0; | |
476 | list_for_each_entry(entry, &dev->msi_list, list) { | |
477 | entries[i].vector = entry->irq; | |
478 | set_irq_msi(entry->irq, entry); | |
479 | i++; | |
480 | } | |
1da177e4 | 481 | /* Set MSI-X enabled bits */ |
ba698ad4 | 482 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 EB |
483 | msix_set_enable(dev, 1); |
484 | dev->msix_enabled = 1; | |
1da177e4 | 485 | |
8d181018 MW |
486 | list_for_each_entry(entry, &dev->msi_list, list) { |
487 | int vector = entry->msi_attrib.entry_nr; | |
488 | entry->masked = readl(base + vector * PCI_MSIX_ENTRY_SIZE + | |
489 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); | |
490 | } | |
491 | ||
1da177e4 LT |
492 | return 0; |
493 | } | |
494 | ||
24334a12 | 495 | /** |
17bbc12a | 496 | * pci_msi_check_device - check whether MSI may be enabled on a device |
24334a12 | 497 | * @dev: pointer to the pci_dev data structure of MSI device function |
c9953a73 | 498 | * @nvec: how many MSIs have been requested ? |
b1e2303d | 499 | * @type: are we checking for MSI or MSI-X ? |
24334a12 | 500 | * |
0306ebfa | 501 | * Look at global flags, the device itself, and its parent busses |
17bbc12a ME |
502 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
503 | * supported return 0, else return an error code. | |
24334a12 | 504 | **/ |
c9953a73 | 505 | static int pci_msi_check_device(struct pci_dev* dev, int nvec, int type) |
24334a12 BG |
506 | { |
507 | struct pci_bus *bus; | |
c9953a73 | 508 | int ret; |
24334a12 | 509 | |
0306ebfa | 510 | /* MSI must be globally enabled and supported by the device */ |
24334a12 BG |
511 | if (!pci_msi_enable || !dev || dev->no_msi) |
512 | return -EINVAL; | |
513 | ||
314e77b3 ME |
514 | /* |
515 | * You can't ask to have 0 or less MSIs configured. | |
516 | * a) it's stupid .. | |
517 | * b) the list manipulation code assumes nvec >= 1. | |
518 | */ | |
519 | if (nvec < 1) | |
520 | return -ERANGE; | |
521 | ||
0306ebfa BG |
522 | /* Any bridge which does NOT route MSI transactions from it's |
523 | * secondary bus to it's primary bus must set NO_MSI flag on | |
524 | * the secondary pci_bus. | |
525 | * We expect only arch-specific PCI host bus controller driver | |
526 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
527 | */ | |
24334a12 BG |
528 | for (bus = dev->bus; bus; bus = bus->parent) |
529 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
530 | return -EINVAL; | |
531 | ||
c9953a73 ME |
532 | ret = arch_msi_check_device(dev, nvec, type); |
533 | if (ret) | |
534 | return ret; | |
535 | ||
b1e2303d ME |
536 | if (!pci_find_capability(dev, type)) |
537 | return -EINVAL; | |
538 | ||
24334a12 BG |
539 | return 0; |
540 | } | |
541 | ||
1da177e4 | 542 | /** |
1c8d7b0a MW |
543 | * pci_enable_msi_block - configure device's MSI capability structure |
544 | * @dev: device to configure | |
545 | * @nvec: number of interrupts to configure | |
1da177e4 | 546 | * |
1c8d7b0a MW |
547 | * Allocate IRQs for a device with the MSI capability. |
548 | * This function returns a negative errno if an error occurs. If it | |
549 | * is unable to allocate the number of interrupts requested, it returns | |
550 | * the number of interrupts it might be able to allocate. If it successfully | |
551 | * allocates at least the number of interrupts requested, it returns 0 and | |
552 | * updates the @dev's irq member to the lowest new interrupt number; the | |
553 | * other interrupt numbers allocated to this device are consecutive. | |
554 | */ | |
555 | int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec) | |
1da177e4 | 556 | { |
1c8d7b0a MW |
557 | int status, pos, maxvec; |
558 | u16 msgctl; | |
559 | ||
560 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
561 | if (!pos) | |
562 | return -EINVAL; | |
563 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); | |
564 | maxvec = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); | |
565 | if (nvec > maxvec) | |
566 | return maxvec; | |
1da177e4 | 567 | |
1c8d7b0a | 568 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI); |
c9953a73 ME |
569 | if (status) |
570 | return status; | |
1da177e4 | 571 | |
ded86d8d | 572 | WARN_ON(!!dev->msi_enabled); |
1da177e4 | 573 | |
1c8d7b0a | 574 | /* Check whether driver already requested MSI-X irqs */ |
b1cbf4e4 | 575 | if (dev->msix_enabled) { |
80ccba11 BH |
576 | dev_info(&dev->dev, "can't enable MSI " |
577 | "(MSI-X already enabled)\n"); | |
b1cbf4e4 | 578 | return -EINVAL; |
1da177e4 | 579 | } |
1c8d7b0a MW |
580 | |
581 | status = msi_capability_init(dev, nvec); | |
1da177e4 LT |
582 | return status; |
583 | } | |
1c8d7b0a | 584 | EXPORT_SYMBOL(pci_enable_msi_block); |
1da177e4 | 585 | |
f2440d9a | 586 | void pci_msi_shutdown(struct pci_dev *dev) |
1da177e4 | 587 | { |
f2440d9a MW |
588 | struct msi_desc *desc; |
589 | u32 mask; | |
590 | u16 ctrl; | |
110828c9 | 591 | unsigned pos; |
1da177e4 | 592 | |
128bc5fc | 593 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
594 | return; |
595 | ||
110828c9 MW |
596 | BUG_ON(list_empty(&dev->msi_list)); |
597 | desc = list_first_entry(&dev->msi_list, struct msi_desc, list); | |
598 | pos = desc->msi_attrib.pos; | |
599 | ||
600 | msi_set_enable(dev, pos, 0); | |
ba698ad4 | 601 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 602 | dev->msi_enabled = 0; |
7bd007e4 | 603 | |
110828c9 | 604 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &ctrl); |
f2440d9a MW |
605 | mask = msi_capable_mask(ctrl); |
606 | msi_mask_irq(desc, mask, ~mask); | |
e387b9ee ME |
607 | |
608 | /* Restore dev->irq to its default pin-assertion irq */ | |
f2440d9a | 609 | dev->irq = desc->msi_attrib.default_irq; |
d52877c7 | 610 | } |
24d27553 | 611 | |
d52877c7 YL |
612 | void pci_disable_msi(struct pci_dev* dev) |
613 | { | |
614 | struct msi_desc *entry; | |
615 | ||
616 | if (!pci_msi_enable || !dev || !dev->msi_enabled) | |
617 | return; | |
618 | ||
619 | pci_msi_shutdown(dev); | |
620 | ||
621 | entry = list_entry(dev->msi_list.next, struct msi_desc, list); | |
379f5327 | 622 | if (entry->msi_attrib.is_msix) |
d52877c7 YL |
623 | return; |
624 | ||
625 | msi_free_irqs(dev); | |
1da177e4 | 626 | } |
4cc086fa | 627 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 628 | |
032de8e2 | 629 | static int msi_free_irqs(struct pci_dev* dev) |
1da177e4 | 630 | { |
032de8e2 | 631 | struct msi_desc *entry, *tmp; |
7ede9c1f | 632 | |
b3b7cc7b | 633 | list_for_each_entry(entry, &dev->msi_list, list) { |
1c8d7b0a MW |
634 | int i, nvec; |
635 | if (!entry->irq) | |
636 | continue; | |
637 | nvec = 1 << entry->msi_attrib.multiple; | |
638 | for (i = 0; i < nvec; i++) | |
639 | BUG_ON(irq_has_action(entry->irq + i)); | |
b3b7cc7b | 640 | } |
1da177e4 | 641 | |
032de8e2 | 642 | arch_teardown_msi_irqs(dev); |
1da177e4 | 643 | |
032de8e2 | 644 | list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) { |
24d27553 | 645 | if (entry->msi_attrib.is_msix) { |
032de8e2 ME |
646 | writel(1, entry->mask_base + entry->msi_attrib.entry_nr |
647 | * PCI_MSIX_ENTRY_SIZE | |
648 | + PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); | |
78b7611c EB |
649 | |
650 | if (list_is_last(&entry->list, &dev->msi_list)) | |
651 | iounmap(entry->mask_base); | |
032de8e2 ME |
652 | } |
653 | list_del(&entry->list); | |
654 | kfree(entry); | |
1da177e4 LT |
655 | } |
656 | ||
657 | return 0; | |
658 | } | |
659 | ||
a52e2e35 RW |
660 | /** |
661 | * pci_msix_table_size - return the number of device's MSI-X table entries | |
662 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
663 | */ | |
664 | int pci_msix_table_size(struct pci_dev *dev) | |
665 | { | |
666 | int pos; | |
667 | u16 control; | |
668 | ||
669 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
670 | if (!pos) | |
671 | return 0; | |
672 | ||
673 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
674 | return multi_msix_capable(control); | |
675 | } | |
676 | ||
1da177e4 LT |
677 | /** |
678 | * pci_enable_msix - configure device's MSI-X capability structure | |
679 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 680 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 681 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
682 | * |
683 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 684 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
685 | * MSI-X mode enabled on its hardware device function. A return of zero |
686 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 687 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 688 | * Or a return of > 0 indicates that driver request is exceeding the number |
57fbf52c MT |
689 | * of irqs or MSI-X vectors available. Driver should use the returned value to |
690 | * re-send its request. | |
1da177e4 LT |
691 | **/ |
692 | int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec) | |
693 | { | |
a52e2e35 | 694 | int status, nr_entries; |
ded86d8d | 695 | int i, j; |
1da177e4 | 696 | |
c9953a73 | 697 | if (!entries) |
1da177e4 LT |
698 | return -EINVAL; |
699 | ||
c9953a73 ME |
700 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX); |
701 | if (status) | |
702 | return status; | |
703 | ||
a52e2e35 | 704 | nr_entries = pci_msix_table_size(dev); |
1da177e4 | 705 | if (nvec > nr_entries) |
57fbf52c | 706 | return nr_entries; |
1da177e4 LT |
707 | |
708 | /* Check for any invalid entries */ | |
709 | for (i = 0; i < nvec; i++) { | |
710 | if (entries[i].entry >= nr_entries) | |
711 | return -EINVAL; /* invalid entry */ | |
712 | for (j = i + 1; j < nvec; j++) { | |
713 | if (entries[i].entry == entries[j].entry) | |
714 | return -EINVAL; /* duplicate entry */ | |
715 | } | |
716 | } | |
ded86d8d | 717 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 718 | |
1ce03373 | 719 | /* Check whether driver already requested for MSI irq */ |
b1cbf4e4 | 720 | if (dev->msi_enabled) { |
80ccba11 BH |
721 | dev_info(&dev->dev, "can't enable MSI-X " |
722 | "(MSI IRQ already assigned)\n"); | |
1da177e4 LT |
723 | return -EINVAL; |
724 | } | |
1da177e4 | 725 | status = msix_capability_init(dev, entries, nvec); |
1da177e4 LT |
726 | return status; |
727 | } | |
4cc086fa | 728 | EXPORT_SYMBOL(pci_enable_msix); |
1da177e4 | 729 | |
fc4afc7b | 730 | static void msix_free_all_irqs(struct pci_dev *dev) |
1da177e4 | 731 | { |
032de8e2 | 732 | msi_free_irqs(dev); |
fc4afc7b ME |
733 | } |
734 | ||
d52877c7 | 735 | void pci_msix_shutdown(struct pci_dev* dev) |
fc4afc7b | 736 | { |
128bc5fc | 737 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
738 | return; |
739 | ||
b1cbf4e4 | 740 | msix_set_enable(dev, 0); |
ba698ad4 | 741 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 742 | dev->msix_enabled = 0; |
d52877c7 YL |
743 | } |
744 | void pci_disable_msix(struct pci_dev* dev) | |
745 | { | |
746 | if (!pci_msi_enable || !dev || !dev->msix_enabled) | |
747 | return; | |
748 | ||
749 | pci_msix_shutdown(dev); | |
7bd007e4 | 750 | |
fc4afc7b | 751 | msix_free_all_irqs(dev); |
1da177e4 | 752 | } |
4cc086fa | 753 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 LT |
754 | |
755 | /** | |
1ce03373 | 756 | * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state |
1da177e4 LT |
757 | * @dev: pointer to the pci_dev data structure of MSI(X) device function |
758 | * | |
eaae4b3a | 759 | * Being called during hotplug remove, from which the device function |
1ce03373 | 760 | * is hot-removed. All previous assigned MSI/MSI-X irqs, if |
1da177e4 LT |
761 | * allocated for this device function, are reclaimed to unused state, |
762 | * which may be used later on. | |
763 | **/ | |
764 | void msi_remove_pci_irq_vectors(struct pci_dev* dev) | |
765 | { | |
1da177e4 LT |
766 | if (!pci_msi_enable || !dev) |
767 | return; | |
768 | ||
032de8e2 ME |
769 | if (dev->msi_enabled) |
770 | msi_free_irqs(dev); | |
1da177e4 | 771 | |
fc4afc7b ME |
772 | if (dev->msix_enabled) |
773 | msix_free_all_irqs(dev); | |
1da177e4 LT |
774 | } |
775 | ||
309e57df MW |
776 | void pci_no_msi(void) |
777 | { | |
778 | pci_msi_enable = 0; | |
779 | } | |
c9953a73 | 780 | |
07ae95f9 AP |
781 | /** |
782 | * pci_msi_enabled - is MSI enabled? | |
783 | * | |
784 | * Returns true if MSI has not been disabled by the command-line option | |
785 | * pci=nomsi. | |
786 | **/ | |
787 | int pci_msi_enabled(void) | |
d389fec6 | 788 | { |
07ae95f9 | 789 | return pci_msi_enable; |
d389fec6 | 790 | } |
07ae95f9 | 791 | EXPORT_SYMBOL(pci_msi_enabled); |
d389fec6 | 792 | |
07ae95f9 | 793 | void pci_msi_init_pci_dev(struct pci_dev *dev) |
d389fec6 | 794 | { |
07ae95f9 | 795 | INIT_LIST_HEAD(&dev->msi_list); |
d389fec6 | 796 | } |