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1da177e4 LT |
1 | /* |
2 | * Standard Hot Plug Controller Driver | |
3 | * | |
4 | * Copyright (C) 1995,2001 Compaq Computer Corporation | |
5 | * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) | |
6 | * Copyright (C) 2001 IBM | |
7 | * Copyright (C) 2003-2004 Intel Corporation | |
8 | * | |
9 | * All rights reserved. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
19 | * NON INFRINGEMENT. See the GNU General Public License for more | |
20 | * details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
8cf4c195 | 26 | * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> |
1da177e4 LT |
27 | * |
28 | */ | |
29 | #ifndef _SHPCHP_H | |
30 | #define _SHPCHP_H | |
31 | ||
32 | #include <linux/types.h> | |
33 | #include <linux/pci.h> | |
7a54f25c | 34 | #include <linux/pci_hotplug.h> |
1da177e4 | 35 | #include <linux/delay.h> |
4e57b681 | 36 | #include <linux/sched.h> /* signal_pending(), struct timer_list */ |
6aa4cdd0 | 37 | #include <linux/mutex.h> |
4e57b681 | 38 | |
1da177e4 LT |
39 | #if !defined(MODULE) |
40 | #define MY_NAME "shpchp" | |
41 | #else | |
42 | #define MY_NAME THIS_MODULE->name | |
43 | #endif | |
44 | ||
45 | extern int shpchp_poll_mode; | |
46 | extern int shpchp_poll_time; | |
47 | extern int shpchp_debug; | |
f7391f53 | 48 | extern struct workqueue_struct *shpchp_wq; |
1da177e4 | 49 | |
8352e04e | 50 | #define dbg(format, arg...) \ |
1c35b8e5 FS |
51 | do { \ |
52 | if (shpchp_debug) \ | |
53 | printk(KERN_DEBUG "%s: " format, MY_NAME , ## arg); \ | |
54 | } while (0) | |
8352e04e KK |
55 | #define err(format, arg...) \ |
56 | printk(KERN_ERR "%s: " format, MY_NAME , ## arg) | |
57 | #define info(format, arg...) \ | |
58 | printk(KERN_INFO "%s: " format, MY_NAME , ## arg) | |
59 | #define warn(format, arg...) \ | |
60 | printk(KERN_WARNING "%s: " format, MY_NAME , ## arg) | |
1da177e4 | 61 | |
f98ca311 TI |
62 | #define ctrl_dbg(ctrl, format, arg...) \ |
63 | do { \ | |
64 | if (shpchp_debug) \ | |
1c35b8e5 | 65 | dev_printk(KERN_DEBUG, &ctrl->pci_dev->dev, \ |
f98ca311 TI |
66 | format, ## arg); \ |
67 | } while (0) | |
68 | #define ctrl_err(ctrl, format, arg...) \ | |
69 | dev_err(&ctrl->pci_dev->dev, format, ## arg) | |
70 | #define ctrl_info(ctrl, format, arg...) \ | |
71 | dev_info(&ctrl->pci_dev->dev, format, ## arg) | |
72 | #define ctrl_warn(ctrl, format, arg...) \ | |
73 | dev_warn(&ctrl->pci_dev->dev, format, ## arg) | |
74 | ||
75 | ||
bbe779db | 76 | #define SLOT_NAME_SIZE 10 |
1da177e4 | 77 | struct slot { |
1da177e4 LT |
78 | u8 bus; |
79 | u8 device; | |
2178bfad | 80 | u16 status; |
1da177e4 LT |
81 | u32 number; |
82 | u8 is_a_board; | |
1da177e4 | 83 | u8 state; |
1da177e4 | 84 | u8 presence_save; |
2178bfad | 85 | u8 pwr_save; |
1da177e4 LT |
86 | struct controller *ctrl; |
87 | struct hpc_ops *hpc_ops; | |
88 | struct hotplug_slot *hotplug_slot; | |
89 | struct list_head slot_list; | |
c4028958 | 90 | struct delayed_work work; /* work for button event */ |
a246fa4e | 91 | struct mutex lock; |
66f17055 | 92 | u8 hp_slot; |
1da177e4 LT |
93 | }; |
94 | ||
1da177e4 LT |
95 | struct event_info { |
96 | u32 event_type; | |
f7391f53 KK |
97 | struct slot *p_slot; |
98 | struct work_struct work; | |
1da177e4 LT |
99 | }; |
100 | ||
101 | struct controller { | |
6aa4cdd0 | 102 | struct mutex crit_sect; /* critical section mutex */ |
d29aadda | 103 | struct mutex cmd_lock; /* command lock */ |
1da177e4 LT |
104 | int num_slots; /* Number of slots on ctlr */ |
105 | int slot_num_inc; /* 1 or -1 */ | |
1da177e4 | 106 | struct pci_dev *pci_dev; |
5b1a960d | 107 | struct list_head slot_list; |
1da177e4 LT |
108 | struct hpc_ops *hpc_ops; |
109 | wait_queue_head_t queue; /* sleep & wake process */ | |
1da177e4 | 110 | u8 slot_device_offset; |
53044f35 | 111 | u32 pcix_misc2_reg; /* for amd pogo errata */ |
1da177e4 | 112 | u32 first_slot; /* First physical slot number */ |
0455986c KK |
113 | u32 cap_offset; |
114 | unsigned long mmio_base; | |
115 | unsigned long mmio_size; | |
0abe68ce KK |
116 | void __iomem *creg; |
117 | struct timer_list poll_timer; | |
1da177e4 LT |
118 | }; |
119 | ||
1da177e4 | 120 | /* Define AMD SHPC ID */ |
9f593e30 | 121 | #define PCI_DEVICE_ID_AMD_GOLAM_7450 0x7450 |
53044f35 KD |
122 | #define PCI_DEVICE_ID_AMD_POGO_7458 0x7458 |
123 | ||
124 | /* AMD PCIX bridge registers */ | |
53044f35 KD |
125 | #define PCIX_MEM_BASE_LIMIT_OFFSET 0x1C |
126 | #define PCIX_MISCII_OFFSET 0x48 | |
127 | #define PCIX_MISC_BRIDGE_ERRORS_OFFSET 0x80 | |
128 | ||
129 | /* AMD PCIX_MISCII masks and offsets */ | |
130 | #define PERRNONFATALENABLE_MASK 0x00040000 | |
131 | #define PERRFATALENABLE_MASK 0x00080000 | |
132 | #define PERRFLOODENABLE_MASK 0x00100000 | |
133 | #define SERRNONFATALENABLE_MASK 0x00200000 | |
134 | #define SERRFATALENABLE_MASK 0x00400000 | |
135 | ||
136 | /* AMD PCIX_MISC_BRIDGE_ERRORS masks and offsets */ | |
137 | #define PERR_OBSERVED_MASK 0x00000001 | |
138 | ||
139 | /* AMD PCIX_MEM_BASE_LIMIT masks */ | |
140 | #define RSE_MASK 0x40000000 | |
1da177e4 LT |
141 | |
142 | #define INT_BUTTON_IGNORE 0 | |
143 | #define INT_PRESENCE_ON 1 | |
144 | #define INT_PRESENCE_OFF 2 | |
145 | #define INT_SWITCH_CLOSE 3 | |
146 | #define INT_SWITCH_OPEN 4 | |
147 | #define INT_POWER_FAULT 5 | |
148 | #define INT_POWER_FAULT_CLEAR 6 | |
149 | #define INT_BUTTON_PRESS 7 | |
150 | #define INT_BUTTON_RELEASE 8 | |
151 | #define INT_BUTTON_CANCEL 9 | |
152 | ||
153 | #define STATIC_STATE 0 | |
154 | #define BLINKINGON_STATE 1 | |
155 | #define BLINKINGOFF_STATE 2 | |
156 | #define POWERON_STATE 3 | |
157 | #define POWEROFF_STATE 4 | |
158 | ||
1da177e4 LT |
159 | /* Error messages */ |
160 | #define INTERLOCK_OPEN 0x00000002 | |
161 | #define ADD_NOT_SUPPORTED 0x00000003 | |
162 | #define CARD_FUNCTIONING 0x00000005 | |
163 | #define ADAPTER_NOT_SAME 0x00000006 | |
164 | #define NO_ADAPTER_PRESENT 0x00000009 | |
165 | #define NOT_ENOUGH_RESOURCES 0x0000000B | |
166 | #define DEVICE_TYPE_NOT_SUPPORTED 0x0000000C | |
167 | #define WRONG_BUS_FREQUENCY 0x0000000D | |
168 | #define POWER_FAILURE 0x0000000E | |
169 | ||
e1b95dc6 | 170 | extern int __must_check shpchp_create_ctrl_files(struct controller *ctrl); |
8352e04e KK |
171 | extern void shpchp_remove_ctrl_files(struct controller *ctrl); |
172 | extern int shpchp_sysfs_enable_slot(struct slot *slot); | |
173 | extern int shpchp_sysfs_disable_slot(struct slot *slot); | |
0abe68ce KK |
174 | extern u8 shpchp_handle_attention_button(u8 hp_slot, struct controller *ctrl); |
175 | extern u8 shpchp_handle_switch_change(u8 hp_slot, struct controller *ctrl); | |
176 | extern u8 shpchp_handle_presence_change(u8 hp_slot, struct controller *ctrl); | |
177 | extern u8 shpchp_handle_power_fault(u8 hp_slot, struct controller *ctrl); | |
8352e04e KK |
178 | extern int shpchp_configure_device(struct slot *p_slot); |
179 | extern int shpchp_unconfigure_device(struct slot *p_slot); | |
180 | extern void cleanup_slots(struct controller *ctrl); | |
e325e1f0 | 181 | extern void shpchp_queue_pushbutton_work(struct work_struct *work); |
8352e04e | 182 | extern int shpc_init( struct controller *ctrl, struct pci_dev *pdev); |
783c49fc | 183 | |
66f17055 AC |
184 | static inline const char *slot_name(struct slot *slot) |
185 | { | |
186 | return hotplug_slot_name(slot->hotplug_slot); | |
187 | } | |
188 | ||
783c49fc | 189 | #ifdef CONFIG_ACPI |
ac9c052d | 190 | #include <linux/pci-acpi.h> |
783c49fc | 191 | static inline int get_hp_params_from_firmware(struct pci_dev *dev, |
8352e04e | 192 | struct hotplug_params *hpp) |
783c49fc | 193 | { |
7430e34c | 194 | if (ACPI_FAILURE(acpi_get_hp_params_from_firmware(dev->bus, hpp))) |
783c49fc KA |
195 | return -ENODEV; |
196 | return 0; | |
197 | } | |
ac9c052d KK |
198 | |
199 | static inline int get_hp_hw_control_from_firmware(struct pci_dev *dev) | |
200 | { | |
201 | u32 flags = OSC_SHPC_NATIVE_HP_CONTROL; | |
202 | return acpi_get_hp_hw_control_from_firmware(dev, flags); | |
203 | } | |
783c49fc KA |
204 | #else |
205 | #define get_hp_params_from_firmware(dev, hpp) (-ENODEV) | |
ac9c052d | 206 | #define get_hp_hw_control_from_firmware(dev) (0) |
783c49fc KA |
207 | #endif |
208 | ||
1da177e4 LT |
209 | struct ctrl_reg { |
210 | volatile u32 base_offset; | |
211 | volatile u32 slot_avail1; | |
212 | volatile u32 slot_avail2; | |
213 | volatile u32 slot_config; | |
214 | volatile u16 sec_bus_config; | |
215 | volatile u8 msi_ctrl; | |
216 | volatile u8 prog_interface; | |
217 | volatile u16 cmd; | |
218 | volatile u16 cmd_status; | |
219 | volatile u32 intr_loc; | |
220 | volatile u32 serr_loc; | |
221 | volatile u32 serr_intr_enable; | |
222 | volatile u32 slot1; | |
1da177e4 LT |
223 | } __attribute__ ((packed)); |
224 | ||
225 | /* offsets to the controller registers based on the above structure layout */ | |
226 | enum ctrl_offsets { | |
8352e04e KK |
227 | BASE_OFFSET = offsetof(struct ctrl_reg, base_offset), |
228 | SLOT_AVAIL1 = offsetof(struct ctrl_reg, slot_avail1), | |
229 | SLOT_AVAIL2 = offsetof(struct ctrl_reg, slot_avail2), | |
230 | SLOT_CONFIG = offsetof(struct ctrl_reg, slot_config), | |
231 | SEC_BUS_CONFIG = offsetof(struct ctrl_reg, sec_bus_config), | |
232 | MSI_CTRL = offsetof(struct ctrl_reg, msi_ctrl), | |
233 | PROG_INTERFACE = offsetof(struct ctrl_reg, prog_interface), | |
234 | CMD = offsetof(struct ctrl_reg, cmd), | |
235 | CMD_STATUS = offsetof(struct ctrl_reg, cmd_status), | |
236 | INTR_LOC = offsetof(struct ctrl_reg, intr_loc), | |
237 | SERR_LOC = offsetof(struct ctrl_reg, serr_loc), | |
238 | SERR_INTR_ENABLE = offsetof(struct ctrl_reg, serr_intr_enable), | |
239 | SLOT1 = offsetof(struct ctrl_reg, slot1), | |
1da177e4 | 240 | }; |
1da177e4 | 241 | |
8352e04e | 242 | static inline struct slot *get_slot(struct hotplug_slot *hotplug_slot) |
9f593e30 | 243 | { |
8352e04e | 244 | return hotplug_slot->private; |
1da177e4 LT |
245 | } |
246 | ||
8352e04e | 247 | static inline struct slot *shpchp_find_slot(struct controller *ctrl, u8 device) |
1da177e4 | 248 | { |
5b1a960d | 249 | struct slot *slot; |
1da177e4 | 250 | |
5b1a960d KK |
251 | list_for_each_entry(slot, &ctrl->slot_list, slot_list) { |
252 | if (slot->device == device) | |
253 | return slot; | |
1da177e4 LT |
254 | } |
255 | ||
be7bce25 | 256 | ctrl_err(ctrl, "Slot (device=0x%02x) not found\n", device); |
5b1a960d | 257 | return NULL; |
1da177e4 LT |
258 | } |
259 | ||
53044f35 KD |
260 | static inline void amd_pogo_errata_save_misc_reg(struct slot *p_slot) |
261 | { | |
262 | u32 pcix_misc2_temp; | |
263 | ||
264 | /* save MiscII register */ | |
265 | pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp); | |
266 | ||
267 | p_slot->ctrl->pcix_misc2_reg = pcix_misc2_temp; | |
268 | ||
269 | /* clear SERR/PERR enable bits */ | |
270 | pcix_misc2_temp &= ~SERRFATALENABLE_MASK; | |
271 | pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK; | |
272 | pcix_misc2_temp &= ~PERRFLOODENABLE_MASK; | |
273 | pcix_misc2_temp &= ~PERRFATALENABLE_MASK; | |
274 | pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK; | |
275 | pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp); | |
276 | } | |
277 | ||
278 | static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot) | |
279 | { | |
280 | u32 pcix_misc2_temp; | |
281 | u32 pcix_bridge_errors_reg; | |
282 | u32 pcix_mem_base_reg; | |
283 | u8 perr_set; | |
284 | u8 rse_set; | |
285 | ||
286 | /* write-one-to-clear Bridge_Errors[ PERR_OBSERVED ] */ | |
287 | pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg); | |
288 | perr_set = pcix_bridge_errors_reg & PERR_OBSERVED_MASK; | |
289 | if (perr_set) { | |
f98ca311 | 290 | ctrl_dbg(p_slot->ctrl, |
be7bce25 TI |
291 | "Bridge_Errors[ PERR_OBSERVED = %08X] (W1C)\n", |
292 | perr_set); | |
53044f35 KD |
293 | |
294 | pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set); | |
295 | } | |
296 | ||
297 | /* write-one-to-clear Memory_Base_Limit[ RSE ] */ | |
298 | pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg); | |
299 | rse_set = pcix_mem_base_reg & RSE_MASK; | |
300 | if (rse_set) { | |
be7bce25 | 301 | ctrl_dbg(p_slot->ctrl, "Memory_Base_Limit[ RSE ] (W1C)\n"); |
53044f35 KD |
302 | |
303 | pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set); | |
304 | } | |
305 | /* restore MiscII register */ | |
306 | pci_read_config_dword( p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp ); | |
307 | ||
308 | if (p_slot->ctrl->pcix_misc2_reg & SERRFATALENABLE_MASK) | |
309 | pcix_misc2_temp |= SERRFATALENABLE_MASK; | |
310 | else | |
311 | pcix_misc2_temp &= ~SERRFATALENABLE_MASK; | |
312 | ||
313 | if (p_slot->ctrl->pcix_misc2_reg & SERRNONFATALENABLE_MASK) | |
314 | pcix_misc2_temp |= SERRNONFATALENABLE_MASK; | |
315 | else | |
316 | pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK; | |
317 | ||
318 | if (p_slot->ctrl->pcix_misc2_reg & PERRFLOODENABLE_MASK) | |
319 | pcix_misc2_temp |= PERRFLOODENABLE_MASK; | |
320 | else | |
321 | pcix_misc2_temp &= ~PERRFLOODENABLE_MASK; | |
322 | ||
323 | if (p_slot->ctrl->pcix_misc2_reg & PERRFATALENABLE_MASK) | |
324 | pcix_misc2_temp |= PERRFATALENABLE_MASK; | |
325 | else | |
326 | pcix_misc2_temp &= ~PERRFATALENABLE_MASK; | |
327 | ||
328 | if (p_slot->ctrl->pcix_misc2_reg & PERRNONFATALENABLE_MASK) | |
329 | pcix_misc2_temp |= PERRNONFATALENABLE_MASK; | |
330 | else | |
331 | pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK; | |
332 | pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp); | |
333 | } | |
334 | ||
1da177e4 | 335 | struct hpc_ops { |
8352e04e KK |
336 | int (*power_on_slot)(struct slot *slot); |
337 | int (*slot_enable)(struct slot *slot); | |
338 | int (*slot_disable)(struct slot *slot); | |
339 | int (*set_bus_speed_mode)(struct slot *slot, enum pci_bus_speed speed); | |
340 | int (*get_power_status)(struct slot *slot, u8 *status); | |
341 | int (*get_attention_status)(struct slot *slot, u8 *status); | |
342 | int (*set_attention_status)(struct slot *slot, u8 status); | |
343 | int (*get_latch_status)(struct slot *slot, u8 *status); | |
344 | int (*get_adapter_status)(struct slot *slot, u8 *status); | |
345 | int (*get_max_bus_speed)(struct slot *slot, enum pci_bus_speed *speed); | |
346 | int (*get_cur_bus_speed)(struct slot *slot, enum pci_bus_speed *speed); | |
347 | int (*get_adapter_speed)(struct slot *slot, enum pci_bus_speed *speed); | |
348 | int (*get_mode1_ECC_cap)(struct slot *slot, u8 *mode); | |
349 | int (*get_prog_int)(struct slot *slot, u8 *prog_int); | |
350 | int (*query_power_fault)(struct slot *slot); | |
351 | void (*green_led_on)(struct slot *slot); | |
352 | void (*green_led_off)(struct slot *slot); | |
353 | void (*green_led_blink)(struct slot *slot); | |
354 | void (*release_ctlr)(struct controller *ctrl); | |
355 | int (*check_cmd_status)(struct controller *ctrl); | |
1da177e4 LT |
356 | }; |
357 | ||
358 | #endif /* _SHPCHP_H */ |