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1da177e4 LT |
1 | /* |
2 | * PCI Express PCI Hot Plug Driver | |
3 | * | |
4 | * Copyright (C) 1995,2001 Compaq Computer Corporation | |
5 | * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) | |
6 | * Copyright (C) 2001 IBM Corp. | |
7 | * Copyright (C) 2003-2004 Intel Corporation | |
8 | * | |
9 | * All rights reserved. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
19 | * NON INFRINGEMENT. See the GNU General Public License for more | |
20 | * details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
8cf4c195 | 26 | * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> |
1da177e4 LT |
27 | * |
28 | */ | |
29 | ||
1da177e4 LT |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
32 | #include <linux/types.h> | |
de25968c TS |
33 | #include <linux/signal.h> |
34 | #include <linux/jiffies.h> | |
35 | #include <linux/timer.h> | |
1da177e4 | 36 | #include <linux/pci.h> |
5d1b8c9e AM |
37 | #include <linux/interrupt.h> |
38 | ||
1da177e4 LT |
39 | #include "../pci.h" |
40 | #include "pciehp.h" | |
1da177e4 LT |
41 | #ifdef DEBUG |
42 | #define DBG_K_TRACE_ENTRY ((unsigned int)0x00000001) /* On function entry */ | |
43 | #define DBG_K_TRACE_EXIT ((unsigned int)0x00000002) /* On function exit */ | |
44 | #define DBG_K_INFO ((unsigned int)0x00000004) /* Info messages */ | |
45 | #define DBG_K_ERROR ((unsigned int)0x00000008) /* Error messages */ | |
46 | #define DBG_K_TRACE (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT) | |
47 | #define DBG_K_STANDARD (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE) | |
48 | /* Redefine this flagword to set debug level */ | |
49 | #define DEBUG_LEVEL DBG_K_STANDARD | |
50 | ||
51 | #define DEFINE_DBG_BUFFER char __dbg_str_buf[256]; | |
52 | ||
53 | #define DBG_PRINT( dbg_flags, args... ) \ | |
54 | do { \ | |
55 | if ( DEBUG_LEVEL & ( dbg_flags ) ) \ | |
56 | { \ | |
57 | int len; \ | |
58 | len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \ | |
59 | __FILE__, __LINE__, __FUNCTION__ ); \ | |
60 | sprintf( __dbg_str_buf + len, args ); \ | |
61 | printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \ | |
62 | } \ | |
63 | } while (0) | |
64 | ||
65 | #define DBG_ENTER_ROUTINE DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]"); | |
66 | #define DBG_LEAVE_ROUTINE DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]"); | |
67 | #else | |
68 | #define DEFINE_DBG_BUFFER | |
69 | #define DBG_ENTER_ROUTINE | |
70 | #define DBG_LEAVE_ROUTINE | |
71 | #endif /* DEBUG */ | |
72 | ||
73 | struct ctrl_reg { | |
74 | u8 cap_id; | |
75 | u8 nxt_ptr; | |
76 | u16 cap_reg; | |
77 | u32 dev_cap; | |
78 | u16 dev_ctrl; | |
79 | u16 dev_status; | |
80 | u32 lnk_cap; | |
81 | u16 lnk_ctrl; | |
82 | u16 lnk_status; | |
83 | u32 slot_cap; | |
84 | u16 slot_ctrl; | |
85 | u16 slot_status; | |
86 | u16 root_ctrl; | |
87 | u16 rsvp; | |
88 | u32 root_status; | |
89 | } __attribute__ ((packed)); | |
90 | ||
91 | /* offsets to the controller registers based on the above structure layout */ | |
92 | enum ctrl_offsets { | |
93 | PCIECAPID = offsetof(struct ctrl_reg, cap_id), | |
94 | NXTCAPPTR = offsetof(struct ctrl_reg, nxt_ptr), | |
95 | CAPREG = offsetof(struct ctrl_reg, cap_reg), | |
96 | DEVCAP = offsetof(struct ctrl_reg, dev_cap), | |
97 | DEVCTRL = offsetof(struct ctrl_reg, dev_ctrl), | |
98 | DEVSTATUS = offsetof(struct ctrl_reg, dev_status), | |
99 | LNKCAP = offsetof(struct ctrl_reg, lnk_cap), | |
100 | LNKCTRL = offsetof(struct ctrl_reg, lnk_ctrl), | |
101 | LNKSTATUS = offsetof(struct ctrl_reg, lnk_status), | |
102 | SLOTCAP = offsetof(struct ctrl_reg, slot_cap), | |
103 | SLOTCTRL = offsetof(struct ctrl_reg, slot_ctrl), | |
104 | SLOTSTATUS = offsetof(struct ctrl_reg, slot_status), | |
105 | ROOTCTRL = offsetof(struct ctrl_reg, root_ctrl), | |
106 | ROOTSTATUS = offsetof(struct ctrl_reg, root_status), | |
107 | }; | |
108 | static int pcie_cap_base = 0; /* Base of the PCI Express capability item structure */ | |
109 | ||
8b245e45 DS |
110 | #define PCIE_CAP_ID(cb) ( cb + PCIECAPID ) |
111 | #define NXT_CAP_PTR(cb) ( cb + NXTCAPPTR ) | |
112 | #define CAP_REG(cb) ( cb + CAPREG ) | |
113 | #define DEV_CAP(cb) ( cb + DEVCAP ) | |
114 | #define DEV_CTRL(cb) ( cb + DEVCTRL ) | |
115 | #define DEV_STATUS(cb) ( cb + DEVSTATUS ) | |
116 | #define LNK_CAP(cb) ( cb + LNKCAP ) | |
117 | #define LNK_CTRL(cb) ( cb + LNKCTRL ) | |
118 | #define LNK_STATUS(cb) ( cb + LNKSTATUS ) | |
119 | #define SLOT_CAP(cb) ( cb + SLOTCAP ) | |
120 | #define SLOT_CTRL(cb) ( cb + SLOTCTRL ) | |
121 | #define SLOT_STATUS(cb) ( cb + SLOTSTATUS ) | |
122 | #define ROOT_CTRL(cb) ( cb + ROOTCTRL ) | |
123 | #define ROOT_STATUS(cb) ( cb + ROOTSTATUS ) | |
1da177e4 LT |
124 | |
125 | #define hp_register_read_word(pdev, reg , value) \ | |
126 | pci_read_config_word(pdev, reg, &value) | |
127 | ||
128 | #define hp_register_read_dword(pdev, reg , value) \ | |
129 | pci_read_config_dword(pdev, reg, &value) | |
130 | ||
131 | #define hp_register_write_word(pdev, reg , value) \ | |
132 | pci_write_config_word(pdev, reg, value) | |
133 | ||
134 | #define hp_register_dwrite_word(pdev, reg , value) \ | |
135 | pci_write_config_dword(pdev, reg, value) | |
136 | ||
137 | /* Field definitions in PCI Express Capabilities Register */ | |
138 | #define CAP_VER 0x000F | |
139 | #define DEV_PORT_TYPE 0x00F0 | |
140 | #define SLOT_IMPL 0x0100 | |
141 | #define MSG_NUM 0x3E00 | |
142 | ||
143 | /* Device or Port Type */ | |
144 | #define NAT_ENDPT 0x00 | |
145 | #define LEG_ENDPT 0x01 | |
146 | #define ROOT_PORT 0x04 | |
147 | #define UP_STREAM 0x05 | |
148 | #define DN_STREAM 0x06 | |
149 | #define PCIE_PCI_BRDG 0x07 | |
150 | #define PCI_PCIE_BRDG 0x10 | |
151 | ||
152 | /* Field definitions in Device Capabilities Register */ | |
153 | #define DATTN_BUTTN_PRSN 0x1000 | |
154 | #define DATTN_LED_PRSN 0x2000 | |
155 | #define DPWR_LED_PRSN 0x4000 | |
156 | ||
157 | /* Field definitions in Link Capabilities Register */ | |
158 | #define MAX_LNK_SPEED 0x000F | |
159 | #define MAX_LNK_WIDTH 0x03F0 | |
160 | ||
161 | /* Link Width Encoding */ | |
162 | #define LNK_X1 0x01 | |
163 | #define LNK_X2 0x02 | |
164 | #define LNK_X4 0x04 | |
165 | #define LNK_X8 0x08 | |
166 | #define LNK_X12 0x0C | |
167 | #define LNK_X16 0x10 | |
168 | #define LNK_X32 0x20 | |
169 | ||
170 | /*Field definitions of Link Status Register */ | |
171 | #define LNK_SPEED 0x000F | |
172 | #define NEG_LINK_WD 0x03F0 | |
173 | #define LNK_TRN_ERR 0x0400 | |
174 | #define LNK_TRN 0x0800 | |
175 | #define SLOT_CLK_CONF 0x1000 | |
176 | ||
177 | /* Field definitions in Slot Capabilities Register */ | |
178 | #define ATTN_BUTTN_PRSN 0x00000001 | |
179 | #define PWR_CTRL_PRSN 0x00000002 | |
180 | #define MRL_SENS_PRSN 0x00000004 | |
181 | #define ATTN_LED_PRSN 0x00000008 | |
182 | #define PWR_LED_PRSN 0x00000010 | |
183 | #define HP_SUPR_RM_SUP 0x00000020 | |
184 | #define HP_CAP 0x00000040 | |
185 | #define SLOT_PWR_VALUE 0x000003F8 | |
186 | #define SLOT_PWR_LIMIT 0x00000C00 | |
187 | #define PSN 0xFFF80000 /* PSN: Physical Slot Number */ | |
188 | ||
189 | /* Field definitions in Slot Control Register */ | |
190 | #define ATTN_BUTTN_ENABLE 0x0001 | |
191 | #define PWR_FAULT_DETECT_ENABLE 0x0002 | |
192 | #define MRL_DETECT_ENABLE 0x0004 | |
193 | #define PRSN_DETECT_ENABLE 0x0008 | |
194 | #define CMD_CMPL_INTR_ENABLE 0x0010 | |
195 | #define HP_INTR_ENABLE 0x0020 | |
196 | #define ATTN_LED_CTRL 0x00C0 | |
197 | #define PWR_LED_CTRL 0x0300 | |
198 | #define PWR_CTRL 0x0400 | |
199 | ||
200 | /* Attention indicator and Power indicator states */ | |
201 | #define LED_ON 0x01 | |
202 | #define LED_BLINK 0x10 | |
203 | #define LED_OFF 0x11 | |
204 | ||
205 | /* Power Control Command */ | |
206 | #define POWER_ON 0 | |
207 | #define POWER_OFF 0x0400 | |
208 | ||
209 | /* Field definitions in Slot Status Register */ | |
210 | #define ATTN_BUTTN_PRESSED 0x0001 | |
211 | #define PWR_FAULT_DETECTED 0x0002 | |
212 | #define MRL_SENS_CHANGED 0x0004 | |
213 | #define PRSN_DETECT_CHANGED 0x0008 | |
214 | #define CMD_COMPLETED 0x0010 | |
215 | #define MRL_STATE 0x0020 | |
216 | #define PRSN_STATE 0x0040 | |
217 | ||
1da177e4 LT |
218 | static spinlock_t hpc_event_lock; |
219 | ||
220 | DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */ | |
1da177e4 | 221 | static int ctlr_seq_num = 0; /* Controller sequence # */ |
1da177e4 | 222 | |
48fe3915 KK |
223 | static irqreturn_t pcie_isr(int irq, void *dev_id); |
224 | static void start_int_poll_timer(struct controller *ctrl, int sec); | |
1da177e4 LT |
225 | |
226 | /* This is the interrupt polling timeout function. */ | |
48fe3915 | 227 | static void int_poll_timeout(unsigned long data) |
1da177e4 | 228 | { |
48fe3915 | 229 | struct controller *ctrl = (struct controller *)data; |
1da177e4 LT |
230 | |
231 | DBG_ENTER_ROUTINE | |
232 | ||
1da177e4 | 233 | /* Poll for interrupt events. regs == NULL => polling */ |
48fe3915 | 234 | pcie_isr(0, ctrl); |
1da177e4 | 235 | |
48fe3915 | 236 | init_timer(&ctrl->poll_timer); |
1da177e4 LT |
237 | if (!pciehp_poll_time) |
238 | pciehp_poll_time = 2; /* reset timer to poll in 2 secs if user doesn't specify at module installation*/ | |
239 | ||
48fe3915 | 240 | start_int_poll_timer(ctrl, pciehp_poll_time); |
1da177e4 LT |
241 | } |
242 | ||
243 | /* This function starts the interrupt polling timer. */ | |
48fe3915 | 244 | static void start_int_poll_timer(struct controller *ctrl, int sec) |
1da177e4 | 245 | { |
48fe3915 KK |
246 | /* Clamp to sane value */ |
247 | if ((sec <= 0) || (sec > 60)) | |
248 | sec = 2; | |
249 | ||
250 | ctrl->poll_timer.function = &int_poll_timeout; | |
251 | ctrl->poll_timer.data = (unsigned long)ctrl; | |
252 | ctrl->poll_timer.expires = jiffies + sec * HZ; | |
253 | add_timer(&ctrl->poll_timer); | |
1da177e4 LT |
254 | } |
255 | ||
256 | static int pcie_write_cmd(struct slot *slot, u16 cmd) | |
257 | { | |
48fe3915 | 258 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
259 | int retval = 0; |
260 | u16 slot_status; | |
261 | ||
262 | DBG_ENTER_ROUTINE | |
263 | ||
48fe3915 | 264 | retval = hp_register_read_word(ctrl->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status); |
1da177e4 LT |
265 | if (retval) { |
266 | err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__); | |
267 | return retval; | |
268 | } | |
1da177e4 LT |
269 | |
270 | if ((slot_status & CMD_COMPLETED) == CMD_COMPLETED ) { | |
271 | /* After 1 sec and CMD_COMPLETED still not set, just proceed forward to issue | |
272 | the next command according to spec. Just print out the error message */ | |
273 | dbg("%s : CMD_COMPLETED not clear after 1 sec.\n", __FUNCTION__); | |
274 | } | |
275 | ||
48fe3915 | 276 | retval = hp_register_write_word(ctrl->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), cmd | CMD_CMPL_INTR_ENABLE); |
1da177e4 LT |
277 | if (retval) { |
278 | err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__); | |
279 | return retval; | |
280 | } | |
1da177e4 LT |
281 | |
282 | DBG_LEAVE_ROUTINE | |
283 | return retval; | |
284 | } | |
285 | ||
286 | static int hpc_check_lnk_status(struct controller *ctrl) | |
287 | { | |
1da177e4 LT |
288 | u16 lnk_status; |
289 | int retval = 0; | |
290 | ||
291 | DBG_ENTER_ROUTINE | |
292 | ||
48fe3915 | 293 | retval = hp_register_read_word(ctrl->pci_dev, LNK_STATUS(ctrl->cap_base), lnk_status); |
1da177e4 LT |
294 | if (retval) { |
295 | err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__); | |
296 | return retval; | |
297 | } | |
298 | ||
299 | dbg("%s: lnk_status = %x\n", __FUNCTION__, lnk_status); | |
300 | if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) || | |
301 | !(lnk_status & NEG_LINK_WD)) { | |
302 | err("%s : Link Training Error occurs \n", __FUNCTION__); | |
303 | retval = -1; | |
304 | return retval; | |
305 | } | |
306 | ||
307 | DBG_LEAVE_ROUTINE | |
308 | return retval; | |
309 | } | |
310 | ||
311 | ||
312 | static int hpc_get_attention_status(struct slot *slot, u8 *status) | |
313 | { | |
48fe3915 | 314 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
315 | u16 slot_ctrl; |
316 | u8 atten_led_state; | |
317 | int retval = 0; | |
318 | ||
319 | DBG_ENTER_ROUTINE | |
320 | ||
48fe3915 | 321 | retval = hp_register_read_word(ctrl->pci_dev, SLOT_CTRL(ctrl->cap_base), slot_ctrl); |
1da177e4 LT |
322 | if (retval) { |
323 | err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); | |
324 | return retval; | |
325 | } | |
326 | ||
8b245e45 | 327 | dbg("%s: SLOT_CTRL %x, value read %x\n", __FUNCTION__,SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl); |
1da177e4 LT |
328 | |
329 | atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6; | |
330 | ||
331 | switch (atten_led_state) { | |
332 | case 0: | |
333 | *status = 0xFF; /* Reserved */ | |
334 | break; | |
335 | case 1: | |
336 | *status = 1; /* On */ | |
337 | break; | |
338 | case 2: | |
339 | *status = 2; /* Blink */ | |
340 | break; | |
341 | case 3: | |
342 | *status = 0; /* Off */ | |
343 | break; | |
344 | default: | |
345 | *status = 0xFF; | |
346 | break; | |
347 | } | |
348 | ||
349 | DBG_LEAVE_ROUTINE | |
350 | return 0; | |
351 | } | |
352 | ||
48fe3915 | 353 | static int hpc_get_power_status(struct slot *slot, u8 *status) |
1da177e4 | 354 | { |
48fe3915 | 355 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
356 | u16 slot_ctrl; |
357 | u8 pwr_state; | |
358 | int retval = 0; | |
359 | ||
360 | DBG_ENTER_ROUTINE | |
361 | ||
48fe3915 | 362 | retval = hp_register_read_word(ctrl->pci_dev, SLOT_CTRL(ctrl->cap_base), slot_ctrl); |
1da177e4 LT |
363 | if (retval) { |
364 | err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); | |
365 | return retval; | |
366 | } | |
48fe3915 | 367 | dbg("%s: SLOT_CTRL %x value read %x\n", __FUNCTION__, SLOT_CTRL(ctrl->cap_base), slot_ctrl); |
1da177e4 LT |
368 | |
369 | pwr_state = (slot_ctrl & PWR_CTRL) >> 10; | |
370 | ||
371 | switch (pwr_state) { | |
372 | case 0: | |
373 | *status = 1; | |
374 | break; | |
375 | case 1: | |
376 | *status = 0; | |
377 | break; | |
378 | default: | |
379 | *status = 0xFF; | |
380 | break; | |
381 | } | |
382 | ||
383 | DBG_LEAVE_ROUTINE | |
384 | return retval; | |
385 | } | |
386 | ||
387 | ||
388 | static int hpc_get_latch_status(struct slot *slot, u8 *status) | |
389 | { | |
48fe3915 | 390 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
391 | u16 slot_status; |
392 | int retval = 0; | |
393 | ||
394 | DBG_ENTER_ROUTINE | |
395 | ||
48fe3915 | 396 | retval = hp_register_read_word(ctrl->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status); |
1da177e4 LT |
397 | if (retval) { |
398 | err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__); | |
399 | return retval; | |
400 | } | |
401 | ||
402 | *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1; | |
403 | ||
404 | DBG_LEAVE_ROUTINE | |
405 | return 0; | |
406 | } | |
407 | ||
408 | static int hpc_get_adapter_status(struct slot *slot, u8 *status) | |
409 | { | |
48fe3915 | 410 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
411 | u16 slot_status; |
412 | u8 card_state; | |
413 | int retval = 0; | |
414 | ||
415 | DBG_ENTER_ROUTINE | |
416 | ||
48fe3915 | 417 | retval = hp_register_read_word(ctrl->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status); |
1da177e4 LT |
418 | if (retval) { |
419 | err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__); | |
420 | return retval; | |
421 | } | |
422 | card_state = (u8)((slot_status & PRSN_STATE) >> 6); | |
423 | *status = (card_state == 1) ? 1 : 0; | |
424 | ||
425 | DBG_LEAVE_ROUTINE | |
426 | return 0; | |
427 | } | |
428 | ||
48fe3915 | 429 | static int hpc_query_power_fault(struct slot *slot) |
1da177e4 | 430 | { |
48fe3915 | 431 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
432 | u16 slot_status; |
433 | u8 pwr_fault; | |
434 | int retval = 0; | |
1da177e4 LT |
435 | |
436 | DBG_ENTER_ROUTINE | |
437 | ||
48fe3915 | 438 | retval = hp_register_read_word(ctrl->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status); |
1da177e4 | 439 | if (retval) { |
8239def1 | 440 | err("%s : Cannot check for power fault\n", __FUNCTION__); |
1da177e4 LT |
441 | return retval; |
442 | } | |
443 | pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1); | |
1da177e4 LT |
444 | |
445 | DBG_LEAVE_ROUTINE | |
8239def1 | 446 | return pwr_fault; |
1da177e4 LT |
447 | } |
448 | ||
449 | static int hpc_set_attention_status(struct slot *slot, u8 value) | |
450 | { | |
48fe3915 | 451 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
452 | u16 slot_cmd = 0; |
453 | u16 slot_ctrl; | |
454 | int rc = 0; | |
455 | ||
1a9ed1bf RS |
456 | DBG_ENTER_ROUTINE |
457 | ||
48fe3915 | 458 | rc = hp_register_read_word(ctrl->pci_dev, SLOT_CTRL(ctrl->cap_base), slot_ctrl); |
1da177e4 LT |
459 | if (rc) { |
460 | err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); | |
461 | return rc; | |
462 | } | |
1da177e4 LT |
463 | |
464 | switch (value) { | |
465 | case 0 : /* turn off */ | |
466 | slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x00C0; | |
467 | break; | |
468 | case 1: /* turn on */ | |
469 | slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x0040; | |
470 | break; | |
471 | case 2: /* turn blink */ | |
472 | slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x0080; | |
473 | break; | |
474 | default: | |
475 | return -1; | |
476 | } | |
477 | if (!pciehp_poll_mode) | |
478 | slot_cmd = slot_cmd | HP_INTR_ENABLE; | |
479 | ||
480 | pcie_write_cmd(slot, slot_cmd); | |
8b245e45 | 481 | dbg("%s: SLOT_CTRL %x write cmd %x\n", __FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd); |
1da177e4 | 482 | |
1a9ed1bf | 483 | DBG_LEAVE_ROUTINE |
1da177e4 LT |
484 | return rc; |
485 | } | |
486 | ||
487 | ||
488 | static void hpc_set_green_led_on(struct slot *slot) | |
489 | { | |
48fe3915 | 490 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
491 | u16 slot_cmd; |
492 | u16 slot_ctrl; | |
493 | int rc = 0; | |
494 | ||
1a9ed1bf RS |
495 | DBG_ENTER_ROUTINE |
496 | ||
48fe3915 | 497 | rc = hp_register_read_word(ctrl->pci_dev, SLOT_CTRL(ctrl->cap_base), slot_ctrl); |
1da177e4 LT |
498 | if (rc) { |
499 | err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); | |
500 | return; | |
501 | } | |
1da177e4 LT |
502 | slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0100; |
503 | if (!pciehp_poll_mode) | |
504 | slot_cmd = slot_cmd | HP_INTR_ENABLE; | |
505 | ||
506 | pcie_write_cmd(slot, slot_cmd); | |
507 | ||
8b245e45 | 508 | dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd); |
1a9ed1bf | 509 | DBG_LEAVE_ROUTINE |
1da177e4 LT |
510 | return; |
511 | } | |
512 | ||
513 | static void hpc_set_green_led_off(struct slot *slot) | |
514 | { | |
48fe3915 | 515 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
516 | u16 slot_cmd; |
517 | u16 slot_ctrl; | |
518 | int rc = 0; | |
519 | ||
1a9ed1bf RS |
520 | DBG_ENTER_ROUTINE |
521 | ||
48fe3915 | 522 | rc = hp_register_read_word(ctrl->pci_dev, SLOT_CTRL(ctrl->cap_base), slot_ctrl); |
1da177e4 LT |
523 | if (rc) { |
524 | err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); | |
525 | return; | |
526 | } | |
1da177e4 LT |
527 | |
528 | slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0300; | |
529 | ||
530 | if (!pciehp_poll_mode) | |
531 | slot_cmd = slot_cmd | HP_INTR_ENABLE; | |
532 | pcie_write_cmd(slot, slot_cmd); | |
8b245e45 | 533 | dbg("%s: SLOT_CTRL %x write cmd %x\n", __FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd); |
1da177e4 | 534 | |
1a9ed1bf | 535 | DBG_LEAVE_ROUTINE |
1da177e4 LT |
536 | return; |
537 | } | |
538 | ||
539 | static void hpc_set_green_led_blink(struct slot *slot) | |
540 | { | |
48fe3915 | 541 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
542 | u16 slot_cmd; |
543 | u16 slot_ctrl; | |
544 | int rc = 0; | |
545 | ||
1a9ed1bf RS |
546 | DBG_ENTER_ROUTINE |
547 | ||
48fe3915 | 548 | rc = hp_register_read_word(ctrl->pci_dev, SLOT_CTRL(ctrl->cap_base), slot_ctrl); |
1da177e4 LT |
549 | if (rc) { |
550 | err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); | |
551 | return; | |
552 | } | |
1da177e4 LT |
553 | |
554 | slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0200; | |
555 | ||
556 | if (!pciehp_poll_mode) | |
557 | slot_cmd = slot_cmd | HP_INTR_ENABLE; | |
558 | pcie_write_cmd(slot, slot_cmd); | |
559 | ||
8b245e45 | 560 | dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd); |
1a9ed1bf | 561 | DBG_LEAVE_ROUTINE |
1da177e4 LT |
562 | return; |
563 | } | |
564 | ||
1da177e4 LT |
565 | static void hpc_release_ctlr(struct controller *ctrl) |
566 | { | |
1da177e4 LT |
567 | DBG_ENTER_ROUTINE |
568 | ||
48fe3915 KK |
569 | if (pciehp_poll_mode) |
570 | del_timer(&ctrl->poll_timer); | |
571 | else | |
572 | free_irq(ctrl->pci_dev->irq, ctrl); | |
1da177e4 LT |
573 | |
574 | DBG_LEAVE_ROUTINE | |
1da177e4 LT |
575 | } |
576 | ||
577 | static int hpc_power_on_slot(struct slot * slot) | |
578 | { | |
48fe3915 | 579 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 580 | u16 slot_cmd; |
5a49f203 | 581 | u16 slot_ctrl, slot_status; |
1da177e4 LT |
582 | int retval = 0; |
583 | ||
584 | DBG_ENTER_ROUTINE | |
1da177e4 | 585 | |
1da177e4 | 586 | dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot); |
1da177e4 | 587 | |
5a49f203 | 588 | /* Clear sticky power-fault bit from previous power failures */ |
48fe3915 KK |
589 | hp_register_read_word(ctrl->pci_dev, |
590 | SLOT_STATUS(ctrl->cap_base), slot_status); | |
5a49f203 RS |
591 | slot_status &= PWR_FAULT_DETECTED; |
592 | if (slot_status) | |
48fe3915 KK |
593 | hp_register_write_word(ctrl->pci_dev, |
594 | SLOT_STATUS(ctrl->cap_base), slot_status); | |
1da177e4 | 595 | |
48fe3915 KK |
596 | retval = hp_register_read_word(ctrl->pci_dev, |
597 | SLOT_CTRL(ctrl->cap_base), slot_ctrl); | |
1da177e4 LT |
598 | if (retval) { |
599 | err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); | |
600 | return retval; | |
601 | } | |
1da177e4 LT |
602 | |
603 | slot_cmd = (slot_ctrl & ~PWR_CTRL) | POWER_ON; | |
604 | ||
c7ab337f | 605 | /* Enable detection that we turned off at slot power-off time */ |
1da177e4 | 606 | if (!pciehp_poll_mode) |
c7ab337f TS |
607 | slot_cmd = slot_cmd | |
608 | PWR_FAULT_DETECT_ENABLE | | |
609 | MRL_DETECT_ENABLE | | |
610 | PRSN_DETECT_ENABLE | | |
611 | HP_INTR_ENABLE; | |
1da177e4 LT |
612 | |
613 | retval = pcie_write_cmd(slot, slot_cmd); | |
614 | ||
615 | if (retval) { | |
616 | err("%s: Write %x command failed!\n", __FUNCTION__, slot_cmd); | |
617 | return -1; | |
618 | } | |
8b245e45 | 619 | dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd); |
1da177e4 LT |
620 | |
621 | DBG_LEAVE_ROUTINE | |
622 | ||
623 | return retval; | |
624 | } | |
625 | ||
626 | static int hpc_power_off_slot(struct slot * slot) | |
627 | { | |
48fe3915 | 628 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
629 | u16 slot_cmd; |
630 | u16 slot_ctrl; | |
1da177e4 LT |
631 | int retval = 0; |
632 | ||
633 | DBG_ENTER_ROUTINE | |
1da177e4 | 634 | |
1da177e4 | 635 | dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot); |
1da177e4 | 636 | |
48fe3915 | 637 | retval = hp_register_read_word(ctrl->pci_dev, SLOT_CTRL(ctrl->cap_base), slot_ctrl); |
1da177e4 LT |
638 | if (retval) { |
639 | err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); | |
640 | return retval; | |
641 | } | |
1da177e4 LT |
642 | |
643 | slot_cmd = (slot_ctrl & ~PWR_CTRL) | POWER_OFF; | |
644 | ||
c7ab337f TS |
645 | /* |
646 | * If we get MRL or presence detect interrupts now, the isr | |
647 | * will notice the sticky power-fault bit too and issue power | |
648 | * indicator change commands. This will lead to an endless loop | |
649 | * of command completions, since the power-fault bit remains on | |
650 | * till the slot is powered on again. | |
651 | */ | |
1da177e4 | 652 | if (!pciehp_poll_mode) |
c7ab337f TS |
653 | slot_cmd = (slot_cmd & |
654 | ~PWR_FAULT_DETECT_ENABLE & | |
655 | ~MRL_DETECT_ENABLE & | |
656 | ~PRSN_DETECT_ENABLE) | HP_INTR_ENABLE; | |
1da177e4 LT |
657 | |
658 | retval = pcie_write_cmd(slot, slot_cmd); | |
659 | ||
660 | if (retval) { | |
661 | err("%s: Write command failed!\n", __FUNCTION__); | |
662 | return -1; | |
663 | } | |
8b245e45 | 664 | dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd); |
1da177e4 LT |
665 | |
666 | DBG_LEAVE_ROUTINE | |
667 | ||
668 | return retval; | |
669 | } | |
670 | ||
48fe3915 | 671 | static irqreturn_t pcie_isr(int irq, void *dev_id) |
1da177e4 | 672 | { |
48fe3915 | 673 | struct controller *ctrl = (struct controller *)dev_id; |
1da177e4 LT |
674 | u16 slot_status, intr_detect, intr_loc; |
675 | u16 temp_word; | |
676 | int hp_slot = 0; /* only 1 slot per PCI Express port */ | |
677 | int rc = 0; | |
678 | ||
48fe3915 | 679 | rc = hp_register_read_word(ctrl->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status); |
1da177e4 LT |
680 | if (rc) { |
681 | err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__); | |
682 | return IRQ_NONE; | |
683 | } | |
684 | ||
685 | intr_detect = ( ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED | MRL_SENS_CHANGED | | |
686 | PRSN_DETECT_CHANGED | CMD_COMPLETED ); | |
687 | ||
688 | intr_loc = slot_status & intr_detect; | |
689 | ||
690 | /* Check to see if it was our interrupt */ | |
691 | if ( !intr_loc ) | |
692 | return IRQ_NONE; | |
693 | ||
694 | dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc); | |
695 | /* Mask Hot-plug Interrupt Enable */ | |
696 | if (!pciehp_poll_mode) { | |
48fe3915 | 697 | rc = hp_register_read_word(ctrl->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word); |
1da177e4 LT |
698 | if (rc) { |
699 | err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); | |
700 | return IRQ_NONE; | |
701 | } | |
702 | ||
1da177e4 LT |
703 | dbg("%s: hp_register_read_word SLOT_CTRL with value %x\n", __FUNCTION__, temp_word); |
704 | temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00; | |
705 | ||
48fe3915 | 706 | rc = hp_register_write_word(ctrl->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word); |
1da177e4 LT |
707 | if (rc) { |
708 | err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__); | |
709 | return IRQ_NONE; | |
710 | } | |
1da177e4 | 711 | |
48fe3915 | 712 | rc = hp_register_read_word(ctrl->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status); |
1da177e4 LT |
713 | if (rc) { |
714 | err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__); | |
715 | return IRQ_NONE; | |
716 | } | |
717 | dbg("%s: hp_register_read_word SLOT_STATUS with value %x\n", __FUNCTION__, slot_status); | |
718 | ||
719 | /* Clear command complete interrupt caused by this write */ | |
720 | temp_word = 0x1f; | |
48fe3915 | 721 | rc = hp_register_write_word(ctrl->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word); |
1da177e4 LT |
722 | if (rc) { |
723 | err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__); | |
724 | return IRQ_NONE; | |
725 | } | |
1da177e4 LT |
726 | } |
727 | ||
728 | if (intr_loc & CMD_COMPLETED) { | |
729 | /* | |
730 | * Command Complete Interrupt Pending | |
731 | */ | |
1da177e4 LT |
732 | wake_up_interruptible(&ctrl->queue); |
733 | } | |
734 | ||
48fe3915 KK |
735 | if (intr_loc & MRL_SENS_CHANGED) |
736 | pciehp_handle_switch_change(hp_slot, ctrl); | |
737 | ||
738 | if (intr_loc & ATTN_BUTTN_PRESSED) | |
739 | pciehp_handle_attention_button(hp_slot, ctrl); | |
740 | ||
741 | if (intr_loc & PRSN_DETECT_CHANGED) | |
742 | pciehp_handle_presence_change(hp_slot, ctrl); | |
743 | ||
744 | if (intr_loc & PWR_FAULT_DETECTED) | |
745 | pciehp_handle_power_fault(hp_slot, ctrl); | |
1da177e4 LT |
746 | |
747 | /* Clear all events after serving them */ | |
748 | temp_word = 0x1F; | |
48fe3915 | 749 | rc = hp_register_write_word(ctrl->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word); |
1da177e4 LT |
750 | if (rc) { |
751 | err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__); | |
752 | return IRQ_NONE; | |
753 | } | |
754 | /* Unmask Hot-plug Interrupt Enable */ | |
755 | if (!pciehp_poll_mode) { | |
48fe3915 | 756 | rc = hp_register_read_word(ctrl->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word); |
1da177e4 LT |
757 | if (rc) { |
758 | err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); | |
759 | return IRQ_NONE; | |
760 | } | |
761 | ||
762 | dbg("%s: Unmask Hot-plug Interrupt Enable\n", __FUNCTION__); | |
1da177e4 LT |
763 | temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE; |
764 | ||
48fe3915 | 765 | rc = hp_register_write_word(ctrl->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word); |
1da177e4 LT |
766 | if (rc) { |
767 | err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__); | |
768 | return IRQ_NONE; | |
769 | } | |
1da177e4 | 770 | |
48fe3915 | 771 | rc = hp_register_read_word(ctrl->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status); |
1da177e4 LT |
772 | if (rc) { |
773 | err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__); | |
774 | return IRQ_NONE; | |
775 | } | |
1da177e4 LT |
776 | |
777 | /* Clear command complete interrupt caused by this write */ | |
778 | temp_word = 0x1F; | |
48fe3915 | 779 | rc = hp_register_write_word(ctrl->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word); |
1da177e4 LT |
780 | if (rc) { |
781 | err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__); | |
782 | return IRQ_NONE; | |
783 | } | |
784 | dbg("%s: hp_register_write_word SLOT_STATUS with value %x\n", __FUNCTION__, temp_word); | |
785 | } | |
786 | ||
787 | return IRQ_HANDLED; | |
788 | } | |
789 | ||
790 | static int hpc_get_max_lnk_speed (struct slot *slot, enum pci_bus_speed *value) | |
791 | { | |
48fe3915 | 792 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
793 | enum pcie_link_speed lnk_speed; |
794 | u32 lnk_cap; | |
795 | int retval = 0; | |
796 | ||
797 | DBG_ENTER_ROUTINE | |
798 | ||
48fe3915 | 799 | retval = hp_register_read_dword(ctrl->pci_dev, LNK_CAP(ctrl->cap_base), lnk_cap); |
1da177e4 LT |
800 | if (retval) { |
801 | err("%s : hp_register_read_dword LNK_CAP failed\n", __FUNCTION__); | |
802 | return retval; | |
803 | } | |
804 | ||
805 | switch (lnk_cap & 0x000F) { | |
806 | case 1: | |
807 | lnk_speed = PCIE_2PT5GB; | |
808 | break; | |
809 | default: | |
810 | lnk_speed = PCIE_LNK_SPEED_UNKNOWN; | |
811 | break; | |
812 | } | |
813 | ||
814 | *value = lnk_speed; | |
815 | dbg("Max link speed = %d\n", lnk_speed); | |
816 | DBG_LEAVE_ROUTINE | |
817 | return retval; | |
818 | } | |
819 | ||
820 | static int hpc_get_max_lnk_width (struct slot *slot, enum pcie_link_width *value) | |
821 | { | |
48fe3915 | 822 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
823 | enum pcie_link_width lnk_wdth; |
824 | u32 lnk_cap; | |
825 | int retval = 0; | |
826 | ||
827 | DBG_ENTER_ROUTINE | |
828 | ||
48fe3915 | 829 | retval = hp_register_read_dword(ctrl->pci_dev, LNK_CAP(ctrl->cap_base), lnk_cap); |
1da177e4 LT |
830 | if (retval) { |
831 | err("%s : hp_register_read_dword LNK_CAP failed\n", __FUNCTION__); | |
832 | return retval; | |
833 | } | |
834 | ||
835 | switch ((lnk_cap & 0x03F0) >> 4){ | |
836 | case 0: | |
837 | lnk_wdth = PCIE_LNK_WIDTH_RESRV; | |
838 | break; | |
839 | case 1: | |
840 | lnk_wdth = PCIE_LNK_X1; | |
841 | break; | |
842 | case 2: | |
843 | lnk_wdth = PCIE_LNK_X2; | |
844 | break; | |
845 | case 4: | |
846 | lnk_wdth = PCIE_LNK_X4; | |
847 | break; | |
848 | case 8: | |
849 | lnk_wdth = PCIE_LNK_X8; | |
850 | break; | |
851 | case 12: | |
852 | lnk_wdth = PCIE_LNK_X12; | |
853 | break; | |
854 | case 16: | |
855 | lnk_wdth = PCIE_LNK_X16; | |
856 | break; | |
857 | case 32: | |
858 | lnk_wdth = PCIE_LNK_X32; | |
859 | break; | |
860 | default: | |
861 | lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; | |
862 | break; | |
863 | } | |
864 | ||
865 | *value = lnk_wdth; | |
866 | dbg("Max link width = %d\n", lnk_wdth); | |
867 | DBG_LEAVE_ROUTINE | |
868 | return retval; | |
869 | } | |
870 | ||
871 | static int hpc_get_cur_lnk_speed (struct slot *slot, enum pci_bus_speed *value) | |
872 | { | |
48fe3915 | 873 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
874 | enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN; |
875 | int retval = 0; | |
876 | u16 lnk_status; | |
877 | ||
878 | DBG_ENTER_ROUTINE | |
879 | ||
48fe3915 | 880 | retval = hp_register_read_word(ctrl->pci_dev, LNK_STATUS(ctrl->cap_base), lnk_status); |
1da177e4 LT |
881 | if (retval) { |
882 | err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__); | |
883 | return retval; | |
884 | } | |
885 | ||
886 | switch (lnk_status & 0x0F) { | |
887 | case 1: | |
888 | lnk_speed = PCIE_2PT5GB; | |
889 | break; | |
890 | default: | |
891 | lnk_speed = PCIE_LNK_SPEED_UNKNOWN; | |
892 | break; | |
893 | } | |
894 | ||
895 | *value = lnk_speed; | |
896 | dbg("Current link speed = %d\n", lnk_speed); | |
897 | DBG_LEAVE_ROUTINE | |
898 | return retval; | |
899 | } | |
900 | ||
901 | static int hpc_get_cur_lnk_width (struct slot *slot, enum pcie_link_width *value) | |
902 | { | |
48fe3915 | 903 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
904 | enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; |
905 | int retval = 0; | |
906 | u16 lnk_status; | |
907 | ||
908 | DBG_ENTER_ROUTINE | |
909 | ||
48fe3915 | 910 | retval = hp_register_read_word(ctrl->pci_dev, LNK_STATUS(ctrl->cap_base), lnk_status); |
1da177e4 LT |
911 | if (retval) { |
912 | err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__); | |
913 | return retval; | |
914 | } | |
915 | ||
916 | switch ((lnk_status & 0x03F0) >> 4){ | |
917 | case 0: | |
918 | lnk_wdth = PCIE_LNK_WIDTH_RESRV; | |
919 | break; | |
920 | case 1: | |
921 | lnk_wdth = PCIE_LNK_X1; | |
922 | break; | |
923 | case 2: | |
924 | lnk_wdth = PCIE_LNK_X2; | |
925 | break; | |
926 | case 4: | |
927 | lnk_wdth = PCIE_LNK_X4; | |
928 | break; | |
929 | case 8: | |
930 | lnk_wdth = PCIE_LNK_X8; | |
931 | break; | |
932 | case 12: | |
933 | lnk_wdth = PCIE_LNK_X12; | |
934 | break; | |
935 | case 16: | |
936 | lnk_wdth = PCIE_LNK_X16; | |
937 | break; | |
938 | case 32: | |
939 | lnk_wdth = PCIE_LNK_X32; | |
940 | break; | |
941 | default: | |
942 | lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; | |
943 | break; | |
944 | } | |
945 | ||
946 | *value = lnk_wdth; | |
947 | dbg("Current link width = %d\n", lnk_wdth); | |
948 | DBG_LEAVE_ROUTINE | |
949 | return retval; | |
950 | } | |
951 | ||
952 | static struct hpc_ops pciehp_hpc_ops = { | |
953 | .power_on_slot = hpc_power_on_slot, | |
954 | .power_off_slot = hpc_power_off_slot, | |
955 | .set_attention_status = hpc_set_attention_status, | |
956 | .get_power_status = hpc_get_power_status, | |
957 | .get_attention_status = hpc_get_attention_status, | |
958 | .get_latch_status = hpc_get_latch_status, | |
959 | .get_adapter_status = hpc_get_adapter_status, | |
960 | ||
961 | .get_max_bus_speed = hpc_get_max_lnk_speed, | |
962 | .get_cur_bus_speed = hpc_get_cur_lnk_speed, | |
963 | .get_max_lnk_width = hpc_get_max_lnk_width, | |
964 | .get_cur_lnk_width = hpc_get_cur_lnk_width, | |
965 | ||
966 | .query_power_fault = hpc_query_power_fault, | |
967 | .green_led_on = hpc_set_green_led_on, | |
968 | .green_led_off = hpc_set_green_led_off, | |
969 | .green_led_blink = hpc_set_green_led_blink, | |
970 | ||
971 | .release_ctlr = hpc_release_ctlr, | |
972 | .check_lnk_status = hpc_check_lnk_status, | |
973 | }; | |
974 | ||
783c49fc KA |
975 | #ifdef CONFIG_ACPI |
976 | int pciehp_acpi_get_hp_hw_control_from_firmware(struct pci_dev *dev) | |
977 | { | |
978 | acpi_status status; | |
979 | acpi_handle chandle, handle = DEVICE_ACPI_HANDLE(&(dev->dev)); | |
980 | struct pci_dev *pdev = dev; | |
981 | struct pci_bus *parent; | |
b2e6e3ba | 982 | struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL }; |
783c49fc KA |
983 | |
984 | /* | |
985 | * Per PCI firmware specification, we should run the ACPI _OSC | |
986 | * method to get control of hotplug hardware before using it. | |
987 | * If an _OSC is missing, we look for an OSHP to do the same thing. | |
988 | * To handle different BIOS behavior, we look for _OSC and OSHP | |
989 | * within the scope of the hotplug controller and its parents, upto | |
990 | * the host bridge under which this controller exists. | |
991 | */ | |
992 | while (!handle) { | |
993 | /* | |
994 | * This hotplug controller was not listed in the ACPI name | |
995 | * space at all. Try to get acpi handle of parent pci bus. | |
996 | */ | |
997 | if (!pdev || !pdev->bus->parent) | |
998 | break; | |
999 | parent = pdev->bus->parent; | |
1000 | dbg("Could not find %s in acpi namespace, trying parent\n", | |
1001 | pci_name(pdev)); | |
1002 | if (!parent->self) | |
1003 | /* Parent must be a host bridge */ | |
1004 | handle = acpi_get_pci_rootbridge_handle( | |
1005 | pci_domain_nr(parent), | |
1006 | parent->number); | |
1007 | else | |
1008 | handle = DEVICE_ACPI_HANDLE( | |
1009 | &(parent->self->dev)); | |
1010 | pdev = parent->self; | |
1011 | } | |
1012 | ||
1013 | while (handle) { | |
b2e6e3ba MT |
1014 | acpi_get_name(handle, ACPI_FULL_PATHNAME, &string); |
1015 | dbg("Trying to get hotplug control for %s \n", | |
1016 | (char *)string.pointer); | |
783c49fc KA |
1017 | status = pci_osc_control_set(handle, |
1018 | OSC_PCI_EXPRESS_NATIVE_HP_CONTROL); | |
1019 | if (status == AE_NOT_FOUND) | |
1020 | status = acpi_run_oshp(handle); | |
1021 | if (ACPI_SUCCESS(status)) { | |
1022 | dbg("Gained control for hotplug HW for pci %s (%s)\n", | |
b2e6e3ba | 1023 | pci_name(dev), (char *)string.pointer); |
81b26bca | 1024 | kfree(string.pointer); |
783c49fc KA |
1025 | return 0; |
1026 | } | |
1027 | if (acpi_root_bridge(handle)) | |
1028 | break; | |
1029 | chandle = handle; | |
1030 | status = acpi_get_parent(chandle, &handle); | |
1031 | if (ACPI_FAILURE(status)) | |
1032 | break; | |
1033 | } | |
1034 | ||
1035 | err("Cannot get control of hotplug hardware for pci %s\n", | |
1036 | pci_name(dev)); | |
b2e6e3ba | 1037 | |
81b26bca | 1038 | kfree(string.pointer); |
783c49fc KA |
1039 | return -1; |
1040 | } | |
1041 | #endif | |
1042 | ||
1043 | ||
1044 | ||
ed6cbcf2 | 1045 | int pcie_init(struct controller * ctrl, struct pcie_device *dev) |
1da177e4 | 1046 | { |
1da177e4 LT |
1047 | int rc; |
1048 | static int first = 1; | |
1049 | u16 temp_word; | |
1050 | u16 cap_reg; | |
1051 | u16 intr_enable = 0; | |
1052 | u32 slot_cap; | |
1053 | int cap_base, saved_cap_base; | |
1054 | u16 slot_status, slot_ctrl; | |
1055 | struct pci_dev *pdev; | |
1056 | ||
1057 | DBG_ENTER_ROUTINE | |
1058 | ||
1da177e4 | 1059 | pdev = dev->port; |
48fe3915 | 1060 | ctrl->pci_dev = pdev; /* save pci_dev in context */ |
1da177e4 | 1061 | |
1a9ed1bf RS |
1062 | dbg("%s: hotplug controller vendor id 0x%x device id 0x%x\n", |
1063 | __FUNCTION__, pdev->vendor, pdev->device); | |
1da177e4 LT |
1064 | |
1065 | saved_cap_base = pcie_cap_base; | |
1066 | ||
1067 | if ((cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP)) == 0) { | |
1068 | dbg("%s: Can't find PCI_CAP_ID_EXP (0x10)\n", __FUNCTION__); | |
1069 | goto abort_free_ctlr; | |
1070 | } | |
1071 | ||
8b245e45 | 1072 | ctrl->cap_base = cap_base; |
1da177e4 LT |
1073 | |
1074 | dbg("%s: pcie_cap_base %x\n", __FUNCTION__, pcie_cap_base); | |
1075 | ||
8b245e45 | 1076 | rc = hp_register_read_word(pdev, CAP_REG(ctrl->cap_base), cap_reg); |
1da177e4 LT |
1077 | if (rc) { |
1078 | err("%s : hp_register_read_word CAP_REG failed\n", __FUNCTION__); | |
1079 | goto abort_free_ctlr; | |
1080 | } | |
8b245e45 | 1081 | dbg("%s: CAP_REG offset %x cap_reg %x\n", __FUNCTION__, CAP_REG(ctrl->cap_base), cap_reg); |
1da177e4 | 1082 | |
8b245e45 DS |
1083 | if (((cap_reg & SLOT_IMPL) == 0) || (((cap_reg & DEV_PORT_TYPE) != 0x0040) |
1084 | && ((cap_reg & DEV_PORT_TYPE) != 0x0060))) { | |
1da177e4 LT |
1085 | dbg("%s : This is not a root port or the port is not connected to a slot\n", __FUNCTION__); |
1086 | goto abort_free_ctlr; | |
1087 | } | |
1088 | ||
48fe3915 | 1089 | rc = hp_register_read_dword(ctrl->pci_dev, SLOT_CAP(ctrl->cap_base), slot_cap); |
1da177e4 LT |
1090 | if (rc) { |
1091 | err("%s : hp_register_read_word CAP_REG failed\n", __FUNCTION__); | |
1092 | goto abort_free_ctlr; | |
1093 | } | |
8b245e45 | 1094 | dbg("%s: SLOT_CAP offset %x slot_cap %x\n", __FUNCTION__, SLOT_CAP(ctrl->cap_base), slot_cap); |
1da177e4 LT |
1095 | |
1096 | if (!(slot_cap & HP_CAP)) { | |
1097 | dbg("%s : This slot is not hot-plug capable\n", __FUNCTION__); | |
1098 | goto abort_free_ctlr; | |
1099 | } | |
1100 | /* For debugging purpose */ | |
48fe3915 | 1101 | rc = hp_register_read_word(ctrl->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status); |
1da177e4 LT |
1102 | if (rc) { |
1103 | err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__); | |
1104 | goto abort_free_ctlr; | |
1105 | } | |
8b245e45 | 1106 | dbg("%s: SLOT_STATUS offset %x slot_status %x\n", __FUNCTION__, SLOT_STATUS(ctrl->cap_base), slot_status); |
1da177e4 | 1107 | |
48fe3915 | 1108 | rc = hp_register_read_word(ctrl->pci_dev, SLOT_CTRL(ctrl->cap_base), slot_ctrl); |
1da177e4 LT |
1109 | if (rc) { |
1110 | err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); | |
1111 | goto abort_free_ctlr; | |
1112 | } | |
8b245e45 | 1113 | dbg("%s: SLOT_CTRL offset %x slot_ctrl %x\n", __FUNCTION__, SLOT_CTRL(ctrl->cap_base), slot_ctrl); |
1da177e4 LT |
1114 | |
1115 | if (first) { | |
1116 | spin_lock_init(&hpc_event_lock); | |
1117 | first = 0; | |
1118 | } | |
1119 | ||
1da177e4 LT |
1120 | for ( rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++) |
1121 | if (pci_resource_len(pdev, rc) > 0) | |
1396a8c3 GKH |
1122 | dbg("pci resource[%d] start=0x%llx(len=0x%llx)\n", rc, |
1123 | (unsigned long long)pci_resource_start(pdev, rc), | |
1124 | (unsigned long long)pci_resource_len(pdev, rc)); | |
1da177e4 LT |
1125 | |
1126 | info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device, | |
1127 | pdev->subsystem_vendor, pdev->subsystem_device); | |
1128 | ||
6aa4cdd0 | 1129 | mutex_init(&ctrl->crit_sect); |
dd5619cb KK |
1130 | mutex_init(&ctrl->ctrl_lock); |
1131 | ||
1da177e4 LT |
1132 | /* setup wait queue */ |
1133 | init_waitqueue_head(&ctrl->queue); | |
1134 | ||
1da177e4 | 1135 | /* return PCI Controller Info */ |
48fe3915 KK |
1136 | ctrl->slot_device_offset = 0; |
1137 | ctrl->num_slots = 1; | |
1138 | ctrl->first_slot = slot_cap >> 19; | |
1139 | ctrl->ctrlcap = slot_cap & 0x0000007f; | |
1da177e4 LT |
1140 | |
1141 | /* Mask Hot-plug Interrupt Enable */ | |
8b245e45 | 1142 | rc = hp_register_read_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word); |
1da177e4 LT |
1143 | if (rc) { |
1144 | err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); | |
1145 | goto abort_free_ctlr; | |
1146 | } | |
1147 | ||
8b245e45 | 1148 | dbg("%s: SLOT_CTRL %x value read %x\n", __FUNCTION__, SLOT_CTRL(ctrl->cap_base), temp_word); |
1da177e4 LT |
1149 | temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00; |
1150 | ||
8b245e45 | 1151 | rc = hp_register_write_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word); |
1da177e4 LT |
1152 | if (rc) { |
1153 | err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__); | |
1154 | goto abort_free_ctlr; | |
1155 | } | |
1da177e4 | 1156 | |
48fe3915 | 1157 | rc = hp_register_read_word(ctrl->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status); |
1da177e4 LT |
1158 | if (rc) { |
1159 | err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__); | |
1160 | goto abort_free_ctlr; | |
1161 | } | |
1da177e4 LT |
1162 | |
1163 | temp_word = 0x1F; /* Clear all events */ | |
48fe3915 | 1164 | rc = hp_register_write_word(ctrl->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word); |
1da177e4 LT |
1165 | if (rc) { |
1166 | err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__); | |
1167 | goto abort_free_ctlr; | |
1168 | } | |
1da177e4 | 1169 | |
48fe3915 KK |
1170 | if (pciehp_poll_mode) { |
1171 | /* Install interrupt polling timer. Start with 10 sec delay */ | |
1172 | init_timer(&ctrl->poll_timer); | |
1173 | start_int_poll_timer(ctrl, 10); | |
1da177e4 LT |
1174 | } else { |
1175 | /* Installs the interrupt handler */ | |
48fe3915 KK |
1176 | rc = request_irq(ctrl->pci_dev->irq, pcie_isr, IRQF_SHARED, |
1177 | MY_NAME, (void *)ctrl); | |
1178 | dbg("%s: request_irq %d for hpc%d (returns %d)\n", | |
1179 | __FUNCTION__, ctrl->pci_dev->irq, ctlr_seq_num, rc); | |
1da177e4 | 1180 | if (rc) { |
48fe3915 KK |
1181 | err("Can't get irq %d for the hotplug controller\n", |
1182 | ctrl->pci_dev->irq); | |
1da177e4 LT |
1183 | goto abort_free_ctlr; |
1184 | } | |
1185 | } | |
1a9ed1bf RS |
1186 | dbg("pciehp ctrl b:d:f:irq=0x%x:%x:%x:%x\n", pdev->bus->number, |
1187 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), dev->irq); | |
1188 | ||
8b245e45 | 1189 | rc = hp_register_read_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word); |
1da177e4 LT |
1190 | if (rc) { |
1191 | err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); | |
9c64f977 | 1192 | goto abort_free_irq; |
1da177e4 | 1193 | } |
1da177e4 LT |
1194 | |
1195 | intr_enable = intr_enable | PRSN_DETECT_ENABLE; | |
1196 | ||
1197 | if (ATTN_BUTTN(slot_cap)) | |
1198 | intr_enable = intr_enable | ATTN_BUTTN_ENABLE; | |
1199 | ||
1200 | if (POWER_CTRL(slot_cap)) | |
1201 | intr_enable = intr_enable | PWR_FAULT_DETECT_ENABLE; | |
1202 | ||
1203 | if (MRL_SENS(slot_cap)) | |
1204 | intr_enable = intr_enable | MRL_DETECT_ENABLE; | |
1205 | ||
1206 | temp_word = (temp_word & ~intr_enable) | intr_enable; | |
1207 | ||
1208 | if (pciehp_poll_mode) { | |
1209 | temp_word = (temp_word & ~HP_INTR_ENABLE) | 0x0; | |
1210 | } else { | |
1211 | temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE; | |
1212 | } | |
1da177e4 LT |
1213 | |
1214 | /* Unmask Hot-plug Interrupt Enable for the interrupt notification mechanism case */ | |
8b245e45 | 1215 | rc = hp_register_write_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word); |
1da177e4 LT |
1216 | if (rc) { |
1217 | err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__); | |
9c64f977 | 1218 | goto abort_free_irq; |
1da177e4 | 1219 | } |
48fe3915 | 1220 | rc = hp_register_read_word(ctrl->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status); |
1da177e4 LT |
1221 | if (rc) { |
1222 | err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__); | |
9c64f977 | 1223 | goto abort_disable_intr; |
1da177e4 | 1224 | } |
1da177e4 LT |
1225 | |
1226 | temp_word = 0x1F; /* Clear all events */ | |
48fe3915 | 1227 | rc = hp_register_write_word(ctrl->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word); |
1da177e4 LT |
1228 | if (rc) { |
1229 | err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__); | |
9c64f977 | 1230 | goto abort_disable_intr; |
1da177e4 | 1231 | } |
1da177e4 | 1232 | |
a3a45ec8 RS |
1233 | if (pciehp_force) { |
1234 | dbg("Bypassing BIOS check for pciehp use on %s\n", | |
1235 | pci_name(ctrl->pci_dev)); | |
1236 | } else { | |
6560aa5c | 1237 | rc = pciehp_get_hp_hw_control_from_firmware(ctrl->pci_dev); |
a3a45ec8 | 1238 | if (rc) |
9c64f977 | 1239 | goto abort_disable_intr; |
a3a45ec8 | 1240 | } |
a8a2be94 | 1241 | |
1da177e4 | 1242 | ctlr_seq_num++; |
1da177e4 LT |
1243 | ctrl->hpc_ops = &pciehp_hpc_ops; |
1244 | ||
1245 | DBG_LEAVE_ROUTINE | |
1246 | return 0; | |
1247 | ||
1248 | /* We end up here for the many possible ways to fail this API. */ | |
9c64f977 JB |
1249 | abort_disable_intr: |
1250 | rc = hp_register_read_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word); | |
1251 | if (!rc) { | |
1252 | temp_word &= ~(intr_enable | HP_INTR_ENABLE); | |
1253 | rc = hp_register_write_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word); | |
1254 | } | |
1255 | if (rc) | |
1256 | err("%s : disabling interrupts failed\n", __FUNCTION__); | |
1257 | ||
1258 | abort_free_irq: | |
1259 | if (pciehp_poll_mode) | |
48fe3915 | 1260 | del_timer_sync(&ctrl->poll_timer); |
9c64f977 | 1261 | else |
48fe3915 | 1262 | free_irq(ctrl->pci_dev->irq, ctrl); |
9c64f977 | 1263 | |
1da177e4 LT |
1264 | abort_free_ctlr: |
1265 | pcie_cap_base = saved_cap_base; | |
48fe3915 | 1266 | |
1da177e4 LT |
1267 | DBG_LEAVE_ROUTINE |
1268 | return -1; | |
1269 | } |