[GitHub/LineageOS/android_kernel_samsung_universal7580.git] / drivers / pci / access.c

#include <linux/delay.h>
#include <linux/pci.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/ioport.h>
#include <linux/wait.h>

#include "pci.h"

/*
 * This interrupt-safe spinlock protects all accesses to PCI
 * configuration space.
 */

DEFINE_RAW_SPINLOCK(pci_lock);

/*
 *  Wrappers for all PCI configuration access functions.  They just check
 *  alignment, do locking and call the low-level functions pointed to
 *  by pci_dev->ops.
 */

#define PCI_byte_BAD 0
#define PCI_word_BAD (pos & 1)
#define PCI_dword_BAD (pos & 3)

#define PCI_OP_READ(size,type,len) \
int pci_bus_read_config_##size \
	(struct pci_bus *bus, unsigned int devfn, int pos, type *value)	\
{									\
	int res;							\
	unsigned long flags;						\
	u32 data = 0;							\
	if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER;	\
	raw_spin_lock_irqsave(&pci_lock, flags);			\
	res = bus->ops->read(bus, devfn, pos, len, &data);		\
	*value = (type)data;						\
	raw_spin_unlock_irqrestore(&pci_lock, flags);		\
	return res;							\
}

#define PCI_OP_WRITE(size,type,len) \
int pci_bus_write_config_##size \
	(struct pci_bus *bus, unsigned int devfn, int pos, type value)	\
{									\
	int res;							\
	unsigned long flags;						\
	if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER;	\
	raw_spin_lock_irqsave(&pci_lock, flags);			\
	res = bus->ops->write(bus, devfn, pos, len, value);		\
	raw_spin_unlock_irqrestore(&pci_lock, flags);		\
	return res;							\
}

PCI_OP_READ(byte, u8, 1)
PCI_OP_READ(word, u16, 2)
PCI_OP_READ(dword, u32, 4)
PCI_OP_WRITE(byte, u8, 1)
PCI_OP_WRITE(word, u16, 2)
PCI_OP_WRITE(dword, u32, 4)

EXPORT_SYMBOL(pci_bus_read_config_byte);
EXPORT_SYMBOL(pci_bus_read_config_word);
EXPORT_SYMBOL(pci_bus_read_config_dword);
EXPORT_SYMBOL(pci_bus_write_config_byte);
EXPORT_SYMBOL(pci_bus_write_config_word);
EXPORT_SYMBOL(pci_bus_write_config_dword);

/**
 * pci_bus_set_ops - Set raw operations of pci bus
 * @bus:	pci bus struct
 * @ops:	new raw operations
 *
 * Return previous raw operations
 */
struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops)
{
	struct pci_ops *old_ops;
	unsigned long flags;

	raw_spin_lock_irqsave(&pci_lock, flags);
	old_ops = bus->ops;
	bus->ops = ops;
	raw_spin_unlock_irqrestore(&pci_lock, flags);
	return old_ops;
}
EXPORT_SYMBOL(pci_bus_set_ops);

/**
 * pci_read_vpd - Read one entry from Vital Product Data
 * @dev:	pci device struct
 * @pos:	offset in vpd space
 * @count:	number of bytes to read
 * @buf:	pointer to where to store result
 *
 */
ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf)
{
	if (!dev->vpd || !dev->vpd->ops)
		return -ENODEV;
	return dev->vpd->ops->read(dev, pos, count, buf);
}
EXPORT_SYMBOL(pci_read_vpd);

/**
 * pci_write_vpd - Write entry to Vital Product Data
 * @dev:	pci device struct
 * @pos:	offset in vpd space
 * @count:	number of bytes to write
 * @buf:	buffer containing write data
 *
 */
ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf)
{
	if (!dev->vpd || !dev->vpd->ops)
		return -ENODEV;
	return dev->vpd->ops->write(dev, pos, count, buf);
}
EXPORT_SYMBOL(pci_write_vpd);

/*
 * The following routines are to prevent the user from accessing PCI config
 * space when it's unsafe to do so.  Some devices require this during BIST and
 * we're required to prevent it during D-state transitions.
 *
 * We have a bit per device to indicate it's blocked and a global wait queue
 * for callers to sleep on until devices are unblocked.
 */
static DECLARE_WAIT_QUEUE_HEAD(pci_cfg_wait);

static noinline void pci_wait_cfg(struct pci_dev *dev)
{
	DECLARE_WAITQUEUE(wait, current);

	__add_wait_queue(&pci_cfg_wait, &wait);
	do {
		set_current_state(TASK_UNINTERRUPTIBLE);
		raw_spin_unlock_irq(&pci_lock);
		schedule();
		raw_spin_lock_irq(&pci_lock);
	} while (dev->block_cfg_access);
	__remove_wait_queue(&pci_cfg_wait, &wait);
}

/* Returns 0 on success, negative values indicate error. */
#define PCI_USER_READ_CONFIG(size,type)					\
int pci_user_read_config_##size						\
	(struct pci_dev *dev, int pos, type *val)			\
{									\
	int ret = 0;							\
	u32 data = -1;							\
	if (PCI_##size##_BAD)						\
		return -EINVAL;						\
	raw_spin_lock_irq(&pci_lock);				\
	if (unlikely(dev->block_cfg_access))				\
		pci_wait_cfg(dev);					\
	ret = dev->bus->ops->read(dev->bus, dev->devfn,			\
					pos, sizeof(type), &data);	\
	raw_spin_unlock_irq(&pci_lock);				\
	*val = (type)data;						\
	if (ret > 0)							\
		ret = -EINVAL;						\
	return ret;							\
}

/* Returns 0 on success, negative values indicate error. */
#define PCI_USER_WRITE_CONFIG(size,type)				\
int pci_user_write_config_##size					\
	(struct pci_dev *dev, int pos, type val)			\
{									\
	int ret = -EIO;							\
	if (PCI_##size##_BAD)						\
		return -EINVAL;						\
	raw_spin_lock_irq(&pci_lock);				\
	if (unlikely(dev->block_cfg_access))				\
		pci_wait_cfg(dev);					\
	ret = dev->bus->ops->write(dev->bus, dev->devfn,		\
					pos, sizeof(type), val);	\
	raw_spin_unlock_irq(&pci_lock);				\
	if (ret > 0)							\
		ret = -EINVAL;						\
	return ret;							\
}

PCI_USER_READ_CONFIG(byte, u8)
PCI_USER_READ_CONFIG(word, u16)
PCI_USER_READ_CONFIG(dword, u32)
PCI_USER_WRITE_CONFIG(byte, u8)
PCI_USER_WRITE_CONFIG(word, u16)
PCI_USER_WRITE_CONFIG(dword, u32)

/* VPD access through PCI 2.2+ VPD capability */

#define PCI_VPD_PCI22_SIZE (PCI_VPD_ADDR_MASK + 1)

struct pci_vpd_pci22 {
	struct pci_vpd base;
	struct mutex lock;
	u16	flag;
	bool	busy;
	u8	cap;
};

/*
 * Wait for last operation to complete.
 * This code has to spin since there is no other notification from the PCI
 * hardware. Since the VPD is often implemented by serial attachment to an
 * EEPROM, it may take many milliseconds to complete.
 *
 * Returns 0 on success, negative values indicate error.
 */
static int pci_vpd_pci22_wait(struct pci_dev *dev)
{
	struct pci_vpd_pci22 *vpd =
		container_of(dev->vpd, struct pci_vpd_pci22, base);
	unsigned long timeout = jiffies + HZ/20 + 2;
	u16 status;
	int ret;

	if (!vpd->busy)
		return 0;

	for (;;) {
		ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR,
						&status);
		if (ret < 0)
			return ret;

		if ((status & PCI_VPD_ADDR_F) == vpd->flag) {
			vpd->busy = false;
			return 0;
		}

		if (time_after(jiffies, timeout)) {
			dev_printk(KERN_DEBUG, &dev->dev,
				   "vpd r/w failed.  This is likely a firmware "
				   "bug on this device.  Contact the card "
				   "vendor for a firmware update.");
			return -ETIMEDOUT;
		}
		if (fatal_signal_pending(current))
			return -EINTR;
		if (!cond_resched())
			udelay(10);
	}
}

static ssize_t pci_vpd_pci22_read(struct pci_dev *dev, loff_t pos, size_t count,
				  void *arg)
{
	struct pci_vpd_pci22 *vpd =
		container_of(dev->vpd, struct pci_vpd_pci22, base);
	int ret;
	loff_t end = pos + count;
	u8 *buf = arg;

	if (pos < 0 || pos > vpd->base.len || end > vpd->base.len)
		return -EINVAL;

	if (mutex_lock_killable(&vpd->lock))
		return -EINTR;

	ret = pci_vpd_pci22_wait(dev);
	if (ret < 0)
		goto out;

	while (pos < end) {
		u32 val;
		unsigned int i, skip;

		ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
						 pos & ~3);
		if (ret < 0)
			break;
		vpd->busy = true;
		vpd->flag = PCI_VPD_ADDR_F;
		ret = pci_vpd_pci22_wait(dev);
		if (ret < 0)
			break;

		ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA, &val);
		if (ret < 0)
			break;

		skip = pos & 3;
		for (i = 0;  i < sizeof(u32); i++) {
			if (i >= skip) {
				*buf++ = val;
				if (++pos == end)
					break;
			}
			val >>= 8;
		}
	}
out:
	mutex_unlock(&vpd->lock);
	return ret ? ret : count;
}

static ssize_t pci_vpd_pci22_write(struct pci_dev *dev, loff_t pos, size_t count,
				   const void *arg)
{
	struct pci_vpd_pci22 *vpd =
		container_of(dev->vpd, struct pci_vpd_pci22, base);
	const u8 *buf = arg;
	loff_t end = pos + count;
	int ret = 0;

	if (pos < 0 || (pos & 3) || (count & 3) || end > vpd->base.len)
		return -EINVAL;

	if (mutex_lock_killable(&vpd->lock))
		return -EINTR;

	ret = pci_vpd_pci22_wait(dev);
	if (ret < 0)
		goto out;

	while (pos < end) {
		u32 val;

		val = *buf++;
		val |= *buf++ << 8;
		val |= *buf++ << 16;
		val |= *buf++ << 24;

		ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA, val);
		if (ret < 0)
			break;
		ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
						 pos | PCI_VPD_ADDR_F);
		if (ret < 0)
			break;

		vpd->busy = true;
		vpd->flag = 0;
		ret = pci_vpd_pci22_wait(dev);
		if (ret < 0)
			break;

		pos += sizeof(u32);
	}
out:
	mutex_unlock(&vpd->lock);
	return ret ? ret : count;
}

static void pci_vpd_pci22_release(struct pci_dev *dev)
{
	kfree(container_of(dev->vpd, struct pci_vpd_pci22, base));
}

static const struct pci_vpd_ops pci_vpd_pci22_ops = {
	.read = pci_vpd_pci22_read,
	.write = pci_vpd_pci22_write,
	.release = pci_vpd_pci22_release,
};

int pci_vpd_pci22_init(struct pci_dev *dev)
{
	struct pci_vpd_pci22 *vpd;
	u8 cap;

	cap = pci_find_capability(dev, PCI_CAP_ID_VPD);
	if (!cap)
		return -ENODEV;
	vpd = kzalloc(sizeof(*vpd), GFP_ATOMIC);
	if (!vpd)
		return -ENOMEM;

	vpd->base.len = PCI_VPD_PCI22_SIZE;
	vpd->base.ops = &pci_vpd_pci22_ops;
	mutex_init(&vpd->lock);
	vpd->cap = cap;
	vpd->busy = false;
	dev->vpd = &vpd->base;
	return 0;
}

/**
 * pci_vpd_truncate - Set available Vital Product Data size
 * @dev:	pci device struct
 * @size:	available memory in bytes
 *
 * Adjust size of available VPD area.
 */
int pci_vpd_truncate(struct pci_dev *dev, size_t size)
{
	if (!dev->vpd)
		return -EINVAL;

	/* limited by the access method */
	if (size > dev->vpd->len)
		return -EINVAL;

	dev->vpd->len = size;
	if (dev->vpd->attr)
		dev->vpd->attr->size = size;

	return 0;
}
EXPORT_SYMBOL(pci_vpd_truncate);

/**
 * pci_cfg_access_lock - Lock PCI config reads/writes
 * @dev:	pci device struct
 *
 * When access is locked, any userspace reads or writes to config
 * space and concurrent lock requests will sleep until access is
 * allowed via pci_cfg_access_unlocked again.
 */
void pci_cfg_access_lock(struct pci_dev *dev)
{
	might_sleep();

	raw_spin_lock_irq(&pci_lock);
	if (dev->block_cfg_access)
		pci_wait_cfg(dev);
	dev->block_cfg_access = 1;
	raw_spin_unlock_irq(&pci_lock);
}
EXPORT_SYMBOL_GPL(pci_cfg_access_lock);

/**
 * pci_cfg_access_trylock - try to lock PCI config reads/writes
 * @dev:	pci device struct
 *
 * Same as pci_cfg_access_lock, but will return 0 if access is
 * already locked, 1 otherwise. This function can be used from
 * atomic contexts.
 */
bool pci_cfg_access_trylock(struct pci_dev *dev)
{
	unsigned long flags;
	bool locked = true;

	raw_spin_lock_irqsave(&pci_lock, flags);
	if (dev->block_cfg_access)
		locked = false;
	else
		dev->block_cfg_access = 1;
	raw_spin_unlock_irqrestore(&pci_lock, flags);

	return locked;
}
EXPORT_SYMBOL_GPL(pci_cfg_access_trylock);

/**
 * pci_cfg_access_unlock - Unlock PCI config reads/writes
 * @dev:	pci device struct
 *
 * This function allows PCI config accesses to resume.
 */
void pci_cfg_access_unlock(struct pci_dev *dev)
{
	unsigned long flags;

	raw_spin_lock_irqsave(&pci_lock, flags);

	/* This indicates a problem in the caller, but we don't need
	 * to kill them, unlike a double-block above. */
	WARN_ON(!dev->block_cfg_access);

	dev->block_cfg_access = 0;
	wake_up_all(&pci_cfg_wait);
	raw_spin_unlock_irqrestore(&pci_lock, flags);
}
EXPORT_SYMBOL_GPL(pci_cfg_access_unlock);
Commit	Line	Data
94e61088	1	#include <linux/delay.h>
1da177e4 LT	2	#include <linux/pci.h>
1da177e4 LT	3	#include <linux/module.h>
f6a57033	4	#include <linux/sched.h>
5a0e3ad6	5	#include <linux/slab.h>
1da177e4	6	#include <linux/ioport.h>
7ea7e98f	7	#include <linux/wait.h>
1da177e4	8
48b19148 AB	9	#include "pci.h"
48b19148 AB	10
1da177e4 LT	11	/*
	12	* This interrupt-safe spinlock protects all accesses to PCI
	13	* configuration space.
	14	*/
	15
a2e27787	16	DEFINE_RAW_SPINLOCK(pci_lock);
1da177e4 LT	17
	18	/*
	19	* Wrappers for all PCI configuration access functions. They just check
	20	* alignment, do locking and call the low-level functions pointed to
	21	* by pci_dev->ops.
	22	*/
	23
	24	#define PCI_byte_BAD 0
	25	#define PCI_word_BAD (pos & 1)
	26	#define PCI_dword_BAD (pos & 3)
	27
	28	#define PCI_OP_READ(size,type,len) \
	29	int pci_bus_read_config_##size \
	30	(struct pci_bus bus, unsigned int devfn, int pos, type value) \
	31	{ \
	32	int res; \
	33	unsigned long flags; \
	34	u32 data = 0; \
	35	if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
511dd98c	36	raw_spin_lock_irqsave(&pci_lock, flags); \
1da177e4 LT	37	res = bus->ops->read(bus, devfn, pos, len, &data); \
1da177e4 LT	38	*value = (type)data; \
511dd98c	39	raw_spin_unlock_irqrestore(&pci_lock, flags); \
1da177e4 LT	40	return res; \
	41	}
	42
	43	#define PCI_OP_WRITE(size,type,len) \
	44	int pci_bus_write_config_##size \
	45	(struct pci_bus *bus, unsigned int devfn, int pos, type value) \
	46	{ \
	47	int res; \
	48	unsigned long flags; \
	49	if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
511dd98c	50	raw_spin_lock_irqsave(&pci_lock, flags); \
1da177e4	51	res = bus->ops->write(bus, devfn, pos, len, value); \
511dd98c	52	raw_spin_unlock_irqrestore(&pci_lock, flags); \
1da177e4 LT	53	return res; \
	54	}
	55
	56	PCI_OP_READ(byte, u8, 1)
	57	PCI_OP_READ(word, u16, 2)
	58	PCI_OP_READ(dword, u32, 4)
	59	PCI_OP_WRITE(byte, u8, 1)
	60	PCI_OP_WRITE(word, u16, 2)
	61	PCI_OP_WRITE(dword, u32, 4)
	62
	63	EXPORT_SYMBOL(pci_bus_read_config_byte);
	64	EXPORT_SYMBOL(pci_bus_read_config_word);
	65	EXPORT_SYMBOL(pci_bus_read_config_dword);
	66	EXPORT_SYMBOL(pci_bus_write_config_byte);
	67	EXPORT_SYMBOL(pci_bus_write_config_word);
	68	EXPORT_SYMBOL(pci_bus_write_config_dword);
e04b0ea2	69
a72b46c3 HY	70	/**
	71	* pci_bus_set_ops - Set raw operations of pci bus
	72	* @bus: pci bus struct
	73	* @ops: new raw operations
	74	*
	75	* Return previous raw operations
	76	*/
	77	struct pci_ops pci_bus_set_ops(struct pci_bus bus, struct pci_ops *ops)
	78	{
	79	struct pci_ops *old_ops;
	80	unsigned long flags;
	81
511dd98c	82	raw_spin_lock_irqsave(&pci_lock, flags);
a72b46c3 HY	83	old_ops = bus->ops;
a72b46c3 HY	84	bus->ops = ops;
511dd98c	85	raw_spin_unlock_irqrestore(&pci_lock, flags);
a72b46c3 HY	86	return old_ops;
	87	}
	88	EXPORT_SYMBOL(pci_bus_set_ops);
287d19ce SH	89
	90	/**
	91	* pci_read_vpd - Read one entry from Vital Product Data
	92	* @dev: pci device struct
	93	* @pos: offset in vpd space
	94	* @count: number of bytes to read
	95	* @buf: pointer to where to store result
	96	*
	97	*/
	98	ssize_t pci_read_vpd(struct pci_dev dev, loff_t pos, size_t count, void buf)
	99	{
	100	if (!dev->vpd \|\| !dev->vpd->ops)
	101	return -ENODEV;
	102	return dev->vpd->ops->read(dev, pos, count, buf);
	103	}
	104	EXPORT_SYMBOL(pci_read_vpd);
	105
	106	/**
	107	* pci_write_vpd - Write entry to Vital Product Data
	108	* @dev: pci device struct
	109	* @pos: offset in vpd space
cffb2faf RD	110	* @count: number of bytes to write
cffb2faf RD	111	* @buf: buffer containing write data
287d19ce SH	112	*
	113	*/
	114	ssize_t pci_write_vpd(struct pci_dev dev, loff_t pos, size_t count, const void buf)
	115	{
	116	if (!dev->vpd \|\| !dev->vpd->ops)
	117	return -ENODEV;
	118	return dev->vpd->ops->write(dev, pos, count, buf);
	119	}
	120	EXPORT_SYMBOL(pci_write_vpd);
	121
7ea7e98f MW	122	/*
	123	* The following routines are to prevent the user from accessing PCI config
	124	* space when it's unsafe to do so. Some devices require this during BIST and
	125	* we're required to prevent it during D-state transitions.
	126	*
	127	* We have a bit per device to indicate it's blocked and a global wait queue
	128	* for callers to sleep on until devices are unblocked.
	129	*/
fb51ccbf	130	static DECLARE_WAIT_QUEUE_HEAD(pci_cfg_wait);
e04b0ea2	131
fb51ccbf	132	static noinline void pci_wait_cfg(struct pci_dev *dev)
7ea7e98f MW	133	{
	134	DECLARE_WAITQUEUE(wait, current);
	135
fb51ccbf	136	__add_wait_queue(&pci_cfg_wait, &wait);
7ea7e98f MW	137	do {
7ea7e98f MW	138	set_current_state(TASK_UNINTERRUPTIBLE);
511dd98c	139	raw_spin_unlock_irq(&pci_lock);
7ea7e98f	140	schedule();
511dd98c	141	raw_spin_lock_irq(&pci_lock);
fb51ccbf JK	142	} while (dev->block_cfg_access);
fb51ccbf JK	143	__remove_wait_queue(&pci_cfg_wait, &wait);
e04b0ea2 BK	144	}
e04b0ea2 BK	145
34e32072	146	/* Returns 0 on success, negative values indicate error. */
e04b0ea2 BK	147	#define PCI_USER_READ_CONFIG(size,type) \
	148	int pci_user_read_config_##size \
	149	(struct pci_dev dev, int pos, type val) \
	150	{ \
e04b0ea2 BK	151	int ret = 0; \
e04b0ea2 BK	152	u32 data = -1; \
34e32072 GT	153	if (PCI_##size##_BAD) \
34e32072 GT	154	return -EINVAL; \
511dd98c	155	raw_spin_lock_irq(&pci_lock); \
fb51ccbf JK	156	if (unlikely(dev->block_cfg_access)) \
fb51ccbf JK	157	pci_wait_cfg(dev); \
7ea7e98f	158	ret = dev->bus->ops->read(dev->bus, dev->devfn, \
e04b0ea2	159	pos, sizeof(type), &data); \
511dd98c	160	raw_spin_unlock_irq(&pci_lock); \
e04b0ea2	161	*val = (type)data; \
34e32072 GT	162	if (ret > 0) \
34e32072 GT	163	ret = -EINVAL; \
e04b0ea2 BK	164	return ret; \
	165	}
	166
34e32072	167	/* Returns 0 on success, negative values indicate error. */
e04b0ea2 BK	168	#define PCI_USER_WRITE_CONFIG(size,type) \
	169	int pci_user_write_config_##size \
	170	(struct pci_dev *dev, int pos, type val) \
	171	{ \
e04b0ea2	172	int ret = -EIO; \
34e32072 GT	173	if (PCI_##size##_BAD) \
34e32072 GT	174	return -EINVAL; \
511dd98c	175	raw_spin_lock_irq(&pci_lock); \
fb51ccbf JK	176	if (unlikely(dev->block_cfg_access)) \
fb51ccbf JK	177	pci_wait_cfg(dev); \
7ea7e98f	178	ret = dev->bus->ops->write(dev->bus, dev->devfn, \
e04b0ea2	179	pos, sizeof(type), val); \
511dd98c	180	raw_spin_unlock_irq(&pci_lock); \
34e32072 GT	181	if (ret > 0) \
34e32072 GT	182	ret = -EINVAL; \
e04b0ea2 BK	183	return ret; \
	184	}
	185
	186	PCI_USER_READ_CONFIG(byte, u8)
	187	PCI_USER_READ_CONFIG(word, u16)
	188	PCI_USER_READ_CONFIG(dword, u32)
	189	PCI_USER_WRITE_CONFIG(byte, u8)
	190	PCI_USER_WRITE_CONFIG(word, u16)
	191	PCI_USER_WRITE_CONFIG(dword, u32)
	192
94e61088 BH	193	/* VPD access through PCI 2.2+ VPD capability */
	194
	195	#define PCI_VPD_PCI22_SIZE (PCI_VPD_ADDR_MASK + 1)
	196
	197	struct pci_vpd_pci22 {
	198	struct pci_vpd base;
1120f8b8 SH	199	struct mutex lock;
1120f8b8 SH	200	u16 flag;
94e61088	201	bool busy;
1120f8b8	202	u8 cap;
94e61088 BH	203	};
94e61088 BH	204
1120f8b8 SH	205	/*
	206	* Wait for last operation to complete.
	207	* This code has to spin since there is no other notification from the PCI
	208	* hardware. Since the VPD is often implemented by serial attachment to an
	209	* EEPROM, it may take many milliseconds to complete.
34e32072 GT	210	*
34e32072 GT	211	* Returns 0 on success, negative values indicate error.
1120f8b8	212	*/
94e61088 BH	213	static int pci_vpd_pci22_wait(struct pci_dev *dev)
	214	{
	215	struct pci_vpd_pci22 *vpd =
	216	container_of(dev->vpd, struct pci_vpd_pci22, base);
1120f8b8 SH	217	unsigned long timeout = jiffies + HZ/20 + 2;
1120f8b8 SH	218	u16 status;
94e61088 BH	219	int ret;
	220
	221	if (!vpd->busy)
	222	return 0;
	223
94e61088	224	for (;;) {
1120f8b8	225	ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR,
94e61088	226	&status);
34e32072	227	if (ret < 0)
94e61088	228	return ret;
1120f8b8 SH	229
1120f8b8 SH	230	if ((status & PCI_VPD_ADDR_F) == vpd->flag) {
94e61088 BH	231	vpd->busy = false;
	232	return 0;
	233	}
1120f8b8	234
5030718e PB	235	if (time_after(jiffies, timeout)) {
	236	dev_printk(KERN_DEBUG, &dev->dev,
	237	"vpd r/w failed. This is likely a firmware "
	238	"bug on this device. Contact the card "
	239	"vendor for a firmware update.");
94e61088	240	return -ETIMEDOUT;
5030718e	241	}
1120f8b8 SH	242	if (fatal_signal_pending(current))
	243	return -EINTR;
	244	if (!cond_resched())
	245	udelay(10);
94e61088 BH	246	}
	247	}
	248
287d19ce SH	249	static ssize_t pci_vpd_pci22_read(struct pci_dev *dev, loff_t pos, size_t count,
287d19ce SH	250	void *arg)
94e61088 BH	251	{
	252	struct pci_vpd_pci22 *vpd =
	253	container_of(dev->vpd, struct pci_vpd_pci22, base);
287d19ce SH	254	int ret;
	255	loff_t end = pos + count;
	256	u8 *buf = arg;
94e61088	257
287d19ce	258	if (pos < 0 \|\| pos > vpd->base.len \|\| end > vpd->base.len)
94e61088	259	return -EINVAL;
94e61088	260
1120f8b8 SH	261	if (mutex_lock_killable(&vpd->lock))
	262	return -EINTR;
	263
94e61088 BH	264	ret = pci_vpd_pci22_wait(dev);
	265	if (ret < 0)
	266	goto out;
1120f8b8	267
287d19ce SH	268	while (pos < end) {
	269	u32 val;
	270	unsigned int i, skip;
	271
	272	ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
	273	pos & ~3);
	274	if (ret < 0)
	275	break;
	276	vpd->busy = true;
	277	vpd->flag = PCI_VPD_ADDR_F;
	278	ret = pci_vpd_pci22_wait(dev);
	279	if (ret < 0)
	280	break;
	281
	282	ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA, &val);
	283	if (ret < 0)
	284	break;
	285
	286	skip = pos & 3;
	287	for (i = 0; i < sizeof(u32); i++) {
	288	if (i >= skip) {
	289	*buf++ = val;
	290	if (++pos == end)
	291	break;
	292	}
	293	val >>= 8;
	294	}
	295	}
94e61088	296	out:
1120f8b8	297	mutex_unlock(&vpd->lock);
287d19ce	298	return ret ? ret : count;
94e61088 BH	299	}
94e61088 BH	300
287d19ce SH	301	static ssize_t pci_vpd_pci22_write(struct pci_dev *dev, loff_t pos, size_t count,
287d19ce SH	302	const void *arg)
94e61088 BH	303	{
	304	struct pci_vpd_pci22 *vpd =
	305	container_of(dev->vpd, struct pci_vpd_pci22, base);
287d19ce SH	306	const u8 *buf = arg;
287d19ce SH	307	loff_t end = pos + count;
1120f8b8	308	int ret = 0;
94e61088	309
287d19ce	310	if (pos < 0 \|\| (pos & 3) \|\| (count & 3) \|\| end > vpd->base.len)
94e61088 BH	311	return -EINVAL;
94e61088 BH	312
1120f8b8 SH	313	if (mutex_lock_killable(&vpd->lock))
1120f8b8 SH	314	return -EINTR;
287d19ce	315
94e61088 BH	316	ret = pci_vpd_pci22_wait(dev);
	317	if (ret < 0)
	318	goto out;
287d19ce SH	319
	320	while (pos < end) {
	321	u32 val;
	322
	323	val = *buf++;
	324	val \|= *buf++ << 8;
	325	val \|= *buf++ << 16;
	326	val \|= *buf++ << 24;
	327
	328	ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA, val);
	329	if (ret < 0)
	330	break;
	331	ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
	332	pos \| PCI_VPD_ADDR_F);
	333	if (ret < 0)
	334	break;
	335
	336	vpd->busy = true;
	337	vpd->flag = 0;
	338	ret = pci_vpd_pci22_wait(dev);
d97ecd81 GT	339	if (ret < 0)
d97ecd81 GT	340	break;
287d19ce SH	341
	342	pos += sizeof(u32);
	343	}
94e61088	344	out:
1120f8b8	345	mutex_unlock(&vpd->lock);
287d19ce	346	return ret ? ret : count;
94e61088 BH	347	}
94e61088 BH	348
94e61088 BH	349	static void pci_vpd_pci22_release(struct pci_dev *dev)
	350	{
	351	kfree(container_of(dev->vpd, struct pci_vpd_pci22, base));
	352	}
	353
287d19ce	354	static const struct pci_vpd_ops pci_vpd_pci22_ops = {
94e61088 BH	355	.read = pci_vpd_pci22_read,
94e61088 BH	356	.write = pci_vpd_pci22_write,
94e61088 BH	357	.release = pci_vpd_pci22_release,
	358	};
	359
	360	int pci_vpd_pci22_init(struct pci_dev *dev)
	361	{
	362	struct pci_vpd_pci22 *vpd;
	363	u8 cap;
	364
	365	cap = pci_find_capability(dev, PCI_CAP_ID_VPD);
	366	if (!cap)
	367	return -ENODEV;
	368	vpd = kzalloc(sizeof(*vpd), GFP_ATOMIC);
	369	if (!vpd)
	370	return -ENOMEM;
	371
99cb233d	372	vpd->base.len = PCI_VPD_PCI22_SIZE;
94e61088	373	vpd->base.ops = &pci_vpd_pci22_ops;
1120f8b8	374	mutex_init(&vpd->lock);
94e61088 BH	375	vpd->cap = cap;
	376	vpd->busy = false;
	377	dev->vpd = &vpd->base;
	378	return 0;
	379	}
	380
db567943 SH	381	/**
	382	* pci_vpd_truncate - Set available Vital Product Data size
	383	* @dev: pci device struct
	384	* @size: available memory in bytes
	385	*
	386	* Adjust size of available VPD area.
	387	*/
	388	int pci_vpd_truncate(struct pci_dev *dev, size_t size)
	389	{
	390	if (!dev->vpd)
	391	return -EINVAL;
	392
	393	/* limited by the access method */
	394	if (size > dev->vpd->len)
	395	return -EINVAL;
	396
	397	dev->vpd->len = size;
d407e32e AV	398	if (dev->vpd->attr)
d407e32e AV	399	dev->vpd->attr->size = size;
db567943 SH	400
	401	return 0;
	402	}
	403	EXPORT_SYMBOL(pci_vpd_truncate);
	404
e04b0ea2	405	/**
fb51ccbf	406	* pci_cfg_access_lock - Lock PCI config reads/writes
e04b0ea2 BK	407	* @dev: pci device struct
e04b0ea2 BK	408	*
fb51ccbf JK	409	* When access is locked, any userspace reads or writes to config
	410	* space and concurrent lock requests will sleep until access is
	411	* allowed via pci_cfg_access_unlocked again.
7ea7e98f	412	*/
fb51ccbf JK	413	void pci_cfg_access_lock(struct pci_dev *dev)
	414	{
	415	might_sleep();
	416
	417	raw_spin_lock_irq(&pci_lock);
	418	if (dev->block_cfg_access)
	419	pci_wait_cfg(dev);
	420	dev->block_cfg_access = 1;
	421	raw_spin_unlock_irq(&pci_lock);
	422	}
	423	EXPORT_SYMBOL_GPL(pci_cfg_access_lock);
	424
	425	/**
	426	* pci_cfg_access_trylock - try to lock PCI config reads/writes
	427	* @dev: pci device struct
	428	*
	429	* Same as pci_cfg_access_lock, but will return 0 if access is
	430	* already locked, 1 otherwise. This function can be used from
	431	* atomic contexts.
	432	*/
	433	bool pci_cfg_access_trylock(struct pci_dev *dev)
e04b0ea2 BK	434	{
e04b0ea2 BK	435	unsigned long flags;
fb51ccbf	436	bool locked = true;
e04b0ea2	437
511dd98c	438	raw_spin_lock_irqsave(&pci_lock, flags);
fb51ccbf JK	439	if (dev->block_cfg_access)
	440	locked = false;
	441	else
	442	dev->block_cfg_access = 1;
511dd98c	443	raw_spin_unlock_irqrestore(&pci_lock, flags);
7ea7e98f	444
fb51ccbf	445	return locked;
e04b0ea2	446	}
fb51ccbf	447	EXPORT_SYMBOL_GPL(pci_cfg_access_trylock);
e04b0ea2 BK	448
e04b0ea2 BK	449	/**
fb51ccbf	450	* pci_cfg_access_unlock - Unlock PCI config reads/writes
e04b0ea2 BK	451	* @dev: pci device struct
e04b0ea2 BK	452	*
fb51ccbf	453	* This function allows PCI config accesses to resume.
7ea7e98f	454	*/
fb51ccbf	455	void pci_cfg_access_unlock(struct pci_dev *dev)
e04b0ea2 BK	456	{
	457	unsigned long flags;
	458
511dd98c	459	raw_spin_lock_irqsave(&pci_lock, flags);
7ea7e98f MW	460
	461	/* This indicates a problem in the caller, but we don't need
	462	* to kill them, unlike a double-block above. */
fb51ccbf	463	WARN_ON(!dev->block_cfg_access);
7ea7e98f	464
fb51ccbf JK	465	dev->block_cfg_access = 0;
fb51ccbf JK	466	wake_up_all(&pci_cfg_wait);
511dd98c	467	raw_spin_unlock_irqrestore(&pci_lock, flags);
e04b0ea2	468	}
fb51ccbf	469	EXPORT_SYMBOL_GPL(pci_cfg_access_unlock);