Commit | Line | Data |
---|---|---|
f5fc0f86 LC |
1 | /* |
2 | * This file is part of wl1271 | |
3 | * | |
4 | * Copyright (C) 2009 Nokia Corporation | |
5 | * | |
6 | * Contact: Luciano Coelho <luciano.coelho@nokia.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * version 2 as published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but | |
13 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
20 | * 02110-1301 USA | |
21 | * | |
22 | */ | |
23 | ||
5a0e3ad6 TH |
24 | #include <linux/gfp.h> |
25 | ||
00d20100 SL |
26 | #include "wl12xx.h" |
27 | #include "acx.h" | |
28 | #include "reg.h" | |
29 | #include "rx.h" | |
30 | #include "io.h" | |
f5fc0f86 | 31 | |
c8bde243 | 32 | static u8 wl1271_rx_get_mem_block(struct wl1271_fw_common_status *status, |
f5fc0f86 LC |
33 | u32 drv_rx_counter) |
34 | { | |
d0f63b20 LC |
35 | return le32_to_cpu(status->rx_pkt_descs[drv_rx_counter]) & |
36 | RX_MEM_BLOCK_MASK; | |
f5fc0f86 LC |
37 | } |
38 | ||
c8bde243 | 39 | static u32 wl1271_rx_get_buf_size(struct wl1271_fw_common_status *status, |
f5fc0f86 LC |
40 | u32 drv_rx_counter) |
41 | { | |
d0f63b20 LC |
42 | return (le32_to_cpu(status->rx_pkt_descs[drv_rx_counter]) & |
43 | RX_BUF_SIZE_MASK) >> RX_BUF_SIZE_SHIFT_DIV; | |
f5fc0f86 LC |
44 | } |
45 | ||
f5fc0f86 LC |
46 | static void wl1271_rx_status(struct wl1271 *wl, |
47 | struct wl1271_rx_descriptor *desc, | |
48 | struct ieee80211_rx_status *status, | |
49 | u8 beacon) | |
50 | { | |
51 | memset(status, 0, sizeof(struct ieee80211_rx_status)); | |
52 | ||
6a2de93b | 53 | if ((desc->flags & WL1271_RX_DESC_BAND_MASK) == WL1271_RX_DESC_BAND_BG) |
0af0467f | 54 | status->band = IEEE80211_BAND_2GHZ; |
6a2de93b | 55 | else |
0af0467f | 56 | status->band = IEEE80211_BAND_5GHZ; |
6a2de93b | 57 | |
0af0467f | 58 | status->rate_idx = wl1271_rate_to_idx(desc->rate, status->band); |
a4102645 | 59 | |
00d20100 | 60 | #ifdef CONFIG_WL12XX_HT |
18357850 SL |
61 | /* 11n support */ |
62 | if (desc->rate <= CONF_HW_RXTX_RATE_MCS0) | |
63 | status->flag |= RX_FLAG_HT; | |
64 | #endif | |
65 | ||
f5fc0f86 LC |
66 | status->signal = desc->rssi; |
67 | ||
ece550d0 JL |
68 | /* |
69 | * FIXME: In wl1251, the SNR should be divided by two. In wl1271 we | |
70 | * need to divide by two for now, but TI has been discussing about | |
71 | * changing it. This needs to be rechecked. | |
72 | */ | |
73 | wl->noise = desc->rssi - (desc->snr >> 1); | |
74 | ||
0af0467f JO |
75 | status->freq = ieee80211_channel_to_frequency(desc->channel, |
76 | status->band); | |
f5fc0f86 LC |
77 | |
78 | if (desc->flags & WL1271_RX_DESC_ENCRYPT_MASK) { | |
34c8e3d2 | 79 | u8 desc_err_code = desc->status & WL1271_RX_DESC_STATUS_MASK; |
f5fc0f86 | 80 | |
34c8e3d2 AN |
81 | status->flag |= RX_FLAG_IV_STRIPPED | RX_FLAG_MMIC_STRIPPED | |
82 | RX_FLAG_DECRYPTED; | |
83 | ||
84 | if (unlikely(desc_err_code == WL1271_RX_DESC_MIC_FAIL)) { | |
5d07b668 | 85 | status->flag |= RX_FLAG_MMIC_ERROR; |
34c8e3d2 AN |
86 | wl1271_warning("Michael MIC error"); |
87 | } | |
f5fc0f86 | 88 | } |
f5fc0f86 LC |
89 | } |
90 | ||
1f37cbc9 | 91 | static int wl1271_rx_handle_data(struct wl1271 *wl, u8 *data, u32 length) |
f5fc0f86 | 92 | { |
f5fc0f86 LC |
93 | struct wl1271_rx_descriptor *desc; |
94 | struct sk_buff *skb; | |
92fe9b5f | 95 | struct ieee80211_hdr *hdr; |
f5fc0f86 LC |
96 | u8 *buf; |
97 | u8 beacon = 0; | |
98 | ||
93c5bb68 KV |
99 | /* |
100 | * In PLT mode we seem to get frames and mac80211 warns about them, | |
101 | * workaround this by not retrieving them at all. | |
102 | */ | |
103 | if (unlikely(wl->state == WL1271_STATE_PLT)) | |
1f37cbc9 | 104 | return -EINVAL; |
93c5bb68 | 105 | |
34c8e3d2 AN |
106 | /* the data read starts with the descriptor */ |
107 | desc = (struct wl1271_rx_descriptor *) data; | |
108 | ||
109 | switch (desc->status & WL1271_RX_DESC_STATUS_MASK) { | |
110 | /* discard corrupted packets */ | |
111 | case WL1271_RX_DESC_DRIVER_RX_Q_FAIL: | |
112 | case WL1271_RX_DESC_DECRYPT_FAIL: | |
113 | wl1271_warning("corrupted packet in RX with status: 0x%x", | |
114 | desc->status & WL1271_RX_DESC_STATUS_MASK); | |
115 | return -EINVAL; | |
116 | case WL1271_RX_DESC_SUCCESS: | |
117 | case WL1271_RX_DESC_MIC_FAIL: | |
118 | break; | |
119 | default: | |
120 | wl1271_error("invalid RX descriptor status: 0x%x", | |
121 | desc->status & WL1271_RX_DESC_STATUS_MASK); | |
122 | return -EINVAL; | |
123 | } | |
124 | ||
e9a6269d | 125 | skb = __dev_alloc_skb(length, GFP_KERNEL); |
f5fc0f86 LC |
126 | if (!skb) { |
127 | wl1271_error("Couldn't allocate RX frame"); | |
1f37cbc9 | 128 | return -ENOMEM; |
f5fc0f86 LC |
129 | } |
130 | ||
131 | buf = skb_put(skb, length); | |
1f37cbc9 | 132 | memcpy(buf, data, length); |
f5fc0f86 | 133 | |
f5fc0f86 LC |
134 | /* now we pull the descriptor out of the buffer */ |
135 | skb_pull(skb, sizeof(*desc)); | |
136 | ||
92fe9b5f EP |
137 | hdr = (struct ieee80211_hdr *)skb->data; |
138 | if (ieee80211_is_beacon(hdr->frame_control)) | |
f5fc0f86 LC |
139 | beacon = 1; |
140 | ||
58be4607 | 141 | wl1271_rx_status(wl, desc, IEEE80211_SKB_RXCB(skb), beacon); |
f5fc0f86 | 142 | |
a20a5b7e EP |
143 | wl1271_debug(DEBUG_RX, "rx skb 0x%p: %d B %s", skb, |
144 | skb->len - desc->pad_len, | |
f5fc0f86 LC |
145 | beacon ? "beacon" : ""); |
146 | ||
b9f2e39d JO |
147 | skb_trim(skb, skb->len - desc->pad_len); |
148 | ||
a620865e IY |
149 | skb_queue_tail(&wl->deferred_rx_queue, skb); |
150 | ieee80211_queue_work(wl->hw, &wl->netstack_work); | |
1f37cbc9 IY |
151 | |
152 | return 0; | |
f5fc0f86 LC |
153 | } |
154 | ||
c8bde243 | 155 | void wl1271_rx(struct wl1271 *wl, struct wl1271_fw_common_status *status) |
f5fc0f86 LC |
156 | { |
157 | struct wl1271_acx_mem_map *wl_mem_map = wl->target_mem_map; | |
158 | u32 buf_size; | |
159 | u32 fw_rx_counter = status->fw_rx_counter & NUM_RX_PKT_DESC_MOD_MASK; | |
160 | u32 drv_rx_counter = wl->rx_counter & NUM_RX_PKT_DESC_MOD_MASK; | |
1f37cbc9 | 161 | u32 rx_counter; |
f5fc0f86 | 162 | u32 mem_block; |
1f37cbc9 IY |
163 | u32 pkt_length; |
164 | u32 pkt_offset; | |
f5fc0f86 LC |
165 | |
166 | while (drv_rx_counter != fw_rx_counter) { | |
1f37cbc9 IY |
167 | buf_size = 0; |
168 | rx_counter = drv_rx_counter; | |
169 | while (rx_counter != fw_rx_counter) { | |
170 | pkt_length = wl1271_rx_get_buf_size(status, rx_counter); | |
171 | if (buf_size + pkt_length > WL1271_AGGR_BUFFER_SIZE) | |
172 | break; | |
173 | buf_size += pkt_length; | |
174 | rx_counter++; | |
175 | rx_counter &= NUM_RX_PKT_DESC_MOD_MASK; | |
176 | } | |
f5fc0f86 LC |
177 | |
178 | if (buf_size == 0) { | |
179 | wl1271_warning("received empty data"); | |
180 | break; | |
181 | } | |
182 | ||
ae77eccf SL |
183 | if (wl->chip.id != CHIP_ID_1283_PG20) { |
184 | /* | |
185 | * Choose the block we want to read | |
186 | * For aggregated packets, only the first memory block | |
187 | * should be retrieved. The FW takes care of the rest. | |
188 | */ | |
189 | mem_block = wl1271_rx_get_mem_block(status, | |
190 | drv_rx_counter); | |
191 | ||
192 | wl->rx_mem_pool_addr.addr = (mem_block << 8) + | |
193 | le32_to_cpu(wl_mem_map->packet_memory_pool_start); | |
194 | ||
195 | wl->rx_mem_pool_addr.addr_extra = | |
196 | wl->rx_mem_pool_addr.addr + 4; | |
197 | ||
198 | wl1271_write(wl, WL1271_SLV_REG_DATA, | |
199 | &wl->rx_mem_pool_addr, | |
200 | sizeof(wl->rx_mem_pool_addr), false); | |
201 | } | |
1f37cbc9 IY |
202 | |
203 | /* Read all available packets at once */ | |
204 | wl1271_read(wl, WL1271_SLV_MEM_DATA, wl->aggr_buf, | |
205 | buf_size, true); | |
206 | ||
207 | /* Split data into separate packets */ | |
208 | pkt_offset = 0; | |
209 | while (pkt_offset < buf_size) { | |
210 | pkt_length = wl1271_rx_get_buf_size(status, | |
211 | drv_rx_counter); | |
fb2382c7 JO |
212 | /* |
213 | * the handle data call can only fail in memory-outage | |
214 | * conditions, in that case the received frame will just | |
215 | * be dropped. | |
216 | */ | |
217 | wl1271_rx_handle_data(wl, | |
218 | wl->aggr_buf + pkt_offset, | |
219 | pkt_length); | |
1f37cbc9 IY |
220 | wl->rx_counter++; |
221 | drv_rx_counter++; | |
222 | drv_rx_counter &= NUM_RX_PKT_DESC_MOD_MASK; | |
223 | pkt_offset += pkt_length; | |
224 | } | |
f5fc0f86 | 225 | } |
606ea9fa IY |
226 | |
227 | /* | |
228 | * Write the driver's packet counter to the FW. This is only required | |
229 | * for older hardware revisions | |
230 | */ | |
231 | if (wl->quirks & WL12XX_QUIRK_END_OF_TRANSACTION) | |
232 | wl1271_write32(wl, RX_DRIVER_COUNTER_ADDRESS, wl->rx_counter); | |
f5fc0f86 | 233 | } |
ae113b57 AN |
234 | |
235 | void wl1271_set_default_filters(struct wl1271 *wl) | |
236 | { | |
237 | if (wl->bss_type == BSS_TYPE_AP_BSS) { | |
238 | wl->rx_config = WL1271_DEFAULT_AP_RX_CONFIG; | |
239 | wl->rx_filter = WL1271_DEFAULT_AP_RX_FILTER; | |
240 | } else { | |
241 | wl->rx_config = WL1271_DEFAULT_STA_RX_CONFIG; | |
242 | wl->rx_filter = WL1271_DEFAULT_STA_RX_FILTER; | |
243 | } | |
244 | } |