Commit | Line | Data |
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521a5b21 TP |
1 | /* |
2 | * This file is part of wl1271 | |
3 | * | |
4 | * Copyright (C) 1998-2009 Texas Instruments. All rights reserved. | |
5 | * Copyright (C) 2008-2010 Nokia Corporation | |
6 | * | |
7 | * Contact: Luciano Coelho <luciano.coelho@nokia.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * version 2 as published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
21 | * 02110-1301 USA | |
22 | * | |
23 | */ | |
24 | ||
00d20100 SL |
25 | #ifndef __IO_H__ |
26 | #define __IO_H__ | |
521a5b21 | 27 | |
a6b7a407 | 28 | #include <linux/irqreturn.h> |
760d969f TP |
29 | |
30 | #define HW_ACCESS_MEMORY_MAX_RANGE 0x1FFC0 | |
31 | ||
32 | #define HW_PARTITION_REGISTERS_ADDR 0x1FFC0 | |
33 | #define HW_PART0_SIZE_ADDR (HW_PARTITION_REGISTERS_ADDR) | |
34 | #define HW_PART0_START_ADDR (HW_PARTITION_REGISTERS_ADDR + 4) | |
35 | #define HW_PART1_SIZE_ADDR (HW_PARTITION_REGISTERS_ADDR + 8) | |
36 | #define HW_PART1_START_ADDR (HW_PARTITION_REGISTERS_ADDR + 12) | |
37 | #define HW_PART2_SIZE_ADDR (HW_PARTITION_REGISTERS_ADDR + 16) | |
38 | #define HW_PART2_START_ADDR (HW_PARTITION_REGISTERS_ADDR + 20) | |
39 | #define HW_PART3_START_ADDR (HW_PARTITION_REGISTERS_ADDR + 24) | |
40 | ||
41 | #define HW_ACCESS_REGISTER_SIZE 4 | |
42 | ||
43 | #define HW_ACCESS_PRAM_MAX_RANGE 0x3c000 | |
44 | ||
521a5b21 TP |
45 | struct wl1271; |
46 | ||
dd5512eb | 47 | void wlcore_disable_interrupts(struct wl1271 *wl); |
b666bb7f | 48 | void wlcore_disable_interrupts_nosync(struct wl1271 *wl); |
dd5512eb | 49 | void wlcore_enable_interrupts(struct wl1271 *wl); |
54f7e503 | 50 | |
9b280722 TP |
51 | void wl1271_io_reset(struct wl1271 *wl); |
52 | void wl1271_io_init(struct wl1271 *wl); | |
25a43d78 | 53 | int wlcore_translate_addr(struct wl1271 *wl, int addr); |
521a5b21 | 54 | |
b42f91ba | 55 | /* Raw target IO, address is not translated */ |
0c2a6ce0 IY |
56 | static inline int wlcore_raw_write(struct wl1271 *wl, int addr, void *buf, |
57 | size_t len, bool fixed) | |
b42f91ba | 58 | { |
0c2a6ce0 | 59 | return wl->if_ops->write(wl->dev, addr, buf, len, fixed); |
b42f91ba | 60 | } |
7b048c52 | 61 | |
0c2a6ce0 IY |
62 | static inline int wlcore_raw_read(struct wl1271 *wl, int addr, void *buf, |
63 | size_t len, bool fixed) | |
b42f91ba | 64 | { |
0c2a6ce0 | 65 | return wl->if_ops->read(wl->dev, addr, buf, len, fixed); |
b42f91ba | 66 | } |
7b048c52 | 67 | |
8b7c0fc3 IY |
68 | static inline int wlcore_raw_read_data(struct wl1271 *wl, int reg, void *buf, |
69 | size_t len, bool fixed) | |
00782136 | 70 | { |
8b7c0fc3 | 71 | return wlcore_raw_read(wl, wl->rtable[reg], buf, len, fixed); |
00782136 LC |
72 | } |
73 | ||
8b7c0fc3 IY |
74 | static inline int wlcore_raw_write_data(struct wl1271 *wl, int reg, void *buf, |
75 | size_t len, bool fixed) | |
00782136 | 76 | { |
8b7c0fc3 | 77 | return wlcore_raw_write(wl, wl->rtable[reg], buf, len, fixed); |
00782136 LC |
78 | } |
79 | ||
7b048c52 TP |
80 | static inline u32 wl1271_raw_read32(struct wl1271 *wl, int addr) |
81 | { | |
0c2a6ce0 | 82 | wlcore_raw_read(wl, addr, &wl->buffer_32, |
7b048c52 TP |
83 | sizeof(wl->buffer_32), false); |
84 | ||
554d7209 | 85 | return le32_to_cpu(wl->buffer_32); |
7b048c52 TP |
86 | } |
87 | ||
88 | static inline void wl1271_raw_write32(struct wl1271 *wl, int addr, u32 val) | |
89 | { | |
554d7209 | 90 | wl->buffer_32 = cpu_to_le32(val); |
0c2a6ce0 | 91 | wlcore_raw_write(wl, addr, &wl->buffer_32, |
7b048c52 TP |
92 | sizeof(wl->buffer_32), false); |
93 | } | |
2d5e82b8 | 94 | |
045b9b5f IY |
95 | static inline int wlcore_read(struct wl1271 *wl, int addr, void *buf, |
96 | size_t len, bool fixed) | |
b42f91ba TP |
97 | { |
98 | int physical; | |
99 | ||
25a43d78 | 100 | physical = wlcore_translate_addr(wl, addr); |
b42f91ba | 101 | |
045b9b5f | 102 | return wlcore_raw_read(wl, physical, buf, len, fixed); |
b42f91ba TP |
103 | } |
104 | ||
105 | static inline void wl1271_write(struct wl1271 *wl, int addr, void *buf, | |
106 | size_t len, bool fixed) | |
107 | { | |
108 | int physical; | |
109 | ||
25a43d78 | 110 | physical = wlcore_translate_addr(wl, addr); |
b42f91ba | 111 | |
0c2a6ce0 | 112 | wlcore_raw_write(wl, physical, buf, len, fixed); |
b42f91ba TP |
113 | } |
114 | ||
00782136 LC |
115 | static inline void wlcore_write_data(struct wl1271 *wl, int reg, void *buf, |
116 | size_t len, bool fixed) | |
117 | { | |
118 | wl1271_write(wl, wl->rtable[reg], buf, len, fixed); | |
119 | } | |
120 | ||
045b9b5f | 121 | static inline int wlcore_read_data(struct wl1271 *wl, int reg, void *buf, |
00782136 LC |
122 | size_t len, bool fixed) |
123 | { | |
045b9b5f | 124 | return wlcore_read(wl, wl->rtable[reg], buf, len, fixed); |
00782136 LC |
125 | } |
126 | ||
95dac04f IY |
127 | static inline void wl1271_read_hwaddr(struct wl1271 *wl, int hwaddr, |
128 | void *buf, size_t len, bool fixed) | |
129 | { | |
130 | int physical; | |
131 | int addr; | |
132 | ||
133 | /* Addresses are stored internally as addresses to 32 bytes blocks */ | |
134 | addr = hwaddr << 5; | |
135 | ||
25a43d78 | 136 | physical = wlcore_translate_addr(wl, addr); |
95dac04f | 137 | |
0c2a6ce0 | 138 | wlcore_raw_read(wl, physical, buf, len, fixed); |
95dac04f IY |
139 | } |
140 | ||
b42f91ba TP |
141 | static inline u32 wl1271_read32(struct wl1271 *wl, int addr) |
142 | { | |
25a43d78 | 143 | return wl1271_raw_read32(wl, wlcore_translate_addr(wl, addr)); |
b42f91ba TP |
144 | } |
145 | ||
146 | static inline void wl1271_write32(struct wl1271 *wl, int addr, u32 val) | |
147 | { | |
25a43d78 | 148 | wl1271_raw_write32(wl, wlcore_translate_addr(wl, addr), val); |
b42f91ba TP |
149 | } |
150 | ||
00782136 LC |
151 | static inline u32 wlcore_read_reg(struct wl1271 *wl, int reg) |
152 | { | |
153 | return wl1271_raw_read32(wl, | |
154 | wlcore_translate_addr(wl, wl->rtable[reg])); | |
155 | } | |
156 | ||
157 | static inline void wlcore_write_reg(struct wl1271 *wl, int reg, u32 val) | |
158 | { | |
159 | wl1271_raw_write32(wl, wlcore_translate_addr(wl, wl->rtable[reg]), val); | |
160 | } | |
161 | ||
becd551c TP |
162 | static inline void wl1271_power_off(struct wl1271 *wl) |
163 | { | |
645865fc IY |
164 | int ret; |
165 | ||
166 | if (!test_bit(WL1271_FLAG_GPIO_POWER, &wl->flags)) | |
167 | return; | |
168 | ||
169 | ret = wl->if_ops->power(wl->dev, false); | |
170 | if (!ret) | |
171 | clear_bit(WL1271_FLAG_GPIO_POWER, &wl->flags); | |
becd551c TP |
172 | } |
173 | ||
2cc78ff7 | 174 | static inline int wl1271_power_on(struct wl1271 *wl) |
becd551c | 175 | { |
a390e85c | 176 | int ret = wl->if_ops->power(wl->dev, true); |
2cc78ff7 OBC |
177 | if (ret == 0) |
178 | set_bit(WL1271_FLAG_GPIO_POWER, &wl->flags); | |
179 | ||
180 | return ret; | |
becd551c TP |
181 | } |
182 | ||
25a43d78 LC |
183 | void wlcore_set_partition(struct wl1271 *wl, |
184 | const struct wlcore_partition_set *p); | |
b42f91ba | 185 | |
4b32a2c9 FB |
186 | bool wl1271_set_block_size(struct wl1271 *wl); |
187 | ||
2d5e82b8 TP |
188 | /* Functions from wl1271_main.c */ |
189 | ||
ae47c45f | 190 | int wl1271_tx_dummy_packet(struct wl1271 *wl); |
2d5e82b8 | 191 | |
25a43d78 LC |
192 | void wlcore_select_partition(struct wl1271 *wl, u8 part); |
193 | ||
521a5b21 | 194 | #endif |