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cfg80211 API for channels/bitrates, mac80211 and driver conversion
[GitHub/LineageOS/android_kernel_samsung_universal7580.git] / drivers / net / wireless / rtl8187_dev.c
CommitLineData
605bebe2
MW		 1/*
2 * Linux device driver for RTL8187
3 *
4 * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
5 * Copyright 2007 Andrea Merello <andreamrl@tiscali.it>
6 *
7 * Based on the r8187 driver, which is:
8 * Copyright 2005 Andrea Merello <andreamrl@tiscali.it>, et al.
9 *
0aec00ae
JL		 10 * Magic delays and register offsets below are taken from the original
11 * r8187 driver sources. Thanks to Realtek for their support!
605bebe2
MW		 12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/init.h>
19#include <linux/usb.h>
20#include <linux/delay.h>
21#include <linux/etherdevice.h>
22#include <linux/eeprom_93cx6.h>
23#include <net/mac80211.h>
24
25#include "rtl8187.h"
26#include "rtl8187_rtl8225.h"
27
28MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
29MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>");
30MODULE_DESCRIPTION("RTL8187 USB wireless driver");
31MODULE_LICENSE("GPL");
32
33static struct usb_device_id rtl8187_table[] __devinitdata = {
34 /* Realtek */
35 {USB_DEVICE(0x0bda, 0x8187)},
36 /* Netgear */
37 {USB_DEVICE(0x0846, 0x6100)},
38 {USB_DEVICE(0x0846, 0x6a00)},
c3cf60a9
MW		 39 /* HP */
40 {USB_DEVICE(0x03f0, 0xca02)},
9934550d
MM		 41 /* Sitecom */
42 {USB_DEVICE(0x0df6, 0x000d)},
605bebe2
MW		 43 {}
44};
45
46MODULE_DEVICE_TABLE(usb, rtl8187_table);
47
8318d78a
JB		 48static const struct ieee80211_rate rtl818x_rates[] = {
49 { .bitrate = 10, .hw_value = 0, },
50 { .bitrate = 20, .hw_value = 1, },
51 { .bitrate = 55, .hw_value = 2, },
52 { .bitrate = 110, .hw_value = 3, },
53 { .bitrate = 60, .hw_value = 4, },
54 { .bitrate = 90, .hw_value = 5, },
55 { .bitrate = 120, .hw_value = 6, },
56 { .bitrate = 180, .hw_value = 7, },
57 { .bitrate = 240, .hw_value = 8, },
58 { .bitrate = 360, .hw_value = 9, },
59 { .bitrate = 480, .hw_value = 10, },
60 { .bitrate = 540, .hw_value = 11, },
61};
62
63static const struct ieee80211_channel rtl818x_channels[] = {
64 { .center_freq = 2412 },
65 { .center_freq = 2417 },
66 { .center_freq = 2422 },
67 { .center_freq = 2427 },
68 { .center_freq = 2432 },
69 { .center_freq = 2437 },
70 { .center_freq = 2442 },
71 { .center_freq = 2447 },
72 { .center_freq = 2452 },
73 { .center_freq = 2457 },
74 { .center_freq = 2462 },
75 { .center_freq = 2467 },
76 { .center_freq = 2472 },
77 { .center_freq = 2484 },
78};
79
4150c572
JB		 80static void rtl8187_iowrite_async_cb(struct urb *urb)
81{
82 kfree(urb->context);
83 usb_free_urb(urb);
84}
85
86static void rtl8187_iowrite_async(struct rtl8187_priv *priv, __le16 addr,
87 void *data, u16 len)
88{
89 struct usb_ctrlrequest *dr;
90 struct urb *urb;
91 struct rtl8187_async_write_data {
92 u8 data[4];
93 struct usb_ctrlrequest dr;
94 } *buf;
95
96 buf = kmalloc(sizeof(*buf), GFP_ATOMIC);
97 if (!buf)
98 return;
99
100 urb = usb_alloc_urb(0, GFP_ATOMIC);
101 if (!urb) {
102 kfree(buf);
103 return;
104 }
105
106 dr = &buf->dr;
107
108 dr->bRequestType = RTL8187_REQT_WRITE;
109 dr->bRequest = RTL8187_REQ_SET_REG;
110 dr->wValue = addr;
111 dr->wIndex = 0;
112 dr->wLength = cpu_to_le16(len);
113
114 memcpy(buf, data, len);
115
116 usb_fill_control_urb(urb, priv->udev, usb_sndctrlpipe(priv->udev, 0),
117 (unsigned char *)dr, buf, len,
118 rtl8187_iowrite_async_cb, buf);
119 usb_submit_urb(urb, GFP_ATOMIC);
120}
121
122static inline void rtl818x_iowrite32_async(struct rtl8187_priv *priv,
123 __le32 *addr, u32 val)
124{
125 __le32 buf = cpu_to_le32(val);
126
127 rtl8187_iowrite_async(priv, cpu_to_le16((unsigned long)addr),
128 &buf, sizeof(buf));
129}
130
605bebe2
MW		 131void rtl8187_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data)
132{
133 struct rtl8187_priv *priv = dev->priv;
134
135 data <<= 8;
136 data |= addr | 0x80;
137
138 rtl818x_iowrite8(priv, &priv->map->PHY[3], (data >> 24) & 0xFF);
139 rtl818x_iowrite8(priv, &priv->map->PHY[2], (data >> 16) & 0xFF);
140 rtl818x_iowrite8(priv, &priv->map->PHY[1], (data >> 8) & 0xFF);
141 rtl818x_iowrite8(priv, &priv->map->PHY[0], data & 0xFF);
142
143 msleep(1);
144}
145
146static void rtl8187_tx_cb(struct urb *urb)
147{
1955fd0b 148 struct ieee80211_tx_status status;
605bebe2
MW		 149 struct sk_buff *skb = (struct sk_buff *)urb->context;
150 struct rtl8187_tx_info *info = (struct rtl8187_tx_info *)skb->cb;
151
1955fd0b
JB		 152 memset(&status, 0, sizeof(status));
153
605bebe2
MW		 154 usb_free_urb(info->urb);
155 if (info->control)
156 memcpy(&status.control, info->control, sizeof(status.control));
157 kfree(info->control);
158 skb_pull(skb, sizeof(struct rtl8187_tx_hdr));
159 status.flags |= IEEE80211_TX_STATUS_ACK;
160 ieee80211_tx_status_irqsafe(info->dev, skb, &status);
161}
162
163static int rtl8187_tx(struct ieee80211_hw *dev, struct sk_buff *skb,
164 struct ieee80211_tx_control *control)
165{
166 struct rtl8187_priv *priv = dev->priv;
167 struct rtl8187_tx_hdr *hdr;
168 struct rtl8187_tx_info *info;
169 struct urb *urb;
98798f48
MW		 170 __le16 rts_dur = 0;
171 u32 flags;
605bebe2
MW		 172
173 urb = usb_alloc_urb(0, GFP_ATOMIC);
174 if (!urb) {
175 kfree_skb(skb);
176 return 0;
177 }
178
98798f48
MW		 179 flags = skb->len;
180 flags |= RTL8187_TX_FLAG_NO_ENCRYPT;
8318d78a
JB		 181 flags |= control->rts_cts_rate->hw_value << 19;
182 flags |= control->tx_rate->hw_value << 24;
98798f48
MW		 183 if (ieee80211_get_morefrag((struct ieee80211_hdr *)skb->data))
184 flags |= RTL8187_TX_FLAG_MORE_FRAG;
605bebe2 185 if (control->flags & IEEE80211_TXCTL_USE_RTS_CTS) {
98798f48 186 flags |= RTL8187_TX_FLAG_RTS;
32bfd35d
JB		 187 rts_dur = ieee80211_rts_duration(dev, priv->vif,
188 skb->len, control);
605bebe2
MW		 189 }
190 if (control->flags & IEEE80211_TXCTL_USE_CTS_PROTECT)
98798f48
MW		 191 flags |= RTL8187_TX_FLAG_CTS;
192
193 hdr = (struct rtl8187_tx_hdr *)skb_push(skb, sizeof(*hdr));
194 hdr->flags = cpu_to_le32(flags);
605bebe2 195 hdr->len = 0;
98798f48
MW		 196 hdr->rts_duration = rts_dur;
197 hdr->retry = cpu_to_le32(control->retry_limit << 8);
605bebe2
MW		 198
199 info = (struct rtl8187_tx_info *)skb->cb;
200 info->control = kmemdup(control, sizeof(*control), GFP_ATOMIC);
201 info->urb = urb;
202 info->dev = dev;
203 usb_fill_bulk_urb(urb, priv->udev, usb_sndbulkpipe(priv->udev, 2),
204 hdr, skb->len, rtl8187_tx_cb, skb);
205 usb_submit_urb(urb, GFP_ATOMIC);
206
207 return 0;
208}
209
210static void rtl8187_rx_cb(struct urb *urb)
211{
212 struct sk_buff *skb = (struct sk_buff *)urb->context;
213 struct rtl8187_rx_info *info = (struct rtl8187_rx_info *)skb->cb;
214 struct ieee80211_hw *dev = info->dev;
215 struct rtl8187_priv *priv = dev->priv;
216 struct rtl8187_rx_hdr *hdr;
217 struct ieee80211_rx_status rx_status = { 0 };
218 int rate, signal;
4150c572 219 u32 flags;
605bebe2
MW		 220
221 spin_lock(&priv->rx_queue.lock);
222 if (skb->next)
223 __skb_unlink(skb, &priv->rx_queue);
224 else {
225 spin_unlock(&priv->rx_queue.lock);
226 return;
227 }
228 spin_unlock(&priv->rx_queue.lock);
229
230 if (unlikely(urb->status)) {
231 usb_free_urb(urb);
232 dev_kfree_skb_irq(skb);
233 return;
234 }
235
236 skb_put(skb, urb->actual_length);
237 hdr = (struct rtl8187_rx_hdr *)(skb_tail_pointer(skb) - sizeof(*hdr));
4150c572
JB		 238 flags = le32_to_cpu(hdr->flags);
239 skb_trim(skb, flags & 0x0FFF);
605bebe2
MW		 240
241 signal = hdr->agc >> 1;
4150c572 242 rate = (flags >> 20) & 0xF;
605bebe2
MW		 243 if (rate > 3) { /* OFDM rate */
244 if (signal > 90)
245 signal = 90;
246 else if (signal < 25)
247 signal = 25;
248 signal = 90 - signal;
249 } else { /* CCK rate */
250 if (signal > 95)
251 signal = 95;
252 else if (signal < 30)
253 signal = 30;
254 signal = 95 - signal;
255 }
256
257 rx_status.antenna = (hdr->signal >> 7) & 1;
258 rx_status.signal = 64 - min(hdr->noise, (u8)64);
259 rx_status.ssi = signal;
8318d78a
JB		 260 rx_status.rate_idx = rate;
261 rx_status.freq = dev->conf.channel->center_freq;
262 rx_status.band = dev->conf.channel->band;
605bebe2 263 rx_status.mactime = le64_to_cpu(hdr->mac_time);
03bffc13 264 rx_status.flag |= RX_FLAG_TSFT;
4150c572
JB		 265 if (flags & (1 << 13))
266 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
605bebe2
MW		 267 ieee80211_rx_irqsafe(dev, skb, &rx_status);
268
269 skb = dev_alloc_skb(RTL8187_MAX_RX);
270 if (unlikely(!skb)) {
271 usb_free_urb(urb);
272 /* TODO check rx queue length and refill *somewhere* */
273 return;
274 }
275
276 info = (struct rtl8187_rx_info *)skb->cb;
277 info->urb = urb;
278 info->dev = dev;
279 urb->transfer_buffer = skb_tail_pointer(skb);
280 urb->context = skb;
281 skb_queue_tail(&priv->rx_queue, skb);
282
283 usb_submit_urb(urb, GFP_ATOMIC);
284}
285
286static int rtl8187_init_urbs(struct ieee80211_hw *dev)
287{
288 struct rtl8187_priv *priv = dev->priv;
289 struct urb *entry;
290 struct sk_buff *skb;
291 struct rtl8187_rx_info *info;
292
293 while (skb_queue_len(&priv->rx_queue) < 8) {
294 skb = __dev_alloc_skb(RTL8187_MAX_RX, GFP_KERNEL);
295 if (!skb)
296 break;
297 entry = usb_alloc_urb(0, GFP_KERNEL);
298 if (!entry) {
299 kfree_skb(skb);
300 break;
301 }
302 usb_fill_bulk_urb(entry, priv->udev,
303 usb_rcvbulkpipe(priv->udev, 1),
304 skb_tail_pointer(skb),
305 RTL8187_MAX_RX, rtl8187_rx_cb, skb);
306 info = (struct rtl8187_rx_info *)skb->cb;
307 info->urb = entry;
308 info->dev = dev;
309 skb_queue_tail(&priv->rx_queue, skb);
310 usb_submit_urb(entry, GFP_KERNEL);
311 }
312
313 return 0;
314}
315
316static int rtl8187_init_hw(struct ieee80211_hw *dev)
317{
318 struct rtl8187_priv *priv = dev->priv;
319 u8 reg;
320 int i;
321
322 /* reset */
323 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
324 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
325 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
326 rtl818x_iowrite32(priv, &priv->map->ANAPARAM, RTL8225_ANAPARAM_ON);
327 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2, RTL8225_ANAPARAM2_ON);
328 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
329 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
330
331 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
332
333 msleep(200);
334 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x10);
335 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x11);
336 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x00);
337 msleep(200);
338
339 reg = rtl818x_ioread8(priv, &priv->map->CMD);
340 reg &= (1 << 1);
341 reg |= RTL818X_CMD_RESET;
342 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
343
344 i = 10;
345 do {
346 msleep(2);
347 if (!(rtl818x_ioread8(priv, &priv->map->CMD) &
348 RTL818X_CMD_RESET))
349 break;
350 } while (--i);
351
352 if (!i) {
353 printk(KERN_ERR "%s: Reset timeout!\n", wiphy_name(dev->wiphy));
354 return -ETIMEDOUT;
355 }
356
357 /* reload registers from eeprom */
358 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD);
359
360 i = 10;
361 do {
362 msleep(4);
363 if (!(rtl818x_ioread8(priv, &priv->map->EEPROM_CMD) &
364 RTL818X_EEPROM_CMD_CONFIG))
365 break;
366 } while (--i);
367
368 if (!i) {
369 printk(KERN_ERR "%s: eeprom reset timeout!\n",
370 wiphy_name(dev->wiphy));
371 return -ETIMEDOUT;
372 }
373
374 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
375 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
376 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
377 rtl818x_iowrite32(priv, &priv->map->ANAPARAM, RTL8225_ANAPARAM_ON);
378 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2, RTL8225_ANAPARAM2_ON);
379 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
380 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
381
382 /* setup card */
383 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0);
384 rtl818x_iowrite8(priv, &priv->map->GPIO, 0);
385
386 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, (4 << 8));
387 rtl818x_iowrite8(priv, &priv->map->GPIO, 1);
388 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0);
389
390 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
605bebe2
MW		 391
392 rtl818x_iowrite16(priv, (__le16 *)0xFFF4, 0xFFFF);
393 reg = rtl818x_ioread8(priv, &priv->map->CONFIG1);
394 reg &= 0x3F;
395 reg |= 0x80;
396 rtl818x_iowrite8(priv, &priv->map->CONFIG1, reg);
397
398 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
399
400 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
401 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
402 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0x81);
403
404 // TODO: set RESP_RATE and BRSR properly
405 rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (8 << 4) | 0);
406 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
407
408 /* host_usb_init */
409 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0);
410 rtl818x_iowrite8(priv, &priv->map->GPIO, 0);
411 reg = rtl818x_ioread8(priv, (u8 *)0xFE53);
412 rtl818x_iowrite8(priv, (u8 *)0xFE53, reg | (1 << 7));
413 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, (4 << 8));
414 rtl818x_iowrite8(priv, &priv->map->GPIO, 0x20);
415 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0);
416 rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x80);
417 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x80);
418 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x80);
419 msleep(100);
420
421 rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x000a8008);
422 rtl818x_iowrite16(priv, &priv->map->BRSR, 0xFFFF);
423 rtl818x_iowrite32(priv, &priv->map->RF_PARA, 0x00100044);
424 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
425 rtl818x_iowrite8(priv, &priv->map->CONFIG3, 0x44);
426 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
427 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FF7);
428 msleep(100);
429
f6532111 430 priv->rf->init(dev);
605bebe2
MW		 431
432 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
f6532111
MW		 433 reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) & ~1;
434 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg | 1);
605bebe2
MW		 435 rtl818x_iowrite16(priv, (__le16 *)0xFFFE, 0x10);
436 rtl818x_iowrite8(priv, &priv->map->TALLY_SEL, 0x80);
437 rtl818x_iowrite8(priv, (u8 *)0xFFFF, 0x60);
f6532111 438 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg);
605bebe2
MW		 439
440 return 0;
441}
442
4150c572 443static int rtl8187_start(struct ieee80211_hw *dev)
605bebe2
MW		 444{
445 struct rtl8187_priv *priv = dev->priv;
446 u32 reg;
447 int ret;
448
449 ret = rtl8187_init_hw(dev);
450 if (ret)
451 return ret;
452
453 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
454
2fe14263
MW		 455 rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
456 rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0);
457
605bebe2
MW		 458 rtl8187_init_urbs(dev);
459
460 reg = RTL818X_RX_CONF_ONLYERLPKT |
461 RTL818X_RX_CONF_RX_AUTORESETPHY |
462 RTL818X_RX_CONF_BSSID |
463 RTL818X_RX_CONF_MGMT |
605bebe2
MW		 464 RTL818X_RX_CONF_DATA |
465 (7 << 13 /* RX FIFO threshold NONE */) |
466 (7 << 10 /* MAX RX DMA */) |
467 RTL818X_RX_CONF_BROADCAST |
605bebe2 468 RTL818X_RX_CONF_NICMAC;
605bebe2 469
4150c572 470 priv->rx_conf = reg;
605bebe2
MW		 471 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
472
473 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
474 reg &= ~RTL818X_CW_CONF_PERPACKET_CW_SHIFT;
475 reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
476 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
477
478 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
479 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT;
480 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
481 reg &= ~RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
482 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
483
484 reg = RTL818X_TX_CONF_CW_MIN |
485 (7 << 21 /* MAX TX DMA */) |
486 RTL818X_TX_CONF_NO_ICV;
487 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
488
489 reg = rtl818x_ioread8(priv, &priv->map->CMD);
490 reg |= RTL818X_CMD_TX_ENABLE;
491 reg |= RTL818X_CMD_RX_ENABLE;
492 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
493
494 return 0;
495}
496
4150c572 497static void rtl8187_stop(struct ieee80211_hw *dev)
605bebe2
MW		 498{
499 struct rtl8187_priv *priv = dev->priv;
500 struct rtl8187_rx_info *info;
501 struct sk_buff *skb;
502 u32 reg;
503
504 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
505
506 reg = rtl818x_ioread8(priv, &priv->map->CMD);
507 reg &= ~RTL818X_CMD_TX_ENABLE;
508 reg &= ~RTL818X_CMD_RX_ENABLE;
509 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
510
f6532111 511 priv->rf->stop(dev);
605bebe2
MW		 512
513 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
514 reg = rtl818x_ioread8(priv, &priv->map->CONFIG4);
515 rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF);
516 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
517
518 while ((skb = skb_dequeue(&priv->rx_queue))) {
519 info = (struct rtl8187_rx_info *)skb->cb;
520 usb_kill_urb(info->urb);
521 kfree_skb(skb);
522 }
4150c572 523 return;
605bebe2
MW		 524}
525
526static int rtl8187_add_interface(struct ieee80211_hw *dev,
527 struct ieee80211_if_init_conf *conf)
528{
529 struct rtl8187_priv *priv = dev->priv;
4150c572 530 int i;
605bebe2 531
4150c572
JB		 532 if (priv->mode != IEEE80211_IF_TYPE_MNTR)
533 return -EOPNOTSUPP;
605bebe2
MW		 534
535 switch (conf->type) {
536 case IEEE80211_IF_TYPE_STA:
605bebe2
MW		 537 priv->mode = conf->type;
538 break;
539 default:
540 return -EOPNOTSUPP;
541 }
542
4150c572
JB		 543 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
544 for (i = 0; i < ETH_ALEN; i++)
545 rtl818x_iowrite8(priv, &priv->map->MAC[i],
546 ((u8 *)conf->mac_addr)[i]);
547 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
605bebe2
MW		 548
549 return 0;
550}
551
552static void rtl8187_remove_interface(struct ieee80211_hw *dev,
553 struct ieee80211_if_init_conf *conf)
554{
555 struct rtl8187_priv *priv = dev->priv;
4150c572 556 priv->mode = IEEE80211_IF_TYPE_MNTR;
605bebe2
MW		 557}
558
559static int rtl8187_config(struct ieee80211_hw *dev, struct ieee80211_conf *conf)
560{
561 struct rtl8187_priv *priv = dev->priv;
f6532111
MW		 562 u32 reg;
563
564 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
565 /* Enable TX loopback on MAC level to avoid TX during channel
566 * changes, as this has be seen to causes problems and the
567 * card will stop work until next reset
568 */
569 rtl818x_iowrite32(priv, &priv->map->TX_CONF,
570 reg | RTL818X_TX_CONF_LOOPBACK_MAC);
571 msleep(10);
572 priv->rf->set_chan(dev, conf);
573 msleep(10);
574 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
605bebe2
MW		 575
576 rtl818x_iowrite8(priv, &priv->map->SIFS, 0x22);
577
578 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME) {
579 rtl818x_iowrite8(priv, &priv->map->SLOT, 0x9);
580 rtl818x_iowrite8(priv, &priv->map->DIFS, 0x14);
581 rtl818x_iowrite8(priv, &priv->map->EIFS, 91 - 0x14);
582 rtl818x_iowrite8(priv, &priv->map->CW_VAL, 0x73);
583 } else {
584 rtl818x_iowrite8(priv, &priv->map->SLOT, 0x14);
585 rtl818x_iowrite8(priv, &priv->map->DIFS, 0x24);
586 rtl818x_iowrite8(priv, &priv->map->EIFS, 91 - 0x24);
587 rtl818x_iowrite8(priv, &priv->map->CW_VAL, 0xa5);
588 }
589
590 rtl818x_iowrite16(priv, &priv->map->ATIM_WND, 2);
591 rtl818x_iowrite16(priv, &priv->map->ATIMTR_INTERVAL, 100);
592 rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL, 100);
593 rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL_TIME, 100);
594 return 0;
595}
596
32bfd35d
JB		 597static int rtl8187_config_interface(struct ieee80211_hw *dev,
598 struct ieee80211_vif *vif,
605bebe2
MW		 599 struct ieee80211_if_conf *conf)
600{
601 struct rtl8187_priv *priv = dev->priv;
602 int i;
603
604 for (i = 0; i < ETH_ALEN; i++)
605 rtl818x_iowrite8(priv, &priv->map->BSSID[i], conf->bssid[i]);
606
607 if (is_valid_ether_addr(conf->bssid))
608 rtl818x_iowrite8(priv, &priv->map->MSR, RTL818X_MSR_INFRA);
609 else
610 rtl818x_iowrite8(priv, &priv->map->MSR, RTL818X_MSR_NO_LINK);
611
612 return 0;
613}
614
4150c572
JB		 615static void rtl8187_configure_filter(struct ieee80211_hw *dev,
616 unsigned int changed_flags,
617 unsigned int *total_flags,
2fe14263 618 int mc_count, struct dev_addr_list *mclist)
4150c572
JB		 619{
620 struct rtl8187_priv *priv = dev->priv;
621
4150c572
JB		 622 if (changed_flags & FIF_FCSFAIL)
623 priv->rx_conf ^= RTL818X_RX_CONF_FCS;
624 if (changed_flags & FIF_CONTROL)
625 priv->rx_conf ^= RTL818X_RX_CONF_CTRL;
626 if (changed_flags & FIF_OTHER_BSS)
627 priv->rx_conf ^= RTL818X_RX_CONF_MONITOR;
2fe14263 628 if (*total_flags & FIF_ALLMULTI || mc_count > 0)
4150c572 629 priv->rx_conf |= RTL818X_RX_CONF_MULTICAST;
2fe14263
MW		 630 else
631 priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST;
632
633 *total_flags = 0;
4150c572 634
4150c572
JB		 635 if (priv->rx_conf & RTL818X_RX_CONF_FCS)
636 *total_flags |= FIF_FCSFAIL;
637 if (priv->rx_conf & RTL818X_RX_CONF_CTRL)
638 *total_flags |= FIF_CONTROL;
639 if (priv->rx_conf & RTL818X_RX_CONF_MONITOR)
640 *total_flags |= FIF_OTHER_BSS;
2fe14263
MW		 641 if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST)
642 *total_flags |= FIF_ALLMULTI;
4150c572
JB		 643
644 rtl818x_iowrite32_async(priv, &priv->map->RX_CONF, priv->rx_conf);
645}
646
605bebe2
MW		 647static const struct ieee80211_ops rtl8187_ops = {
648 .tx = rtl8187_tx,
4150c572 649 .start = rtl8187_start,
605bebe2
MW		 650 .stop = rtl8187_stop,
651 .add_interface = rtl8187_add_interface,
652 .remove_interface = rtl8187_remove_interface,
653 .config = rtl8187_config,
654 .config_interface = rtl8187_config_interface,
4150c572 655 .configure_filter = rtl8187_configure_filter,
605bebe2
MW		 656};
657
658static void rtl8187_eeprom_register_read(struct eeprom_93cx6 *eeprom)
659{
660 struct ieee80211_hw *dev = eeprom->data;
661 struct rtl8187_priv *priv = dev->priv;
662 u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
663
664 eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE;
665 eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ;
666 eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK;
667 eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS;
668}
669
670static void rtl8187_eeprom_register_write(struct eeprom_93cx6 *eeprom)
671{
672 struct ieee80211_hw *dev = eeprom->data;
673 struct rtl8187_priv *priv = dev->priv;
674 u8 reg = RTL818X_EEPROM_CMD_PROGRAM;
675
676 if (eeprom->reg_data_in)
677 reg |= RTL818X_EEPROM_CMD_WRITE;
678 if (eeprom->reg_data_out)
679 reg |= RTL818X_EEPROM_CMD_READ;
680 if (eeprom->reg_data_clock)
681 reg |= RTL818X_EEPROM_CMD_CK;
682 if (eeprom->reg_chip_select)
683 reg |= RTL818X_EEPROM_CMD_CS;
684
685 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg);
686 udelay(10);
687}
688
689static int __devinit rtl8187_probe(struct usb_interface *intf,
690 const struct usb_device_id *id)
691{
692 struct usb_device *udev = interface_to_usbdev(intf);
693 struct ieee80211_hw *dev;
694 struct rtl8187_priv *priv;
695 struct eeprom_93cx6 eeprom;
696 struct ieee80211_channel *channel;
697 u16 txpwr, reg;
698 int err, i;
0795af57 699 DECLARE_MAC_BUF(mac);
605bebe2
MW		 700
701 dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8187_ops);
702 if (!dev) {
703 printk(KERN_ERR "rtl8187: ieee80211 alloc failed\n");
704 return -ENOMEM;
705 }
706
707 priv = dev->priv;
708
709 SET_IEEE80211_DEV(dev, &intf->dev);
710 usb_set_intfdata(intf, dev);
711 priv->udev = udev;
712
713 usb_get_dev(udev);
714
715 skb_queue_head_init(&priv->rx_queue);
8318d78a
JB		 716
717 BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels));
718 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates));
719
605bebe2
MW		 720 memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels));
721 memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates));
722 priv->map = (struct rtl818x_csr *)0xFF00;
8318d78a
JB		 723
724 priv->band.band = IEEE80211_BAND_2GHZ;
725 priv->band.channels = priv->channels;
726 priv->band.n_channels = ARRAY_SIZE(rtl818x_channels);
727 priv->band.bitrates = priv->rates;
728 priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates);
729 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
730
731
4150c572 732 priv->mode = IEEE80211_IF_TYPE_MNTR;
605bebe2 733 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
7848ba7d 734 IEEE80211_HW_RX_INCLUDES_FCS;
605bebe2
MW		 735 dev->extra_tx_headroom = sizeof(struct rtl8187_tx_hdr);
736 dev->queues = 1;
737 dev->max_rssi = 65;
738 dev->max_signal = 64;
739
605bebe2
MW		 740 eeprom.data = dev;
741 eeprom.register_read = rtl8187_eeprom_register_read;
742 eeprom.register_write = rtl8187_eeprom_register_write;
743 if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6))
744 eeprom.width = PCI_EEPROM_WIDTH_93C66;
745 else
746 eeprom.width = PCI_EEPROM_WIDTH_93C46;
747
748 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
749 udelay(10);
750
751 eeprom_93cx6_multiread(&eeprom, RTL8187_EEPROM_MAC_ADDR,
752 (__le16 __force *)dev->wiphy->perm_addr, 3);
753 if (!is_valid_ether_addr(dev->wiphy->perm_addr)) {
754 printk(KERN_WARNING "rtl8187: Invalid hwaddr! Using randomly "
755 "generated MAC address\n");
756 random_ether_addr(dev->wiphy->perm_addr);
757 }
758
759 channel = priv->channels;
760 for (i = 0; i < 3; i++) {
761 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_1 + i,
762 &txpwr);
8318d78a
JB		 763 (*channel++).hw_value = txpwr & 0xFF;
764 (*channel++).hw_value = txpwr >> 8;
605bebe2
MW		 765 }
766 for (i = 0; i < 2; i++) {
767 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_4 + i,
768 &txpwr);
8318d78a
JB		 769 (*channel++).hw_value = txpwr & 0xFF;
770 (*channel++).hw_value = txpwr >> 8;
605bebe2
MW		 771 }
772 for (i = 0; i < 2; i++) {
773 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_6 + i,
774 &txpwr);
8318d78a
JB		 775 (*channel++).hw_value = txpwr & 0xFF;
776 (*channel++).hw_value = txpwr >> 8;
605bebe2
MW		 777 }
778
779 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_BASE,
780 &priv->txpwr_base);
781
f6532111
MW		 782 reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) & ~1;
783 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg | 1);
605bebe2
MW		 784 /* 0 means asic B-cut, we should use SW 3 wire
785 * bit-by-bit banging for radio. 1 means we can use
786 * USB specific request to write radio registers */
787 priv->asic_rev = rtl818x_ioread8(priv, (u8 *)0xFFFE) & 0x3;
f6532111 788 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg);
605bebe2
MW		 789 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
790
f6532111 791 priv->rf = rtl8187_detect_rf(dev);
605bebe2
MW		 792
793 err = ieee80211_register_hw(dev);
794 if (err) {
795 printk(KERN_ERR "rtl8187: Cannot register device\n");
796 goto err_free_dev;
797 }
798
0795af57
JP		 799 printk(KERN_INFO "%s: hwaddr %s, rtl8187 V%d + %s\n",
800 wiphy_name(dev->wiphy), print_mac(mac, dev->wiphy->perm_addr),
f6532111 801 priv->asic_rev, priv->rf->name);
605bebe2
MW		 802
803 return 0;
804
805 err_free_dev:
806 ieee80211_free_hw(dev);
807 usb_set_intfdata(intf, NULL);
808 usb_put_dev(udev);
809 return err;
810}
811
812static void __devexit rtl8187_disconnect(struct usb_interface *intf)
813{
814 struct ieee80211_hw *dev = usb_get_intfdata(intf);
815 struct rtl8187_priv *priv;
816
817 if (!dev)
818 return;
819
820 ieee80211_unregister_hw(dev);
821
822 priv = dev->priv;
823 usb_put_dev(interface_to_usbdev(intf));
824 ieee80211_free_hw(dev);
825}
826
827static struct usb_driver rtl8187_driver = {
828 .name = KBUILD_MODNAME,
829 .id_table = rtl8187_table,
830 .probe = rtl8187_probe,
831 .disconnect = rtl8187_disconnect,
832};
833
834static int __init rtl8187_init(void)
835{
836 return usb_register(&rtl8187_driver);
837}
838
839static void __exit rtl8187_exit(void)
840{
841 usb_deregister(&rtl8187_driver);
842}
843
844module_init(rtl8187_init);
845module_exit(rtl8187_exit);