rt2x00: configure different txdesc parameters for non HT channel
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / rt2x00 / rt2x00queue.c
CommitLineData
181d6902 1/*
7e613e16
ID
2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3 Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 4 Copyright (C) 2004 - 2009 Gertjan van Wingerde <gwingerde@gmail.com>
181d6902
ID
5 <http://rt2x00.serialmonkey.com>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the
19 Free Software Foundation, Inc.,
20 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 */
22
23/*
24 Module: rt2x00lib
25 Abstract: rt2x00 queue specific routines.
26 */
27
5a0e3ad6 28#include <linux/slab.h>
181d6902
ID
29#include <linux/kernel.h>
30#include <linux/module.h>
c4da0048 31#include <linux/dma-mapping.h>
181d6902
ID
32
33#include "rt2x00.h"
34#include "rt2x00lib.h"
35
fa69560f 36struct sk_buff *rt2x00queue_alloc_rxskb(struct queue_entry *entry)
239c249d 37{
fa69560f 38 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
c4da0048
GW
39 struct sk_buff *skb;
40 struct skb_frame_desc *skbdesc;
2bb057d0
ID
41 unsigned int frame_size;
42 unsigned int head_size = 0;
43 unsigned int tail_size = 0;
239c249d
GW
44
45 /*
46 * The frame size includes descriptor size, because the
47 * hardware directly receive the frame into the skbuffer.
48 */
c4da0048 49 frame_size = entry->queue->data_size + entry->queue->desc_size;
239c249d
GW
50
51 /*
ff352391
ID
52 * The payload should be aligned to a 4-byte boundary,
53 * this means we need at least 3 bytes for moving the frame
54 * into the correct offset.
239c249d 55 */
2bb057d0
ID
56 head_size = 4;
57
58 /*
59 * For IV/EIV/ICV assembly we must make sure there is
60 * at least 8 bytes bytes available in headroom for IV/EIV
9c3444d3 61 * and 8 bytes for ICV data as tailroon.
2bb057d0 62 */
7dab73b3 63 if (test_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags)) {
2bb057d0 64 head_size += 8;
9c3444d3 65 tail_size += 8;
2bb057d0 66 }
239c249d
GW
67
68 /*
69 * Allocate skbuffer.
70 */
2bb057d0 71 skb = dev_alloc_skb(frame_size + head_size + tail_size);
239c249d
GW
72 if (!skb)
73 return NULL;
74
2bb057d0
ID
75 /*
76 * Make sure we not have a frame with the requested bytes
77 * available in the head and tail.
78 */
79 skb_reserve(skb, head_size);
239c249d
GW
80 skb_put(skb, frame_size);
81
c4da0048
GW
82 /*
83 * Populate skbdesc.
84 */
85 skbdesc = get_skb_frame_desc(skb);
86 memset(skbdesc, 0, sizeof(*skbdesc));
87 skbdesc->entry = entry;
88
7dab73b3 89 if (test_bit(REQUIRE_DMA, &rt2x00dev->cap_flags)) {
c4da0048
GW
90 skbdesc->skb_dma = dma_map_single(rt2x00dev->dev,
91 skb->data,
92 skb->len,
93 DMA_FROM_DEVICE);
94 skbdesc->flags |= SKBDESC_DMA_MAPPED_RX;
95 }
96
239c249d
GW
97 return skb;
98}
30caa6e3 99
fa69560f 100void rt2x00queue_map_txskb(struct queue_entry *entry)
30caa6e3 101{
fa69560f
ID
102 struct device *dev = entry->queue->rt2x00dev->dev;
103 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
c4da0048 104
3ee54a07 105 skbdesc->skb_dma =
fa69560f 106 dma_map_single(dev, entry->skb->data, entry->skb->len, DMA_TO_DEVICE);
c4da0048
GW
107 skbdesc->flags |= SKBDESC_DMA_MAPPED_TX;
108}
109EXPORT_SYMBOL_GPL(rt2x00queue_map_txskb);
110
fa69560f 111void rt2x00queue_unmap_skb(struct queue_entry *entry)
c4da0048 112{
fa69560f
ID
113 struct device *dev = entry->queue->rt2x00dev->dev;
114 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
c4da0048
GW
115
116 if (skbdesc->flags & SKBDESC_DMA_MAPPED_RX) {
fa69560f 117 dma_unmap_single(dev, skbdesc->skb_dma, entry->skb->len,
c4da0048
GW
118 DMA_FROM_DEVICE);
119 skbdesc->flags &= ~SKBDESC_DMA_MAPPED_RX;
546adf29 120 } else if (skbdesc->flags & SKBDESC_DMA_MAPPED_TX) {
fa69560f 121 dma_unmap_single(dev, skbdesc->skb_dma, entry->skb->len,
c4da0048
GW
122 DMA_TO_DEVICE);
123 skbdesc->flags &= ~SKBDESC_DMA_MAPPED_TX;
124 }
125}
0b8004aa 126EXPORT_SYMBOL_GPL(rt2x00queue_unmap_skb);
c4da0048 127
fa69560f 128void rt2x00queue_free_skb(struct queue_entry *entry)
c4da0048 129{
fa69560f 130 if (!entry->skb)
9a613195
ID
131 return;
132
fa69560f
ID
133 rt2x00queue_unmap_skb(entry);
134 dev_kfree_skb_any(entry->skb);
135 entry->skb = NULL;
30caa6e3 136}
239c249d 137
daee6c09 138void rt2x00queue_align_frame(struct sk_buff *skb)
9f166171 139{
9f166171 140 unsigned int frame_length = skb->len;
daee6c09 141 unsigned int align = ALIGN_SIZE(skb, 0);
9f166171
ID
142
143 if (!align)
144 return;
145
daee6c09
ID
146 skb_push(skb, align);
147 memmove(skb->data, skb->data + align, frame_length);
148 skb_trim(skb, frame_length);
149}
150
daee6c09
ID
151void rt2x00queue_insert_l2pad(struct sk_buff *skb, unsigned int header_length)
152{
2e331462 153 unsigned int payload_length = skb->len - header_length;
daee6c09
ID
154 unsigned int header_align = ALIGN_SIZE(skb, 0);
155 unsigned int payload_align = ALIGN_SIZE(skb, header_length);
e54be4e7 156 unsigned int l2pad = payload_length ? L2PAD_SIZE(header_length) : 0;
daee6c09 157
2e331462
GW
158 /*
159 * Adjust the header alignment if the payload needs to be moved more
160 * than the header.
161 */
162 if (payload_align > header_align)
163 header_align += 4;
164
165 /* There is nothing to do if no alignment is needed */
166 if (!header_align)
167 return;
daee6c09 168
2e331462
GW
169 /* Reserve the amount of space needed in front of the frame */
170 skb_push(skb, header_align);
171
172 /*
173 * Move the header.
174 */
175 memmove(skb->data, skb->data + header_align, header_length);
176
177 /* Move the payload, if present and if required */
178 if (payload_length && payload_align)
daee6c09 179 memmove(skb->data + header_length + l2pad,
a5186e99 180 skb->data + header_length + l2pad + payload_align,
2e331462
GW
181 payload_length);
182
183 /* Trim the skb to the correct size */
184 skb_trim(skb, header_length + l2pad + payload_length);
9f166171
ID
185}
186
daee6c09
ID
187void rt2x00queue_remove_l2pad(struct sk_buff *skb, unsigned int header_length)
188{
a061a93b
GW
189 /*
190 * L2 padding is only present if the skb contains more than just the
191 * IEEE 802.11 header.
192 */
193 unsigned int l2pad = (skb->len > header_length) ?
194 L2PAD_SIZE(header_length) : 0;
daee6c09 195
354e39db 196 if (!l2pad)
daee6c09
ID
197 return;
198
a061a93b
GW
199 memmove(skb->data + l2pad, skb->data, header_length);
200 skb_pull(skb, l2pad);
daee6c09
ID
201}
202
77b5621b
GW
203static void rt2x00queue_create_tx_descriptor_seq(struct rt2x00_dev *rt2x00dev,
204 struct sk_buff *skb,
7b40982e
ID
205 struct txentry_desc *txdesc)
206{
77b5621b
GW
207 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
208 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
7b40982e 209 struct rt2x00_intf *intf = vif_to_intf(tx_info->control.vif);
7b40982e 210
c262e08b 211 if (!(tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ))
7b40982e
ID
212 return;
213
7fe7ee77
HS
214 __set_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags);
215
77b5621b 216 if (!test_bit(REQUIRE_SW_SEQNO, &rt2x00dev->cap_flags))
7fe7ee77
HS
217 return;
218
7b40982e 219 /*
7fe7ee77
HS
220 * The hardware is not able to insert a sequence number. Assign a
221 * software generated one here.
7b40982e
ID
222 *
223 * This is wrong because beacons are not getting sequence
224 * numbers assigned properly.
225 *
226 * A secondary problem exists for drivers that cannot toggle
227 * sequence counting per-frame, since those will override the
228 * sequence counter given by mac80211.
229 */
798eefde 230 spin_lock(&intf->seqlock);
7b40982e
ID
231
232 if (test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags))
233 intf->seqno += 0x10;
234 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
235 hdr->seq_ctrl |= cpu_to_le16(intf->seqno);
236
798eefde 237 spin_unlock(&intf->seqlock);
7b40982e 238
7b40982e
ID
239}
240
77b5621b
GW
241static void rt2x00queue_create_tx_descriptor_plcp(struct rt2x00_dev *rt2x00dev,
242 struct sk_buff *skb,
7b40982e
ID
243 struct txentry_desc *txdesc,
244 const struct rt2x00_rate *hwrate)
245{
77b5621b 246 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
7b40982e
ID
247 struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0];
248 unsigned int data_length;
249 unsigned int duration;
250 unsigned int residual;
251
2517794b
HS
252 /*
253 * Determine with what IFS priority this frame should be send.
254 * Set ifs to IFS_SIFS when the this is not the first fragment,
255 * or this fragment came after RTS/CTS.
256 */
257 if (test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags))
258 txdesc->u.plcp.ifs = IFS_BACKOFF;
259 else
260 txdesc->u.plcp.ifs = IFS_SIFS;
261
7b40982e 262 /* Data length + CRC + Crypto overhead (IV/EIV/ICV/MIC) */
77b5621b
GW
263 data_length = skb->len + 4;
264 data_length += rt2x00crypto_tx_overhead(rt2x00dev, skb);
7b40982e
ID
265
266 /*
267 * PLCP setup
268 * Length calculation depends on OFDM/CCK rate.
269 */
26a1d07f
HS
270 txdesc->u.plcp.signal = hwrate->plcp;
271 txdesc->u.plcp.service = 0x04;
7b40982e
ID
272
273 if (hwrate->flags & DEV_RATE_OFDM) {
26a1d07f
HS
274 txdesc->u.plcp.length_high = (data_length >> 6) & 0x3f;
275 txdesc->u.plcp.length_low = data_length & 0x3f;
7b40982e
ID
276 } else {
277 /*
278 * Convert length to microseconds.
279 */
280 residual = GET_DURATION_RES(data_length, hwrate->bitrate);
281 duration = GET_DURATION(data_length, hwrate->bitrate);
282
283 if (residual != 0) {
284 duration++;
285
286 /*
287 * Check if we need to set the Length Extension
288 */
289 if (hwrate->bitrate == 110 && residual <= 30)
26a1d07f 290 txdesc->u.plcp.service |= 0x80;
7b40982e
ID
291 }
292
26a1d07f
HS
293 txdesc->u.plcp.length_high = (duration >> 8) & 0xff;
294 txdesc->u.plcp.length_low = duration & 0xff;
7b40982e
ID
295
296 /*
297 * When preamble is enabled we should set the
298 * preamble bit for the signal.
299 */
300 if (txrate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
26a1d07f 301 txdesc->u.plcp.signal |= 0x08;
7b40982e
ID
302 }
303}
304
77b5621b
GW
305static void rt2x00queue_create_tx_descriptor_ht(struct rt2x00_dev *rt2x00dev,
306 struct sk_buff *skb,
46a01ec0
GW
307 struct txentry_desc *txdesc,
308 const struct rt2x00_rate *hwrate)
309{
77b5621b 310 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
46a01ec0 311 struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0];
77b5621b 312 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
ead2bb64 313 struct rt2x00_sta *sta_priv = NULL;
46a01ec0 314
ead2bb64 315 if (tx_info->control.sta) {
46a01ec0
GW
316 txdesc->u.ht.mpdu_density =
317 tx_info->control.sta->ht_cap.ampdu_density;
318
ead2bb64
HS
319 sta_priv = sta_to_rt2x00_sta(tx_info->control.sta);
320 txdesc->u.ht.wcid = sta_priv->wcid;
321 }
322
46a01ec0
GW
323 /*
324 * If IEEE80211_TX_RC_MCS is set txrate->idx just contains the
325 * mcs rate to be used
326 */
327 if (txrate->flags & IEEE80211_TX_RC_MCS) {
328 txdesc->u.ht.mcs = txrate->idx;
329
330 /*
331 * MIMO PS should be set to 1 for STA's using dynamic SM PS
332 * when using more then one tx stream (>MCS7).
333 */
334 if (tx_info->control.sta && txdesc->u.ht.mcs > 7 &&
335 ((tx_info->control.sta->ht_cap.cap &
336 IEEE80211_HT_CAP_SM_PS) >>
337 IEEE80211_HT_CAP_SM_PS_SHIFT) ==
338 WLAN_HT_CAP_SM_PS_DYNAMIC)
339 __set_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags);
340 } else {
341 txdesc->u.ht.mcs = rt2x00_get_rate_mcs(hwrate->mcs);
342 if (txrate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
343 txdesc->u.ht.mcs |= 0x08;
344 }
345
da40f407
SG
346 if (test_bit(CONFIG_HT_DISABLED, &rt2x00dev->flags)) {
347 if (!(tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT))
348 txdesc->u.ht.txop = TXOP_SIFS;
349 else
350 txdesc->u.ht.txop = TXOP_BACKOFF;
351
352 /* Left zero on all other settings. */
353 return;
354 }
355
356 txdesc->u.ht.ba_size = 7; /* FIXME: What value is needed? */
357
358 /*
359 * Only one STBC stream is supported for now.
360 */
361 if (tx_info->flags & IEEE80211_TX_CTL_STBC)
362 txdesc->u.ht.stbc = 1;
363
46a01ec0
GW
364 /*
365 * This frame is eligible for an AMPDU, however, don't aggregate
366 * frames that are intended to probe a specific tx rate.
367 */
368 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU &&
369 !(tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE))
370 __set_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags);
371
372 /*
373 * Set 40Mhz mode if necessary (for legacy rates this will
374 * duplicate the frame to both channels).
375 */
376 if (txrate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH ||
377 txrate->flags & IEEE80211_TX_RC_DUP_DATA)
378 __set_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags);
379 if (txrate->flags & IEEE80211_TX_RC_SHORT_GI)
380 __set_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags);
381
382 /*
383 * Determine IFS values
384 * - Use TXOP_BACKOFF for management frames except beacons
385 * - Use TXOP_SIFS for fragment bursts
386 * - Use TXOP_HTTXOP for everything else
387 *
388 * Note: rt2800 devices won't use CTS protection (if used)
389 * for frames not transmitted with TXOP_HTTXOP
390 */
391 if (ieee80211_is_mgmt(hdr->frame_control) &&
392 !ieee80211_is_beacon(hdr->frame_control))
393 txdesc->u.ht.txop = TXOP_BACKOFF;
394 else if (!(tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT))
395 txdesc->u.ht.txop = TXOP_SIFS;
396 else
397 txdesc->u.ht.txop = TXOP_HTTXOP;
398}
399
77b5621b
GW
400static void rt2x00queue_create_tx_descriptor(struct rt2x00_dev *rt2x00dev,
401 struct sk_buff *skb,
bd88a781 402 struct txentry_desc *txdesc)
7050ec82 403{
77b5621b
GW
404 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
405 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
55b585e2
HS
406 struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0];
407 struct ieee80211_rate *rate;
408 const struct rt2x00_rate *hwrate = NULL;
7050ec82
ID
409
410 memset(txdesc, 0, sizeof(*txdesc));
411
9f166171 412 /*
df624ca5 413 * Header and frame information.
9f166171 414 */
77b5621b
GW
415 txdesc->length = skb->len;
416 txdesc->header_length = ieee80211_get_hdrlen_from_skb(skb);
9f166171 417
7050ec82
ID
418 /*
419 * Check whether this frame is to be acked.
420 */
e039fa4a 421 if (!(tx_info->flags & IEEE80211_TX_CTL_NO_ACK))
7050ec82
ID
422 __set_bit(ENTRY_TXD_ACK, &txdesc->flags);
423
424 /*
425 * Check if this is a RTS/CTS frame
426 */
ac104462
ID
427 if (ieee80211_is_rts(hdr->frame_control) ||
428 ieee80211_is_cts(hdr->frame_control)) {
7050ec82 429 __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
ac104462 430 if (ieee80211_is_rts(hdr->frame_control))
7050ec82 431 __set_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags);
e039fa4a 432 else
7050ec82 433 __set_bit(ENTRY_TXD_CTS_FRAME, &txdesc->flags);
e039fa4a 434 if (tx_info->control.rts_cts_rate_idx >= 0)
2e92e6f2 435 rate =
e039fa4a 436 ieee80211_get_rts_cts_rate(rt2x00dev->hw, tx_info);
7050ec82
ID
437 }
438
439 /*
440 * Determine retry information.
441 */
e6a9854b 442 txdesc->retry_limit = tx_info->control.rates[0].count - 1;
42c82857 443 if (txdesc->retry_limit >= rt2x00dev->long_retry)
7050ec82
ID
444 __set_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags);
445
446 /*
447 * Check if more fragments are pending
448 */
2606e422 449 if (ieee80211_has_morefrags(hdr->frame_control)) {
7050ec82
ID
450 __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
451 __set_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags);
452 }
453
2606e422
HS
454 /*
455 * Check if more frames (!= fragments) are pending
456 */
457 if (tx_info->flags & IEEE80211_TX_CTL_MORE_FRAMES)
458 __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
459
7050ec82
ID
460 /*
461 * Beacons and probe responses require the tsf timestamp
1bce85cf 462 * to be inserted into the frame.
7050ec82 463 */
1bce85cf
HS
464 if (ieee80211_is_beacon(hdr->frame_control) ||
465 ieee80211_is_probe_resp(hdr->frame_control))
7050ec82
ID
466 __set_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags);
467
7b40982e 468 if ((tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) &&
2517794b 469 !test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags))
7050ec82 470 __set_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags);
7050ec82 471
076f9582
ID
472 /*
473 * Determine rate modulation.
474 */
55b585e2
HS
475 if (txrate->flags & IEEE80211_TX_RC_GREEN_FIELD)
476 txdesc->rate_mode = RATE_MODE_HT_GREENFIELD;
477 else if (txrate->flags & IEEE80211_TX_RC_MCS)
478 txdesc->rate_mode = RATE_MODE_HT_MIX;
479 else {
480 rate = ieee80211_get_tx_rate(rt2x00dev->hw, tx_info);
481 hwrate = rt2x00_get_rate(rate->hw_value);
482 if (hwrate->flags & DEV_RATE_OFDM)
483 txdesc->rate_mode = RATE_MODE_OFDM;
484 else
485 txdesc->rate_mode = RATE_MODE_CCK;
486 }
7050ec82 487
7b40982e
ID
488 /*
489 * Apply TX descriptor handling by components
490 */
77b5621b
GW
491 rt2x00crypto_create_tx_descriptor(rt2x00dev, skb, txdesc);
492 rt2x00queue_create_tx_descriptor_seq(rt2x00dev, skb, txdesc);
26a1d07f 493
7dab73b3 494 if (test_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags))
77b5621b
GW
495 rt2x00queue_create_tx_descriptor_ht(rt2x00dev, skb, txdesc,
496 hwrate);
26a1d07f 497 else
77b5621b
GW
498 rt2x00queue_create_tx_descriptor_plcp(rt2x00dev, skb, txdesc,
499 hwrate);
7050ec82 500}
7050ec82 501
78eea11b
GW
502static int rt2x00queue_write_tx_data(struct queue_entry *entry,
503 struct txentry_desc *txdesc)
504{
505 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
506
507 /*
508 * This should not happen, we already checked the entry
509 * was ours. When the hardware disagrees there has been
510 * a queue corruption!
511 */
512 if (unlikely(rt2x00dev->ops->lib->get_entry_state &&
513 rt2x00dev->ops->lib->get_entry_state(entry))) {
514 ERROR(rt2x00dev,
515 "Corrupt queue %d, accessing entry which is not ours.\n"
516 "Please file bug report to %s.\n",
517 entry->queue->qid, DRV_PROJECT);
518 return -EINVAL;
519 }
520
521 /*
522 * Add the requested extra tx headroom in front of the skb.
523 */
524 skb_push(entry->skb, rt2x00dev->ops->extra_tx_headroom);
525 memset(entry->skb->data, 0, rt2x00dev->ops->extra_tx_headroom);
526
527 /*
76dd5ddf 528 * Call the driver's write_tx_data function, if it exists.
78eea11b 529 */
76dd5ddf
GW
530 if (rt2x00dev->ops->lib->write_tx_data)
531 rt2x00dev->ops->lib->write_tx_data(entry, txdesc);
78eea11b
GW
532
533 /*
534 * Map the skb to DMA.
535 */
7dab73b3 536 if (test_bit(REQUIRE_DMA, &rt2x00dev->cap_flags))
fa69560f 537 rt2x00queue_map_txskb(entry);
78eea11b
GW
538
539 return 0;
540}
541
bd88a781
ID
542static void rt2x00queue_write_tx_descriptor(struct queue_entry *entry,
543 struct txentry_desc *txdesc)
7050ec82 544{
b869767b 545 struct data_queue *queue = entry->queue;
7050ec82 546
93331458 547 queue->rt2x00dev->ops->lib->write_tx_desc(entry, txdesc);
7050ec82
ID
548
549 /*
550 * All processing on the frame has been completed, this means
551 * it is now ready to be dumped to userspace through debugfs.
552 */
93331458 553 rt2x00debug_dump_frame(queue->rt2x00dev, DUMP_FRAME_TX, entry->skb);
6295d815
GW
554}
555
8be4eed0 556static void rt2x00queue_kick_tx_queue(struct data_queue *queue,
6295d815
GW
557 struct txentry_desc *txdesc)
558{
7050ec82 559 /*
b869767b 560 * Check if we need to kick the queue, there are however a few rules
6295d815 561 * 1) Don't kick unless this is the last in frame in a burst.
b869767b
ID
562 * When the burst flag is set, this frame is always followed
563 * by another frame which in some way are related to eachother.
564 * This is true for fragments, RTS or CTS-to-self frames.
6295d815 565 * 2) Rule 1 can be broken when the available entries
b869767b 566 * in the queue are less then a certain threshold.
7050ec82 567 */
b869767b
ID
568 if (rt2x00queue_threshold(queue) ||
569 !test_bit(ENTRY_TXD_BURST, &txdesc->flags))
dbba306f 570 queue->rt2x00dev->ops->lib->kick_queue(queue);
7050ec82 571}
7050ec82 572
7351c6bd
JB
573int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb,
574 bool local)
6db3786a 575{
e6a9854b 576 struct ieee80211_tx_info *tx_info;
77a861c4 577 struct queue_entry *entry;
6db3786a 578 struct txentry_desc txdesc;
d74f5ba4 579 struct skb_frame_desc *skbdesc;
e6a9854b 580 u8 rate_idx, rate_flags;
77a861c4
GW
581 int ret = 0;
582
6db3786a
ID
583 /*
584 * Copy all TX descriptor information into txdesc,
585 * after that we are free to use the skb->cb array
586 * for our information.
587 */
77b5621b 588 rt2x00queue_create_tx_descriptor(queue->rt2x00dev, skb, &txdesc);
6db3786a 589
d74f5ba4 590 /*
e6a9854b 591 * All information is retrieved from the skb->cb array,
2bb057d0 592 * now we should claim ownership of the driver part of that
e6a9854b 593 * array, preserving the bitrate index and flags.
d74f5ba4 594 */
e6a9854b
JB
595 tx_info = IEEE80211_SKB_CB(skb);
596 rate_idx = tx_info->control.rates[0].idx;
597 rate_flags = tx_info->control.rates[0].flags;
0e3de998 598 skbdesc = get_skb_frame_desc(skb);
d74f5ba4 599 memset(skbdesc, 0, sizeof(*skbdesc));
e6a9854b
JB
600 skbdesc->tx_rate_idx = rate_idx;
601 skbdesc->tx_rate_flags = rate_flags;
d74f5ba4 602
7351c6bd
JB
603 if (local)
604 skbdesc->flags |= SKBDESC_NOT_MAC80211;
605
2bb057d0
ID
606 /*
607 * When hardware encryption is supported, and this frame
608 * is to be encrypted, we should strip the IV/EIV data from
3ad2f3fb 609 * the frame so we can provide it to the driver separately.
2bb057d0
ID
610 */
611 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc.flags) &&
dddfb478 612 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc.flags)) {
7dab73b3 613 if (test_bit(REQUIRE_COPY_IV, &queue->rt2x00dev->cap_flags))
9eb4e21e 614 rt2x00crypto_tx_copy_iv(skb, &txdesc);
dddfb478 615 else
9eb4e21e 616 rt2x00crypto_tx_remove_iv(skb, &txdesc);
dddfb478 617 }
2bb057d0 618
93354cbb 619 /*
25985edc 620 * When DMA allocation is required we should guarantee to the
93354cbb 621 * driver that the DMA is aligned to a 4-byte boundary.
93354cbb
ID
622 * However some drivers require L2 padding to pad the payload
623 * rather then the header. This could be a requirement for
624 * PCI and USB devices, while header alignment only is valid
625 * for PCI devices.
626 */
7dab73b3 627 if (test_bit(REQUIRE_L2PAD, &queue->rt2x00dev->cap_flags))
128f8f77 628 rt2x00queue_insert_l2pad(skb, txdesc.header_length);
7dab73b3 629 else if (test_bit(REQUIRE_DMA, &queue->rt2x00dev->cap_flags))
128f8f77
GW
630 rt2x00queue_align_frame(skb);
631
3780d038
SG
632 /*
633 * That function must be called with bh disabled.
634 */
128f8f77
GW
635 spin_lock(&queue->tx_lock);
636
637 if (unlikely(rt2x00queue_full(queue))) {
638 ERROR(queue->rt2x00dev,
639 "Dropping frame due to full tx queue %d.\n", queue->qid);
640 ret = -ENOBUFS;
641 goto out;
642 }
643
644 entry = rt2x00queue_get_entry(queue, Q_INDEX);
645
646 if (unlikely(test_and_set_bit(ENTRY_OWNER_DEVICE_DATA,
647 &entry->flags))) {
648 ERROR(queue->rt2x00dev,
649 "Arrived at non-free entry in the non-full queue %d.\n"
650 "Please file bug report to %s.\n",
651 queue->qid, DRV_PROJECT);
652 ret = -EINVAL;
653 goto out;
654 }
655
656 skbdesc->entry = entry;
657 entry->skb = skb;
9f166171 658
2bb057d0
ID
659 /*
660 * It could be possible that the queue was corrupted and this
0e3de998
ID
661 * call failed. Since we always return NETDEV_TX_OK to mac80211,
662 * this frame will simply be dropped.
2bb057d0 663 */
78eea11b 664 if (unlikely(rt2x00queue_write_tx_data(entry, &txdesc))) {
0262ab0d 665 clear_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags);
2bb057d0 666 entry->skb = NULL;
77a861c4
GW
667 ret = -EIO;
668 goto out;
6db3786a
ID
669 }
670
0262ab0d 671 set_bit(ENTRY_DATA_PENDING, &entry->flags);
6db3786a 672
75256f03 673 rt2x00queue_index_inc(entry, Q_INDEX);
6db3786a 674 rt2x00queue_write_tx_descriptor(entry, &txdesc);
8be4eed0 675 rt2x00queue_kick_tx_queue(queue, &txdesc);
6db3786a 676
77a861c4
GW
677out:
678 spin_unlock(&queue->tx_lock);
679 return ret;
6db3786a
ID
680}
681
69cf36a4
HS
682int rt2x00queue_clear_beacon(struct rt2x00_dev *rt2x00dev,
683 struct ieee80211_vif *vif)
684{
685 struct rt2x00_intf *intf = vif_to_intf(vif);
686
687 if (unlikely(!intf->beacon))
688 return -ENOBUFS;
689
690 mutex_lock(&intf->beacon_skb_mutex);
691
692 /*
693 * Clean up the beacon skb.
694 */
695 rt2x00queue_free_skb(intf->beacon);
696
697 /*
698 * Clear beacon (single bssid devices don't need to clear the beacon
699 * since the beacon queue will get stopped anyway).
700 */
701 if (rt2x00dev->ops->lib->clear_beacon)
702 rt2x00dev->ops->lib->clear_beacon(intf->beacon);
703
704 mutex_unlock(&intf->beacon_skb_mutex);
705
706 return 0;
707}
708
8414ff07
HS
709int rt2x00queue_update_beacon_locked(struct rt2x00_dev *rt2x00dev,
710 struct ieee80211_vif *vif)
bd88a781
ID
711{
712 struct rt2x00_intf *intf = vif_to_intf(vif);
713 struct skb_frame_desc *skbdesc;
714 struct txentry_desc txdesc;
bd88a781
ID
715
716 if (unlikely(!intf->beacon))
717 return -ENOBUFS;
718
17512dc3
IP
719 /*
720 * Clean up the beacon skb.
721 */
fa69560f 722 rt2x00queue_free_skb(intf->beacon);
17512dc3 723
bd88a781 724 intf->beacon->skb = ieee80211_beacon_get(rt2x00dev->hw, vif);
8414ff07 725 if (!intf->beacon->skb)
bd88a781
ID
726 return -ENOMEM;
727
728 /*
729 * Copy all TX descriptor information into txdesc,
730 * after that we are free to use the skb->cb array
731 * for our information.
732 */
77b5621b 733 rt2x00queue_create_tx_descriptor(rt2x00dev, intf->beacon->skb, &txdesc);
bd88a781 734
bd88a781
ID
735 /*
736 * Fill in skb descriptor
737 */
738 skbdesc = get_skb_frame_desc(intf->beacon->skb);
739 memset(skbdesc, 0, sizeof(*skbdesc));
bd88a781
ID
740 skbdesc->entry = intf->beacon;
741
bd88a781 742 /*
69cf36a4 743 * Send beacon to hardware.
bd88a781 744 */
f224f4ef 745 rt2x00dev->ops->lib->write_beacon(intf->beacon, &txdesc);
bd88a781 746
8414ff07
HS
747 return 0;
748
749}
750
751int rt2x00queue_update_beacon(struct rt2x00_dev *rt2x00dev,
752 struct ieee80211_vif *vif)
753{
754 struct rt2x00_intf *intf = vif_to_intf(vif);
755 int ret;
756
757 mutex_lock(&intf->beacon_skb_mutex);
758 ret = rt2x00queue_update_beacon_locked(rt2x00dev, vif);
17512dc3
IP
759 mutex_unlock(&intf->beacon_skb_mutex);
760
8414ff07 761 return ret;
bd88a781
ID
762}
763
10e11568 764bool rt2x00queue_for_each_entry(struct data_queue *queue,
5eb7efe8
ID
765 enum queue_index start,
766 enum queue_index end,
10e11568
HS
767 void *data,
768 bool (*fn)(struct queue_entry *entry,
769 void *data))
5eb7efe8
ID
770{
771 unsigned long irqflags;
772 unsigned int index_start;
773 unsigned int index_end;
774 unsigned int i;
775
776 if (unlikely(start >= Q_INDEX_MAX || end >= Q_INDEX_MAX)) {
777 ERROR(queue->rt2x00dev,
778 "Entry requested from invalid index range (%d - %d)\n",
779 start, end);
10e11568 780 return true;
5eb7efe8
ID
781 }
782
783 /*
784 * Only protect the range we are going to loop over,
785 * if during our loop a extra entry is set to pending
786 * it should not be kicked during this run, since it
787 * is part of another TX operation.
788 */
813f0339 789 spin_lock_irqsave(&queue->index_lock, irqflags);
5eb7efe8
ID
790 index_start = queue->index[start];
791 index_end = queue->index[end];
813f0339 792 spin_unlock_irqrestore(&queue->index_lock, irqflags);
5eb7efe8
ID
793
794 /*
25985edc 795 * Start from the TX done pointer, this guarantees that we will
5eb7efe8
ID
796 * send out all frames in the correct order.
797 */
798 if (index_start < index_end) {
10e11568
HS
799 for (i = index_start; i < index_end; i++) {
800 if (fn(&queue->entries[i], data))
801 return true;
802 }
5eb7efe8 803 } else {
10e11568
HS
804 for (i = index_start; i < queue->limit; i++) {
805 if (fn(&queue->entries[i], data))
806 return true;
807 }
5eb7efe8 808
10e11568
HS
809 for (i = 0; i < index_end; i++) {
810 if (fn(&queue->entries[i], data))
811 return true;
812 }
5eb7efe8 813 }
10e11568
HS
814
815 return false;
5eb7efe8
ID
816}
817EXPORT_SYMBOL_GPL(rt2x00queue_for_each_entry);
818
181d6902
ID
819struct queue_entry *rt2x00queue_get_entry(struct data_queue *queue,
820 enum queue_index index)
821{
822 struct queue_entry *entry;
5f46c4d0 823 unsigned long irqflags;
181d6902
ID
824
825 if (unlikely(index >= Q_INDEX_MAX)) {
826 ERROR(queue->rt2x00dev,
827 "Entry requested from invalid index type (%d)\n", index);
828 return NULL;
829 }
830
813f0339 831 spin_lock_irqsave(&queue->index_lock, irqflags);
181d6902
ID
832
833 entry = &queue->entries[queue->index[index]];
834
813f0339 835 spin_unlock_irqrestore(&queue->index_lock, irqflags);
181d6902
ID
836
837 return entry;
838}
839EXPORT_SYMBOL_GPL(rt2x00queue_get_entry);
840
75256f03 841void rt2x00queue_index_inc(struct queue_entry *entry, enum queue_index index)
181d6902 842{
75256f03 843 struct data_queue *queue = entry->queue;
5f46c4d0
ID
844 unsigned long irqflags;
845
181d6902
ID
846 if (unlikely(index >= Q_INDEX_MAX)) {
847 ERROR(queue->rt2x00dev,
848 "Index change on invalid index type (%d)\n", index);
849 return;
850 }
851
813f0339 852 spin_lock_irqsave(&queue->index_lock, irqflags);
181d6902
ID
853
854 queue->index[index]++;
855 if (queue->index[index] >= queue->limit)
856 queue->index[index] = 0;
857
75256f03 858 entry->last_action = jiffies;
652a9dd2 859
10b6b801
ID
860 if (index == Q_INDEX) {
861 queue->length++;
862 } else if (index == Q_INDEX_DONE) {
863 queue->length--;
55887511 864 queue->count++;
10b6b801 865 }
181d6902 866
813f0339 867 spin_unlock_irqrestore(&queue->index_lock, irqflags);
181d6902 868}
181d6902 869
0b7fde54
ID
870void rt2x00queue_pause_queue(struct data_queue *queue)
871{
872 if (!test_bit(DEVICE_STATE_PRESENT, &queue->rt2x00dev->flags) ||
873 !test_bit(QUEUE_STARTED, &queue->flags) ||
874 test_and_set_bit(QUEUE_PAUSED, &queue->flags))
875 return;
876
877 switch (queue->qid) {
f615e9a3
ID
878 case QID_AC_VO:
879 case QID_AC_VI:
0b7fde54
ID
880 case QID_AC_BE:
881 case QID_AC_BK:
0b7fde54
ID
882 /*
883 * For TX queues, we have to disable the queue
884 * inside mac80211.
885 */
886 ieee80211_stop_queue(queue->rt2x00dev->hw, queue->qid);
887 break;
888 default:
889 break;
890 }
891}
892EXPORT_SYMBOL_GPL(rt2x00queue_pause_queue);
893
894void rt2x00queue_unpause_queue(struct data_queue *queue)
895{
896 if (!test_bit(DEVICE_STATE_PRESENT, &queue->rt2x00dev->flags) ||
897 !test_bit(QUEUE_STARTED, &queue->flags) ||
898 !test_and_clear_bit(QUEUE_PAUSED, &queue->flags))
899 return;
900
901 switch (queue->qid) {
f615e9a3
ID
902 case QID_AC_VO:
903 case QID_AC_VI:
0b7fde54
ID
904 case QID_AC_BE:
905 case QID_AC_BK:
0b7fde54
ID
906 /*
907 * For TX queues, we have to enable the queue
908 * inside mac80211.
909 */
910 ieee80211_wake_queue(queue->rt2x00dev->hw, queue->qid);
911 break;
5be65609
ID
912 case QID_RX:
913 /*
914 * For RX we need to kick the queue now in order to
915 * receive frames.
916 */
917 queue->rt2x00dev->ops->lib->kick_queue(queue);
0b7fde54
ID
918 default:
919 break;
920 }
921}
922EXPORT_SYMBOL_GPL(rt2x00queue_unpause_queue);
923
924void rt2x00queue_start_queue(struct data_queue *queue)
925{
926 mutex_lock(&queue->status_lock);
927
928 if (!test_bit(DEVICE_STATE_PRESENT, &queue->rt2x00dev->flags) ||
929 test_and_set_bit(QUEUE_STARTED, &queue->flags)) {
930 mutex_unlock(&queue->status_lock);
931 return;
932 }
933
934 set_bit(QUEUE_PAUSED, &queue->flags);
935
936 queue->rt2x00dev->ops->lib->start_queue(queue);
937
938 rt2x00queue_unpause_queue(queue);
939
940 mutex_unlock(&queue->status_lock);
941}
942EXPORT_SYMBOL_GPL(rt2x00queue_start_queue);
943
944void rt2x00queue_stop_queue(struct data_queue *queue)
945{
946 mutex_lock(&queue->status_lock);
947
948 if (!test_and_clear_bit(QUEUE_STARTED, &queue->flags)) {
949 mutex_unlock(&queue->status_lock);
950 return;
951 }
952
953 rt2x00queue_pause_queue(queue);
954
955 queue->rt2x00dev->ops->lib->stop_queue(queue);
956
957 mutex_unlock(&queue->status_lock);
958}
959EXPORT_SYMBOL_GPL(rt2x00queue_stop_queue);
960
5be65609
ID
961void rt2x00queue_flush_queue(struct data_queue *queue, bool drop)
962{
5be65609
ID
963 bool started;
964 bool tx_queue =
f615e9a3 965 (queue->qid == QID_AC_VO) ||
5be65609 966 (queue->qid == QID_AC_VI) ||
f615e9a3
ID
967 (queue->qid == QID_AC_BE) ||
968 (queue->qid == QID_AC_BK);
5be65609
ID
969
970 mutex_lock(&queue->status_lock);
971
972 /*
973 * If the queue has been started, we must stop it temporarily
974 * to prevent any new frames to be queued on the device. If
975 * we are not dropping the pending frames, the queue must
976 * only be stopped in the software and not the hardware,
977 * otherwise the queue will never become empty on its own.
978 */
979 started = test_bit(QUEUE_STARTED, &queue->flags);
980 if (started) {
981 /*
982 * Pause the queue
983 */
984 rt2x00queue_pause_queue(queue);
985
986 /*
987 * If we are not supposed to drop any pending
988 * frames, this means we must force a start (=kick)
989 * to the queue to make sure the hardware will
990 * start transmitting.
991 */
992 if (!drop && tx_queue)
993 queue->rt2x00dev->ops->lib->kick_queue(queue);
994 }
995
996 /*
152a5992
ID
997 * Check if driver supports flushing, if that is the case we can
998 * defer the flushing to the driver. Otherwise we must use the
999 * alternative which just waits for the queue to become empty.
5be65609 1000 */
152a5992
ID
1001 if (likely(queue->rt2x00dev->ops->lib->flush_queue))
1002 queue->rt2x00dev->ops->lib->flush_queue(queue, drop);
5be65609
ID
1003
1004 /*
1005 * The queue flush has failed...
1006 */
1007 if (unlikely(!rt2x00queue_empty(queue)))
21957c31 1008 WARNING(queue->rt2x00dev, "Queue %d failed to flush\n", queue->qid);
5be65609
ID
1009
1010 /*
1011 * Restore the queue to the previous status
1012 */
1013 if (started)
1014 rt2x00queue_unpause_queue(queue);
1015
1016 mutex_unlock(&queue->status_lock);
1017}
1018EXPORT_SYMBOL_GPL(rt2x00queue_flush_queue);
1019
0b7fde54
ID
1020void rt2x00queue_start_queues(struct rt2x00_dev *rt2x00dev)
1021{
1022 struct data_queue *queue;
1023
1024 /*
1025 * rt2x00queue_start_queue will call ieee80211_wake_queue
1026 * for each queue after is has been properly initialized.
1027 */
1028 tx_queue_for_each(rt2x00dev, queue)
1029 rt2x00queue_start_queue(queue);
1030
1031 rt2x00queue_start_queue(rt2x00dev->rx);
1032}
1033EXPORT_SYMBOL_GPL(rt2x00queue_start_queues);
1034
1035void rt2x00queue_stop_queues(struct rt2x00_dev *rt2x00dev)
1036{
1037 struct data_queue *queue;
1038
1039 /*
1040 * rt2x00queue_stop_queue will call ieee80211_stop_queue
1041 * as well, but we are completely shutting doing everything
1042 * now, so it is much safer to stop all TX queues at once,
1043 * and use rt2x00queue_stop_queue for cleaning up.
1044 */
1045 ieee80211_stop_queues(rt2x00dev->hw);
1046
1047 tx_queue_for_each(rt2x00dev, queue)
1048 rt2x00queue_stop_queue(queue);
1049
1050 rt2x00queue_stop_queue(rt2x00dev->rx);
1051}
1052EXPORT_SYMBOL_GPL(rt2x00queue_stop_queues);
1053
5be65609
ID
1054void rt2x00queue_flush_queues(struct rt2x00_dev *rt2x00dev, bool drop)
1055{
1056 struct data_queue *queue;
1057
1058 tx_queue_for_each(rt2x00dev, queue)
1059 rt2x00queue_flush_queue(queue, drop);
1060
1061 rt2x00queue_flush_queue(rt2x00dev->rx, drop);
1062}
1063EXPORT_SYMBOL_GPL(rt2x00queue_flush_queues);
1064
181d6902
ID
1065static void rt2x00queue_reset(struct data_queue *queue)
1066{
5f46c4d0 1067 unsigned long irqflags;
652a9dd2 1068 unsigned int i;
5f46c4d0 1069
813f0339 1070 spin_lock_irqsave(&queue->index_lock, irqflags);
181d6902
ID
1071
1072 queue->count = 0;
1073 queue->length = 0;
652a9dd2 1074
75256f03 1075 for (i = 0; i < Q_INDEX_MAX; i++)
652a9dd2 1076 queue->index[i] = 0;
181d6902 1077
813f0339 1078 spin_unlock_irqrestore(&queue->index_lock, irqflags);
181d6902
ID
1079}
1080
798b7adb 1081void rt2x00queue_init_queues(struct rt2x00_dev *rt2x00dev)
181d6902
ID
1082{
1083 struct data_queue *queue;
1084 unsigned int i;
1085
798b7adb 1086 queue_for_each(rt2x00dev, queue) {
181d6902
ID
1087 rt2x00queue_reset(queue);
1088
64e7d723 1089 for (i = 0; i < queue->limit; i++)
798b7adb 1090 rt2x00dev->ops->lib->clear_entry(&queue->entries[i]);
181d6902
ID
1091 }
1092}
1093
1094static int rt2x00queue_alloc_entries(struct data_queue *queue,
1095 const struct data_queue_desc *qdesc)
1096{
1097 struct queue_entry *entries;
1098 unsigned int entry_size;
1099 unsigned int i;
1100
1101 rt2x00queue_reset(queue);
1102
1103 queue->limit = qdesc->entry_num;
b869767b 1104 queue->threshold = DIV_ROUND_UP(qdesc->entry_num, 10);
181d6902
ID
1105 queue->data_size = qdesc->data_size;
1106 queue->desc_size = qdesc->desc_size;
1107
1108 /*
1109 * Allocate all queue entries.
1110 */
1111 entry_size = sizeof(*entries) + qdesc->priv_size;
baeb2ffa 1112 entries = kcalloc(queue->limit, entry_size, GFP_KERNEL);
181d6902
ID
1113 if (!entries)
1114 return -ENOMEM;
1115
1116#define QUEUE_ENTRY_PRIV_OFFSET(__base, __index, __limit, __esize, __psize) \
f8bfbc31
ME
1117 (((char *)(__base)) + ((__limit) * (__esize)) + \
1118 ((__index) * (__psize)))
181d6902
ID
1119
1120 for (i = 0; i < queue->limit; i++) {
1121 entries[i].flags = 0;
1122 entries[i].queue = queue;
1123 entries[i].skb = NULL;
1124 entries[i].entry_idx = i;
1125 entries[i].priv_data =
1126 QUEUE_ENTRY_PRIV_OFFSET(entries, i, queue->limit,
1127 sizeof(*entries), qdesc->priv_size);
1128 }
1129
1130#undef QUEUE_ENTRY_PRIV_OFFSET
1131
1132 queue->entries = entries;
1133
1134 return 0;
1135}
1136
fa69560f 1137static void rt2x00queue_free_skbs(struct data_queue *queue)
30caa6e3
GW
1138{
1139 unsigned int i;
1140
1141 if (!queue->entries)
1142 return;
1143
1144 for (i = 0; i < queue->limit; i++) {
fa69560f 1145 rt2x00queue_free_skb(&queue->entries[i]);
30caa6e3
GW
1146 }
1147}
1148
fa69560f 1149static int rt2x00queue_alloc_rxskbs(struct data_queue *queue)
30caa6e3
GW
1150{
1151 unsigned int i;
1152 struct sk_buff *skb;
1153
1154 for (i = 0; i < queue->limit; i++) {
fa69560f 1155 skb = rt2x00queue_alloc_rxskb(&queue->entries[i]);
30caa6e3 1156 if (!skb)
61243d8e 1157 return -ENOMEM;
30caa6e3
GW
1158 queue->entries[i].skb = skb;
1159 }
1160
1161 return 0;
30caa6e3
GW
1162}
1163
181d6902
ID
1164int rt2x00queue_initialize(struct rt2x00_dev *rt2x00dev)
1165{
1166 struct data_queue *queue;
1167 int status;
1168
181d6902
ID
1169 status = rt2x00queue_alloc_entries(rt2x00dev->rx, rt2x00dev->ops->rx);
1170 if (status)
1171 goto exit;
1172
1173 tx_queue_for_each(rt2x00dev, queue) {
1174 status = rt2x00queue_alloc_entries(queue, rt2x00dev->ops->tx);
1175 if (status)
1176 goto exit;
1177 }
1178
1179 status = rt2x00queue_alloc_entries(rt2x00dev->bcn, rt2x00dev->ops->bcn);
1180 if (status)
1181 goto exit;
1182
7dab73b3 1183 if (test_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags)) {
e74df4a7 1184 status = rt2x00queue_alloc_entries(rt2x00dev->atim,
30caa6e3
GW
1185 rt2x00dev->ops->atim);
1186 if (status)
1187 goto exit;
1188 }
181d6902 1189
fa69560f 1190 status = rt2x00queue_alloc_rxskbs(rt2x00dev->rx);
181d6902
ID
1191 if (status)
1192 goto exit;
1193
1194 return 0;
1195
1196exit:
1197 ERROR(rt2x00dev, "Queue entries allocation failed.\n");
1198
1199 rt2x00queue_uninitialize(rt2x00dev);
1200
1201 return status;
1202}
1203
1204void rt2x00queue_uninitialize(struct rt2x00_dev *rt2x00dev)
1205{
1206 struct data_queue *queue;
1207
fa69560f 1208 rt2x00queue_free_skbs(rt2x00dev->rx);
30caa6e3 1209
181d6902
ID
1210 queue_for_each(rt2x00dev, queue) {
1211 kfree(queue->entries);
1212 queue->entries = NULL;
1213 }
1214}
1215
8f539276
ID
1216static void rt2x00queue_init(struct rt2x00_dev *rt2x00dev,
1217 struct data_queue *queue, enum data_queue_qid qid)
1218{
0b7fde54 1219 mutex_init(&queue->status_lock);
77a861c4 1220 spin_lock_init(&queue->tx_lock);
813f0339 1221 spin_lock_init(&queue->index_lock);
8f539276
ID
1222
1223 queue->rt2x00dev = rt2x00dev;
1224 queue->qid = qid;
2af0a570 1225 queue->txop = 0;
8f539276
ID
1226 queue->aifs = 2;
1227 queue->cw_min = 5;
1228 queue->cw_max = 10;
1229}
1230
181d6902
ID
1231int rt2x00queue_allocate(struct rt2x00_dev *rt2x00dev)
1232{
1233 struct data_queue *queue;
1234 enum data_queue_qid qid;
1235 unsigned int req_atim =
7dab73b3 1236 !!test_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags);
181d6902
ID
1237
1238 /*
1239 * We need the following queues:
1240 * RX: 1
61448f88 1241 * TX: ops->tx_queues
181d6902
ID
1242 * Beacon: 1
1243 * Atim: 1 (if required)
1244 */
61448f88 1245 rt2x00dev->data_queues = 2 + rt2x00dev->ops->tx_queues + req_atim;
181d6902 1246
baeb2ffa 1247 queue = kcalloc(rt2x00dev->data_queues, sizeof(*queue), GFP_KERNEL);
181d6902
ID
1248 if (!queue) {
1249 ERROR(rt2x00dev, "Queue allocation failed.\n");
1250 return -ENOMEM;
1251 }
1252
1253 /*
1254 * Initialize pointers
1255 */
1256 rt2x00dev->rx = queue;
1257 rt2x00dev->tx = &queue[1];
61448f88 1258 rt2x00dev->bcn = &queue[1 + rt2x00dev->ops->tx_queues];
e74df4a7 1259 rt2x00dev->atim = req_atim ? &queue[2 + rt2x00dev->ops->tx_queues] : NULL;
181d6902
ID
1260
1261 /*
1262 * Initialize queue parameters.
1263 * RX: qid = QID_RX
f615e9a3 1264 * TX: qid = QID_AC_VO + index
181d6902
ID
1265 * TX: cw_min: 2^5 = 32.
1266 * TX: cw_max: 2^10 = 1024.
565a019a
ID
1267 * BCN: qid = QID_BEACON
1268 * ATIM: qid = QID_ATIM
181d6902 1269 */
8f539276 1270 rt2x00queue_init(rt2x00dev, rt2x00dev->rx, QID_RX);
181d6902 1271
f615e9a3 1272 qid = QID_AC_VO;
8f539276
ID
1273 tx_queue_for_each(rt2x00dev, queue)
1274 rt2x00queue_init(rt2x00dev, queue, qid++);
181d6902 1275
e74df4a7 1276 rt2x00queue_init(rt2x00dev, rt2x00dev->bcn, QID_BEACON);
181d6902 1277 if (req_atim)
e74df4a7 1278 rt2x00queue_init(rt2x00dev, rt2x00dev->atim, QID_ATIM);
181d6902
ID
1279
1280 return 0;
1281}
1282
1283void rt2x00queue_free(struct rt2x00_dev *rt2x00dev)
1284{
1285 kfree(rt2x00dev->rx);
1286 rt2x00dev->rx = NULL;
1287 rt2x00dev->tx = NULL;
1288 rt2x00dev->bcn = NULL;
1289}