mac80211: remove more excess kernel-doc
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / rt2x00 / rt2x00queue.c
CommitLineData
181d6902
ID
1/*
2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2x00lib
23 Abstract: rt2x00 queue specific routines.
24 */
25
26#include <linux/kernel.h>
27#include <linux/module.h>
c4da0048 28#include <linux/dma-mapping.h>
181d6902
ID
29
30#include "rt2x00.h"
31#include "rt2x00lib.h"
32
c4da0048
GW
33struct sk_buff *rt2x00queue_alloc_rxskb(struct rt2x00_dev *rt2x00dev,
34 struct queue_entry *entry)
239c249d 35{
c4da0048
GW
36 struct sk_buff *skb;
37 struct skb_frame_desc *skbdesc;
2bb057d0
ID
38 unsigned int frame_size;
39 unsigned int head_size = 0;
40 unsigned int tail_size = 0;
239c249d
GW
41
42 /*
43 * The frame size includes descriptor size, because the
44 * hardware directly receive the frame into the skbuffer.
45 */
c4da0048 46 frame_size = entry->queue->data_size + entry->queue->desc_size;
239c249d
GW
47
48 /*
ff352391
ID
49 * The payload should be aligned to a 4-byte boundary,
50 * this means we need at least 3 bytes for moving the frame
51 * into the correct offset.
239c249d 52 */
2bb057d0
ID
53 head_size = 4;
54
55 /*
56 * For IV/EIV/ICV assembly we must make sure there is
57 * at least 8 bytes bytes available in headroom for IV/EIV
58 * and 4 bytes for ICV data as tailroon.
59 */
60#ifdef CONFIG_RT2X00_LIB_CRYPTO
61 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
62 head_size += 8;
63 tail_size += 4;
64 }
65#endif /* CONFIG_RT2X00_LIB_CRYPTO */
239c249d
GW
66
67 /*
68 * Allocate skbuffer.
69 */
2bb057d0 70 skb = dev_alloc_skb(frame_size + head_size + tail_size);
239c249d
GW
71 if (!skb)
72 return NULL;
73
2bb057d0
ID
74 /*
75 * Make sure we not have a frame with the requested bytes
76 * available in the head and tail.
77 */
78 skb_reserve(skb, head_size);
239c249d
GW
79 skb_put(skb, frame_size);
80
c4da0048
GW
81 /*
82 * Populate skbdesc.
83 */
84 skbdesc = get_skb_frame_desc(skb);
85 memset(skbdesc, 0, sizeof(*skbdesc));
86 skbdesc->entry = entry;
87
88 if (test_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags)) {
89 skbdesc->skb_dma = dma_map_single(rt2x00dev->dev,
90 skb->data,
91 skb->len,
92 DMA_FROM_DEVICE);
93 skbdesc->flags |= SKBDESC_DMA_MAPPED_RX;
94 }
95
239c249d
GW
96 return skb;
97}
30caa6e3 98
c4da0048 99void rt2x00queue_map_txskb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
30caa6e3 100{
c4da0048
GW
101 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
102
3ee54a07
ID
103 /*
104 * If device has requested headroom, we should make sure that
105 * is also mapped to the DMA so it can be used for transfering
106 * additional descriptor information to the hardware.
107 */
108 skb_push(skb, rt2x00dev->hw->extra_tx_headroom);
109
110 skbdesc->skb_dma =
111 dma_map_single(rt2x00dev->dev, skb->data, skb->len, DMA_TO_DEVICE);
112
113 /*
114 * Restore data pointer to original location again.
115 */
116 skb_pull(skb, rt2x00dev->hw->extra_tx_headroom);
117
c4da0048
GW
118 skbdesc->flags |= SKBDESC_DMA_MAPPED_TX;
119}
120EXPORT_SYMBOL_GPL(rt2x00queue_map_txskb);
121
122void rt2x00queue_unmap_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
123{
124 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
125
126 if (skbdesc->flags & SKBDESC_DMA_MAPPED_RX) {
127 dma_unmap_single(rt2x00dev->dev, skbdesc->skb_dma, skb->len,
128 DMA_FROM_DEVICE);
129 skbdesc->flags &= ~SKBDESC_DMA_MAPPED_RX;
130 }
131
132 if (skbdesc->flags & SKBDESC_DMA_MAPPED_TX) {
3ee54a07
ID
133 /*
134 * Add headroom to the skb length, it has been removed
135 * by the driver, but it was actually mapped to DMA.
136 */
137 dma_unmap_single(rt2x00dev->dev, skbdesc->skb_dma,
138 skb->len + rt2x00dev->hw->extra_tx_headroom,
c4da0048
GW
139 DMA_TO_DEVICE);
140 skbdesc->flags &= ~SKBDESC_DMA_MAPPED_TX;
141 }
142}
c4da0048
GW
143
144void rt2x00queue_free_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
145{
9a613195
ID
146 if (!skb)
147 return;
148
61243d8e 149 rt2x00queue_unmap_skb(rt2x00dev, skb);
30caa6e3
GW
150 dev_kfree_skb_any(skb);
151}
239c249d 152
bd88a781
ID
153static void rt2x00queue_create_tx_descriptor(struct queue_entry *entry,
154 struct txentry_desc *txdesc)
7050ec82 155{
2e92e6f2 156 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
e039fa4a 157 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
7050ec82 158 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data;
2e92e6f2 159 struct ieee80211_rate *rate =
e039fa4a 160 ieee80211_get_tx_rate(rt2x00dev->hw, tx_info);
7050ec82
ID
161 const struct rt2x00_rate *hwrate;
162 unsigned int data_length;
163 unsigned int duration;
164 unsigned int residual;
d4764b29 165 unsigned long irqflags;
7050ec82
ID
166
167 memset(txdesc, 0, sizeof(*txdesc));
168
169 /*
170 * Initialize information from queue
171 */
172 txdesc->queue = entry->queue->qid;
173 txdesc->cw_min = entry->queue->cw_min;
174 txdesc->cw_max = entry->queue->cw_max;
175 txdesc->aifs = entry->queue->aifs;
176
2bb057d0 177 /* Data length + CRC + IV/EIV/ICV/MMIC (when using encryption) */
7050ec82
ID
178 data_length = entry->skb->len + 4;
179
7050ec82
ID
180 /*
181 * Check whether this frame is to be acked.
182 */
e039fa4a 183 if (!(tx_info->flags & IEEE80211_TX_CTL_NO_ACK))
7050ec82
ID
184 __set_bit(ENTRY_TXD_ACK, &txdesc->flags);
185
2bb057d0
ID
186#ifdef CONFIG_RT2X00_LIB_CRYPTO
187 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags) &&
188 !entry->skb->do_not_encrypt) {
189 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
190
191 __set_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags);
192
193 txdesc->cipher = rt2x00crypto_key_to_cipher(hw_key);
194
195 if (hw_key->flags & IEEE80211_KEY_FLAG_PAIRWISE)
196 __set_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags);
197
198 txdesc->key_idx = hw_key->hw_key_idx;
199 txdesc->iv_offset = ieee80211_get_hdrlen_from_skb(entry->skb);
200
201 /*
202 * Extend frame length to include all encryption overhead
203 * that will be added by the hardware.
204 */
205 data_length += rt2x00crypto_tx_overhead(tx_info);
206
207 if (!(hw_key->flags & IEEE80211_KEY_FLAG_GENERATE_IV))
208 __set_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags);
209
210 if (!(hw_key->flags & IEEE80211_KEY_FLAG_GENERATE_MMIC))
211 __set_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags);
212 }
213#endif /* CONFIG_RT2X00_LIB_CRYPTO */
214
7050ec82
ID
215 /*
216 * Check if this is a RTS/CTS frame
217 */
ac104462
ID
218 if (ieee80211_is_rts(hdr->frame_control) ||
219 ieee80211_is_cts(hdr->frame_control)) {
7050ec82 220 __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
ac104462 221 if (ieee80211_is_rts(hdr->frame_control))
7050ec82 222 __set_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags);
e039fa4a 223 else
7050ec82 224 __set_bit(ENTRY_TXD_CTS_FRAME, &txdesc->flags);
e039fa4a 225 if (tx_info->control.rts_cts_rate_idx >= 0)
2e92e6f2 226 rate =
e039fa4a 227 ieee80211_get_rts_cts_rate(rt2x00dev->hw, tx_info);
7050ec82
ID
228 }
229
230 /*
231 * Determine retry information.
232 */
e6a9854b
JB
233 txdesc->retry_limit = tx_info->control.rates[0].count - 1;
234 /*
235 * XXX: If at this point we knew whether the HW is going to use
236 * the RETRY_MODE bit or the retry_limit (currently all
237 * use the RETRY_MODE bit) we could do something like b43
238 * does, set the RETRY_MODE bit when the RC algorithm is
239 * requesting more than the long retry limit.
240 */
241 if (tx_info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
7050ec82
ID
242 __set_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags);
243
244 /*
245 * Check if more fragments are pending
246 */
8b7b1e05 247 if (ieee80211_has_morefrags(hdr->frame_control)) {
7050ec82
ID
248 __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
249 __set_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags);
250 }
251
252 /*
253 * Beacons and probe responses require the tsf timestamp
254 * to be inserted into the frame.
255 */
ac104462
ID
256 if (ieee80211_is_beacon(hdr->frame_control) ||
257 ieee80211_is_probe_resp(hdr->frame_control))
7050ec82
ID
258 __set_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags);
259
260 /*
261 * Determine with what IFS priority this frame should be send.
262 * Set ifs to IFS_SIFS when the this is not the first fragment,
263 * or this fragment came after RTS/CTS.
264 */
265 if (test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags)) {
266 txdesc->ifs = IFS_SIFS;
e039fa4a 267 } else if (tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) {
7050ec82
ID
268 __set_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags);
269 txdesc->ifs = IFS_BACKOFF;
270 } else {
271 txdesc->ifs = IFS_SIFS;
272 }
273
5adf6d63
ID
274 /*
275 * Hardware should insert sequence counter.
276 * FIXME: We insert a software sequence counter first for
277 * hardware that doesn't support hardware sequence counting.
278 *
279 * This is wrong because beacons are not getting sequence
280 * numbers assigned properly.
281 *
282 * A secondary problem exists for drivers that cannot toggle
283 * sequence counting per-frame, since those will override the
284 * sequence counter given by mac80211.
285 */
286 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
25d834e1
JB
287 if (likely(tx_info->control.vif)) {
288 struct rt2x00_intf *intf;
5adf6d63 289
25d834e1 290 intf = vif_to_intf(tx_info->control.vif);
5adf6d63 291
25d834e1 292 spin_lock_irqsave(&intf->seqlock, irqflags);
5adf6d63 293
25d834e1
JB
294 if (test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags))
295 intf->seqno += 0x10;
296 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
297 hdr->seq_ctrl |= cpu_to_le16(intf->seqno);
298
299 spin_unlock_irqrestore(&intf->seqlock, irqflags);
300
301 __set_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags);
302 }
5adf6d63
ID
303 }
304
7050ec82
ID
305 /*
306 * PLCP setup
307 * Length calculation depends on OFDM/CCK rate.
308 */
309 hwrate = rt2x00_get_rate(rate->hw_value);
310 txdesc->signal = hwrate->plcp;
311 txdesc->service = 0x04;
312
313 if (hwrate->flags & DEV_RATE_OFDM) {
314 __set_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags);
315
316 txdesc->length_high = (data_length >> 6) & 0x3f;
317 txdesc->length_low = data_length & 0x3f;
318 } else {
319 /*
320 * Convert length to microseconds.
321 */
322 residual = get_duration_res(data_length, hwrate->bitrate);
323 duration = get_duration(data_length, hwrate->bitrate);
324
325 if (residual != 0) {
326 duration++;
327
328 /*
329 * Check if we need to set the Length Extension
330 */
331 if (hwrate->bitrate == 110 && residual <= 30)
332 txdesc->service |= 0x80;
333 }
334
335 txdesc->length_high = (duration >> 8) & 0xff;
336 txdesc->length_low = duration & 0xff;
337
338 /*
339 * When preamble is enabled we should set the
340 * preamble bit for the signal.
341 */
342 if (rt2x00_get_rate_preamble(rate->hw_value))
343 txdesc->signal |= 0x08;
344 }
345}
7050ec82 346
bd88a781
ID
347static void rt2x00queue_write_tx_descriptor(struct queue_entry *entry,
348 struct txentry_desc *txdesc)
7050ec82 349{
b869767b
ID
350 struct data_queue *queue = entry->queue;
351 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
7050ec82
ID
352
353 rt2x00dev->ops->lib->write_tx_desc(rt2x00dev, entry->skb, txdesc);
354
355 /*
356 * All processing on the frame has been completed, this means
357 * it is now ready to be dumped to userspace through debugfs.
358 */
359 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_TX, entry->skb);
360
361 /*
b869767b
ID
362 * Check if we need to kick the queue, there are however a few rules
363 * 1) Don't kick beacon queue
364 * 2) Don't kick unless this is the last in frame in a burst.
365 * When the burst flag is set, this frame is always followed
366 * by another frame which in some way are related to eachother.
367 * This is true for fragments, RTS or CTS-to-self frames.
368 * 3) Rule 2 can be broken when the available entries
369 * in the queue are less then a certain threshold.
7050ec82 370 */
b869767b
ID
371 if (entry->queue->qid == QID_BEACON)
372 return;
373
374 if (rt2x00queue_threshold(queue) ||
375 !test_bit(ENTRY_TXD_BURST, &txdesc->flags))
376 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, queue->qid);
7050ec82 377}
7050ec82 378
6db3786a
ID
379int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb)
380{
e6a9854b 381 struct ieee80211_tx_info *tx_info;
6db3786a
ID
382 struct queue_entry *entry = rt2x00queue_get_entry(queue, Q_INDEX);
383 struct txentry_desc txdesc;
d74f5ba4 384 struct skb_frame_desc *skbdesc;
8713a7cc 385 unsigned int iv_len = 0;
e6a9854b 386 u8 rate_idx, rate_flags;
6db3786a
ID
387
388 if (unlikely(rt2x00queue_full(queue)))
389 return -EINVAL;
390
0262ab0d 391 if (test_and_set_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags)) {
6db3786a
ID
392 ERROR(queue->rt2x00dev,
393 "Arrived at non-free entry in the non-full queue %d.\n"
394 "Please file bug report to %s.\n",
395 queue->qid, DRV_PROJECT);
396 return -EINVAL;
397 }
398
399 /*
400 * Copy all TX descriptor information into txdesc,
401 * after that we are free to use the skb->cb array
402 * for our information.
403 */
404 entry->skb = skb;
405 rt2x00queue_create_tx_descriptor(entry, &txdesc);
406
8713a7cc
FF
407 if (IEEE80211_SKB_CB(skb)->control.hw_key != NULL)
408 iv_len = IEEE80211_SKB_CB(skb)->control.hw_key->iv_len;
409
d74f5ba4 410 /*
e6a9854b 411 * All information is retrieved from the skb->cb array,
2bb057d0 412 * now we should claim ownership of the driver part of that
e6a9854b 413 * array, preserving the bitrate index and flags.
d74f5ba4 414 */
e6a9854b
JB
415 tx_info = IEEE80211_SKB_CB(skb);
416 rate_idx = tx_info->control.rates[0].idx;
417 rate_flags = tx_info->control.rates[0].flags;
d74f5ba4
ID
418 skbdesc = get_skb_frame_desc(entry->skb);
419 memset(skbdesc, 0, sizeof(*skbdesc));
420 skbdesc->entry = entry;
e6a9854b
JB
421 skbdesc->tx_rate_idx = rate_idx;
422 skbdesc->tx_rate_flags = rate_flags;
d74f5ba4 423
2bb057d0
ID
424 /*
425 * When hardware encryption is supported, and this frame
426 * is to be encrypted, we should strip the IV/EIV data from
427 * the frame so we can provide it to the driver seperately.
428 */
429 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc.flags) &&
8713a7cc 430 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc.flags)) {
2bb057d0 431 rt2x00crypto_tx_remove_iv(skb, iv_len);
76708dee 432 }
2bb057d0
ID
433
434 /*
435 * It could be possible that the queue was corrupted and this
436 * call failed. Just drop the frame, we cannot rollback and pass
437 * the frame to mac80211 because the skb->cb has now been tainted.
438 */
6db3786a 439 if (unlikely(queue->rt2x00dev->ops->lib->write_tx_data(entry))) {
0262ab0d 440 clear_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags);
2bb057d0
ID
441 dev_kfree_skb_any(entry->skb);
442 entry->skb = NULL;
443 return 0;
6db3786a
ID
444 }
445
d74f5ba4
ID
446 if (test_bit(DRIVER_REQUIRE_DMA, &queue->rt2x00dev->flags))
447 rt2x00queue_map_txskb(queue->rt2x00dev, skb);
448
0262ab0d 449 set_bit(ENTRY_DATA_PENDING, &entry->flags);
6db3786a
ID
450
451 rt2x00queue_index_inc(queue, Q_INDEX);
452 rt2x00queue_write_tx_descriptor(entry, &txdesc);
453
454 return 0;
455}
456
bd88a781
ID
457int rt2x00queue_update_beacon(struct rt2x00_dev *rt2x00dev,
458 struct ieee80211_vif *vif)
459{
460 struct rt2x00_intf *intf = vif_to_intf(vif);
461 struct skb_frame_desc *skbdesc;
462 struct txentry_desc txdesc;
463 __le32 desc[16];
464
465 if (unlikely(!intf->beacon))
466 return -ENOBUFS;
467
468 intf->beacon->skb = ieee80211_beacon_get(rt2x00dev->hw, vif);
469 if (!intf->beacon->skb)
470 return -ENOMEM;
471
472 /*
473 * Copy all TX descriptor information into txdesc,
474 * after that we are free to use the skb->cb array
475 * for our information.
476 */
477 rt2x00queue_create_tx_descriptor(intf->beacon, &txdesc);
478
479 /*
480 * For the descriptor we use a local array from where the
481 * driver can move it to the correct location required for
482 * the hardware.
483 */
484 memset(desc, 0, sizeof(desc));
485
486 /*
487 * Fill in skb descriptor
488 */
489 skbdesc = get_skb_frame_desc(intf->beacon->skb);
490 memset(skbdesc, 0, sizeof(*skbdesc));
491 skbdesc->desc = desc;
492 skbdesc->desc_len = intf->beacon->queue->desc_size;
493 skbdesc->entry = intf->beacon;
494
495 /*
496 * Write TX descriptor into reserved room in front of the beacon.
497 */
498 rt2x00queue_write_tx_descriptor(intf->beacon, &txdesc);
499
500 /*
501 * Send beacon to hardware.
502 * Also enable beacon generation, which might have been disabled
503 * by the driver during the config_beacon() callback function.
504 */
505 rt2x00dev->ops->lib->write_beacon(intf->beacon);
506 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, QID_BEACON);
507
508 return 0;
509}
510
181d6902 511struct data_queue *rt2x00queue_get_queue(struct rt2x00_dev *rt2x00dev,
e58c6aca 512 const enum data_queue_qid queue)
181d6902
ID
513{
514 int atim = test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
515
61448f88 516 if (queue < rt2x00dev->ops->tx_queues && rt2x00dev->tx)
181d6902
ID
517 return &rt2x00dev->tx[queue];
518
519 if (!rt2x00dev->bcn)
520 return NULL;
521
e58c6aca 522 if (queue == QID_BEACON)
181d6902 523 return &rt2x00dev->bcn[0];
e58c6aca 524 else if (queue == QID_ATIM && atim)
181d6902
ID
525 return &rt2x00dev->bcn[1];
526
527 return NULL;
528}
529EXPORT_SYMBOL_GPL(rt2x00queue_get_queue);
530
531struct queue_entry *rt2x00queue_get_entry(struct data_queue *queue,
532 enum queue_index index)
533{
534 struct queue_entry *entry;
5f46c4d0 535 unsigned long irqflags;
181d6902
ID
536
537 if (unlikely(index >= Q_INDEX_MAX)) {
538 ERROR(queue->rt2x00dev,
539 "Entry requested from invalid index type (%d)\n", index);
540 return NULL;
541 }
542
5f46c4d0 543 spin_lock_irqsave(&queue->lock, irqflags);
181d6902
ID
544
545 entry = &queue->entries[queue->index[index]];
546
5f46c4d0 547 spin_unlock_irqrestore(&queue->lock, irqflags);
181d6902
ID
548
549 return entry;
550}
551EXPORT_SYMBOL_GPL(rt2x00queue_get_entry);
552
553void rt2x00queue_index_inc(struct data_queue *queue, enum queue_index index)
554{
5f46c4d0
ID
555 unsigned long irqflags;
556
181d6902
ID
557 if (unlikely(index >= Q_INDEX_MAX)) {
558 ERROR(queue->rt2x00dev,
559 "Index change on invalid index type (%d)\n", index);
560 return;
561 }
562
5f46c4d0 563 spin_lock_irqsave(&queue->lock, irqflags);
181d6902
ID
564
565 queue->index[index]++;
566 if (queue->index[index] >= queue->limit)
567 queue->index[index] = 0;
568
10b6b801
ID
569 if (index == Q_INDEX) {
570 queue->length++;
571 } else if (index == Q_INDEX_DONE) {
572 queue->length--;
55887511 573 queue->count++;
10b6b801 574 }
181d6902 575
5f46c4d0 576 spin_unlock_irqrestore(&queue->lock, irqflags);
181d6902 577}
181d6902
ID
578
579static void rt2x00queue_reset(struct data_queue *queue)
580{
5f46c4d0
ID
581 unsigned long irqflags;
582
583 spin_lock_irqsave(&queue->lock, irqflags);
181d6902
ID
584
585 queue->count = 0;
586 queue->length = 0;
587 memset(queue->index, 0, sizeof(queue->index));
588
5f46c4d0 589 spin_unlock_irqrestore(&queue->lock, irqflags);
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ID
590}
591
592void rt2x00queue_init_rx(struct rt2x00_dev *rt2x00dev)
593{
594 struct data_queue *queue = rt2x00dev->rx;
595 unsigned int i;
596
597 rt2x00queue_reset(queue);
598
599 if (!rt2x00dev->ops->lib->init_rxentry)
600 return;
601
9c0ab712
ID
602 for (i = 0; i < queue->limit; i++) {
603 queue->entries[i].flags = 0;
604
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ID
605 rt2x00dev->ops->lib->init_rxentry(rt2x00dev,
606 &queue->entries[i]);
9c0ab712 607 }
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608}
609
610void rt2x00queue_init_tx(struct rt2x00_dev *rt2x00dev)
611{
612 struct data_queue *queue;
613 unsigned int i;
614
615 txall_queue_for_each(rt2x00dev, queue) {
616 rt2x00queue_reset(queue);
617
618 if (!rt2x00dev->ops->lib->init_txentry)
619 continue;
620
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ID
621 for (i = 0; i < queue->limit; i++) {
622 queue->entries[i].flags = 0;
623
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ID
624 rt2x00dev->ops->lib->init_txentry(rt2x00dev,
625 &queue->entries[i]);
9c0ab712 626 }
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ID
627 }
628}
629
630static int rt2x00queue_alloc_entries(struct data_queue *queue,
631 const struct data_queue_desc *qdesc)
632{
633 struct queue_entry *entries;
634 unsigned int entry_size;
635 unsigned int i;
636
637 rt2x00queue_reset(queue);
638
639 queue->limit = qdesc->entry_num;
b869767b 640 queue->threshold = DIV_ROUND_UP(qdesc->entry_num, 10);
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ID
641 queue->data_size = qdesc->data_size;
642 queue->desc_size = qdesc->desc_size;
643
644 /*
645 * Allocate all queue entries.
646 */
647 entry_size = sizeof(*entries) + qdesc->priv_size;
648 entries = kzalloc(queue->limit * entry_size, GFP_KERNEL);
649 if (!entries)
650 return -ENOMEM;
651
652#define QUEUE_ENTRY_PRIV_OFFSET(__base, __index, __limit, __esize, __psize) \
231be4e9
AB
653 ( ((char *)(__base)) + ((__limit) * (__esize)) + \
654 ((__index) * (__psize)) )
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ID
655
656 for (i = 0; i < queue->limit; i++) {
657 entries[i].flags = 0;
658 entries[i].queue = queue;
659 entries[i].skb = NULL;
660 entries[i].entry_idx = i;
661 entries[i].priv_data =
662 QUEUE_ENTRY_PRIV_OFFSET(entries, i, queue->limit,
663 sizeof(*entries), qdesc->priv_size);
664 }
665
666#undef QUEUE_ENTRY_PRIV_OFFSET
667
668 queue->entries = entries;
669
670 return 0;
671}
672
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GW
673static void rt2x00queue_free_skbs(struct rt2x00_dev *rt2x00dev,
674 struct data_queue *queue)
30caa6e3
GW
675{
676 unsigned int i;
677
678 if (!queue->entries)
679 return;
680
681 for (i = 0; i < queue->limit; i++) {
682 if (queue->entries[i].skb)
c4da0048 683 rt2x00queue_free_skb(rt2x00dev, queue->entries[i].skb);
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GW
684 }
685}
686
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GW
687static int rt2x00queue_alloc_rxskbs(struct rt2x00_dev *rt2x00dev,
688 struct data_queue *queue)
30caa6e3
GW
689{
690 unsigned int i;
691 struct sk_buff *skb;
692
693 for (i = 0; i < queue->limit; i++) {
c4da0048 694 skb = rt2x00queue_alloc_rxskb(rt2x00dev, &queue->entries[i]);
30caa6e3 695 if (!skb)
61243d8e 696 return -ENOMEM;
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GW
697 queue->entries[i].skb = skb;
698 }
699
700 return 0;
30caa6e3
GW
701}
702
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703int rt2x00queue_initialize(struct rt2x00_dev *rt2x00dev)
704{
705 struct data_queue *queue;
706 int status;
707
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ID
708 status = rt2x00queue_alloc_entries(rt2x00dev->rx, rt2x00dev->ops->rx);
709 if (status)
710 goto exit;
711
712 tx_queue_for_each(rt2x00dev, queue) {
713 status = rt2x00queue_alloc_entries(queue, rt2x00dev->ops->tx);
714 if (status)
715 goto exit;
716 }
717
718 status = rt2x00queue_alloc_entries(rt2x00dev->bcn, rt2x00dev->ops->bcn);
719 if (status)
720 goto exit;
721
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GW
722 if (test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags)) {
723 status = rt2x00queue_alloc_entries(&rt2x00dev->bcn[1],
724 rt2x00dev->ops->atim);
725 if (status)
726 goto exit;
727 }
181d6902 728
c4da0048 729 status = rt2x00queue_alloc_rxskbs(rt2x00dev, rt2x00dev->rx);
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ID
730 if (status)
731 goto exit;
732
733 return 0;
734
735exit:
736 ERROR(rt2x00dev, "Queue entries allocation failed.\n");
737
738 rt2x00queue_uninitialize(rt2x00dev);
739
740 return status;
741}
742
743void rt2x00queue_uninitialize(struct rt2x00_dev *rt2x00dev)
744{
745 struct data_queue *queue;
746
c4da0048 747 rt2x00queue_free_skbs(rt2x00dev, rt2x00dev->rx);
30caa6e3 748
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ID
749 queue_for_each(rt2x00dev, queue) {
750 kfree(queue->entries);
751 queue->entries = NULL;
752 }
753}
754
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ID
755static void rt2x00queue_init(struct rt2x00_dev *rt2x00dev,
756 struct data_queue *queue, enum data_queue_qid qid)
757{
758 spin_lock_init(&queue->lock);
759
760 queue->rt2x00dev = rt2x00dev;
761 queue->qid = qid;
2af0a570 762 queue->txop = 0;
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ID
763 queue->aifs = 2;
764 queue->cw_min = 5;
765 queue->cw_max = 10;
766}
767
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768int rt2x00queue_allocate(struct rt2x00_dev *rt2x00dev)
769{
770 struct data_queue *queue;
771 enum data_queue_qid qid;
772 unsigned int req_atim =
773 !!test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
774
775 /*
776 * We need the following queues:
777 * RX: 1
61448f88 778 * TX: ops->tx_queues
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ID
779 * Beacon: 1
780 * Atim: 1 (if required)
781 */
61448f88 782 rt2x00dev->data_queues = 2 + rt2x00dev->ops->tx_queues + req_atim;
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783
784 queue = kzalloc(rt2x00dev->data_queues * sizeof(*queue), GFP_KERNEL);
785 if (!queue) {
786 ERROR(rt2x00dev, "Queue allocation failed.\n");
787 return -ENOMEM;
788 }
789
790 /*
791 * Initialize pointers
792 */
793 rt2x00dev->rx = queue;
794 rt2x00dev->tx = &queue[1];
61448f88 795 rt2x00dev->bcn = &queue[1 + rt2x00dev->ops->tx_queues];
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796
797 /*
798 * Initialize queue parameters.
799 * RX: qid = QID_RX
800 * TX: qid = QID_AC_BE + index
801 * TX: cw_min: 2^5 = 32.
802 * TX: cw_max: 2^10 = 1024.
565a019a
ID
803 * BCN: qid = QID_BEACON
804 * ATIM: qid = QID_ATIM
181d6902 805 */
8f539276 806 rt2x00queue_init(rt2x00dev, rt2x00dev->rx, QID_RX);
181d6902 807
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ID
808 qid = QID_AC_BE;
809 tx_queue_for_each(rt2x00dev, queue)
810 rt2x00queue_init(rt2x00dev, queue, qid++);
181d6902 811
565a019a 812 rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[0], QID_BEACON);
181d6902 813 if (req_atim)
565a019a 814 rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[1], QID_ATIM);
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ID
815
816 return 0;
817}
818
819void rt2x00queue_free(struct rt2x00_dev *rt2x00dev)
820{
821 kfree(rt2x00dev->rx);
822 rt2x00dev->rx = NULL;
823 rt2x00dev->tx = NULL;
824 rt2x00dev->bcn = NULL;
825}