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Make linux/wireless.h be able to compile
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / rt2x00 / rt2500pci.c
CommitLineData
95ea3627 1/*
811aa9ca 2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2500pci
23 Abstract: rt2500pci device specific routines.
24 Supported chipsets: RT2560.
25 */
26
95ea3627
ID		 27#include <linux/delay.h>
28#include <linux/etherdevice.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/pci.h>
33#include <linux/eeprom_93cx6.h>
34
35#include "rt2x00.h"
36#include "rt2x00pci.h"
37#include "rt2500pci.h"
38
39/*
40 * Register access.
41 * All access to the CSR registers will go through the methods
42 * rt2x00pci_register_read and rt2x00pci_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
51 */
0e14f6d3 52static u32 rt2500pci_bbp_check(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 53{
54 u32 reg;
55 unsigned int i;
56
57 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
58 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
59 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
60 break;
61 udelay(REGISTER_BUSY_DELAY);
62 }
63
64 return reg;
65}
66
0e14f6d3 67static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 68 const unsigned int word, const u8 value)
69{
70 u32 reg;
71
72 /*
73 * Wait until the BBP becomes ready.
74 */
75 reg = rt2500pci_bbp_check(rt2x00dev);
76 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
77 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
78 return;
79 }
80
81 /*
82 * Write the data into the BBP.
83 */
84 reg = 0;
85 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
86 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
87 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
88 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
89
90 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
91}
92
0e14f6d3 93static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 94 const unsigned int word, u8 *value)
95{
96 u32 reg;
97
98 /*
99 * Wait until the BBP becomes ready.
100 */
101 reg = rt2500pci_bbp_check(rt2x00dev);
102 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
103 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
104 return;
105 }
106
107 /*
108 * Write the request into the BBP.
109 */
110 reg = 0;
111 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
112 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
113 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
114
115 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
116
117 /*
118 * Wait until the BBP becomes ready.
119 */
120 reg = rt2500pci_bbp_check(rt2x00dev);
121 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
122 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
123 *value = 0xff;
124 return;
125 }
126
127 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
128}
129
0e14f6d3 130static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 131 const unsigned int word, const u32 value)
132{
133 u32 reg;
134 unsigned int i;
135
136 if (!word)
137 return;
138
139 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
140 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
141 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
142 goto rf_write;
143 udelay(REGISTER_BUSY_DELAY);
144 }
145
146 ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
147 return;
148
149rf_write:
150 reg = 0;
151 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
152 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
153 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
154 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
155
156 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
157 rt2x00_rf_write(rt2x00dev, word, value);
158}
159
160static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
161{
162 struct rt2x00_dev *rt2x00dev = eeprom->data;
163 u32 reg;
164
165 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
166
167 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
168 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
169 eeprom->reg_data_clock =
170 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
171 eeprom->reg_chip_select =
172 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
173}
174
175static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
176{
177 struct rt2x00_dev *rt2x00dev = eeprom->data;
178 u32 reg = 0;
179
180 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
181 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
182 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
183 !!eeprom->reg_data_clock);
184 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
185 !!eeprom->reg_chip_select);
186
187 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
188}
189
190#ifdef CONFIG_RT2X00_LIB_DEBUGFS
191#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
192
0e14f6d3 193static void rt2500pci_read_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 194 const unsigned int word, u32 *data)
195{
196 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
197}
198
0e14f6d3 199static void rt2500pci_write_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 200 const unsigned int word, u32 data)
201{
202 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
203}
204
205static const struct rt2x00debug rt2500pci_rt2x00debug = {
206 .owner = THIS_MODULE,
207 .csr = {
208 .read = rt2500pci_read_csr,
209 .write = rt2500pci_write_csr,
210 .word_size = sizeof(u32),
211 .word_count = CSR_REG_SIZE / sizeof(u32),
212 },
213 .eeprom = {
214 .read = rt2x00_eeprom_read,
215 .write = rt2x00_eeprom_write,
216 .word_size = sizeof(u16),
217 .word_count = EEPROM_SIZE / sizeof(u16),
218 },
219 .bbp = {
220 .read = rt2500pci_bbp_read,
221 .write = rt2500pci_bbp_write,
222 .word_size = sizeof(u8),
223 .word_count = BBP_SIZE / sizeof(u8),
224 },
225 .rf = {
226 .read = rt2x00_rf_read,
227 .write = rt2500pci_rf_write,
228 .word_size = sizeof(u32),
229 .word_count = RF_SIZE / sizeof(u32),
230 },
231};
232#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
233
234#ifdef CONFIG_RT2500PCI_RFKILL
235static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
236{
237 u32 reg;
238
239 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
240 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
241}
81873e9c
ID		 242#else
243#define rt2500pci_rfkill_poll NULL
dcf5475b 244#endif /* CONFIG_RT2500PCI_RFKILL */
95ea3627 245
a9450b70 246#ifdef CONFIG_RT2500PCI_LEDS
a2e1d52a 247static void rt2500pci_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 248 enum led_brightness brightness)
249{
250 struct rt2x00_led *led =
251 container_of(led_cdev, struct rt2x00_led, led_dev);
252 unsigned int enabled = brightness != LED_OFF;
a9450b70
ID		 253 u32 reg;
254
255 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
256
a2e1d52a 257 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
a9450b70 258 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
a2e1d52a
ID		 259 else if (led->type == LED_TYPE_ACTIVITY)
260 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
a9450b70
ID		 261
262 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
263}
a2e1d52a
ID		 264
265static int rt2500pci_blink_set(struct led_classdev *led_cdev,
266 unsigned long *delay_on,
267 unsigned long *delay_off)
268{
269 struct rt2x00_led *led =
270 container_of(led_cdev, struct rt2x00_led, led_dev);
271 u32 reg;
272
273 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
274 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
275 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
276 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
277
278 return 0;
279}
a9450b70
ID		 280#endif /* CONFIG_RT2500PCI_LEDS */
281
95ea3627
ID		 282/*
283 * Configuration handlers.
284 */
3a643d24
ID		 285static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev,
286 const unsigned int filter_flags)
287{
288 u32 reg;
289
290 /*
291 * Start configuration steps.
292 * Note that the version error will always be dropped
293 * and broadcast frames will always be accepted since
294 * there is no filter for it at this time.
295 */
296 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
297 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
298 !(filter_flags & FIF_FCSFAIL));
299 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
300 !(filter_flags & FIF_PLCPFAIL));
301 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
302 !(filter_flags & FIF_CONTROL));
303 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
304 !(filter_flags & FIF_PROMISC_IN_BSS));
305 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
e0b005fa
ID		 306 !(filter_flags & FIF_PROMISC_IN_BSS) &&
307 !rt2x00dev->intf_ap_count);
3a643d24
ID		 308 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
309 rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
310 !(filter_flags & FIF_ALLMULTI));
311 rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
312 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
313}
314
6bb40dd1
ID		 315static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
316 struct rt2x00_intf *intf,
317 struct rt2x00intf_conf *conf,
318 const unsigned int flags)
95ea3627 319{
181d6902 320 struct data_queue *queue =
5957da4c 321 rt2x00queue_get_queue(rt2x00dev, RT2X00_BCN_QUEUE_BEACON);
6bb40dd1 322 unsigned int bcn_preload;
95ea3627
ID		 323 u32 reg;
324
6bb40dd1 325 if (flags & CONFIG_UPDATE_TYPE) {
6bb40dd1
ID		 326 /*
327 * Enable beacon config
328 */
329 bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20);
330 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
331 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
332 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN, queue->cw_min);
333 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
95ea3627 334
6bb40dd1
ID		 335 /*
336 * Enable synchronisation.
337 */
338 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
fd3c91c5 339 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
6bb40dd1 340 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
fd3c91c5 341 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
6bb40dd1
ID		 342 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
343 }
344
345 if (flags & CONFIG_UPDATE_MAC)
346 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
347 conf->mac, sizeof(conf->mac));
348
349 if (flags & CONFIG_UPDATE_BSSID)
350 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
351 conf->bssid, sizeof(conf->bssid));
95ea3627
ID		 352}
353
3a643d24
ID		 354static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
355 struct rt2x00lib_erp *erp)
95ea3627 356{
5c58ee51 357 int preamble_mask;
95ea3627 358 u32 reg;
95ea3627 359
5c58ee51
ID		 360 /*
361 * When short preamble is enabled, we should set bit 0x08
362 */
72810379 363 preamble_mask = erp->short_preamble << 3;
95ea3627
ID		 364
365 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
72810379
ID		 366 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT,
367 erp->ack_timeout);
368 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
369 erp->ack_consume_time);
95ea3627
ID		 370 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
371
95ea3627 372 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
5c58ee51 373 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble_mask);
95ea3627
ID		 374 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
375 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
376 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
377
378 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
5c58ee51 379 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
95ea3627
ID		 380 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
381 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
382 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
383
384 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
5c58ee51 385 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
95ea3627
ID		 386 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
387 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
388 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
389
390 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
5c58ee51 391 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
95ea3627
ID		 392 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
393 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
394 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
395}
396
397static void rt2500pci_config_phymode(struct rt2x00_dev *rt2x00dev,
5c58ee51 398 const int basic_rate_mask)
95ea3627 399{
5c58ee51 400 rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
95ea3627
ID		 401}
402
403static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
5c58ee51 404 struct rf_channel *rf, const int txpower)
95ea3627 405{
95ea3627
ID		 406 u8 r70;
407
95ea3627
ID		 408 /*
409 * Set TXpower.
410 */
5c58ee51 411 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
95ea3627
ID		 412
413 /*
414 * Switch on tuning bits.
415 * For RT2523 devices we do not need to update the R1 register.
416 */
417 if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
5c58ee51
ID		 418 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
419 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
95ea3627
ID		 420
421 /*
422 * For RT2525 we should first set the channel to half band higher.
423 */
424 if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
425 static const u32 vals[] = {
426 0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
427 0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
428 0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
429 0x00080d2e, 0x00080d3a
430 };
431
5c58ee51
ID		 432 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
433 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
434 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
435 if (rf->rf4)
436 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
95ea3627
ID		 437 }
438
5c58ee51
ID		 439 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
440 rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
441 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
442 if (rf->rf4)
443 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
95ea3627
ID		 444
445 /*
446 * Channel 14 requires the Japan filter bit to be set.
447 */
448 r70 = 0x46;
5c58ee51 449 rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
95ea3627
ID		 450 rt2500pci_bbp_write(rt2x00dev, 70, r70);
451
452 msleep(1);
453
454 /*
455 * Switch off tuning bits.
456 * For RT2523 devices we do not need to update the R1 register.
457 */
458 if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) {
5c58ee51
ID		 459 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
460 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
95ea3627
ID		 461 }
462
5c58ee51
ID		 463 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
464 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 465
466 /*
467 * Clear false CRC during channel switch.
468 */
5c58ee51 469 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
95ea3627
ID		 470}
471
472static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
473 const int txpower)
474{
475 u32 rf3;
476
477 rt2x00_rf_read(rt2x00dev, 3, &rf3);
478 rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
479 rt2500pci_rf_write(rt2x00dev, 3, rf3);
480}
481
482static void rt2500pci_config_antenna(struct rt2x00_dev *rt2x00dev,
addc81bd 483 struct antenna_setup *ant)
95ea3627
ID		 484{
485 u32 reg;
486 u8 r14;
487 u8 r2;
488
a4fe07d9
ID		 489 /*
490 * We should never come here because rt2x00lib is supposed
491 * to catch this and send us the correct antenna explicitely.
492 */
493 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
494 ant->tx == ANTENNA_SW_DIVERSITY);
495
95ea3627
ID		 496 rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
497 rt2500pci_bbp_read(rt2x00dev, 14, &r14);
498 rt2500pci_bbp_read(rt2x00dev, 2, &r2);
499
500 /*
501 * Configure the TX antenna.
502 */
addc81bd 503 switch (ant->tx) {
95ea3627
ID		 504 case ANTENNA_A:
505 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
506 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
507 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
508 break;
509 case ANTENNA_B:
a4fe07d9 510 default:
95ea3627
ID		 511 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
512 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
513 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
514 break;
515 }
516
517 /*
518 * Configure the RX antenna.
519 */
addc81bd 520 switch (ant->rx) {
95ea3627
ID		 521 case ANTENNA_A:
522 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
523 break;
524 case ANTENNA_B:
a4fe07d9 525 default:
95ea3627
ID		 526 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
527 break;
528 }
529
530 /*
531 * RT2525E and RT5222 need to flip TX I/Q
532 */
533 if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
534 rt2x00_rf(&rt2x00dev->chip, RF5222)) {
535 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
536 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
537 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
538
539 /*
540 * RT2525E does not need RX I/Q Flip.
541 */
542 if (rt2x00_rf(&rt2x00dev->chip, RF2525E))
543 rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
544 } else {
545 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
546 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
547 }
548
549 rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
550 rt2500pci_bbp_write(rt2x00dev, 14, r14);
551 rt2500pci_bbp_write(rt2x00dev, 2, r2);
552}
553
554static void rt2500pci_config_duration(struct rt2x00_dev *rt2x00dev,
5c58ee51 555 struct rt2x00lib_conf *libconf)
95ea3627
ID		 556{
557 u32 reg;
558
559 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
5c58ee51 560 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
95ea3627
ID		 561 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
562
563 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
5c58ee51
ID		 564 rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
565 rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
95ea3627
ID		 566 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
567
568 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
5c58ee51
ID		 569 rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
570 rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
95ea3627
ID		 571 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
572
573 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
574 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
575 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
576 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
577
578 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
5c58ee51
ID		 579 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
580 libconf->conf->beacon_int * 16);
581 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
582 libconf->conf->beacon_int * 16);
95ea3627
ID		 583 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
584}
585
586static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 587 struct rt2x00lib_conf *libconf,
588 const unsigned int flags)
95ea3627 589{
95ea3627 590 if (flags & CONFIG_UPDATE_PHYMODE)
5c58ee51 591 rt2500pci_config_phymode(rt2x00dev, libconf->basic_rates);
95ea3627 592 if (flags & CONFIG_UPDATE_CHANNEL)
5c58ee51
ID		 593 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
594 libconf->conf->power_level);
95ea3627 595 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
5c58ee51
ID		 596 rt2500pci_config_txpower(rt2x00dev,
597 libconf->conf->power_level);
95ea3627 598 if (flags & CONFIG_UPDATE_ANTENNA)
addc81bd 599 rt2500pci_config_antenna(rt2x00dev, &libconf->ant);
95ea3627 600 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
5c58ee51 601 rt2500pci_config_duration(rt2x00dev, libconf);
95ea3627
ID		 602}
603
95ea3627
ID		 604/*
605 * Link tuning
606 */
ebcf26da
ID		 607static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
608 struct link_qual *qual)
95ea3627
ID		 609{
610 u32 reg;
611
612 /*
613 * Update FCS error count from register.
614 */
615 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
ebcf26da 616 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
95ea3627
ID		 617
618 /*
619 * Update False CCA count from register.
620 */
621 rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
ebcf26da 622 qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
95ea3627
ID		 623}
624
625static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
626{
627 rt2500pci_bbp_write(rt2x00dev, 17, 0x48);
628 rt2x00dev->link.vgc_level = 0x48;
629}
630
631static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev)
632{
633 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
634 u8 r17;
635
636 /*
637 * To prevent collisions with MAC ASIC on chipsets
638 * up to version C the link tuning should halt after 20
6bb40dd1 639 * seconds while being associated.
95ea3627 640 */
755a957d 641 if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D &&
6bb40dd1 642 rt2x00dev->intf_associated &&
95ea3627
ID		 643 rt2x00dev->link.count > 20)
644 return;
645
646 rt2500pci_bbp_read(rt2x00dev, 17, &r17);
647
648 /*
649 * Chipset versions C and lower should directly continue
6bb40dd1
ID		 650 * to the dynamic CCA tuning. Chipset version D and higher
651 * should go straight to dynamic CCA tuning when they
652 * are not associated.
95ea3627 653 */
6bb40dd1
ID		 654 if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D ||
655 !rt2x00dev->intf_associated)
95ea3627
ID		 656 goto dynamic_cca_tune;
657
658 /*
659 * A too low RSSI will cause too much false CCA which will
660 * then corrupt the R17 tuning. To remidy this the tuning should
661 * be stopped (While making sure the R17 value will not exceed limits)
662 */
663 if (rssi < -80 && rt2x00dev->link.count > 20) {
664 if (r17 >= 0x41) {
665 r17 = rt2x00dev->link.vgc_level;
666 rt2500pci_bbp_write(rt2x00dev, 17, r17);
667 }
668 return;
669 }
670
671 /*
672 * Special big-R17 for short distance
673 */
674 if (rssi >= -58) {
675 if (r17 != 0x50)
676 rt2500pci_bbp_write(rt2x00dev, 17, 0x50);
677 return;
678 }
679
680 /*
681 * Special mid-R17 for middle distance
682 */
683 if (rssi >= -74) {
684 if (r17 != 0x41)
685 rt2500pci_bbp_write(rt2x00dev, 17, 0x41);
686 return;
687 }
688
689 /*
690 * Leave short or middle distance condition, restore r17
691 * to the dynamic tuning range.
692 */
693 if (r17 >= 0x41) {
694 rt2500pci_bbp_write(rt2x00dev, 17, rt2x00dev->link.vgc_level);
695 return;
696 }
697
698dynamic_cca_tune:
699
700 /*
701 * R17 is inside the dynamic tuning range,
702 * start tuning the link based on the false cca counter.
703 */
ebcf26da 704 if (rt2x00dev->link.qual.false_cca > 512 && r17 < 0x40) {
95ea3627
ID		 705 rt2500pci_bbp_write(rt2x00dev, 17, ++r17);
706 rt2x00dev->link.vgc_level = r17;
ebcf26da 707 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > 0x32) {
95ea3627
ID		 708 rt2500pci_bbp_write(rt2x00dev, 17, --r17);
709 rt2x00dev->link.vgc_level = r17;
710 }
711}
712
713/*
714 * Initialization functions.
715 */
837e7f24 716static void rt2500pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
181d6902 717 struct queue_entry *entry)
95ea3627 718{
181d6902 719 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
95ea3627
ID		 720 u32 word;
721
181d6902 722 rt2x00_desc_read(priv_rx->desc, 1, &word);
30b3a23c 723 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->data_dma);
181d6902 724 rt2x00_desc_write(priv_rx->desc, 1, word);
95ea3627 725
181d6902 726 rt2x00_desc_read(priv_rx->desc, 0, &word);
837e7f24 727 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
181d6902 728 rt2x00_desc_write(priv_rx->desc, 0, word);
95ea3627
ID		 729}
730
837e7f24 731static void rt2500pci_init_txentry(struct rt2x00_dev *rt2x00dev,
181d6902 732 struct queue_entry *entry)
95ea3627 733{
181d6902 734 struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
95ea3627
ID		 735 u32 word;
736
181d6902 737 rt2x00_desc_read(priv_tx->desc, 1, &word);
30b3a23c 738 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->data_dma);
181d6902 739 rt2x00_desc_write(priv_tx->desc, 1, word);
95ea3627 740
181d6902 741 rt2x00_desc_read(priv_tx->desc, 0, &word);
837e7f24
ID		 742 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
743 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
181d6902 744 rt2x00_desc_write(priv_tx->desc, 0, word);
95ea3627
ID		 745}
746
181d6902 747static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
95ea3627 748{
181d6902
ID		 749 struct queue_entry_priv_pci_rx *priv_rx;
750 struct queue_entry_priv_pci_tx *priv_tx;
95ea3627
ID		 751 u32 reg;
752
95ea3627
ID		 753 /*
754 * Initialize registers.
755 */
756 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
181d6902
ID		 757 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
758 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
759 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
760 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
95ea3627
ID		 761 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
762
181d6902 763 priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
95ea3627 764 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
30b3a23c
ID		 765 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
766 priv_tx->desc_dma);
95ea3627
ID		 767 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
768
181d6902 769 priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
95ea3627 770 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
30b3a23c
ID		 771 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
772 priv_tx->desc_dma);
95ea3627
ID		 773 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
774
181d6902 775 priv_tx = rt2x00dev->bcn[1].entries[0].priv_data;
95ea3627 776 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
30b3a23c
ID		 777 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
778 priv_tx->desc_dma);
95ea3627
ID		 779 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
780
181d6902 781 priv_tx = rt2x00dev->bcn[0].entries[0].priv_data;
95ea3627 782 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
30b3a23c
ID		 783 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
784 priv_tx->desc_dma);
95ea3627
ID		 785 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
786
787 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
788 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
181d6902 789 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
95ea3627
ID		 790 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
791
181d6902 792 priv_rx = rt2x00dev->rx->entries[0].priv_data;
95ea3627 793 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
dac37d72 794 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER, priv_rx->desc_dma);
95ea3627
ID		 795 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
796
797 return 0;
798}
799
800static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
801{
802 u32 reg;
803
804 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
805 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
806 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
807 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
808
809 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
810 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
811 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
812 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
813 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
814
815 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
816 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
817 rt2x00dev->rx->data_size / 128);
818 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
819
820 /*
821 * Always use CWmin and CWmax set in descriptor.
822 */
823 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
824 rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
825 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
826
827 rt2x00pci_register_write(rt2x00dev, CNT3, 0);
828
829 rt2x00pci_register_read(rt2x00dev, TXCSR8, &reg);
830 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
831 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
832 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
833 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
834 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
835 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
836 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
837 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
838 rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
839
840 rt2x00pci_register_read(rt2x00dev, ARTCSR0, &reg);
841 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
842 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
843 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
844 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
845 rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
846
847 rt2x00pci_register_read(rt2x00dev, ARTCSR1, &reg);
848 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
849 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
850 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
851 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
852 rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
853
854 rt2x00pci_register_read(rt2x00dev, ARTCSR2, &reg);
855 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
856 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
857 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
858 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
859 rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
860
861 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
862 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
863 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
864 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
865 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
866 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
867 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
868 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
869 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
870 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
871
872 rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
873 rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
874 rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
875 rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
876 rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
877 rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
878 rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
879 rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
880 rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
881
882 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
883
884 rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
885 rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
886
887 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
888 return -EBUSY;
889
890 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
891 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
892
893 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
894 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
895 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
896
897 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
898 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
899 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
900 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
901 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
902 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
903 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
904 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
905
906 rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
907
908 rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
909
910 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
911 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
912 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
913 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
914 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
915
916 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
917 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
918 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
919 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
920
921 /*
922 * We must clear the FCS and FIFO error count.
923 * These registers are cleared on read,
924 * so we may pass a useless variable to store the value.
925 */
926 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
927 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
928
929 return 0;
930}
931
932static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
933{
934 unsigned int i;
935 u16 eeprom;
936 u8 reg_id;
937 u8 value;
938
939 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
940 rt2500pci_bbp_read(rt2x00dev, 0, &value);
941 if ((value != 0xff) && (value != 0x00))
942 goto continue_csr_init;
943 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
944 udelay(REGISTER_BUSY_DELAY);
945 }
946
947 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
948 return -EACCES;
949
950continue_csr_init:
951 rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
952 rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
953 rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
954 rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
955 rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
956 rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
957 rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
958 rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
959 rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
960 rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
961 rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
962 rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
963 rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
964 rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
965 rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
966 rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
967 rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
968 rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
969 rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
970 rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
971 rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
972 rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
973 rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
974 rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
975 rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
976 rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
977 rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
978 rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
979 rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
980 rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
981
95ea3627
ID		 982 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
983 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
984
985 if (eeprom != 0xffff && eeprom != 0x0000) {
986 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
987 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 988 rt2500pci_bbp_write(rt2x00dev, reg_id, value);
989 }
990 }
95ea3627
ID		 991
992 return 0;
993}
994
995/*
996 * Device state switch handlers.
997 */
998static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
999 enum dev_state state)
1000{
1001 u32 reg;
1002
1003 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1004 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
1005 state == STATE_RADIO_RX_OFF);
1006 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1007}
1008
1009static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1010 enum dev_state state)
1011{
1012 int mask = (state == STATE_RADIO_IRQ_OFF);
1013 u32 reg;
1014
1015 /*
1016 * When interrupts are being enabled, the interrupt registers
1017 * should clear the register to assure a clean state.
1018 */
1019 if (state == STATE_RADIO_IRQ_ON) {
1020 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1021 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1022 }
1023
1024 /*
1025 * Only toggle the interrupts bits we are going to use.
1026 * Non-checked interrupt bits are disabled by default.
1027 */
1028 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1029 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1030 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1031 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1032 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1033 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1034 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1035}
1036
1037static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1038{
1039 /*
1040 * Initialize all registers.
1041 */
181d6902 1042 if (rt2500pci_init_queues(rt2x00dev) ||
95ea3627
ID		 1043 rt2500pci_init_registers(rt2x00dev) ||
1044 rt2500pci_init_bbp(rt2x00dev)) {
1045 ERROR(rt2x00dev, "Register initialization failed.\n");
1046 return -EIO;
1047 }
1048
1049 /*
1050 * Enable interrupts.
1051 */
1052 rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1053
95ea3627
ID		 1054 return 0;
1055}
1056
1057static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1058{
1059 u32 reg;
1060
95ea3627
ID		 1061 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1062
1063 /*
1064 * Disable synchronisation.
1065 */
1066 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1067
1068 /*
1069 * Cancel RX and TX.
1070 */
1071 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1072 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1073 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1074
1075 /*
1076 * Disable interrupts.
1077 */
1078 rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1079}
1080
1081static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1082 enum dev_state state)
1083{
1084 u32 reg;
1085 unsigned int i;
1086 char put_to_sleep;
1087 char bbp_state;
1088 char rf_state;
1089
1090 put_to_sleep = (state != STATE_AWAKE);
1091
1092 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1093 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1094 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1095 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1096 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1097 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1098
1099 /*
1100 * Device is not guaranteed to be in the requested state yet.
1101 * We must wait until the register indicates that the
1102 * device has entered the correct state.
1103 */
1104 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1105 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1106 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1107 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1108 if (bbp_state == state && rf_state == state)
1109 return 0;
1110 msleep(10);
1111 }
1112
1113 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1114 "current device state: bbp %d and rf %d.\n",
1115 state, bbp_state, rf_state);
1116
1117 return -EBUSY;
1118}
1119
1120static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1121 enum dev_state state)
1122{
1123 int retval = 0;
1124
1125 switch (state) {
1126 case STATE_RADIO_ON:
1127 retval = rt2500pci_enable_radio(rt2x00dev);
1128 break;
1129 case STATE_RADIO_OFF:
1130 rt2500pci_disable_radio(rt2x00dev);
1131 break;
1132 case STATE_RADIO_RX_ON:
61667d8d
ID		 1133 case STATE_RADIO_RX_ON_LINK:
1134 rt2500pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
1135 break;
95ea3627 1136 case STATE_RADIO_RX_OFF:
61667d8d
ID		 1137 case STATE_RADIO_RX_OFF_LINK:
1138 rt2500pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
95ea3627
ID		 1139 break;
1140 case STATE_DEEP_SLEEP:
1141 case STATE_SLEEP:
1142 case STATE_STANDBY:
1143 case STATE_AWAKE:
1144 retval = rt2500pci_set_state(rt2x00dev, state);
1145 break;
1146 default:
1147 retval = -ENOTSUPP;
1148 break;
1149 }
1150
1151 return retval;
1152}
1153
1154/*
1155 * TX descriptor initialization
1156 */
1157static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
dd3193e1 1158 struct sk_buff *skb,
181d6902 1159 struct txentry_desc *txdesc,
95ea3627
ID		 1160 struct ieee80211_tx_control *control)
1161{
181d6902 1162 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
dd3193e1 1163 __le32 *txd = skbdesc->desc;
95ea3627
ID		 1164 u32 word;
1165
1166 /*
1167 * Start writing the descriptor words.
1168 */
1169 rt2x00_desc_read(txd, 2, &word);
1170 rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
181d6902
ID		 1171 rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs);
1172 rt2x00_set_field32(&word, TXD_W2_CWMIN, txdesc->cw_min);
1173 rt2x00_set_field32(&word, TXD_W2_CWMAX, txdesc->cw_max);
95ea3627
ID		 1174 rt2x00_desc_write(txd, 2, word);
1175
1176 rt2x00_desc_read(txd, 3, &word);
181d6902
ID		 1177 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1178 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1179 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, txdesc->length_low);
1180 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, txdesc->length_high);
95ea3627
ID		 1181 rt2x00_desc_write(txd, 3, word);
1182
1183 rt2x00_desc_read(txd, 10, &word);
1184 rt2x00_set_field32(&word, TXD_W10_RTS,
181d6902 1185 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
95ea3627
ID		 1186 rt2x00_desc_write(txd, 10, word);
1187
1188 rt2x00_desc_read(txd, 0, &word);
1189 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1190 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1191 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1192 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1193 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1194 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1195 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1196 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1197 rt2x00_set_field32(&word, TXD_W0_OFDM,
181d6902 1198 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
95ea3627 1199 rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
181d6902 1200 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627
ID		 1201 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1202 !!(control->flags &
1203 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
dd3193e1 1204 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
95ea3627
ID		 1205 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1206 rt2x00_desc_write(txd, 0, word);
1207}
1208
1209/*
1210 * TX data initialization
1211 */
1212static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
5957da4c 1213 const unsigned int queue)
95ea3627
ID		 1214{
1215 u32 reg;
1216
5957da4c 1217 if (queue == RT2X00_BCN_QUEUE_BEACON) {
95ea3627
ID		 1218 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1219 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
8af244cc
ID		 1220 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1221 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
95ea3627
ID		 1222 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1223 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1224 }
1225 return;
1226 }
1227
1228 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
ddc827f9
ID		 1229 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO,
1230 (queue == IEEE80211_TX_QUEUE_DATA0));
1231 rt2x00_set_field32(&reg, TXCSR0_KICK_TX,
1232 (queue == IEEE80211_TX_QUEUE_DATA1));
1233 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM,
5957da4c 1234 (queue == RT2X00_BCN_QUEUE_ATIM));
95ea3627
ID		 1235 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1236}
1237
1238/*
1239 * RX control handlers
1240 */
181d6902
ID		 1241static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1242 struct rxdone_entry_desc *rxdesc)
95ea3627 1243{
181d6902 1244 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
95ea3627
ID		 1245 u32 word0;
1246 u32 word2;
1247
181d6902
ID		 1248 rt2x00_desc_read(priv_rx->desc, 0, &word0);
1249 rt2x00_desc_read(priv_rx->desc, 2, &word2);
95ea3627 1250
181d6902 1251 rxdesc->flags = 0;
4150c572 1252 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1253 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
4150c572 1254 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
181d6902
ID		 1255 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1256
89993890
ID		 1257 /*
1258 * Obtain the status about this packet.
1259 * When frame was received with an OFDM bitrate,
1260 * the signal is the PLCP value. If it was received with
1261 * a CCK bitrate the signal is the rate in 100kbit/s.
1262 */
181d6902
ID		 1263 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1264 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1265 entry->queue->rt2x00dev->rssi_offset;
181d6902 1266 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02
ID		 1267
1268 rxdesc->dev_flags = 0;
1269 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1270 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1271 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1272 rxdesc->dev_flags |= RXDONE_MY_BSS;
95ea3627
ID		 1273}
1274
1275/*
1276 * Interrupt functions.
1277 */
181d6902
ID		 1278static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1279 const enum ieee80211_tx_queue queue_idx)
95ea3627 1280{
181d6902
ID		 1281 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1282 struct queue_entry_priv_pci_tx *priv_tx;
1283 struct queue_entry *entry;
1284 struct txdone_entry_desc txdesc;
95ea3627 1285 u32 word;
95ea3627 1286
181d6902
ID		 1287 while (!rt2x00queue_empty(queue)) {
1288 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1289 priv_tx = entry->priv_data;
1290 rt2x00_desc_read(priv_tx->desc, 0, &word);
95ea3627
ID		 1291
1292 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1293 !rt2x00_get_field32(word, TXD_W0_VALID))
1294 break;
1295
1296 /*
1297 * Obtain the status about this packet.
1298 */
181d6902
ID		 1299 txdesc.status = rt2x00_get_field32(word, TXD_W0_RESULT);
1300 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
95ea3627 1301
181d6902 1302 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
95ea3627 1303 }
95ea3627
ID		 1304}
1305
1306static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1307{
1308 struct rt2x00_dev *rt2x00dev = dev_instance;
1309 u32 reg;
1310
1311 /*
1312 * Get the interrupt sources & saved to local variable.
1313 * Write register value back to clear pending interrupts.
1314 */
1315 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1316 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1317
1318 if (!reg)
1319 return IRQ_NONE;
1320
1321 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1322 return IRQ_HANDLED;
1323
1324 /*
1325 * Handle interrupts, walk through all bits
1326 * and run the tasks, the bits are checked in order of
1327 * priority.
1328 */
1329
1330 /*
1331 * 1 - Beacon timer expired interrupt.
1332 */
1333 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1334 rt2x00lib_beacondone(rt2x00dev);
1335
1336 /*
1337 * 2 - Rx ring done interrupt.
1338 */
1339 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1340 rt2x00pci_rxdone(rt2x00dev);
1341
1342 /*
1343 * 3 - Atim ring transmit done interrupt.
1344 */
1345 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
5957da4c 1346 rt2500pci_txdone(rt2x00dev, RT2X00_BCN_QUEUE_ATIM);
95ea3627
ID		 1347
1348 /*
1349 * 4 - Priority ring transmit done interrupt.
1350 */
1351 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1352 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1353
1354 /*
1355 * 5 - Tx ring transmit done interrupt.
1356 */
1357 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1358 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1359
1360 return IRQ_HANDLED;
1361}
1362
1363/*
1364 * Device probe functions.
1365 */
1366static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1367{
1368 struct eeprom_93cx6 eeprom;
1369 u32 reg;
1370 u16 word;
1371 u8 *mac;
1372
1373 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1374
1375 eeprom.data = rt2x00dev;
1376 eeprom.register_read = rt2500pci_eepromregister_read;
1377 eeprom.register_write = rt2500pci_eepromregister_write;
1378 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1379 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1380 eeprom.reg_data_in = 0;
1381 eeprom.reg_data_out = 0;
1382 eeprom.reg_data_clock = 0;
1383 eeprom.reg_chip_select = 0;
1384
1385 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1386 EEPROM_SIZE / sizeof(u16));
1387
1388 /*
1389 * Start validation of the data that has been read.
1390 */
1391 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1392 if (!is_valid_ether_addr(mac)) {
0795af57
JP		 1393 DECLARE_MAC_BUF(macbuf);
1394
95ea3627 1395 random_ether_addr(mac);
0795af57
JP		 1396 EEPROM(rt2x00dev, "MAC: %s\n",
1397 print_mac(macbuf, mac));
95ea3627
ID		 1398 }
1399
1400 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1401 if (word == 0xffff) {
1402 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 1403 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1404 ANTENNA_SW_DIVERSITY);
1405 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1406 ANTENNA_SW_DIVERSITY);
1407 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1408 LED_MODE_DEFAULT);
95ea3627
ID		 1409 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1410 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1411 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1412 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1413 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1414 }
1415
1416 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1417 if (word == 0xffff) {
1418 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1419 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1420 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1421 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1422 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1423 }
1424
1425 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1426 if (word == 0xffff) {
1427 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1428 DEFAULT_RSSI_OFFSET);
1429 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1430 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1431 }
1432
1433 return 0;
1434}
1435
1436static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1437{
1438 u32 reg;
1439 u16 value;
1440 u16 eeprom;
1441
1442 /*
1443 * Read EEPROM word for configuration.
1444 */
1445 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1446
1447 /*
1448 * Identify RF chipset.
1449 */
1450 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1451 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1452 rt2x00_set_chip(rt2x00dev, RT2560, value, reg);
1453
1454 if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
1455 !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
1456 !rt2x00_rf(&rt2x00dev->chip, RF2524) &&
1457 !rt2x00_rf(&rt2x00dev->chip, RF2525) &&
1458 !rt2x00_rf(&rt2x00dev->chip, RF2525E) &&
1459 !rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1460 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1461 return -ENODEV;
1462 }
1463
1464 /*
1465 * Identify default antenna configuration.
1466 */
addc81bd 1467 rt2x00dev->default_ant.tx =
95ea3627 1468 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1469 rt2x00dev->default_ant.rx =
95ea3627
ID		 1470 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1471
1472 /*
1473 * Store led mode, for correct led behaviour.
1474 */
a9450b70
ID		 1475#ifdef CONFIG_RT2500PCI_LEDS
1476 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1477
a2e1d52a
ID		 1478 rt2x00dev->led_radio.rt2x00dev = rt2x00dev;
1479 rt2x00dev->led_radio.type = LED_TYPE_RADIO;
1480 rt2x00dev->led_radio.led_dev.brightness_set =
1481 rt2500pci_brightness_set;
1482 rt2x00dev->led_radio.led_dev.blink_set =
1483 rt2500pci_blink_set;
1484 rt2x00dev->led_radio.flags = LED_INITIALIZED;
1485
1486 if (value == LED_MODE_TXRX_ACTIVITY) {
1487 rt2x00dev->led_qual.rt2x00dev = rt2x00dev;
1488 rt2x00dev->led_radio.type = LED_TYPE_ACTIVITY;
1489 rt2x00dev->led_qual.led_dev.brightness_set =
1490 rt2500pci_brightness_set;
1491 rt2x00dev->led_qual.led_dev.blink_set =
1492 rt2500pci_blink_set;
1493 rt2x00dev->led_qual.flags = LED_INITIALIZED;
a9450b70
ID		 1494 }
1495#endif /* CONFIG_RT2500PCI_LEDS */
95ea3627
ID		 1496
1497 /*
1498 * Detect if this device has an hardware controlled radio.
1499 */
81873e9c 1500#ifdef CONFIG_RT2500PCI_RFKILL
95ea3627 1501 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
066cb637 1502 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
81873e9c 1503#endif /* CONFIG_RT2500PCI_RFKILL */
95ea3627
ID		 1504
1505 /*
1506 * Check if the BBP tuning should be enabled.
1507 */
1508 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1509
1510 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1511 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1512
1513 /*
1514 * Read the RSSI <-> dBm offset information.
1515 */
1516 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1517 rt2x00dev->rssi_offset =
1518 rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1519
1520 return 0;
1521}
1522
1523/*
1524 * RF value list for RF2522
1525 * Supports: 2.4 GHz
1526 */
1527static const struct rf_channel rf_vals_bg_2522[] = {
1528 { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 },
1529 { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 },
1530 { 3, 0x00002050, 0x000c2002, 0x00000101, 0 },
1531 { 4, 0x00002050, 0x000c2016, 0x00000101, 0 },
1532 { 5, 0x00002050, 0x000c202a, 0x00000101, 0 },
1533 { 6, 0x00002050, 0x000c203e, 0x00000101, 0 },
1534 { 7, 0x00002050, 0x000c2052, 0x00000101, 0 },
1535 { 8, 0x00002050, 0x000c2066, 0x00000101, 0 },
1536 { 9, 0x00002050, 0x000c207a, 0x00000101, 0 },
1537 { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1538 { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1539 { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1540 { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1541 { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1542};
1543
1544/*
1545 * RF value list for RF2523
1546 * Supports: 2.4 GHz
1547 */
1548static const struct rf_channel rf_vals_bg_2523[] = {
1549 { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1550 { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1551 { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1552 { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1553 { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1554 { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1555 { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1556 { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1557 { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1558 { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1559 { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1560 { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1561 { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1562 { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1563};
1564
1565/*
1566 * RF value list for RF2524
1567 * Supports: 2.4 GHz
1568 */
1569static const struct rf_channel rf_vals_bg_2524[] = {
1570 { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1571 { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1572 { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1573 { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1574 { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1575 { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1576 { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1577 { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1578 { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1579 { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1580 { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1581 { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1582 { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1583 { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1584};
1585
1586/*
1587 * RF value list for RF2525
1588 * Supports: 2.4 GHz
1589 */
1590static const struct rf_channel rf_vals_bg_2525[] = {
1591 { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1592 { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1593 { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1594 { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1595 { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1596 { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1597 { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1598 { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1599 { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1600 { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1601 { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1602 { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1603 { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1604 { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1605};
1606
1607/*
1608 * RF value list for RF2525e
1609 * Supports: 2.4 GHz
1610 */
1611static const struct rf_channel rf_vals_bg_2525e[] = {
1612 { 1, 0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1613 { 2, 0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1614 { 3, 0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1615 { 4, 0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1616 { 5, 0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1617 { 6, 0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1618 { 7, 0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1619 { 8, 0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1620 { 9, 0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1621 { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1622 { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1623 { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1624 { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1625 { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1626};
1627
1628/*
1629 * RF value list for RF5222
1630 * Supports: 2.4 GHz & 5.2 GHz
1631 */
1632static const struct rf_channel rf_vals_5222[] = {
1633 { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1634 { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1635 { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1636 { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1637 { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1638 { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1639 { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1640 { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1641 { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1642 { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1643 { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1644 { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1645 { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1646 { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1647
1648 /* 802.11 UNI / HyperLan 2 */
1649 { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1650 { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1651 { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1652 { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1653 { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1654 { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1655 { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1656 { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1657
1658 /* 802.11 HyperLan 2 */
1659 { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1660 { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1661 { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1662 { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1663 { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1664 { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1665 { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1666 { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1667 { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1668 { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1669
1670 /* 802.11 UNII */
1671 { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1672 { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1673 { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1674 { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1675 { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1676};
1677
1678static void rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1679{
1680 struct hw_mode_spec *spec = &rt2x00dev->spec;
1681 u8 *txpower;
1682 unsigned int i;
1683
1684 /*
1685 * Initialize all hw fields.
1686 */
4150c572 1687 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
95ea3627
ID		 1688 rt2x00dev->hw->extra_tx_headroom = 0;
1689 rt2x00dev->hw->max_signal = MAX_SIGNAL;
1690 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1691 rt2x00dev->hw->queues = 2;
1692
1693 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1694 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1695 rt2x00_eeprom_addr(rt2x00dev,
1696 EEPROM_MAC_ADDR_0));
1697
1698 /*
1699 * Convert tx_power array in eeprom.
1700 */
1701 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1702 for (i = 0; i < 14; i++)
1703 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1704
1705 /*
1706 * Initialize hw_mode information.
1707 */
31562e80
ID		 1708 spec->supported_bands = SUPPORT_BAND_2GHZ;
1709 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
95ea3627
ID		 1710 spec->tx_power_a = NULL;
1711 spec->tx_power_bg = txpower;
1712 spec->tx_power_default = DEFAULT_TXPOWER;
1713
1714 if (rt2x00_rf(&rt2x00dev->chip, RF2522)) {
1715 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1716 spec->channels = rf_vals_bg_2522;
1717 } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) {
1718 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1719 spec->channels = rf_vals_bg_2523;
1720 } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) {
1721 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1722 spec->channels = rf_vals_bg_2524;
1723 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
1724 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1725 spec->channels = rf_vals_bg_2525;
1726 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
1727 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1728 spec->channels = rf_vals_bg_2525e;
1729 } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
31562e80 1730 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 1731 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1732 spec->channels = rf_vals_5222;
95ea3627
ID		 1733 }
1734}
1735
1736static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1737{
1738 int retval;
1739
1740 /*
1741 * Allocate eeprom data.
1742 */
1743 retval = rt2500pci_validate_eeprom(rt2x00dev);
1744 if (retval)
1745 return retval;
1746
1747 retval = rt2500pci_init_eeprom(rt2x00dev);
1748 if (retval)
1749 return retval;
1750
1751 /*
1752 * Initialize hw specifications.
1753 */
1754 rt2500pci_probe_hw_mode(rt2x00dev);
1755
1756 /*
181d6902 1757 * This device requires the atim queue
95ea3627 1758 */
181d6902 1759 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
95ea3627
ID		 1760
1761 /*
1762 * Set the rssi offset.
1763 */
1764 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1765
1766 return 0;
1767}
1768
1769/*
1770 * IEEE80211 stack callback functions.
1771 */
1772static int rt2500pci_set_retry_limit(struct ieee80211_hw *hw,
1773 u32 short_retry, u32 long_retry)
1774{
1775 struct rt2x00_dev *rt2x00dev = hw->priv;
1776 u32 reg;
1777
1778 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1779 rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1780 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1781 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1782
1783 return 0;
1784}
1785
1786static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1787{
1788 struct rt2x00_dev *rt2x00dev = hw->priv;
1789 u64 tsf;
1790 u32 reg;
1791
1792 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1793 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1794 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1795 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1796
1797 return tsf;
1798}
1799
5957da4c
ID		 1800static int rt2500pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
1801 struct ieee80211_tx_control *control)
1802{
1803 struct rt2x00_dev *rt2x00dev = hw->priv;
1804 struct rt2x00_intf *intf = vif_to_intf(control->vif);
1805 struct queue_entry_priv_pci_tx *priv_tx;
1806 struct skb_frame_desc *skbdesc;
8af244cc 1807 u32 reg;
5957da4c
ID		 1808
1809 if (unlikely(!intf->beacon))
1810 return -ENOBUFS;
1811
1812 priv_tx = intf->beacon->priv_data;
1813
1814 /*
1815 * Fill in skb descriptor
1816 */
1817 skbdesc = get_skb_frame_desc(skb);
1818 memset(skbdesc, 0, sizeof(*skbdesc));
baf26a7e 1819 skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
5957da4c
ID		 1820 skbdesc->data = skb->data;
1821 skbdesc->data_len = skb->len;
1822 skbdesc->desc = priv_tx->desc;
1823 skbdesc->desc_len = intf->beacon->queue->desc_size;
1824 skbdesc->entry = intf->beacon;
1825
8af244cc
ID		 1826 /*
1827 * Disable beaconing while we are reloading the beacon data,
1828 * otherwise we might be sending out invalid data.
1829 */
1830 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1831 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1832 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1833 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1834 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1835
5957da4c
ID		 1836 /*
1837 * mac80211 doesn't provide the control->queue variable
1838 * for beacons. Set our own queue identification so
1839 * it can be used during descriptor initialization.
1840 */
1841 control->queue = RT2X00_BCN_QUEUE_BEACON;
1842 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
1843
1844 /*
1845 * Enable beacon generation.
1846 * Write entire beacon with descriptor to register,
1847 * and kick the beacon generator.
1848 */
1849 memcpy(priv_tx->data, skb->data, skb->len);
1850 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, control->queue);
1851
1852 return 0;
1853}
1854
95ea3627
ID		 1855static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1856{
1857 struct rt2x00_dev *rt2x00dev = hw->priv;
1858 u32 reg;
1859
1860 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1861 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1862}
1863
1864static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1865 .tx = rt2x00mac_tx,
4150c572
JB		 1866 .start = rt2x00mac_start,
1867 .stop = rt2x00mac_stop,
95ea3627
ID		 1868 .add_interface = rt2x00mac_add_interface,
1869 .remove_interface = rt2x00mac_remove_interface,
1870 .config = rt2x00mac_config,
1871 .config_interface = rt2x00mac_config_interface,
3a643d24 1872 .configure_filter = rt2x00mac_configure_filter,
95ea3627
ID		 1873 .get_stats = rt2x00mac_get_stats,
1874 .set_retry_limit = rt2500pci_set_retry_limit,
471b3efd 1875 .bss_info_changed = rt2x00mac_bss_info_changed,
95ea3627
ID		 1876 .conf_tx = rt2x00mac_conf_tx,
1877 .get_tx_stats = rt2x00mac_get_tx_stats,
1878 .get_tsf = rt2500pci_get_tsf,
5957da4c 1879 .beacon_update = rt2500pci_beacon_update,
95ea3627
ID		 1880 .tx_last_beacon = rt2500pci_tx_last_beacon,
1881};
1882
1883static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1884 .irq_handler = rt2500pci_interrupt,
1885 .probe_hw = rt2500pci_probe_hw,
1886 .initialize = rt2x00pci_initialize,
1887 .uninitialize = rt2x00pci_uninitialize,
837e7f24
ID		 1888 .init_rxentry = rt2500pci_init_rxentry,
1889 .init_txentry = rt2500pci_init_txentry,
95ea3627 1890 .set_device_state = rt2500pci_set_device_state,
95ea3627 1891 .rfkill_poll = rt2500pci_rfkill_poll,
95ea3627
ID		 1892 .link_stats = rt2500pci_link_stats,
1893 .reset_tuner = rt2500pci_reset_tuner,
1894 .link_tuner = rt2500pci_link_tuner,
1895 .write_tx_desc = rt2500pci_write_tx_desc,
1896 .write_tx_data = rt2x00pci_write_tx_data,
1897 .kick_tx_queue = rt2500pci_kick_tx_queue,
1898 .fill_rxdone = rt2500pci_fill_rxdone,
3a643d24 1899 .config_filter = rt2500pci_config_filter,
6bb40dd1 1900 .config_intf = rt2500pci_config_intf,
72810379 1901 .config_erp = rt2500pci_config_erp,
95ea3627
ID		 1902 .config = rt2500pci_config,
1903};
1904
181d6902
ID		 1905static const struct data_queue_desc rt2500pci_queue_rx = {
1906 .entry_num = RX_ENTRIES,
1907 .data_size = DATA_FRAME_SIZE,
1908 .desc_size = RXD_DESC_SIZE,
1909 .priv_size = sizeof(struct queue_entry_priv_pci_rx),
1910};
1911
1912static const struct data_queue_desc rt2500pci_queue_tx = {
1913 .entry_num = TX_ENTRIES,
1914 .data_size = DATA_FRAME_SIZE,
1915 .desc_size = TXD_DESC_SIZE,
1916 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1917};
1918
1919static const struct data_queue_desc rt2500pci_queue_bcn = {
1920 .entry_num = BEACON_ENTRIES,
1921 .data_size = MGMT_FRAME_SIZE,
1922 .desc_size = TXD_DESC_SIZE,
1923 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1924};
1925
1926static const struct data_queue_desc rt2500pci_queue_atim = {
1927 .entry_num = ATIM_ENTRIES,
1928 .data_size = DATA_FRAME_SIZE,
1929 .desc_size = TXD_DESC_SIZE,
1930 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1931};
1932
95ea3627 1933static const struct rt2x00_ops rt2500pci_ops = {
2360157c 1934 .name = KBUILD_MODNAME,
6bb40dd1
ID		 1935 .max_sta_intf = 1,
1936 .max_ap_intf = 1,
95ea3627
ID		 1937 .eeprom_size = EEPROM_SIZE,
1938 .rf_size = RF_SIZE,
181d6902
ID		 1939 .rx = &rt2500pci_queue_rx,
1940 .tx = &rt2500pci_queue_tx,
1941 .bcn = &rt2500pci_queue_bcn,
1942 .atim = &rt2500pci_queue_atim,
95ea3627
ID		 1943 .lib = &rt2500pci_rt2x00_ops,
1944 .hw = &rt2500pci_mac80211_ops,
1945#ifdef CONFIG_RT2X00_LIB_DEBUGFS
1946 .debugfs = &rt2500pci_rt2x00debug,
1947#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1948};
1949
1950/*
1951 * RT2500pci module information.
1952 */
1953static struct pci_device_id rt2500pci_device_table[] = {
1954 { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
1955 { 0, }
1956};
1957
1958MODULE_AUTHOR(DRV_PROJECT);
1959MODULE_VERSION(DRV_VERSION);
1960MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1961MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1962MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1963MODULE_LICENSE("GPL");
1964
1965static struct pci_driver rt2500pci_driver = {
2360157c 1966 .name = KBUILD_MODNAME,
95ea3627
ID		 1967 .id_table = rt2500pci_device_table,
1968 .probe = rt2x00pci_probe,
1969 .remove = __devexit_p(rt2x00pci_remove),
1970 .suspend = rt2x00pci_suspend,
1971 .resume = rt2x00pci_resume,
1972};
1973
1974static int __init rt2500pci_init(void)
1975{
1976 return pci_register_driver(&rt2500pci_driver);
1977}
1978
1979static void __exit rt2500pci_exit(void)
1980{
1981 pci_unregister_driver(&rt2500pci_driver);
1982}
1983
1984module_init(rt2500pci_init);
1985module_exit(rt2500pci_exit);
kernel source for telekom puls (alcatel/mediatek)