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mwl8k: properly report rate on received 40MHz packets
[GitHub/MotorolaMobilityLLC/kernel-slsi.git] / drivers / net / wireless / mwl8k.c
CommitLineData
a66098da 1/*
ce9e2e1b
LB		 2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
a66098da 4 *
a145d575 5 * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
a66098da
LB		 6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
3d76e82c 15#include <linux/sched.h>
a66098da
LB		 16#include <linux/spinlock.h>
17#include <linux/list.h>
18#include <linux/pci.h>
19#include <linux/delay.h>
20#include <linux/completion.h>
21#include <linux/etherdevice.h>
22#include <net/mac80211.h>
23#include <linux/moduleparam.h>
24#include <linux/firmware.h>
25#include <linux/workqueue.h>
26
27#define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
28#define MWL8K_NAME KBUILD_MODNAME
a145d575 29#define MWL8K_VERSION "0.10"
a66098da 30
a66098da
LB		 31/* Register definitions */
32#define MWL8K_HIU_GEN_PTR 0x00000c10
ce9e2e1b
LB		 33#define MWL8K_MODE_STA 0x0000005a
34#define MWL8K_MODE_AP 0x000000a5
a66098da 35#define MWL8K_HIU_INT_CODE 0x00000c14
ce9e2e1b
LB		 36#define MWL8K_FWSTA_READY 0xf0f1f2f4
37#define MWL8K_FWAP_READY 0xf1f2f4a5
38#define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
a66098da
LB		 39#define MWL8K_HIU_SCRATCH 0x00000c40
40
41/* Host->device communications */
42#define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
43#define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
44#define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
45#define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
46#define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
ce9e2e1b
LB		 47#define MWL8K_H2A_INT_DUMMY (1 << 20)
48#define MWL8K_H2A_INT_RESET (1 << 15)
49#define MWL8K_H2A_INT_DOORBELL (1 << 1)
50#define MWL8K_H2A_INT_PPA_READY (1 << 0)
a66098da
LB		 51
52/* Device->host communications */
53#define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
54#define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
55#define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
56#define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
57#define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
ce9e2e1b
LB		 58#define MWL8K_A2H_INT_DUMMY (1 << 20)
59#define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
60#define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
61#define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
62#define MWL8K_A2H_INT_RADIO_ON (1 << 6)
63#define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
64#define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
65#define MWL8K_A2H_INT_OPC_DONE (1 << 2)
66#define MWL8K_A2H_INT_RX_READY (1 << 1)
67#define MWL8K_A2H_INT_TX_DONE (1 << 0)
a66098da
LB		 68
69#define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
70 MWL8K_A2H_INT_CHNL_SWITCHED | \
71 MWL8K_A2H_INT_QUEUE_EMPTY | \
72 MWL8K_A2H_INT_RADAR_DETECT | \
73 MWL8K_A2H_INT_RADIO_ON | \
74 MWL8K_A2H_INT_RADIO_OFF | \
75 MWL8K_A2H_INT_MAC_EVENT | \
76 MWL8K_A2H_INT_OPC_DONE | \
77 MWL8K_A2H_INT_RX_READY | \
78 MWL8K_A2H_INT_TX_DONE)
79
a66098da
LB		 80#define MWL8K_RX_QUEUES 1
81#define MWL8K_TX_QUEUES 4
82
54bc3a0d
LB		 83struct rxd_ops {
84 int rxd_size;
85 void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
86 void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
20f09c3d
LB		 87 int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status,
88 __le16 *qos);
54bc3a0d
LB		 89};
90
45a390dd 91struct mwl8k_device_info {
a74b295e
LB		 92 char *part_name;
93 char *helper_image;
94 char *fw_image;
54bc3a0d 95 struct rxd_ops *rxd_ops;
547810e3 96 u16 modes;
45a390dd
LB		 97};
98
a66098da 99struct mwl8k_rx_queue {
45eb400d 100 int rxd_count;
a66098da
LB		 101
102 /* hw receives here */
45eb400d 103 int head;
a66098da
LB		 104
105 /* refill descs here */
45eb400d 106 int tail;
a66098da 107
54bc3a0d 108 void *rxd;
45eb400d 109 dma_addr_t rxd_dma;
788838eb
LB		 110 struct {
111 struct sk_buff *skb;
112 DECLARE_PCI_UNMAP_ADDR(dma)
113 } *buf;
a66098da
LB		 114};
115
a66098da
LB		 116struct mwl8k_tx_queue {
117 /* hw transmits here */
45eb400d 118 int head;
a66098da
LB		 119
120 /* sw appends here */
45eb400d 121 int tail;
a66098da 122
45eb400d
LB		 123 struct ieee80211_tx_queue_stats stats;
124 struct mwl8k_tx_desc *txd;
125 dma_addr_t txd_dma;
126 struct sk_buff **skb;
a66098da
LB		 127};
128
129/* Pointers to the firmware data and meta information about it. */
130struct mwl8k_firmware {
a66098da
LB		 131 /* Boot helper code */
132 struct firmware *helper;
a74b295e
LB		 133
134 /* Microcode */
135 struct firmware *ucode;
a66098da
LB		 136};
137
138struct mwl8k_priv {
5b9482dd 139 void __iomem *sram;
a66098da
LB		 140 void __iomem *regs;
141 struct ieee80211_hw *hw;
142
143 struct pci_dev *pdev;
a66098da 144
45a390dd 145 struct mwl8k_device_info *device_info;
eae74e65 146 bool ap_fw;
54bc3a0d 147 struct rxd_ops *rxd_ops;
45a390dd 148
a66098da
LB		 149 /* firmware files and meta data */
150 struct mwl8k_firmware fw;
a66098da 151
618952a7
LB		 152 /* firmware access */
153 struct mutex fw_mutex;
154 struct task_struct *fw_mutex_owner;
155 int fw_mutex_depth;
618952a7
LB		 156 struct completion *hostcmd_wait;
157
a66098da
LB		 158 /* lock held over TX and TX reap */
159 spinlock_t tx_lock;
a66098da 160
88de754a
LB		 161 /* TX quiesce completion, protected by fw_mutex and tx_lock */
162 struct completion *tx_wait;
163
a66098da 164 struct ieee80211_vif *vif;
a66098da
LB		 165
166 struct ieee80211_channel *current_channel;
167
168 /* power management status cookie from firmware */
169 u32 *cookie;
170 dma_addr_t cookie_dma;
171
172 u16 num_mcaddrs;
a66098da 173 u8 hw_rev;
2aa7b01f 174 u32 fw_rev;
a66098da
LB		 175
176 /*
177 * Running count of TX packets in flight, to avoid
178 * iterating over the transmit rings each time.
179 */
180 int pending_tx_pkts;
181
182 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
183 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
184
185 /* PHY parameters */
186 struct ieee80211_supported_band band;
187 struct ieee80211_channel channels[14];
140eb5e2 188 struct ieee80211_rate rates[14];
a66098da 189
c46563b7 190 bool radio_on;
68ce3884 191 bool radio_short_preamble;
a43c49a8 192 bool sniffer_enabled;
0439b1f5 193 bool wmm_enabled;
a66098da 194
a66098da
LB		 195 /* XXX need to convert this to handle multiple interfaces */
196 bool capture_beacon;
d89173f2 197 u8 capture_bssid[ETH_ALEN];
a66098da
LB		 198 struct sk_buff *beacon_skb;
199
200 /*
201 * This FJ worker has to be global as it is scheduled from the
202 * RX handler. At this point we don't know which interface it
203 * belongs to until the list of bssids waiting to complete join
204 * is checked.
205 */
206 struct work_struct finalize_join_worker;
207
208 /* Tasklet to reclaim TX descriptors and buffers after tx */
209 struct tasklet_struct tx_reclaim_task;
a66098da
LB		 210};
211
212/* Per interface specific private data */
213struct mwl8k_vif {
a66098da
LB		 214 /* backpointer to parent config block */
215 struct mwl8k_priv *priv;
216
217 /* BSS config of AP or IBSS from mac80211*/
218 struct ieee80211_bss_conf bss_info;
219
220 /* BSSID of AP or IBSS */
d89173f2
LB		 221 u8 bssid[ETH_ALEN];
222 u8 mac_addr[ETH_ALEN];
a66098da 223
a66098da
LB		 224 /* Index into station database.Returned by update_sta_db call */
225 u8 peer_id;
226
227 /* Non AMPDU sequence number assigned by driver */
228 u16 seqno;
a66098da
LB		 229};
230
a94cc97e 231#define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
a66098da
LB		 232
233static const struct ieee80211_channel mwl8k_channels[] = {
234 { .center_freq = 2412, .hw_value = 1, },
235 { .center_freq = 2417, .hw_value = 2, },
236 { .center_freq = 2422, .hw_value = 3, },
237 { .center_freq = 2427, .hw_value = 4, },
238 { .center_freq = 2432, .hw_value = 5, },
239 { .center_freq = 2437, .hw_value = 6, },
240 { .center_freq = 2442, .hw_value = 7, },
241 { .center_freq = 2447, .hw_value = 8, },
242 { .center_freq = 2452, .hw_value = 9, },
243 { .center_freq = 2457, .hw_value = 10, },
244 { .center_freq = 2462, .hw_value = 11, },
245};
246
247static const struct ieee80211_rate mwl8k_rates[] = {
248 { .bitrate = 10, .hw_value = 2, },
249 { .bitrate = 20, .hw_value = 4, },
250 { .bitrate = 55, .hw_value = 11, },
5dfd3e2c
LB		 251 { .bitrate = 110, .hw_value = 22, },
252 { .bitrate = 220, .hw_value = 44, },
a66098da
LB		 253 { .bitrate = 60, .hw_value = 12, },
254 { .bitrate = 90, .hw_value = 18, },
a66098da
LB		 255 { .bitrate = 120, .hw_value = 24, },
256 { .bitrate = 180, .hw_value = 36, },
257 { .bitrate = 240, .hw_value = 48, },
258 { .bitrate = 360, .hw_value = 72, },
259 { .bitrate = 480, .hw_value = 96, },
260 { .bitrate = 540, .hw_value = 108, },
140eb5e2
LB		 261 { .bitrate = 720, .hw_value = 144, },
262};
263
264static const u8 mwl8k_rateids[12] = {
265 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108,
a66098da
LB		 266};
267
a66098da
LB		 268/* Set or get info from Firmware */
269#define MWL8K_CMD_SET 0x0001
270#define MWL8K_CMD_GET 0x0000
271
272/* Firmware command codes */
273#define MWL8K_CMD_CODE_DNLD 0x0001
274#define MWL8K_CMD_GET_HW_SPEC 0x0003
42fba21d 275#define MWL8K_CMD_SET_HW_SPEC 0x0004
a66098da
LB		 276#define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
277#define MWL8K_CMD_GET_STAT 0x0014
ff45fc60
LB		 278#define MWL8K_CMD_RADIO_CONTROL 0x001c
279#define MWL8K_CMD_RF_TX_POWER 0x001e
08b06347 280#define MWL8K_CMD_RF_ANTENNA 0x0020
a66098da
LB		 281#define MWL8K_CMD_SET_PRE_SCAN 0x0107
282#define MWL8K_CMD_SET_POST_SCAN 0x0108
ff45fc60
LB		 283#define MWL8K_CMD_SET_RF_CHANNEL 0x010a
284#define MWL8K_CMD_SET_AID 0x010d
285#define MWL8K_CMD_SET_RATE 0x0110
286#define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
287#define MWL8K_CMD_RTS_THRESHOLD 0x0113
a66098da 288#define MWL8K_CMD_SET_SLOT 0x0114
ff45fc60
LB		 289#define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
290#define MWL8K_CMD_SET_WMM_MODE 0x0123
a66098da 291#define MWL8K_CMD_MIMO_CONFIG 0x0125
ff45fc60 292#define MWL8K_CMD_USE_FIXED_RATE 0x0126
a66098da 293#define MWL8K_CMD_ENABLE_SNIFFER 0x0150
32060e1b 294#define MWL8K_CMD_SET_MAC_ADDR 0x0202
a66098da 295#define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
ff45fc60 296#define MWL8K_CMD_UPDATE_STADB 0x1123
a66098da
LB		 297
298static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
299{
300#define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
301 snprintf(buf, bufsize, "%s", #x);\
302 return buf;\
303 } while (0)
ce9e2e1b 304 switch (cmd & ~0x8000) {
a66098da
LB		 305 MWL8K_CMDNAME(CODE_DNLD);
306 MWL8K_CMDNAME(GET_HW_SPEC);
42fba21d 307 MWL8K_CMDNAME(SET_HW_SPEC);
a66098da
LB		 308 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
309 MWL8K_CMDNAME(GET_STAT);
310 MWL8K_CMDNAME(RADIO_CONTROL);
311 MWL8K_CMDNAME(RF_TX_POWER);
08b06347 312 MWL8K_CMDNAME(RF_ANTENNA);
a66098da
LB		 313 MWL8K_CMDNAME(SET_PRE_SCAN);
314 MWL8K_CMDNAME(SET_POST_SCAN);
315 MWL8K_CMDNAME(SET_RF_CHANNEL);
ff45fc60
LB		 316 MWL8K_CMDNAME(SET_AID);
317 MWL8K_CMDNAME(SET_RATE);
318 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
319 MWL8K_CMDNAME(RTS_THRESHOLD);
a66098da 320 MWL8K_CMDNAME(SET_SLOT);
ff45fc60
LB		 321 MWL8K_CMDNAME(SET_EDCA_PARAMS);
322 MWL8K_CMDNAME(SET_WMM_MODE);
a66098da 323 MWL8K_CMDNAME(MIMO_CONFIG);
ff45fc60 324 MWL8K_CMDNAME(USE_FIXED_RATE);
a66098da 325 MWL8K_CMDNAME(ENABLE_SNIFFER);
32060e1b 326 MWL8K_CMDNAME(SET_MAC_ADDR);
a66098da 327 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
ff45fc60 328 MWL8K_CMDNAME(UPDATE_STADB);
a66098da
LB		 329 default:
330 snprintf(buf, bufsize, "0x%x", cmd);
331 }
332#undef MWL8K_CMDNAME
333
334 return buf;
335}
336
337/* Hardware and firmware reset */
338static void mwl8k_hw_reset(struct mwl8k_priv *priv)
339{
340 iowrite32(MWL8K_H2A_INT_RESET,
341 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
342 iowrite32(MWL8K_H2A_INT_RESET,
343 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
344 msleep(20);
345}
346
347/* Release fw image */
348static void mwl8k_release_fw(struct firmware **fw)
349{
350 if (*fw == NULL)
351 return;
352 release_firmware(*fw);
353 *fw = NULL;
354}
355
356static void mwl8k_release_firmware(struct mwl8k_priv *priv)
357{
358 mwl8k_release_fw(&priv->fw.ucode);
359 mwl8k_release_fw(&priv->fw.helper);
360}
361
362/* Request fw image */
363static int mwl8k_request_fw(struct mwl8k_priv *priv,
c2c357ce 364 const char *fname, struct firmware **fw)
a66098da
LB		 365{
366 /* release current image */
367 if (*fw != NULL)
368 mwl8k_release_fw(fw);
369
370 return request_firmware((const struct firmware **)fw,
c2c357ce 371 fname, &priv->pdev->dev);
a66098da
LB		 372}
373
45a390dd 374static int mwl8k_request_firmware(struct mwl8k_priv *priv)
a66098da 375{
a74b295e 376 struct mwl8k_device_info *di = priv->device_info;
a66098da
LB		 377 int rc;
378
a74b295e
LB		 379 if (di->helper_image != NULL) {
380 rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw.helper);
381 if (rc) {
382 printk(KERN_ERR "%s: Error requesting helper "
383 "firmware file %s\n", pci_name(priv->pdev),
384 di->helper_image);
385 return rc;
386 }
a66098da
LB		 387 }
388
a74b295e 389 rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw.ucode);
a66098da 390 if (rc) {
c2c357ce 391 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
a74b295e 392 pci_name(priv->pdev), di->fw_image);
a66098da
LB		 393 mwl8k_release_fw(&priv->fw.helper);
394 return rc;
395 }
396
397 return 0;
398}
399
7e75b942
BH		 400MODULE_FIRMWARE("mwl8k/helper_8687.fw");
401MODULE_FIRMWARE("mwl8k/fmimage_8687.fw");
402
a66098da
LB		 403struct mwl8k_cmd_pkt {
404 __le16 code;
405 __le16 length;
406 __le16 seq_num;
407 __le16 result;
408 char payload[0];
409} __attribute__((packed));
410
411/*
412 * Firmware loading.
413 */
414static int
415mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
416{
417 void __iomem *regs = priv->regs;
418 dma_addr_t dma_addr;
a66098da
LB		 419 int loops;
420
421 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
422 if (pci_dma_mapping_error(priv->pdev, dma_addr))
423 return -ENOMEM;
424
425 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
426 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
427 iowrite32(MWL8K_H2A_INT_DOORBELL,
428 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
429 iowrite32(MWL8K_H2A_INT_DUMMY,
430 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
431
a66098da
LB		 432 loops = 1000;
433 do {
434 u32 int_code;
435
436 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
437 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
438 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
a66098da
LB		 439 break;
440 }
441
3d76e82c 442 cond_resched();
a66098da
LB		 443 udelay(1);
444 } while (--loops);
445
446 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
447
d4b70570 448 return loops ? 0 : -ETIMEDOUT;
a66098da
LB		 449}
450
451static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
452 const u8 *data, size_t length)
453{
454 struct mwl8k_cmd_pkt *cmd;
455 int done;
456 int rc = 0;
457
458 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
459 if (cmd == NULL)
460 return -ENOMEM;
461
462 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
463 cmd->seq_num = 0;
464 cmd->result = 0;
465
466 done = 0;
467 while (length) {
468 int block_size = length > 256 ? 256 : length;
469
470 memcpy(cmd->payload, data + done, block_size);
471 cmd->length = cpu_to_le16(block_size);
472
473 rc = mwl8k_send_fw_load_cmd(priv, cmd,
474 sizeof(*cmd) + block_size);
475 if (rc)
476 break;
477
478 done += block_size;
479 length -= block_size;
480 }
481
482 if (!rc) {
483 cmd->length = 0;
484 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
485 }
486
487 kfree(cmd);
488
489 return rc;
490}
491
492static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
493 const u8 *data, size_t length)
494{
495 unsigned char *buffer;
496 int may_continue, rc = 0;
497 u32 done, prev_block_size;
498
499 buffer = kmalloc(1024, GFP_KERNEL);
500 if (buffer == NULL)
501 return -ENOMEM;
502
503 done = 0;
504 prev_block_size = 0;
505 may_continue = 1000;
506 while (may_continue > 0) {
507 u32 block_size;
508
509 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
510 if (block_size & 1) {
511 block_size &= ~1;
512 may_continue--;
513 } else {
514 done += prev_block_size;
515 length -= prev_block_size;
516 }
517
518 if (block_size > 1024 || block_size > length) {
519 rc = -EOVERFLOW;
520 break;
521 }
522
523 if (length == 0) {
524 rc = 0;
525 break;
526 }
527
528 if (block_size == 0) {
529 rc = -EPROTO;
530 may_continue--;
531 udelay(1);
532 continue;
533 }
534
535 prev_block_size = block_size;
536 memcpy(buffer, data + done, block_size);
537
538 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
539 if (rc)
540 break;
541 }
542
543 if (!rc && length != 0)
544 rc = -EREMOTEIO;
545
546 kfree(buffer);
547
548 return rc;
549}
550
c2c357ce 551static int mwl8k_load_firmware(struct ieee80211_hw *hw)
a66098da 552{
c2c357ce
LB		 553 struct mwl8k_priv *priv = hw->priv;
554 struct firmware *fw = priv->fw.ucode;
eae74e65 555 struct mwl8k_device_info *di = priv->device_info;
c2c357ce
LB		 556 int rc;
557 int loops;
558
559 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
560 struct firmware *helper = priv->fw.helper;
a66098da 561
c2c357ce
LB		 562 if (helper == NULL) {
563 printk(KERN_ERR "%s: helper image needed but none "
564 "given\n", pci_name(priv->pdev));
565 return -EINVAL;
566 }
a66098da 567
c2c357ce 568 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
a66098da
LB		 569 if (rc) {
570 printk(KERN_ERR "%s: unable to load firmware "
c2c357ce 571 "helper image\n", pci_name(priv->pdev));
a66098da
LB		 572 return rc;
573 }
574 msleep(1);
575
c2c357ce 576 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
a66098da 577 } else {
c2c357ce 578 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
a66098da
LB		 579 }
580
581 if (rc) {
c2c357ce
LB		 582 printk(KERN_ERR "%s: unable to load firmware image\n",
583 pci_name(priv->pdev));
a66098da
LB		 584 return rc;
585 }
586
eae74e65
LB		 587 if (di->modes & BIT(NL80211_IFTYPE_AP))
588 iowrite32(MWL8K_MODE_AP, priv->regs + MWL8K_HIU_GEN_PTR);
589 else
590 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
a66098da
LB		 591 msleep(1);
592
593 loops = 200000;
594 do {
eae74e65
LB		 595 u32 ready_code;
596
597 ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
598 if (ready_code == MWL8K_FWAP_READY) {
599 priv->ap_fw = 1;
600 break;
601 } else if (ready_code == MWL8K_FWSTA_READY) {
602 priv->ap_fw = 0;
a66098da 603 break;
eae74e65
LB		 604 }
605
606 cond_resched();
a66098da
LB		 607 udelay(1);
608 } while (--loops);
609
610 return loops ? 0 : -ETIMEDOUT;
611}
612
613
614/*
615 * Defines shared between transmission and reception.
616 */
617/* HT control fields for firmware */
618struct ewc_ht_info {
619 __le16 control1;
620 __le16 control2;
621 __le16 control3;
622} __attribute__((packed));
623
624/* Firmware Station database operations */
625#define MWL8K_STA_DB_ADD_ENTRY 0
626#define MWL8K_STA_DB_MODIFY_ENTRY 1
627#define MWL8K_STA_DB_DEL_ENTRY 2
628#define MWL8K_STA_DB_FLUSH 3
629
630/* Peer Entry flags - used to define the type of the peer node */
631#define MWL8K_PEER_TYPE_ACCESSPOINT 2
a66098da 632
a66098da
LB		 633struct peer_capability_info {
634 /* Peer type - AP vs. STA. */
635 __u8 peer_type;
636
637 /* Basic 802.11 capabilities from assoc resp. */
638 __le16 basic_caps;
639
640 /* Set if peer supports 802.11n high throughput (HT). */
641 __u8 ht_support;
642
643 /* Valid if HT is supported. */
644 __le16 ht_caps;
645 __u8 extended_ht_caps;
646 struct ewc_ht_info ewc_info;
647
648 /* Legacy rate table. Intersection of our rates and peer rates. */
140eb5e2 649 __u8 legacy_rates[12];
a66098da
LB		 650
651 /* HT rate table. Intersection of our rates and peer rates. */
0b5351a8 652 __u8 ht_rates[16];
c23b5a69 653 __u8 pad[16];
a66098da
LB		 654
655 /* If set, interoperability mode, no proprietary extensions. */
656 __u8 interop;
657 __u8 pad2;
658 __u8 station_id;
659 __le16 amsdu_enabled;
660} __attribute__((packed));
661
662/* Inline functions to manipulate QoS field in data descriptor. */
a66098da
LB		 663static inline u16 mwl8k_qos_setbit_eosp(u16 qos)
664{
665 u16 val_mask = 1 << 4;
666
667 /* End of Service Period Bit 4 */
668 return qos | val_mask;
669}
670
671static inline u16 mwl8k_qos_setbit_ack(u16 qos, u8 ack_policy)
672{
673 u16 val_mask = 0x3;
674 u8 shift = 5;
675 u16 qos_mask = ~(val_mask << shift);
676
677 /* Ack Policy Bit 5-6 */
678 return (qos & qos_mask) | ((ack_policy & val_mask) << shift);
679}
680
681static inline u16 mwl8k_qos_setbit_amsdu(u16 qos)
682{
683 u16 val_mask = 1 << 7;
684
685 /* AMSDU present Bit 7 */
686 return qos | val_mask;
687}
688
689static inline u16 mwl8k_qos_setbit_qlen(u16 qos, u8 len)
690{
691 u16 val_mask = 0xff;
692 u8 shift = 8;
693 u16 qos_mask = ~(val_mask << shift);
694
695 /* Queue Length Bits 8-15 */
696 return (qos & qos_mask) | ((len & val_mask) << shift);
697}
698
699/* DMA header used by firmware and hardware. */
700struct mwl8k_dma_data {
701 __le16 fwlen;
702 struct ieee80211_hdr wh;
20f09c3d 703 char data[0];
a66098da
LB		 704} __attribute__((packed));
705
706/* Routines to add/remove DMA header from skb. */
20f09c3d 707static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos)
a66098da 708{
20f09c3d
LB		 709 struct mwl8k_dma_data *tr;
710 int hdrlen;
711
712 tr = (struct mwl8k_dma_data *)skb->data;
713 hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
714
715 if (hdrlen != sizeof(tr->wh)) {
716 if (ieee80211_is_data_qos(tr->wh.frame_control)) {
717 memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2);
718 *((__le16 *)(tr->data - 2)) = qos;
719 } else {
720 memmove(tr->data - hdrlen, &tr->wh, hdrlen);
721 }
a66098da 722 }
20f09c3d
LB		 723
724 if (hdrlen != sizeof(*tr))
725 skb_pull(skb, sizeof(*tr) - hdrlen);
a66098da
LB		 726}
727
76266b2a 728static inline void mwl8k_add_dma_header(struct sk_buff *skb)
a66098da
LB		 729{
730 struct ieee80211_hdr *wh;
ca009301 731 int hdrlen;
a66098da
LB		 732 struct mwl8k_dma_data *tr;
733
ca009301
LB		 734 /*
735 * Add a firmware DMA header; the firmware requires that we
736 * present a 2-byte payload length followed by a 4-address
737 * header (without QoS field), followed (optionally) by any
738 * WEP/ExtIV header (but only filled in for CCMP).
739 */
a66098da 740 wh = (struct ieee80211_hdr *)skb->data;
ca009301 741
a66098da 742 hdrlen = ieee80211_hdrlen(wh->frame_control);
ca009301
LB		 743 if (hdrlen != sizeof(*tr))
744 skb_push(skb, sizeof(*tr) - hdrlen);
a66098da 745
ca009301
LB		 746 if (ieee80211_is_data_qos(wh->frame_control))
747 hdrlen -= 2;
a66098da
LB		 748
749 tr = (struct mwl8k_dma_data *)skb->data;
750 if (wh != &tr->wh)
751 memmove(&tr->wh, wh, hdrlen);
ca009301
LB		 752 if (hdrlen != sizeof(tr->wh))
753 memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen);
a66098da
LB		 754
755 /*
756 * Firmware length is the length of the fully formed "802.11
757 * payload". That is, everything except for the 802.11 header.
758 * This includes all crypto material including the MIC.
759 */
ca009301 760 tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr));
a66098da
LB		 761}
762
763
764/*
6f6d1e9a
LB		 765 * Packet reception for 88w8366.
766 */
767struct mwl8k_rxd_8366 {
768 __le16 pkt_len;
769 __u8 sq2;
770 __u8 rate;
771 __le32 pkt_phys_addr;
772 __le32 next_rxd_phys_addr;
773 __le16 qos_control;
774 __le16 htsig2;
775 __le32 hw_rssi_info;
776 __le32 hw_noise_floor_info;
777 __u8 noise_floor;
778 __u8 pad0[3];
779 __u8 rssi;
780 __u8 rx_status;
781 __u8 channel;
782 __u8 rx_ctrl;
783} __attribute__((packed));
784
8e9f33f0
LB		 785#define MWL8K_8366_RATE_INFO_MCS_FORMAT 0x80
786#define MWL8K_8366_RATE_INFO_40MHZ 0x40
787#define MWL8K_8366_RATE_INFO_RATEID(x) ((x) & 0x3f)
788
6f6d1e9a
LB		 789#define MWL8K_8366_RX_CTRL_OWNED_BY_HOST 0x80
790
791static void mwl8k_rxd_8366_init(void *_rxd, dma_addr_t next_dma_addr)
792{
793 struct mwl8k_rxd_8366 *rxd = _rxd;
794
795 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
796 rxd->rx_ctrl = MWL8K_8366_RX_CTRL_OWNED_BY_HOST;
797}
798
799static void mwl8k_rxd_8366_refill(void *_rxd, dma_addr_t addr, int len)
800{
801 struct mwl8k_rxd_8366 *rxd = _rxd;
802
803 rxd->pkt_len = cpu_to_le16(len);
804 rxd->pkt_phys_addr = cpu_to_le32(addr);
805 wmb();
806 rxd->rx_ctrl = 0;
807}
808
809static int
20f09c3d
LB		 810mwl8k_rxd_8366_process(void *_rxd, struct ieee80211_rx_status *status,
811 __le16 *qos)
6f6d1e9a
LB		 812{
813 struct mwl8k_rxd_8366 *rxd = _rxd;
814
815 if (!(rxd->rx_ctrl & MWL8K_8366_RX_CTRL_OWNED_BY_HOST))
816 return -1;
817 rmb();
818
819 memset(status, 0, sizeof(*status));
820
821 status->signal = -rxd->rssi;
822 status->noise = -rxd->noise_floor;
823
8e9f33f0 824 if (rxd->rate & MWL8K_8366_RATE_INFO_MCS_FORMAT) {
6f6d1e9a 825 status->flag |= RX_FLAG_HT;
8e9f33f0
LB		 826 if (rxd->rate & MWL8K_8366_RATE_INFO_40MHZ)
827 status->flag |= RX_FLAG_40MHZ;
828 status->rate_idx = MWL8K_8366_RATE_INFO_RATEID(rxd->rate);
6f6d1e9a
LB		 829 } else {
830 int i;
831
832 for (i = 0; i < ARRAY_SIZE(mwl8k_rates); i++) {
833 if (mwl8k_rates[i].hw_value == rxd->rate) {
834 status->rate_idx = i;
835 break;
836 }
837 }
838 }
839
840 status->band = IEEE80211_BAND_2GHZ;
841 status->freq = ieee80211_channel_to_frequency(rxd->channel);
842
20f09c3d
LB		 843 *qos = rxd->qos_control;
844
6f6d1e9a
LB		 845 return le16_to_cpu(rxd->pkt_len);
846}
847
848static struct rxd_ops rxd_8366_ops = {
849 .rxd_size = sizeof(struct mwl8k_rxd_8366),
850 .rxd_init = mwl8k_rxd_8366_init,
851 .rxd_refill = mwl8k_rxd_8366_refill,
852 .rxd_process = mwl8k_rxd_8366_process,
853};
854
855/*
856 * Packet reception for 88w8687.
a66098da 857 */
54bc3a0d 858struct mwl8k_rxd_8687 {
a66098da
LB		 859 __le16 pkt_len;
860 __u8 link_quality;
861 __u8 noise_level;
862 __le32 pkt_phys_addr;
45eb400d 863 __le32 next_rxd_phys_addr;
a66098da
LB		 864 __le16 qos_control;
865 __le16 rate_info;
866 __le32 pad0[4];
867 __u8 rssi;
868 __u8 channel;
869 __le16 pad1;
870 __u8 rx_ctrl;
871 __u8 rx_status;
872 __u8 pad2[2];
873} __attribute__((packed));
874
54bc3a0d
LB		 875#define MWL8K_8687_RATE_INFO_SHORTPRE 0x8000
876#define MWL8K_8687_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
877#define MWL8K_8687_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
878#define MWL8K_8687_RATE_INFO_40MHZ 0x0004
879#define MWL8K_8687_RATE_INFO_SHORTGI 0x0002
880#define MWL8K_8687_RATE_INFO_MCS_FORMAT 0x0001
881
882#define MWL8K_8687_RX_CTRL_OWNED_BY_HOST 0x02
883
884static void mwl8k_rxd_8687_init(void *_rxd, dma_addr_t next_dma_addr)
885{
886 struct mwl8k_rxd_8687 *rxd = _rxd;
887
888 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
889 rxd->rx_ctrl = MWL8K_8687_RX_CTRL_OWNED_BY_HOST;
890}
891
892static void mwl8k_rxd_8687_refill(void *_rxd, dma_addr_t addr, int len)
893{
894 struct mwl8k_rxd_8687 *rxd = _rxd;
895
896 rxd->pkt_len = cpu_to_le16(len);
897 rxd->pkt_phys_addr = cpu_to_le32(addr);
898 wmb();
899 rxd->rx_ctrl = 0;
900}
901
902static int
20f09c3d
LB		 903mwl8k_rxd_8687_process(void *_rxd, struct ieee80211_rx_status *status,
904 __le16 *qos)
54bc3a0d
LB		 905{
906 struct mwl8k_rxd_8687 *rxd = _rxd;
907 u16 rate_info;
908
909 if (!(rxd->rx_ctrl & MWL8K_8687_RX_CTRL_OWNED_BY_HOST))
910 return -1;
911 rmb();
912
913 rate_info = le16_to_cpu(rxd->rate_info);
914
915 memset(status, 0, sizeof(*status));
916
917 status->signal = -rxd->rssi;
918 status->noise = -rxd->noise_level;
919 status->qual = rxd->link_quality;
920 status->antenna = MWL8K_8687_RATE_INFO_ANTSELECT(rate_info);
921 status->rate_idx = MWL8K_8687_RATE_INFO_RATEID(rate_info);
922
923 if (rate_info & MWL8K_8687_RATE_INFO_SHORTPRE)
924 status->flag |= RX_FLAG_SHORTPRE;
925 if (rate_info & MWL8K_8687_RATE_INFO_40MHZ)
926 status->flag |= RX_FLAG_40MHZ;
927 if (rate_info & MWL8K_8687_RATE_INFO_SHORTGI)
928 status->flag |= RX_FLAG_SHORT_GI;
929 if (rate_info & MWL8K_8687_RATE_INFO_MCS_FORMAT)
930 status->flag |= RX_FLAG_HT;
931
932 status->band = IEEE80211_BAND_2GHZ;
933 status->freq = ieee80211_channel_to_frequency(rxd->channel);
934
20f09c3d
LB		 935 *qos = rxd->qos_control;
936
54bc3a0d
LB		 937 return le16_to_cpu(rxd->pkt_len);
938}
939
940static struct rxd_ops rxd_8687_ops = {
941 .rxd_size = sizeof(struct mwl8k_rxd_8687),
942 .rxd_init = mwl8k_rxd_8687_init,
943 .rxd_refill = mwl8k_rxd_8687_refill,
944 .rxd_process = mwl8k_rxd_8687_process,
945};
946
947
a66098da
LB		 948#define MWL8K_RX_DESCS 256
949#define MWL8K_RX_MAXSZ 3800
950
951static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
952{
953 struct mwl8k_priv *priv = hw->priv;
954 struct mwl8k_rx_queue *rxq = priv->rxq + index;
955 int size;
956 int i;
957
45eb400d
LB		 958 rxq->rxd_count = 0;
959 rxq->head = 0;
960 rxq->tail = 0;
a66098da 961
54bc3a0d 962 size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
a66098da 963
45eb400d
LB		 964 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
965 if (rxq->rxd == NULL) {
a66098da 966 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
c2c357ce 967 wiphy_name(hw->wiphy));
a66098da
LB		 968 return -ENOMEM;
969 }
45eb400d 970 memset(rxq->rxd, 0, size);
a66098da 971
788838eb
LB		 972 rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL);
973 if (rxq->buf == NULL) {
a66098da 974 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
c2c357ce 975 wiphy_name(hw->wiphy));
45eb400d 976 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
a66098da
LB		 977 return -ENOMEM;
978 }
788838eb 979 memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf));
a66098da
LB		 980
981 for (i = 0; i < MWL8K_RX_DESCS; i++) {
54bc3a0d
LB		 982 int desc_size;
983 void *rxd;
a66098da 984 int nexti;
54bc3a0d
LB		 985 dma_addr_t next_dma_addr;
986
987 desc_size = priv->rxd_ops->rxd_size;
988 rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
a66098da 989
54bc3a0d
LB		 990 nexti = i + 1;
991 if (nexti == MWL8K_RX_DESCS)
992 nexti = 0;
993 next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
a66098da 994
54bc3a0d 995 priv->rxd_ops->rxd_init(rxd, next_dma_addr);
a66098da
LB		 996 }
997
998 return 0;
999}
1000
1001static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
1002{
1003 struct mwl8k_priv *priv = hw->priv;
1004 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1005 int refilled;
1006
1007 refilled = 0;
45eb400d 1008 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
a66098da 1009 struct sk_buff *skb;
788838eb 1010 dma_addr_t addr;
a66098da 1011 int rx;
54bc3a0d 1012 void *rxd;
a66098da
LB		 1013
1014 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
1015 if (skb == NULL)
1016 break;
1017
788838eb
LB		 1018 addr = pci_map_single(priv->pdev, skb->data,
1019 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
a66098da 1020
54bc3a0d
LB		 1021 rxq->rxd_count++;
1022 rx = rxq->tail++;
1023 if (rxq->tail == MWL8K_RX_DESCS)
1024 rxq->tail = 0;
788838eb
LB		 1025 rxq->buf[rx].skb = skb;
1026 pci_unmap_addr_set(&rxq->buf[rx], dma, addr);
54bc3a0d
LB		 1027
1028 rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
1029 priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
a66098da
LB		 1030
1031 refilled++;
1032 }
1033
1034 return refilled;
1035}
1036
1037/* Must be called only when the card's reception is completely halted */
1038static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
1039{
1040 struct mwl8k_priv *priv = hw->priv;
1041 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1042 int i;
1043
1044 for (i = 0; i < MWL8K_RX_DESCS; i++) {
788838eb
LB		 1045 if (rxq->buf[i].skb != NULL) {
1046 pci_unmap_single(priv->pdev,
1047 pci_unmap_addr(&rxq->buf[i], dma),
1048 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1049 pci_unmap_addr_set(&rxq->buf[i], dma, 0);
1050
1051 kfree_skb(rxq->buf[i].skb);
1052 rxq->buf[i].skb = NULL;
a66098da
LB		 1053 }
1054 }
1055
788838eb
LB		 1056 kfree(rxq->buf);
1057 rxq->buf = NULL;
a66098da
LB		 1058
1059 pci_free_consistent(priv->pdev,
54bc3a0d 1060 MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
45eb400d
LB		 1061 rxq->rxd, rxq->rxd_dma);
1062 rxq->rxd = NULL;
a66098da
LB		 1063}
1064
1065
1066/*
1067 * Scan a list of BSSIDs to process for finalize join.
1068 * Allows for extension to process multiple BSSIDs.
1069 */
1070static inline int
1071mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
1072{
1073 return priv->capture_beacon &&
1074 ieee80211_is_beacon(wh->frame_control) &&
1075 !compare_ether_addr(wh->addr3, priv->capture_bssid);
1076}
1077
3779752d
LB		 1078static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
1079 struct sk_buff *skb)
a66098da 1080{
3779752d
LB		 1081 struct mwl8k_priv *priv = hw->priv;
1082
a66098da 1083 priv->capture_beacon = false;
d89173f2 1084 memset(priv->capture_bssid, 0, ETH_ALEN);
a66098da
LB		 1085
1086 /*
1087 * Use GFP_ATOMIC as rxq_process is called from
1088 * the primary interrupt handler, memory allocation call
1089 * must not sleep.
1090 */
1091 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
1092 if (priv->beacon_skb != NULL)
3779752d 1093 ieee80211_queue_work(hw, &priv->finalize_join_worker);
a66098da
LB		 1094}
1095
1096static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
1097{
1098 struct mwl8k_priv *priv = hw->priv;
1099 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1100 int processed;
1101
1102 processed = 0;
45eb400d 1103 while (rxq->rxd_count && limit--) {
a66098da 1104 struct sk_buff *skb;
54bc3a0d
LB		 1105 void *rxd;
1106 int pkt_len;
a66098da 1107 struct ieee80211_rx_status status;
20f09c3d 1108 __le16 qos;
a66098da 1109
788838eb 1110 skb = rxq->buf[rxq->head].skb;
d25f9f13
LB		 1111 if (skb == NULL)
1112 break;
54bc3a0d
LB		 1113
1114 rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
1115
20f09c3d 1116 pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos);
54bc3a0d
LB		 1117 if (pkt_len < 0)
1118 break;
1119
788838eb
LB		 1120 rxq->buf[rxq->head].skb = NULL;
1121
1122 pci_unmap_single(priv->pdev,
1123 pci_unmap_addr(&rxq->buf[rxq->head], dma),
1124 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1125 pci_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
a66098da 1126
54bc3a0d
LB		 1127 rxq->head++;
1128 if (rxq->head == MWL8K_RX_DESCS)
1129 rxq->head = 0;
1130
45eb400d 1131 rxq->rxd_count--;
a66098da 1132
54bc3a0d 1133 skb_put(skb, pkt_len);
20f09c3d 1134 mwl8k_remove_dma_header(skb, qos);
a66098da 1135
a66098da 1136 /*
c2c357ce
LB		 1137 * Check for a pending join operation. Save a
1138 * copy of the beacon and schedule a tasklet to
1139 * send a FINALIZE_JOIN command to the firmware.
a66098da 1140 */
54bc3a0d 1141 if (mwl8k_capture_bssid(priv, (void *)skb->data))
3779752d 1142 mwl8k_save_beacon(hw, skb);
a66098da 1143
f1d58c25
JB		 1144 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
1145 ieee80211_rx_irqsafe(hw, skb);
a66098da
LB		 1146
1147 processed++;
1148 }
1149
1150 return processed;
1151}
1152
1153
1154/*
1155 * Packet transmission.
1156 */
1157
a66098da
LB		 1158/* Transmit packet ACK policy */
1159#define MWL8K_TXD_ACK_POLICY_NORMAL 0
a66098da
LB		 1160#define MWL8K_TXD_ACK_POLICY_BLOCKACK 3
1161
a66098da
LB		 1162#define MWL8K_TXD_STATUS_OK 0x00000001
1163#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1164#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1165#define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
a66098da 1166#define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
a66098da
LB		 1167
1168struct mwl8k_tx_desc {
1169 __le32 status;
1170 __u8 data_rate;
1171 __u8 tx_priority;
1172 __le16 qos_control;
1173 __le32 pkt_phys_addr;
1174 __le16 pkt_len;
d89173f2 1175 __u8 dest_MAC_addr[ETH_ALEN];
45eb400d 1176 __le32 next_txd_phys_addr;
a66098da
LB		 1177 __le32 reserved;
1178 __le16 rate_info;
1179 __u8 peer_id;
1180 __u8 tx_frag_cnt;
1181} __attribute__((packed));
1182
1183#define MWL8K_TX_DESCS 128
1184
1185static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1186{
1187 struct mwl8k_priv *priv = hw->priv;
1188 struct mwl8k_tx_queue *txq = priv->txq + index;
1189 int size;
1190 int i;
1191
45eb400d
LB		 1192 memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats));
1193 txq->stats.limit = MWL8K_TX_DESCS;
1194 txq->head = 0;
1195 txq->tail = 0;
a66098da
LB		 1196
1197 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1198
45eb400d
LB		 1199 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
1200 if (txq->txd == NULL) {
a66098da 1201 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
c2c357ce 1202 wiphy_name(hw->wiphy));
a66098da
LB		 1203 return -ENOMEM;
1204 }
45eb400d 1205 memset(txq->txd, 0, size);
a66098da 1206
45eb400d
LB		 1207 txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL);
1208 if (txq->skb == NULL) {
a66098da 1209 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
c2c357ce 1210 wiphy_name(hw->wiphy));
45eb400d 1211 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
a66098da
LB		 1212 return -ENOMEM;
1213 }
45eb400d 1214 memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb));
a66098da
LB		 1215
1216 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1217 struct mwl8k_tx_desc *tx_desc;
1218 int nexti;
1219
45eb400d 1220 tx_desc = txq->txd + i;
a66098da
LB		 1221 nexti = (i + 1) % MWL8K_TX_DESCS;
1222
1223 tx_desc->status = 0;
45eb400d
LB		 1224 tx_desc->next_txd_phys_addr =
1225 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
a66098da
LB		 1226 }
1227
1228 return 0;
1229}
1230
1231static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1232{
1233 iowrite32(MWL8K_H2A_INT_PPA_READY,
1234 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1235 iowrite32(MWL8K_H2A_INT_DUMMY,
1236 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1237 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1238}
1239
a66098da
LB		 1240struct mwl8k_txq_info {
1241 u32 fw_owned;
1242 u32 drv_owned;
1243 u32 unused;
1244 u32 len;
1245 u32 head;
1246 u32 tail;
1247};
1248
1249static int mwl8k_scan_tx_ring(struct mwl8k_priv *priv,
c3f967d3 1250 struct mwl8k_txq_info *txinfo)
a66098da
LB		 1251{
1252 int count, desc, status;
1253 struct mwl8k_tx_queue *txq;
1254 struct mwl8k_tx_desc *tx_desc;
1255 int ndescs = 0;
1256
c3f967d3
LB		 1257 memset(txinfo, 0, MWL8K_TX_QUEUES * sizeof(struct mwl8k_txq_info));
1258
c3f967d3 1259 for (count = 0; count < MWL8K_TX_QUEUES; count++) {
a66098da 1260 txq = priv->txq + count;
45eb400d
LB		 1261 txinfo[count].len = txq->stats.len;
1262 txinfo[count].head = txq->head;
1263 txinfo[count].tail = txq->tail;
a66098da 1264 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
45eb400d 1265 tx_desc = txq->txd + desc;
a66098da
LB		 1266 status = le32_to_cpu(tx_desc->status);
1267
1268 if (status & MWL8K_TXD_STATUS_FW_OWNED)
1269 txinfo[count].fw_owned++;
1270 else
1271 txinfo[count].drv_owned++;
1272
1273 if (tx_desc->pkt_len == 0)
1274 txinfo[count].unused++;
1275 }
1276 }
a66098da
LB		 1277
1278 return ndescs;
1279}
1280
618952a7 1281/*
88de754a 1282 * Must be called with priv->fw_mutex held and tx queues stopped.
618952a7 1283 */
950d5b01 1284static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
a66098da 1285{
a66098da 1286 struct mwl8k_priv *priv = hw->priv;
88de754a 1287 DECLARE_COMPLETION_ONSTACK(tx_wait);
ce9e2e1b
LB		 1288 u32 count;
1289 unsigned long timeout;
a66098da
LB		 1290
1291 might_sleep();
1292
a66098da 1293 spin_lock_bh(&priv->tx_lock);
88de754a
LB		 1294 count = priv->pending_tx_pkts;
1295 if (count)
1296 priv->tx_wait = &tx_wait;
a66098da
LB		 1297 spin_unlock_bh(&priv->tx_lock);
1298
1299 if (count) {
c3f967d3 1300 struct mwl8k_txq_info txinfo[MWL8K_TX_QUEUES];
a66098da
LB		 1301 int index;
1302 int newcount;
1303
88de754a 1304 timeout = wait_for_completion_timeout(&tx_wait,
618952a7 1305 msecs_to_jiffies(5000));
a66098da
LB		 1306 if (timeout)
1307 return 0;
1308
1309 spin_lock_bh(&priv->tx_lock);
1310 priv->tx_wait = NULL;
88de754a
LB		 1311 newcount = priv->pending_tx_pkts;
1312 mwl8k_scan_tx_ring(priv, txinfo);
a66098da
LB		 1313 spin_unlock_bh(&priv->tx_lock);
1314
618952a7 1315 printk(KERN_ERR "%s(%u) TIMEDOUT:5000ms Pend:%u-->%u\n",
950d5b01 1316 __func__, __LINE__, count, newcount);
a66098da 1317
c3f967d3 1318 for (index = 0; index < MWL8K_TX_QUEUES; index++)
c2c357ce
LB		 1319 printk(KERN_ERR "TXQ:%u L:%u H:%u T:%u FW:%u "
1320 "DRV:%u U:%u\n",
a66098da
LB		 1321 index,
1322 txinfo[index].len,
1323 txinfo[index].head,
1324 txinfo[index].tail,
1325 txinfo[index].fw_owned,
1326 txinfo[index].drv_owned,
1327 txinfo[index].unused);
ce9e2e1b 1328
a66098da
LB		 1329 return -ETIMEDOUT;
1330 }
1331
1332 return 0;
1333}
1334
c23b5a69
LB		 1335#define MWL8K_TXD_SUCCESS(status) \
1336 ((status) & (MWL8K_TXD_STATUS_OK | \
1337 MWL8K_TXD_STATUS_OK_RETRY | \
1338 MWL8K_TXD_STATUS_OK_MORE_RETRY))
a66098da
LB		 1339
1340static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
1341{
1342 struct mwl8k_priv *priv = hw->priv;
1343 struct mwl8k_tx_queue *txq = priv->txq + index;
1344 int wake = 0;
1345
45eb400d 1346 while (txq->stats.len > 0) {
a66098da 1347 int tx;
a66098da
LB		 1348 struct mwl8k_tx_desc *tx_desc;
1349 unsigned long addr;
ce9e2e1b 1350 int size;
a66098da
LB		 1351 struct sk_buff *skb;
1352 struct ieee80211_tx_info *info;
1353 u32 status;
1354
45eb400d
LB		 1355 tx = txq->head;
1356 tx_desc = txq->txd + tx;
a66098da
LB		 1357
1358 status = le32_to_cpu(tx_desc->status);
1359
1360 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1361 if (!force)
1362 break;
1363 tx_desc->status &=
1364 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1365 }
1366
45eb400d
LB		 1367 txq->head = (tx + 1) % MWL8K_TX_DESCS;
1368 BUG_ON(txq->stats.len == 0);
1369 txq->stats.len--;
a66098da
LB		 1370 priv->pending_tx_pkts--;
1371
1372 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
ce9e2e1b 1373 size = le16_to_cpu(tx_desc->pkt_len);
45eb400d
LB		 1374 skb = txq->skb[tx];
1375 txq->skb[tx] = NULL;
a66098da
LB		 1376
1377 BUG_ON(skb == NULL);
1378 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1379
20f09c3d 1380 mwl8k_remove_dma_header(skb, tx_desc->qos_control);
a66098da
LB		 1381
1382 /* Mark descriptor as unused */
1383 tx_desc->pkt_phys_addr = 0;
1384 tx_desc->pkt_len = 0;
1385
a66098da
LB		 1386 info = IEEE80211_SKB_CB(skb);
1387 ieee80211_tx_info_clear_status(info);
ce9e2e1b 1388 if (MWL8K_TXD_SUCCESS(status))
a66098da 1389 info->flags |= IEEE80211_TX_STAT_ACK;
a66098da
LB		 1390
1391 ieee80211_tx_status_irqsafe(hw, skb);
1392
618952a7 1393 wake = 1;
a66098da
LB		 1394 }
1395
618952a7 1396 if (wake && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
a66098da
LB		 1397 ieee80211_wake_queue(hw, index);
1398}
1399
1400/* must be called only when the card's transmit is completely halted */
1401static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1402{
1403 struct mwl8k_priv *priv = hw->priv;
1404 struct mwl8k_tx_queue *txq = priv->txq + index;
1405
1406 mwl8k_txq_reclaim(hw, index, 1);
1407
45eb400d
LB		 1408 kfree(txq->skb);
1409 txq->skb = NULL;
a66098da
LB		 1410
1411 pci_free_consistent(priv->pdev,
1412 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
45eb400d
LB		 1413 txq->txd, txq->txd_dma);
1414 txq->txd = NULL;
a66098da
LB		 1415}
1416
1417static int
1418mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1419{
1420 struct mwl8k_priv *priv = hw->priv;
1421 struct ieee80211_tx_info *tx_info;
23b33906 1422 struct mwl8k_vif *mwl8k_vif;
a66098da
LB		 1423 struct ieee80211_hdr *wh;
1424 struct mwl8k_tx_queue *txq;
1425 struct mwl8k_tx_desc *tx;
a66098da 1426 dma_addr_t dma;
23b33906
LB		 1427 u32 txstatus;
1428 u8 txdatarate;
1429 u16 qos;
a66098da 1430
23b33906
LB		 1431 wh = (struct ieee80211_hdr *)skb->data;
1432 if (ieee80211_is_data_qos(wh->frame_control))
1433 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1434 else
1435 qos = 0;
a66098da 1436
76266b2a 1437 mwl8k_add_dma_header(skb);
23b33906 1438 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
a66098da
LB		 1439
1440 tx_info = IEEE80211_SKB_CB(skb);
1441 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
a66098da
LB		 1442
1443 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1444 u16 seqno = mwl8k_vif->seqno;
23b33906 1445
a66098da
LB		 1446 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1447 wh->seq_ctrl |= cpu_to_le16(seqno << 4);
1448 mwl8k_vif->seqno = seqno++ % 4096;
1449 }
1450
23b33906
LB		 1451 /* Setup firmware control bit fields for each frame type. */
1452 txstatus = 0;
1453 txdatarate = 0;
1454 if (ieee80211_is_mgmt(wh->frame_control) ||
1455 ieee80211_is_ctl(wh->frame_control)) {
1456 txdatarate = 0;
1457 qos = mwl8k_qos_setbit_eosp(qos);
1458 /* Set Queue size to unspecified */
1459 qos = mwl8k_qos_setbit_qlen(qos, 0xff);
1460 } else if (ieee80211_is_data(wh->frame_control)) {
1461 txdatarate = 1;
1462 if (is_multicast_ether_addr(wh->addr1))
1463 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1464
1465 /* Send pkt in an aggregate if AMPDU frame. */
1466 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1467 qos = mwl8k_qos_setbit_ack(qos,
1468 MWL8K_TXD_ACK_POLICY_BLOCKACK);
1469 else
1470 qos = mwl8k_qos_setbit_ack(qos,
1471 MWL8K_TXD_ACK_POLICY_NORMAL);
1472
1473 if (qos & IEEE80211_QOS_CONTROL_A_MSDU_PRESENT)
1474 qos = mwl8k_qos_setbit_amsdu(qos);
1475 }
a66098da
LB		 1476
1477 dma = pci_map_single(priv->pdev, skb->data,
1478 skb->len, PCI_DMA_TODEVICE);
1479
1480 if (pci_dma_mapping_error(priv->pdev, dma)) {
1481 printk(KERN_DEBUG "%s: failed to dma map skb, "
c2c357ce 1482 "dropping TX frame.\n", wiphy_name(hw->wiphy));
23b33906 1483 dev_kfree_skb(skb);
a66098da
LB		 1484 return NETDEV_TX_OK;
1485 }
1486
23b33906 1487 spin_lock_bh(&priv->tx_lock);
a66098da 1488
23b33906 1489 txq = priv->txq + index;
a66098da 1490
45eb400d
LB		 1491 BUG_ON(txq->skb[txq->tail] != NULL);
1492 txq->skb[txq->tail] = skb;
a66098da 1493
45eb400d 1494 tx = txq->txd + txq->tail;
23b33906
LB		 1495 tx->data_rate = txdatarate;
1496 tx->tx_priority = index;
a66098da 1497 tx->qos_control = cpu_to_le16(qos);
a66098da
LB		 1498 tx->pkt_phys_addr = cpu_to_le32(dma);
1499 tx->pkt_len = cpu_to_le16(skb->len);
23b33906
LB		 1500 tx->rate_info = 0;
1501 tx->peer_id = mwl8k_vif->peer_id;
a66098da 1502 wmb();
23b33906
LB		 1503 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1504
45eb400d
LB		 1505 txq->stats.count++;
1506 txq->stats.len++;
a66098da 1507 priv->pending_tx_pkts++;
a66098da 1508
45eb400d
LB		 1509 txq->tail++;
1510 if (txq->tail == MWL8K_TX_DESCS)
1511 txq->tail = 0;
23b33906 1512
45eb400d 1513 if (txq->head == txq->tail)
a66098da
LB		 1514 ieee80211_stop_queue(hw, index);
1515
23b33906 1516 mwl8k_tx_start(priv);
a66098da
LB		 1517
1518 spin_unlock_bh(&priv->tx_lock);
1519
1520 return NETDEV_TX_OK;
1521}
1522
1523
618952a7
LB		 1524/*
1525 * Firmware access.
1526 *
1527 * We have the following requirements for issuing firmware commands:
1528 * - Some commands require that the packet transmit path is idle when
1529 * the command is issued. (For simplicity, we'll just quiesce the
1530 * transmit path for every command.)
1531 * - There are certain sequences of commands that need to be issued to
1532 * the hardware sequentially, with no other intervening commands.
1533 *
1534 * This leads to an implementation of a "firmware lock" as a mutex that
1535 * can be taken recursively, and which is taken by both the low-level
1536 * command submission function (mwl8k_post_cmd) as well as any users of
1537 * that function that require issuing of an atomic sequence of commands,
1538 * and quiesces the transmit path whenever it's taken.
1539 */
1540static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1541{
1542 struct mwl8k_priv *priv = hw->priv;
1543
1544 if (priv->fw_mutex_owner != current) {
1545 int rc;
1546
1547 mutex_lock(&priv->fw_mutex);
1548 ieee80211_stop_queues(hw);
1549
1550 rc = mwl8k_tx_wait_empty(hw);
1551 if (rc) {
1552 ieee80211_wake_queues(hw);
1553 mutex_unlock(&priv->fw_mutex);
1554
1555 return rc;
1556 }
1557
1558 priv->fw_mutex_owner = current;
1559 }
1560
1561 priv->fw_mutex_depth++;
1562
1563 return 0;
1564}
1565
1566static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1567{
1568 struct mwl8k_priv *priv = hw->priv;
1569
1570 if (!--priv->fw_mutex_depth) {
1571 ieee80211_wake_queues(hw);
1572 priv->fw_mutex_owner = NULL;
1573 mutex_unlock(&priv->fw_mutex);
1574 }
1575}
1576
1577
a66098da
LB		 1578/*
1579 * Command processing.
1580 */
1581
1582/* Timeout firmware commands after 2000ms */
1583#define MWL8K_CMD_TIMEOUT_MS 2000
1584
1585static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1586{
1587 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1588 struct mwl8k_priv *priv = hw->priv;
1589 void __iomem *regs = priv->regs;
1590 dma_addr_t dma_addr;
1591 unsigned int dma_size;
1592 int rc;
a66098da
LB		 1593 unsigned long timeout = 0;
1594 u8 buf[32];
1595
c2c357ce 1596 cmd->result = 0xffff;
a66098da
LB		 1597 dma_size = le16_to_cpu(cmd->length);
1598 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1599 PCI_DMA_BIDIRECTIONAL);
1600 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1601 return -ENOMEM;
1602
618952a7 1603 rc = mwl8k_fw_lock(hw);
39a1e42e
LB		 1604 if (rc) {
1605 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1606 PCI_DMA_BIDIRECTIONAL);
618952a7 1607 return rc;
39a1e42e 1608 }
a66098da 1609
a66098da
LB		 1610 priv->hostcmd_wait = &cmd_wait;
1611 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1612 iowrite32(MWL8K_H2A_INT_DOORBELL,
1613 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1614 iowrite32(MWL8K_H2A_INT_DUMMY,
1615 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
a66098da
LB		 1616
1617 timeout = wait_for_completion_timeout(&cmd_wait,
1618 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1619
618952a7
LB		 1620 priv->hostcmd_wait = NULL;
1621
1622 mwl8k_fw_unlock(hw);
1623
37055bd4
LB		 1624 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1625 PCI_DMA_BIDIRECTIONAL);
1626
a66098da 1627 if (!timeout) {
a66098da 1628 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
c2c357ce 1629 wiphy_name(hw->wiphy),
a66098da
LB		 1630 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1631 MWL8K_CMD_TIMEOUT_MS);
1632 rc = -ETIMEDOUT;
1633 } else {
ce9e2e1b 1634 rc = cmd->result ? -EINVAL : 0;
a66098da
LB		 1635 if (rc)
1636 printk(KERN_ERR "%s: Command %s error 0x%x\n",
c2c357ce 1637 wiphy_name(hw->wiphy),
a66098da 1638 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
76c962a2 1639 le16_to_cpu(cmd->result));
a66098da
LB		 1640 }
1641
a66098da
LB		 1642 return rc;
1643}
1644
1645/*
04b147b1 1646 * CMD_GET_HW_SPEC (STA version).
a66098da 1647 */
04b147b1 1648struct mwl8k_cmd_get_hw_spec_sta {
a66098da
LB		 1649 struct mwl8k_cmd_pkt header;
1650 __u8 hw_rev;
1651 __u8 host_interface;
1652 __le16 num_mcaddrs;
d89173f2 1653 __u8 perm_addr[ETH_ALEN];
a66098da
LB		 1654 __le16 region_code;
1655 __le32 fw_rev;
1656 __le32 ps_cookie;
1657 __le32 caps;
1658 __u8 mcs_bitmap[16];
1659 __le32 rx_queue_ptr;
1660 __le32 num_tx_queues;
1661 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1662 __le32 caps2;
1663 __le32 num_tx_desc_per_queue;
45eb400d 1664 __le32 total_rxd;
a66098da
LB		 1665} __attribute__((packed));
1666
04b147b1 1667static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
a66098da
LB		 1668{
1669 struct mwl8k_priv *priv = hw->priv;
04b147b1 1670 struct mwl8k_cmd_get_hw_spec_sta *cmd;
a66098da
LB		 1671 int rc;
1672 int i;
1673
1674 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1675 if (cmd == NULL)
1676 return -ENOMEM;
1677
1678 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1679 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1680
1681 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1682 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
45eb400d 1683 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
4ff6432e 1684 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
a66098da 1685 for (i = 0; i < MWL8K_TX_QUEUES; i++)
45eb400d 1686 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
4ff6432e 1687 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
45eb400d 1688 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
a66098da
LB		 1689
1690 rc = mwl8k_post_cmd(hw, &cmd->header);
1691
1692 if (!rc) {
1693 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1694 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
4ff6432e 1695 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
a66098da 1696 priv->hw_rev = cmd->hw_rev;
a66098da
LB		 1697 }
1698
1699 kfree(cmd);
1700 return rc;
1701}
1702
42fba21d
LB		 1703/*
1704 * CMD_GET_HW_SPEC (AP version).
1705 */
1706struct mwl8k_cmd_get_hw_spec_ap {
1707 struct mwl8k_cmd_pkt header;
1708 __u8 hw_rev;
1709 __u8 host_interface;
1710 __le16 num_wcb;
1711 __le16 num_mcaddrs;
1712 __u8 perm_addr[ETH_ALEN];
1713 __le16 region_code;
1714 __le16 num_antenna;
1715 __le32 fw_rev;
1716 __le32 wcbbase0;
1717 __le32 rxwrptr;
1718 __le32 rxrdptr;
1719 __le32 ps_cookie;
1720 __le32 wcbbase1;
1721 __le32 wcbbase2;
1722 __le32 wcbbase3;
1723} __attribute__((packed));
1724
1725static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
1726{
1727 struct mwl8k_priv *priv = hw->priv;
1728 struct mwl8k_cmd_get_hw_spec_ap *cmd;
1729 int rc;
1730
1731 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1732 if (cmd == NULL)
1733 return -ENOMEM;
1734
1735 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1736 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1737
1738 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1739 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1740
1741 rc = mwl8k_post_cmd(hw, &cmd->header);
1742
1743 if (!rc) {
1744 int off;
1745
1746 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1747 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1748 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1749 priv->hw_rev = cmd->hw_rev;
1750
1751 off = le32_to_cpu(cmd->wcbbase0) & 0xffff;
1752 iowrite32(cpu_to_le32(priv->txq[0].txd_dma), priv->sram + off);
1753
1754 off = le32_to_cpu(cmd->rxwrptr) & 0xffff;
1755 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1756
1757 off = le32_to_cpu(cmd->rxrdptr) & 0xffff;
1758 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1759
1760 off = le32_to_cpu(cmd->wcbbase1) & 0xffff;
1761 iowrite32(cpu_to_le32(priv->txq[1].txd_dma), priv->sram + off);
1762
1763 off = le32_to_cpu(cmd->wcbbase2) & 0xffff;
1764 iowrite32(cpu_to_le32(priv->txq[2].txd_dma), priv->sram + off);
1765
1766 off = le32_to_cpu(cmd->wcbbase3) & 0xffff;
1767 iowrite32(cpu_to_le32(priv->txq[3].txd_dma), priv->sram + off);
1768 }
1769
1770 kfree(cmd);
1771 return rc;
1772}
1773
1774/*
1775 * CMD_SET_HW_SPEC.
1776 */
1777struct mwl8k_cmd_set_hw_spec {
1778 struct mwl8k_cmd_pkt header;
1779 __u8 hw_rev;
1780 __u8 host_interface;
1781 __le16 num_mcaddrs;
1782 __u8 perm_addr[ETH_ALEN];
1783 __le16 region_code;
1784 __le32 fw_rev;
1785 __le32 ps_cookie;
1786 __le32 caps;
1787 __le32 rx_queue_ptr;
1788 __le32 num_tx_queues;
1789 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1790 __le32 flags;
1791 __le32 num_tx_desc_per_queue;
1792 __le32 total_rxd;
1793} __attribute__((packed));
1794
1795#define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
1796
1797static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw)
1798{
1799 struct mwl8k_priv *priv = hw->priv;
1800 struct mwl8k_cmd_set_hw_spec *cmd;
1801 int rc;
1802 int i;
1803
1804 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1805 if (cmd == NULL)
1806 return -ENOMEM;
1807
1808 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC);
1809 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1810
1811 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1812 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
1813 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1814 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1815 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
1816 cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT);
1817 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1818 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
1819
1820 rc = mwl8k_post_cmd(hw, &cmd->header);
1821 kfree(cmd);
1822
1823 return rc;
1824}
1825
a66098da
LB		 1826/*
1827 * CMD_MAC_MULTICAST_ADR.
1828 */
1829struct mwl8k_cmd_mac_multicast_adr {
1830 struct mwl8k_cmd_pkt header;
1831 __le16 action;
1832 __le16 numaddr;
ce9e2e1b 1833 __u8 addr[0][ETH_ALEN];
a66098da
LB		 1834};
1835
d5e30845
LB		 1836#define MWL8K_ENABLE_RX_DIRECTED 0x0001
1837#define MWL8K_ENABLE_RX_MULTICAST 0x0002
1838#define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
1839#define MWL8K_ENABLE_RX_BROADCAST 0x0008
ce9e2e1b 1840
e81cd2d6 1841static struct mwl8k_cmd_pkt *
447ced07 1842__mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
e81cd2d6 1843 int mc_count, struct dev_addr_list *mclist)
a66098da 1844{
e81cd2d6 1845 struct mwl8k_priv *priv = hw->priv;
a66098da 1846 struct mwl8k_cmd_mac_multicast_adr *cmd;
e81cd2d6 1847 int size;
e81cd2d6 1848
447ced07 1849 if (allmulti || mc_count > priv->num_mcaddrs) {
d5e30845
LB		 1850 allmulti = 1;
1851 mc_count = 0;
1852 }
e81cd2d6
LB		 1853
1854 size = sizeof(*cmd) + mc_count * ETH_ALEN;
ce9e2e1b 1855
e81cd2d6 1856 cmd = kzalloc(size, GFP_ATOMIC);
a66098da 1857 if (cmd == NULL)
e81cd2d6 1858 return NULL;
a66098da
LB		 1859
1860 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1861 cmd->header.length = cpu_to_le16(size);
d5e30845
LB		 1862 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
1863 MWL8K_ENABLE_RX_BROADCAST);
1864
1865 if (allmulti) {
1866 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
1867 } else if (mc_count) {
1868 int i;
1869
1870 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1871 cmd->numaddr = cpu_to_le16(mc_count);
1872 for (i = 0; i < mc_count && mclist; i++) {
1873 if (mclist->da_addrlen != ETH_ALEN) {
1874 kfree(cmd);
1875 return NULL;
1876 }
1877 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
1878 mclist = mclist->next;
a66098da 1879 }
a66098da
LB		 1880 }
1881
e81cd2d6 1882 return &cmd->header;
a66098da
LB		 1883}
1884
1885/*
1886 * CMD_802_11_GET_STAT.
1887 */
1888struct mwl8k_cmd_802_11_get_stat {
1889 struct mwl8k_cmd_pkt header;
a66098da
LB		 1890 __le32 stats[64];
1891} __attribute__((packed));
1892
1893#define MWL8K_STAT_ACK_FAILURE 9
1894#define MWL8K_STAT_RTS_FAILURE 12
1895#define MWL8K_STAT_FCS_ERROR 24
1896#define MWL8K_STAT_RTS_SUCCESS 11
1897
1898static int mwl8k_cmd_802_11_get_stat(struct ieee80211_hw *hw,
1899 struct ieee80211_low_level_stats *stats)
1900{
1901 struct mwl8k_cmd_802_11_get_stat *cmd;
1902 int rc;
1903
1904 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1905 if (cmd == NULL)
1906 return -ENOMEM;
1907
1908 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1909 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 1910
1911 rc = mwl8k_post_cmd(hw, &cmd->header);
1912 if (!rc) {
1913 stats->dot11ACKFailureCount =
1914 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1915 stats->dot11RTSFailureCount =
1916 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1917 stats->dot11FCSErrorCount =
1918 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1919 stats->dot11RTSSuccessCount =
1920 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1921 }
1922 kfree(cmd);
1923
1924 return rc;
1925}
1926
1927/*
1928 * CMD_802_11_RADIO_CONTROL.
1929 */
1930struct mwl8k_cmd_802_11_radio_control {
1931 struct mwl8k_cmd_pkt header;
1932 __le16 action;
1933 __le16 control;
1934 __le16 radio_on;
1935} __attribute__((packed));
1936
c46563b7
LB		 1937static int
1938mwl8k_cmd_802_11_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
a66098da
LB		 1939{
1940 struct mwl8k_priv *priv = hw->priv;
1941 struct mwl8k_cmd_802_11_radio_control *cmd;
1942 int rc;
1943
c46563b7 1944 if (enable == priv->radio_on && !force)
a66098da
LB		 1945 return 0;
1946
a66098da
LB		 1947 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1948 if (cmd == NULL)
1949 return -ENOMEM;
1950
1951 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
1952 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1953 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
68ce3884 1954 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
a66098da
LB		 1955 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
1956
1957 rc = mwl8k_post_cmd(hw, &cmd->header);
1958 kfree(cmd);
1959
1960 if (!rc)
c46563b7 1961 priv->radio_on = enable;
a66098da
LB		 1962
1963 return rc;
1964}
1965
c46563b7
LB		 1966static int mwl8k_cmd_802_11_radio_disable(struct ieee80211_hw *hw)
1967{
1968 return mwl8k_cmd_802_11_radio_control(hw, 0, 0);
1969}
1970
1971static int mwl8k_cmd_802_11_radio_enable(struct ieee80211_hw *hw)
1972{
1973 return mwl8k_cmd_802_11_radio_control(hw, 1, 0);
1974}
1975
a66098da
LB		 1976static int
1977mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
1978{
1979 struct mwl8k_priv *priv;
1980
1981 if (hw == NULL || hw->priv == NULL)
1982 return -EINVAL;
1983 priv = hw->priv;
1984
68ce3884 1985 priv->radio_short_preamble = short_preamble;
a66098da 1986
c46563b7 1987 return mwl8k_cmd_802_11_radio_control(hw, 1, 1);
a66098da
LB		 1988}
1989
1990/*
1991 * CMD_802_11_RF_TX_POWER.
1992 */
1993#define MWL8K_TX_POWER_LEVEL_TOTAL 8
1994
1995struct mwl8k_cmd_802_11_rf_tx_power {
1996 struct mwl8k_cmd_pkt header;
1997 __le16 action;
1998 __le16 support_level;
1999 __le16 current_level;
2000 __le16 reserved;
2001 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
2002} __attribute__((packed));
2003
2004static int mwl8k_cmd_802_11_rf_tx_power(struct ieee80211_hw *hw, int dBm)
2005{
2006 struct mwl8k_cmd_802_11_rf_tx_power *cmd;
2007 int rc;
2008
2009 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2010 if (cmd == NULL)
2011 return -ENOMEM;
2012
2013 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
2014 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2015 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2016 cmd->support_level = cpu_to_le16(dBm);
2017
2018 rc = mwl8k_post_cmd(hw, &cmd->header);
2019 kfree(cmd);
2020
2021 return rc;
2022}
2023
08b06347
LB		 2024/*
2025 * CMD_RF_ANTENNA.
2026 */
2027struct mwl8k_cmd_rf_antenna {
2028 struct mwl8k_cmd_pkt header;
2029 __le16 antenna;
2030 __le16 mode;
2031} __attribute__((packed));
2032
2033#define MWL8K_RF_ANTENNA_RX 1
2034#define MWL8K_RF_ANTENNA_TX 2
2035
2036static int
2037mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask)
2038{
2039 struct mwl8k_cmd_rf_antenna *cmd;
2040 int rc;
2041
2042 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2043 if (cmd == NULL)
2044 return -ENOMEM;
2045
2046 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA);
2047 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2048 cmd->antenna = cpu_to_le16(antenna);
2049 cmd->mode = cpu_to_le16(mask);
2050
2051 rc = mwl8k_post_cmd(hw, &cmd->header);
2052 kfree(cmd);
2053
2054 return rc;
2055}
2056
a66098da
LB		 2057/*
2058 * CMD_SET_PRE_SCAN.
2059 */
2060struct mwl8k_cmd_set_pre_scan {
2061 struct mwl8k_cmd_pkt header;
2062} __attribute__((packed));
2063
2064static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
2065{
2066 struct mwl8k_cmd_set_pre_scan *cmd;
2067 int rc;
2068
2069 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2070 if (cmd == NULL)
2071 return -ENOMEM;
2072
2073 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
2074 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2075
2076 rc = mwl8k_post_cmd(hw, &cmd->header);
2077 kfree(cmd);
2078
2079 return rc;
2080}
2081
2082/*
2083 * CMD_SET_POST_SCAN.
2084 */
2085struct mwl8k_cmd_set_post_scan {
2086 struct mwl8k_cmd_pkt header;
2087 __le32 isibss;
d89173f2 2088 __u8 bssid[ETH_ALEN];
a66098da
LB		 2089} __attribute__((packed));
2090
2091static int
ce9e2e1b 2092mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, __u8 *mac)
a66098da
LB		 2093{
2094 struct mwl8k_cmd_set_post_scan *cmd;
2095 int rc;
2096
2097 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2098 if (cmd == NULL)
2099 return -ENOMEM;
2100
2101 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
2102 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2103 cmd->isibss = 0;
d89173f2 2104 memcpy(cmd->bssid, mac, ETH_ALEN);
a66098da
LB		 2105
2106 rc = mwl8k_post_cmd(hw, &cmd->header);
2107 kfree(cmd);
2108
2109 return rc;
2110}
2111
2112/*
2113 * CMD_SET_RF_CHANNEL.
2114 */
2115struct mwl8k_cmd_set_rf_channel {
2116 struct mwl8k_cmd_pkt header;
2117 __le16 action;
2118 __u8 current_channel;
2119 __le32 channel_flags;
2120} __attribute__((packed));
2121
2122static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
2123 struct ieee80211_channel *channel)
2124{
2125 struct mwl8k_cmd_set_rf_channel *cmd;
2126 int rc;
2127
2128 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2129 if (cmd == NULL)
2130 return -ENOMEM;
2131
2132 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
2133 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2134 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2135 cmd->current_channel = channel->hw_value;
2136 if (channel->band == IEEE80211_BAND_2GHZ)
2137 cmd->channel_flags = cpu_to_le32(0x00000081);
2138 else
2139 cmd->channel_flags = cpu_to_le32(0x00000000);
2140
2141 rc = mwl8k_post_cmd(hw, &cmd->header);
2142 kfree(cmd);
2143
2144 return rc;
2145}
2146
2147/*
2148 * CMD_SET_SLOT.
2149 */
2150struct mwl8k_cmd_set_slot {
2151 struct mwl8k_cmd_pkt header;
2152 __le16 action;
2153 __u8 short_slot;
2154} __attribute__((packed));
2155
5539bb51 2156static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
a66098da
LB		 2157{
2158 struct mwl8k_cmd_set_slot *cmd;
2159 int rc;
2160
2161 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2162 if (cmd == NULL)
2163 return -ENOMEM;
2164
2165 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
2166 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2167 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
5539bb51 2168 cmd->short_slot = short_slot_time;
a66098da
LB		 2169
2170 rc = mwl8k_post_cmd(hw, &cmd->header);
2171 kfree(cmd);
2172
2173 return rc;
2174}
2175
2176/*
2177 * CMD_MIMO_CONFIG.
2178 */
2179struct mwl8k_cmd_mimo_config {
2180 struct mwl8k_cmd_pkt header;
2181 __le32 action;
2182 __u8 rx_antenna_map;
2183 __u8 tx_antenna_map;
2184} __attribute__((packed));
2185
2186static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
2187{
2188 struct mwl8k_cmd_mimo_config *cmd;
2189 int rc;
2190
2191 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2192 if (cmd == NULL)
2193 return -ENOMEM;
2194
2195 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
2196 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2197 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
2198 cmd->rx_antenna_map = rx;
2199 cmd->tx_antenna_map = tx;
2200
2201 rc = mwl8k_post_cmd(hw, &cmd->header);
2202 kfree(cmd);
2203
2204 return rc;
2205}
2206
2207/*
2208 * CMD_ENABLE_SNIFFER.
2209 */
2210struct mwl8k_cmd_enable_sniffer {
2211 struct mwl8k_cmd_pkt header;
2212 __le32 action;
2213} __attribute__((packed));
2214
2215static int mwl8k_enable_sniffer(struct ieee80211_hw *hw, bool enable)
2216{
2217 struct mwl8k_cmd_enable_sniffer *cmd;
2218 int rc;
2219
2220 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2221 if (cmd == NULL)
2222 return -ENOMEM;
2223
2224 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
2225 cmd->header.length = cpu_to_le16(sizeof(*cmd));
ce9e2e1b 2226 cmd->action = cpu_to_le32(!!enable);
a66098da
LB		 2227
2228 rc = mwl8k_post_cmd(hw, &cmd->header);
2229 kfree(cmd);
2230
2231 return rc;
2232}
2233
32060e1b
LB		 2234/*
2235 * CMD_SET_MAC_ADDR.
2236 */
2237struct mwl8k_cmd_set_mac_addr {
2238 struct mwl8k_cmd_pkt header;
259a8e7d
LB		 2239 union {
2240 struct {
2241 __le16 mac_type;
2242 __u8 mac_addr[ETH_ALEN];
2243 } mbss;
2244 __u8 mac_addr[ETH_ALEN];
2245 };
32060e1b
LB		 2246} __attribute__((packed));
2247
2248static int mwl8k_set_mac_addr(struct ieee80211_hw *hw, u8 *mac)
2249{
259a8e7d 2250 struct mwl8k_priv *priv = hw->priv;
32060e1b
LB		 2251 struct mwl8k_cmd_set_mac_addr *cmd;
2252 int rc;
2253
2254 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2255 if (cmd == NULL)
2256 return -ENOMEM;
2257
2258 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
2259 cmd->header.length = cpu_to_le16(sizeof(*cmd));
259a8e7d
LB		 2260 if (priv->ap_fw) {
2261 cmd->mbss.mac_type = 0;
2262 memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN);
2263 } else {
2264 memcpy(cmd->mac_addr, mac, ETH_ALEN);
2265 }
32060e1b
LB		 2266
2267 rc = mwl8k_post_cmd(hw, &cmd->header);
2268 kfree(cmd);
2269
2270 return rc;
2271}
2272
2273
a66098da 2274/*
ce9e2e1b 2275 * CMD_SET_RATEADAPT_MODE.
a66098da
LB		 2276 */
2277struct mwl8k_cmd_set_rate_adapt_mode {
2278 struct mwl8k_cmd_pkt header;
2279 __le16 action;
2280 __le16 mode;
2281} __attribute__((packed));
2282
2283static int mwl8k_cmd_setrateadaptmode(struct ieee80211_hw *hw, __u16 mode)
2284{
2285 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
2286 int rc;
2287
2288 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2289 if (cmd == NULL)
2290 return -ENOMEM;
2291
2292 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
2293 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2294 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2295 cmd->mode = cpu_to_le16(mode);
2296
2297 rc = mwl8k_post_cmd(hw, &cmd->header);
2298 kfree(cmd);
2299
2300 return rc;
2301}
2302
2303/*
2304 * CMD_SET_WMM_MODE.
2305 */
2306struct mwl8k_cmd_set_wmm {
2307 struct mwl8k_cmd_pkt header;
2308 __le16 action;
2309} __attribute__((packed));
2310
2311static int mwl8k_set_wmm(struct ieee80211_hw *hw, bool enable)
2312{
2313 struct mwl8k_priv *priv = hw->priv;
2314 struct mwl8k_cmd_set_wmm *cmd;
2315 int rc;
2316
2317 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2318 if (cmd == NULL)
2319 return -ENOMEM;
2320
2321 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
2322 cmd->header.length = cpu_to_le16(sizeof(*cmd));
0439b1f5 2323 cmd->action = cpu_to_le16(!!enable);
a66098da
LB		 2324
2325 rc = mwl8k_post_cmd(hw, &cmd->header);
2326 kfree(cmd);
2327
2328 if (!rc)
0439b1f5 2329 priv->wmm_enabled = enable;
a66098da
LB		 2330
2331 return rc;
2332}
2333
2334/*
2335 * CMD_SET_RTS_THRESHOLD.
2336 */
2337struct mwl8k_cmd_rts_threshold {
2338 struct mwl8k_cmd_pkt header;
2339 __le16 action;
2340 __le16 threshold;
2341} __attribute__((packed));
2342
2343static int mwl8k_rts_threshold(struct ieee80211_hw *hw,
733d3067 2344 u16 action, u16 threshold)
a66098da
LB		 2345{
2346 struct mwl8k_cmd_rts_threshold *cmd;
2347 int rc;
2348
2349 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2350 if (cmd == NULL)
2351 return -ENOMEM;
2352
2353 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
2354 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2355 cmd->action = cpu_to_le16(action);
733d3067 2356 cmd->threshold = cpu_to_le16(threshold);
a66098da
LB		 2357
2358 rc = mwl8k_post_cmd(hw, &cmd->header);
2359 kfree(cmd);
2360
2361 return rc;
2362}
2363
2364/*
2365 * CMD_SET_EDCA_PARAMS.
2366 */
2367struct mwl8k_cmd_set_edca_params {
2368 struct mwl8k_cmd_pkt header;
2369
2370 /* See MWL8K_SET_EDCA_XXX below */
2371 __le16 action;
2372
2373 /* TX opportunity in units of 32 us */
2374 __le16 txop;
2375
2e484c89
LB		 2376 union {
2377 struct {
2378 /* Log exponent of max contention period: 0...15 */
2379 __le32 log_cw_max;
2380
2381 /* Log exponent of min contention period: 0...15 */
2382 __le32 log_cw_min;
2383
2384 /* Adaptive interframe spacing in units of 32us */
2385 __u8 aifs;
2386
2387 /* TX queue to configure */
2388 __u8 txq;
2389 } ap;
2390 struct {
2391 /* Log exponent of max contention period: 0...15 */
2392 __u8 log_cw_max;
a66098da 2393
2e484c89
LB		 2394 /* Log exponent of min contention period: 0...15 */
2395 __u8 log_cw_min;
a66098da 2396
2e484c89
LB		 2397 /* Adaptive interframe spacing in units of 32us */
2398 __u8 aifs;
a66098da 2399
2e484c89
LB		 2400 /* TX queue to configure */
2401 __u8 txq;
2402 } sta;
2403 };
a66098da
LB		 2404} __attribute__((packed));
2405
a66098da
LB		 2406#define MWL8K_SET_EDCA_CW 0x01
2407#define MWL8K_SET_EDCA_TXOP 0x02
2408#define MWL8K_SET_EDCA_AIFS 0x04
2409
2410#define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2411 MWL8K_SET_EDCA_TXOP | \
2412 MWL8K_SET_EDCA_AIFS)
2413
2414static int
2415mwl8k_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2416 __u16 cw_min, __u16 cw_max,
2417 __u8 aifs, __u16 txop)
2418{
2e484c89 2419 struct mwl8k_priv *priv = hw->priv;
a66098da 2420 struct mwl8k_cmd_set_edca_params *cmd;
a66098da
LB		 2421 int rc;
2422
2423 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2424 if (cmd == NULL)
2425 return -ENOMEM;
2426
22995b24
LB		 2427 /*
2428 * Queues 0 (BE) and 1 (BK) are swapped in hardware for
2429 * this call.
2430 */
2431 qnum ^= !(qnum >> 1);
2432
a66098da
LB		 2433 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2434 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 2435 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2436 cmd->txop = cpu_to_le16(txop);
2e484c89
LB		 2437 if (priv->ap_fw) {
2438 cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1));
2439 cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1));
2440 cmd->ap.aifs = aifs;
2441 cmd->ap.txq = qnum;
2442 } else {
2443 cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1);
2444 cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1);
2445 cmd->sta.aifs = aifs;
2446 cmd->sta.txq = qnum;
2447 }
a66098da
LB		 2448
2449 rc = mwl8k_post_cmd(hw, &cmd->header);
2450 kfree(cmd);
2451
2452 return rc;
2453}
2454
2455/*
2456 * CMD_FINALIZE_JOIN.
2457 */
2458
2459/* FJ beacon buffer size is compiled into the firmware. */
2460#define MWL8K_FJ_BEACON_MAXLEN 128
2461
2462struct mwl8k_cmd_finalize_join {
2463 struct mwl8k_cmd_pkt header;
2464 __le32 sleep_interval; /* Number of beacon periods to sleep */
2465 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
2466} __attribute__((packed));
2467
2468static int mwl8k_finalize_join(struct ieee80211_hw *hw, void *frame,
2469 __u16 framelen, __u16 dtim)
2470{
2471 struct mwl8k_cmd_finalize_join *cmd;
2472 struct ieee80211_mgmt *payload = frame;
2473 u16 hdrlen;
2474 u32 payload_len;
2475 int rc;
2476
2477 if (frame == NULL)
2478 return -EINVAL;
2479
2480 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2481 if (cmd == NULL)
2482 return -ENOMEM;
2483
2484 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
2485 cmd->header.length = cpu_to_le16(sizeof(*cmd));
ce9e2e1b 2486 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
a66098da
LB		 2487
2488 hdrlen = ieee80211_hdrlen(payload->frame_control);
2489
2490 payload_len = framelen > hdrlen ? framelen - hdrlen : 0;
2491
2492 /* XXX TBD Might just have to abort and return an error */
2493 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2494 printk(KERN_ERR "%s(): WARNING: Incomplete beacon "
c2c357ce
LB		 2495 "sent to firmware. Sz=%u MAX=%u\n", __func__,
2496 payload_len, MWL8K_FJ_BEACON_MAXLEN);
a66098da 2497
ce9e2e1b
LB		 2498 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2499 payload_len = MWL8K_FJ_BEACON_MAXLEN;
a66098da
LB		 2500
2501 if (payload && payload_len)
2502 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
2503
2504 rc = mwl8k_post_cmd(hw, &cmd->header);
2505 kfree(cmd);
2506 return rc;
2507}
2508
2509/*
2510 * CMD_UPDATE_STADB.
2511 */
2512struct mwl8k_cmd_update_sta_db {
2513 struct mwl8k_cmd_pkt header;
2514
2515 /* See STADB_ACTION_TYPE */
2516 __le32 action;
2517
2518 /* Peer MAC address */
d89173f2 2519 __u8 peer_addr[ETH_ALEN];
a66098da
LB		 2520
2521 __le32 reserved;
2522
2523 /* Peer info - valid during add/update. */
2524 struct peer_capability_info peer_info;
2525} __attribute__((packed));
2526
2527static int mwl8k_cmd_update_sta_db(struct ieee80211_hw *hw,
2528 struct ieee80211_vif *vif, __u32 action)
2529{
2530 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2531 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2532 struct mwl8k_cmd_update_sta_db *cmd;
2533 struct peer_capability_info *peer_info;
a66098da 2534 int rc;
a66098da
LB		 2535
2536 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2537 if (cmd == NULL)
2538 return -ENOMEM;
2539
2540 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2541 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2542
2543 cmd->action = cpu_to_le32(action);
2544 peer_info = &cmd->peer_info;
d89173f2 2545 memcpy(cmd->peer_addr, mv_vif->bssid, ETH_ALEN);
a66098da
LB		 2546
2547 switch (action) {
2548 case MWL8K_STA_DB_ADD_ENTRY:
2549 case MWL8K_STA_DB_MODIFY_ENTRY:
2550 /* Build peer_info block */
2551 peer_info->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2552 peer_info->basic_caps = cpu_to_le16(info->assoc_capability);
140eb5e2
LB		 2553 memcpy(peer_info->legacy_rates, mwl8k_rateids,
2554 sizeof(mwl8k_rateids));
a66098da
LB		 2555 peer_info->interop = 1;
2556 peer_info->amsdu_enabled = 0;
2557
a66098da
LB		 2558 rc = mwl8k_post_cmd(hw, &cmd->header);
2559 if (rc == 0)
2560 mv_vif->peer_id = peer_info->station_id;
2561
2562 break;
2563
2564 case MWL8K_STA_DB_DEL_ENTRY:
2565 case MWL8K_STA_DB_FLUSH:
2566 default:
2567 rc = mwl8k_post_cmd(hw, &cmd->header);
2568 if (rc == 0)
2569 mv_vif->peer_id = 0;
2570 break;
2571 }
2572 kfree(cmd);
2573
2574 return rc;
2575}
2576
2577/*
2578 * CMD_SET_AID.
2579 */
a66098da
LB		 2580#define MWL8K_FRAME_PROT_DISABLED 0x00
2581#define MWL8K_FRAME_PROT_11G 0x07
2582#define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2583#define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
a66098da
LB		 2584
2585struct mwl8k_cmd_update_set_aid {
2586 struct mwl8k_cmd_pkt header;
2587 __le16 aid;
2588
2589 /* AP's MAC address (BSSID) */
d89173f2 2590 __u8 bssid[ETH_ALEN];
a66098da 2591 __le16 protection_mode;
140eb5e2 2592 __u8 supp_rates[14];
a66098da
LB		 2593} __attribute__((packed));
2594
2595static int mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2596 struct ieee80211_vif *vif)
2597{
2598 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2599 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2600 struct mwl8k_cmd_update_set_aid *cmd;
a66098da
LB		 2601 u16 prot_mode;
2602 int rc;
2603
2604 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2605 if (cmd == NULL)
2606 return -ENOMEM;
2607
2608 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
2609 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2610 cmd->aid = cpu_to_le16(info->aid);
2611
d89173f2 2612 memcpy(cmd->bssid, mv_vif->bssid, ETH_ALEN);
a66098da 2613
a66098da
LB		 2614 if (info->use_cts_prot) {
2615 prot_mode = MWL8K_FRAME_PROT_11G;
2616 } else {
9ed6bcce 2617 switch (info->ht_operation_mode &
a66098da
LB		 2618 IEEE80211_HT_OP_MODE_PROTECTION) {
2619 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2620 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2621 break;
2622 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2623 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2624 break;
2625 default:
2626 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2627 break;
2628 }
2629 }
a66098da
LB		 2630 cmd->protection_mode = cpu_to_le16(prot_mode);
2631
140eb5e2 2632 memcpy(cmd->supp_rates, mwl8k_rateids, sizeof(mwl8k_rateids));
a66098da
LB		 2633
2634 rc = mwl8k_post_cmd(hw, &cmd->header);
2635 kfree(cmd);
2636
2637 return rc;
2638}
2639
2640/*
2641 * CMD_SET_RATE.
2642 */
2643struct mwl8k_cmd_update_rateset {
2644 struct mwl8k_cmd_pkt header;
140eb5e2 2645 __u8 legacy_rates[14];
a66098da
LB		 2646
2647 /* Bitmap for supported MCS codes. */
0b5351a8
LB		 2648 __u8 mcs_set[16];
2649 __u8 reserved[16];
a66098da
LB		 2650} __attribute__((packed));
2651
2652static int mwl8k_update_rateset(struct ieee80211_hw *hw,
2653 struct ieee80211_vif *vif)
2654{
a66098da 2655 struct mwl8k_cmd_update_rateset *cmd;
a66098da
LB		 2656 int rc;
2657
2658 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2659 if (cmd == NULL)
2660 return -ENOMEM;
2661
2662 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
2663 cmd->header.length = cpu_to_le16(sizeof(*cmd));
140eb5e2 2664 memcpy(cmd->legacy_rates, mwl8k_rateids, sizeof(mwl8k_rateids));
a66098da
LB		 2665
2666 rc = mwl8k_post_cmd(hw, &cmd->header);
2667 kfree(cmd);
2668
2669 return rc;
2670}
2671
2672/*
2673 * CMD_USE_FIXED_RATE.
2674 */
2675#define MWL8K_RATE_TABLE_SIZE 8
2676#define MWL8K_UCAST_RATE 0
a66098da
LB		 2677#define MWL8K_USE_AUTO_RATE 0x0002
2678
2679struct mwl8k_rate_entry {
2680 /* Set to 1 if HT rate, 0 if legacy. */
2681 __le32 is_ht_rate;
2682
2683 /* Set to 1 to use retry_count field. */
2684 __le32 enable_retry;
2685
2686 /* Specified legacy rate or MCS. */
2687 __le32 rate;
2688
2689 /* Number of allowed retries. */
2690 __le32 retry_count;
2691} __attribute__((packed));
2692
2693struct mwl8k_rate_table {
2694 /* 1 to allow specified rate and below */
2695 __le32 allow_rate_drop;
2696 __le32 num_rates;
2697 struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE];
2698} __attribute__((packed));
2699
2700struct mwl8k_cmd_use_fixed_rate {
2701 struct mwl8k_cmd_pkt header;
2702 __le32 action;
2703 struct mwl8k_rate_table rate_table;
2704
2705 /* Unicast, Broadcast or Multicast */
2706 __le32 rate_type;
2707 __le32 reserved1;
2708 __le32 reserved2;
2709} __attribute__((packed));
2710
2711static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw,
2712 u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table)
2713{
2714 struct mwl8k_cmd_use_fixed_rate *cmd;
2715 int count;
2716 int rc;
2717
2718 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2719 if (cmd == NULL)
2720 return -ENOMEM;
2721
2722 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2723 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2724
2725 cmd->action = cpu_to_le32(action);
2726 cmd->rate_type = cpu_to_le32(rate_type);
2727
2728 if (rate_table != NULL) {
c2c357ce
LB		 2729 /*
2730 * Copy over each field manually so that endian
2731 * conversion can be done.
2732 */
a66098da
LB		 2733 cmd->rate_table.allow_rate_drop =
2734 cpu_to_le32(rate_table->allow_rate_drop);
2735 cmd->rate_table.num_rates =
2736 cpu_to_le32(rate_table->num_rates);
2737
2738 for (count = 0; count < rate_table->num_rates; count++) {
2739 struct mwl8k_rate_entry *dst =
2740 &cmd->rate_table.rate_entry[count];
2741 struct mwl8k_rate_entry *src =
2742 &rate_table->rate_entry[count];
2743
2744 dst->is_ht_rate = cpu_to_le32(src->is_ht_rate);
2745 dst->enable_retry = cpu_to_le32(src->enable_retry);
2746 dst->rate = cpu_to_le32(src->rate);
2747 dst->retry_count = cpu_to_le32(src->retry_count);
2748 }
2749 }
2750
2751 rc = mwl8k_post_cmd(hw, &cmd->header);
2752 kfree(cmd);
2753
2754 return rc;
2755}
2756
2757
2758/*
2759 * Interrupt handling.
2760 */
2761static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2762{
2763 struct ieee80211_hw *hw = dev_id;
2764 struct mwl8k_priv *priv = hw->priv;
2765 u32 status;
2766
2767 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2768 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2769
a66098da
LB		 2770 if (!status)
2771 return IRQ_NONE;
2772
2773 if (status & MWL8K_A2H_INT_TX_DONE)
2774 tasklet_schedule(&priv->tx_reclaim_task);
2775
2776 if (status & MWL8K_A2H_INT_RX_READY) {
2777 while (rxq_process(hw, 0, 1))
2778 rxq_refill(hw, 0, 1);
2779 }
2780
2781 if (status & MWL8K_A2H_INT_OPC_DONE) {
618952a7 2782 if (priv->hostcmd_wait != NULL)
a66098da 2783 complete(priv->hostcmd_wait);
a66098da
LB		 2784 }
2785
2786 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
618952a7 2787 if (!mutex_is_locked(&priv->fw_mutex) &&
88de754a 2788 priv->radio_on && priv->pending_tx_pkts)
618952a7 2789 mwl8k_tx_start(priv);
a66098da
LB		 2790 }
2791
2792 return IRQ_HANDLED;
2793}
2794
2795
2796/*
2797 * Core driver operations.
2798 */
2799static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2800{
2801 struct mwl8k_priv *priv = hw->priv;
2802 int index = skb_get_queue_mapping(skb);
2803 int rc;
2804
2805 if (priv->current_channel == NULL) {
2806 printk(KERN_DEBUG "%s: dropped TX frame since radio "
c2c357ce 2807 "disabled\n", wiphy_name(hw->wiphy));
a66098da
LB		 2808 dev_kfree_skb(skb);
2809 return NETDEV_TX_OK;
2810 }
2811
2812 rc = mwl8k_txq_xmit(hw, index, skb);
2813
2814 return rc;
2815}
2816
a66098da
LB		 2817static int mwl8k_start(struct ieee80211_hw *hw)
2818{
a66098da
LB		 2819 struct mwl8k_priv *priv = hw->priv;
2820 int rc;
2821
a0607fd3 2822 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 2823 IRQF_SHARED, MWL8K_NAME, hw);
2824 if (rc) {
2825 printk(KERN_ERR "%s: failed to register IRQ handler\n",
c2c357ce 2826 wiphy_name(hw->wiphy));
2ec610cb 2827 return -EIO;
a66098da
LB		 2828 }
2829
2ec610cb
LB		 2830 /* Enable tx reclaim tasklet */
2831 tasklet_enable(&priv->tx_reclaim_task);
2832
a66098da 2833 /* Enable interrupts */
c23b5a69 2834 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da 2835
2ec610cb
LB		 2836 rc = mwl8k_fw_lock(hw);
2837 if (!rc) {
2838 rc = mwl8k_cmd_802_11_radio_enable(hw);
a66098da 2839
5e4cf166
LB		 2840 if (!priv->ap_fw) {
2841 if (!rc)
2842 rc = mwl8k_enable_sniffer(hw, 0);
a66098da 2843
5e4cf166
LB		 2844 if (!rc)
2845 rc = mwl8k_cmd_set_pre_scan(hw);
2846
2847 if (!rc)
2848 rc = mwl8k_cmd_set_post_scan(hw,
2849 "\x00\x00\x00\x00\x00\x00");
2850 }
2ec610cb
LB		 2851
2852 if (!rc)
2853 rc = mwl8k_cmd_setrateadaptmode(hw, 0);
a66098da 2854
2ec610cb
LB		 2855 if (!rc)
2856 rc = mwl8k_set_wmm(hw, 0);
a66098da 2857
2ec610cb
LB		 2858 mwl8k_fw_unlock(hw);
2859 }
2860
2861 if (rc) {
2862 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2863 free_irq(priv->pdev->irq, hw);
2864 tasklet_disable(&priv->tx_reclaim_task);
2865 }
a66098da
LB		 2866
2867 return rc;
2868}
2869
a66098da
LB		 2870static void mwl8k_stop(struct ieee80211_hw *hw)
2871{
a66098da
LB		 2872 struct mwl8k_priv *priv = hw->priv;
2873 int i;
2874
d3cea0b8 2875 mwl8k_cmd_802_11_radio_disable(hw);
a66098da
LB		 2876
2877 ieee80211_stop_queues(hw);
2878
a66098da 2879 /* Disable interrupts */
a66098da 2880 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 2881 free_irq(priv->pdev->irq, hw);
2882
2883 /* Stop finalize join worker */
2884 cancel_work_sync(&priv->finalize_join_worker);
2885 if (priv->beacon_skb != NULL)
2886 dev_kfree_skb(priv->beacon_skb);
2887
2888 /* Stop tx reclaim tasklet */
2889 tasklet_disable(&priv->tx_reclaim_task);
2890
a66098da
LB		 2891 /* Return all skbs to mac80211 */
2892 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2893 mwl8k_txq_reclaim(hw, i, 1);
2894}
2895
2896static int mwl8k_add_interface(struct ieee80211_hw *hw,
2897 struct ieee80211_if_init_conf *conf)
2898{
2899 struct mwl8k_priv *priv = hw->priv;
2900 struct mwl8k_vif *mwl8k_vif;
2901
2902 /*
2903 * We only support one active interface at a time.
2904 */
2905 if (priv->vif != NULL)
2906 return -EBUSY;
2907
2908 /*
2909 * We only support managed interfaces for now.
2910 */
240e86ef 2911 if (conf->type != NL80211_IFTYPE_STATION)
a66098da
LB		 2912 return -EINVAL;
2913
a43c49a8
LB		 2914 /*
2915 * Reject interface creation if sniffer mode is active, as
2916 * STA operation is mutually exclusive with hardware sniffer
2917 * mode.
2918 */
2919 if (priv->sniffer_enabled) {
2920 printk(KERN_INFO "%s: unable to create STA "
2921 "interface due to sniffer mode being enabled\n",
2922 wiphy_name(hw->wiphy));
2923 return -EINVAL;
2924 }
2925
a66098da
LB		 2926 /* Clean out driver private area */
2927 mwl8k_vif = MWL8K_VIF(conf->vif);
2928 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
2929
32060e1b
LB		 2930 /* Set and save the mac address */
2931 mwl8k_set_mac_addr(hw, conf->mac_addr);
d89173f2 2932 memcpy(mwl8k_vif->mac_addr, conf->mac_addr, ETH_ALEN);
a66098da
LB		 2933
2934 /* Back pointer to parent config block */
2935 mwl8k_vif->priv = priv;
2936
a66098da
LB		 2937 /* Set Initial sequence number to zero */
2938 mwl8k_vif->seqno = 0;
2939
2940 priv->vif = conf->vif;
2941 priv->current_channel = NULL;
2942
2943 return 0;
2944}
2945
2946static void mwl8k_remove_interface(struct ieee80211_hw *hw,
2947 struct ieee80211_if_init_conf *conf)
2948{
2949 struct mwl8k_priv *priv = hw->priv;
2950
2951 if (priv->vif == NULL)
2952 return;
2953
32060e1b
LB		 2954 mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
2955
a66098da
LB		 2956 priv->vif = NULL;
2957}
2958
ee03a932 2959static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
a66098da 2960{
a66098da
LB		 2961 struct ieee80211_conf *conf = &hw->conf;
2962 struct mwl8k_priv *priv = hw->priv;
ee03a932 2963 int rc;
a66098da 2964
7595d67a
LB		 2965 if (conf->flags & IEEE80211_CONF_IDLE) {
2966 mwl8k_cmd_802_11_radio_disable(hw);
2967 priv->current_channel = NULL;
ee03a932 2968 return 0;
7595d67a
LB		 2969 }
2970
ee03a932
LB		 2971 rc = mwl8k_fw_lock(hw);
2972 if (rc)
2973 return rc;
a66098da 2974
ee03a932
LB		 2975 rc = mwl8k_cmd_802_11_radio_enable(hw);
2976 if (rc)
2977 goto out;
a66098da 2978
ee03a932
LB		 2979 rc = mwl8k_cmd_set_rf_channel(hw, conf->channel);
2980 if (rc)
2981 goto out;
2982
2983 priv->current_channel = conf->channel;
a66098da
LB		 2984
2985 if (conf->power_level > 18)
2986 conf->power_level = 18;
ee03a932
LB		 2987 rc = mwl8k_cmd_802_11_rf_tx_power(hw, conf->power_level);
2988 if (rc)
2989 goto out;
a66098da 2990
08b06347
LB		 2991 if (priv->ap_fw) {
2992 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x7);
2993 if (!rc)
2994 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7);
2995 } else {
2996 rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7);
2997 }
a66098da 2998
ee03a932
LB		 2999out:
3000 mwl8k_fw_unlock(hw);
a66098da 3001
ee03a932 3002 return rc;
a66098da
LB		 3003}
3004
3a980d0a
LB		 3005static void mwl8k_bss_info_changed(struct ieee80211_hw *hw,
3006 struct ieee80211_vif *vif,
3007 struct ieee80211_bss_conf *info,
3008 u32 changed)
a66098da 3009{
a66098da
LB		 3010 struct mwl8k_priv *priv = hw->priv;
3011 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
3a980d0a
LB		 3012 int rc;
3013
3014 if (changed & BSS_CHANGED_BSSID)
3015 memcpy(mwl8k_vif->bssid, info->bssid, ETH_ALEN);
3016
3017 if ((changed & BSS_CHANGED_ASSOC) == 0)
3018 return;
a66098da 3019
a66098da
LB		 3020 priv->capture_beacon = false;
3021
3a980d0a 3022 rc = mwl8k_fw_lock(hw);
942457d6 3023 if (rc)
3a980d0a
LB		 3024 return;
3025
a66098da
LB		 3026 if (info->assoc) {
3027 memcpy(&mwl8k_vif->bss_info, info,
3028 sizeof(struct ieee80211_bss_conf));
3029
3030 /* Install rates */
3a980d0a
LB		 3031 rc = mwl8k_update_rateset(hw, vif);
3032 if (rc)
3033 goto out;
a66098da
LB		 3034
3035 /* Turn on rate adaptation */
3a980d0a
LB		 3036 rc = mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE,
3037 MWL8K_UCAST_RATE, NULL);
3038 if (rc)
3039 goto out;
a66098da
LB		 3040
3041 /* Set radio preamble */
3a980d0a
LB		 3042 rc = mwl8k_set_radio_preamble(hw, info->use_short_preamble);
3043 if (rc)
3044 goto out;
a66098da
LB		 3045
3046 /* Set slot time */
3a980d0a
LB		 3047 rc = mwl8k_cmd_set_slot(hw, info->use_short_slot);
3048 if (rc)
3049 goto out;
a66098da
LB		 3050
3051 /* Update peer rate info */
3a980d0a
LB		 3052 rc = mwl8k_cmd_update_sta_db(hw, vif,
3053 MWL8K_STA_DB_MODIFY_ENTRY);
3054 if (rc)
3055 goto out;
a66098da
LB		 3056
3057 /* Set AID */
3a980d0a
LB		 3058 rc = mwl8k_cmd_set_aid(hw, vif);
3059 if (rc)
3060 goto out;
a66098da
LB		 3061
3062 /*
3063 * Finalize the join. Tell rx handler to process
3064 * next beacon from our BSSID.
3065 */
d89173f2 3066 memcpy(priv->capture_bssid, mwl8k_vif->bssid, ETH_ALEN);
a66098da
LB		 3067 priv->capture_beacon = true;
3068 } else {
3a980d0a 3069 rc = mwl8k_cmd_update_sta_db(hw, vif, MWL8K_STA_DB_DEL_ENTRY);
a66098da
LB		 3070 memset(&mwl8k_vif->bss_info, 0,
3071 sizeof(struct ieee80211_bss_conf));
d89173f2 3072 memset(mwl8k_vif->bssid, 0, ETH_ALEN);
a66098da
LB		 3073 }
3074
3a980d0a
LB		 3075out:
3076 mwl8k_fw_unlock(hw);
a66098da
LB		 3077}
3078
e81cd2d6
LB		 3079static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
3080 int mc_count, struct dev_addr_list *mclist)
3081{
3082 struct mwl8k_cmd_pkt *cmd;
3083
447ced07
LB		 3084 /*
3085 * Synthesize and return a command packet that programs the
3086 * hardware multicast address filter. At this point we don't
3087 * know whether FIF_ALLMULTI is being requested, but if it is,
3088 * we'll end up throwing this packet away and creating a new
3089 * one in mwl8k_configure_filter().
3090 */
3091 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist);
e81cd2d6
LB		 3092
3093 return (unsigned long)cmd;
3094}
3095
a43c49a8
LB		 3096static int
3097mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
3098 unsigned int changed_flags,
3099 unsigned int *total_flags)
3100{
3101 struct mwl8k_priv *priv = hw->priv;
3102
3103 /*
3104 * Hardware sniffer mode is mutually exclusive with STA
3105 * operation, so refuse to enable sniffer mode if a STA
3106 * interface is active.
3107 */
3108 if (priv->vif != NULL) {
3109 if (net_ratelimit())
3110 printk(KERN_INFO "%s: not enabling sniffer "
3111 "mode because STA interface is active\n",
3112 wiphy_name(hw->wiphy));
3113 return 0;
3114 }
3115
3116 if (!priv->sniffer_enabled) {
3117 if (mwl8k_enable_sniffer(hw, 1))
3118 return 0;
3119 priv->sniffer_enabled = true;
3120 }
3121
3122 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
3123 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
3124 FIF_OTHER_BSS;
3125
3126 return 1;
3127}
3128
e6935ea1
LB		 3129static void mwl8k_configure_filter(struct ieee80211_hw *hw,
3130 unsigned int changed_flags,
3131 unsigned int *total_flags,
3132 u64 multicast)
3133{
3134 struct mwl8k_priv *priv = hw->priv;
a43c49a8
LB		 3135 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
3136
c0adae2c
LB		 3137 /*
3138 * AP firmware doesn't allow fine-grained control over
3139 * the receive filter.
3140 */
3141 if (priv->ap_fw) {
3142 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
3143 kfree(cmd);
3144 return;
3145 }
3146
a43c49a8
LB		 3147 /*
3148 * Enable hardware sniffer mode if FIF_CONTROL or
3149 * FIF_OTHER_BSS is requested.
3150 */
3151 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
3152 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
3153 kfree(cmd);
3154 return;
3155 }
a66098da 3156
e6935ea1 3157 /* Clear unsupported feature flags */
447ced07 3158 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
a66098da 3159
e6935ea1
LB		 3160 if (mwl8k_fw_lock(hw))
3161 return;
a66098da 3162
a43c49a8
LB		 3163 if (priv->sniffer_enabled) {
3164 mwl8k_enable_sniffer(hw, 0);
3165 priv->sniffer_enabled = false;
3166 }
3167
e6935ea1 3168 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
77165d88
LB		 3169 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
3170 /*
3171 * Disable the BSS filter.
3172 */
e6935ea1 3173 mwl8k_cmd_set_pre_scan(hw);
77165d88 3174 } else {
a94cc97e
LB		 3175 u8 *bssid;
3176
77165d88
LB		 3177 /*
3178 * Enable the BSS filter.
3179 *
3180 * If there is an active STA interface, use that
3181 * interface's BSSID, otherwise use a dummy one
3182 * (where the OUI part needs to be nonzero for
3183 * the BSSID to be accepted by POST_SCAN).
3184 */
3185 bssid = "\x01\x00\x00\x00\x00\x00";
a94cc97e
LB		 3186 if (priv->vif != NULL)
3187 bssid = MWL8K_VIF(priv->vif)->bssid;
3188
e6935ea1 3189 mwl8k_cmd_set_post_scan(hw, bssid);
a66098da
LB		 3190 }
3191 }
3192
447ced07
LB		 3193 /*
3194 * If FIF_ALLMULTI is being requested, throw away the command
3195 * packet that ->prepare_multicast() built and replace it with
3196 * a command packet that enables reception of all multicast
3197 * packets.
3198 */
3199 if (*total_flags & FIF_ALLMULTI) {
3200 kfree(cmd);
3201 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL);
3202 }
3203
3204 if (cmd != NULL) {
3205 mwl8k_post_cmd(hw, cmd);
3206 kfree(cmd);
e6935ea1 3207 }
a66098da 3208
e6935ea1 3209 mwl8k_fw_unlock(hw);
a66098da
LB		 3210}
3211
a66098da
LB		 3212static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3213{
733d3067 3214 return mwl8k_rts_threshold(hw, MWL8K_CMD_SET, value);
a66098da
LB		 3215}
3216
a66098da
LB		 3217static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
3218 const struct ieee80211_tx_queue_params *params)
3219{
3e4f542c 3220 struct mwl8k_priv *priv = hw->priv;
a66098da 3221 int rc;
a66098da 3222
3e4f542c
LB		 3223 rc = mwl8k_fw_lock(hw);
3224 if (!rc) {
3225 if (!priv->wmm_enabled)
3226 rc = mwl8k_set_wmm(hw, 1);
a66098da 3227
3e4f542c
LB		 3228 if (!rc)
3229 rc = mwl8k_set_edca_params(hw, queue,
3230 params->cw_min,
3231 params->cw_max,
3232 params->aifs,
3233 params->txop);
3234
3235 mwl8k_fw_unlock(hw);
a66098da 3236 }
3e4f542c 3237
a66098da
LB		 3238 return rc;
3239}
3240
3241static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
3242 struct ieee80211_tx_queue_stats *stats)
3243{
3244 struct mwl8k_priv *priv = hw->priv;
3245 struct mwl8k_tx_queue *txq;
3246 int index;
3247
3248 spin_lock_bh(&priv->tx_lock);
3249 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
3250 txq = priv->txq + index;
45eb400d 3251 memcpy(&stats[index], &txq->stats,
a66098da
LB		 3252 sizeof(struct ieee80211_tx_queue_stats));
3253 }
3254 spin_unlock_bh(&priv->tx_lock);
a66098da 3255
954ef509 3256 return 0;
a66098da
LB		 3257}
3258
3259static int mwl8k_get_stats(struct ieee80211_hw *hw,
3260 struct ieee80211_low_level_stats *stats)
3261{
954ef509 3262 return mwl8k_cmd_802_11_get_stat(hw, stats);
a66098da
LB		 3263}
3264
3265static const struct ieee80211_ops mwl8k_ops = {
3266 .tx = mwl8k_tx,
3267 .start = mwl8k_start,
3268 .stop = mwl8k_stop,
3269 .add_interface = mwl8k_add_interface,
3270 .remove_interface = mwl8k_remove_interface,
3271 .config = mwl8k_config,
a66098da 3272 .bss_info_changed = mwl8k_bss_info_changed,
3ac64bee 3273 .prepare_multicast = mwl8k_prepare_multicast,
a66098da
LB		 3274 .configure_filter = mwl8k_configure_filter,
3275 .set_rts_threshold = mwl8k_set_rts_threshold,
3276 .conf_tx = mwl8k_conf_tx,
3277 .get_tx_stats = mwl8k_get_tx_stats,
3278 .get_stats = mwl8k_get_stats,
3279};
3280
3281static void mwl8k_tx_reclaim_handler(unsigned long data)
3282{
3283 int i;
3284 struct ieee80211_hw *hw = (struct ieee80211_hw *) data;
3285 struct mwl8k_priv *priv = hw->priv;
3286
3287 spin_lock_bh(&priv->tx_lock);
3288 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3289 mwl8k_txq_reclaim(hw, i, 0);
3290
88de754a 3291 if (priv->tx_wait != NULL && !priv->pending_tx_pkts) {
ce9e2e1b
LB		 3292 complete(priv->tx_wait);
3293 priv->tx_wait = NULL;
a66098da
LB		 3294 }
3295 spin_unlock_bh(&priv->tx_lock);
3296}
3297
3298static void mwl8k_finalize_join_worker(struct work_struct *work)
3299{
3300 struct mwl8k_priv *priv =
3301 container_of(work, struct mwl8k_priv, finalize_join_worker);
3302 struct sk_buff *skb = priv->beacon_skb;
ce9e2e1b 3303 u8 dtim = MWL8K_VIF(priv->vif)->bss_info.dtim_period;
a66098da
LB		 3304
3305 mwl8k_finalize_join(priv->hw, skb->data, skb->len, dtim);
3306 dev_kfree_skb(skb);
3307
3308 priv->beacon_skb = NULL;
3309}
3310
bcb628d5
JL		 3311enum {
3312 MWL8687 = 0,
3313 MWL8366,
6f6d1e9a
LB		 3314};
3315
bcb628d5
JL		 3316static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = {
3317 {
3318 .part_name = "88w8687",
3319 .helper_image = "mwl8k/helper_8687.fw",
3320 .fw_image = "mwl8k/fmimage_8687.fw",
3321 .rxd_ops = &rxd_8687_ops,
3322 .modes = BIT(NL80211_IFTYPE_STATION),
3323 },
3324 {
3325 .part_name = "88w8366",
3326 .helper_image = "mwl8k/helper_8366.fw",
3327 .fw_image = "mwl8k/fmimage_8366.fw",
3328 .rxd_ops = &rxd_8366_ops,
3329 .modes = 0,
3330 },
45a390dd
LB		 3331};
3332
3333static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
bcb628d5
JL		 3334 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, },
3335 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, },
3336 { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, },
3337 { },
45a390dd
LB		 3338};
3339MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
3340
a66098da
LB		 3341static int __devinit mwl8k_probe(struct pci_dev *pdev,
3342 const struct pci_device_id *id)
3343{
2aa7b01f 3344 static int printed_version = 0;
a66098da
LB		 3345 struct ieee80211_hw *hw;
3346 struct mwl8k_priv *priv;
a66098da
LB		 3347 int rc;
3348 int i;
2aa7b01f
LB		 3349
3350 if (!printed_version) {
3351 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
3352 printed_version = 1;
3353 }
a66098da
LB		 3354
3355 rc = pci_enable_device(pdev);
3356 if (rc) {
3357 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
3358 MWL8K_NAME);
3359 return rc;
3360 }
3361
3362 rc = pci_request_regions(pdev, MWL8K_NAME);
3363 if (rc) {
3364 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
3365 MWL8K_NAME);
3366 return rc;
3367 }
3368
3369 pci_set_master(pdev);
3370
3371 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
3372 if (hw == NULL) {
3373 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
3374 rc = -ENOMEM;
3375 goto err_free_reg;
3376 }
3377
3378 priv = hw->priv;
3379 priv->hw = hw;
3380 priv->pdev = pdev;
bcb628d5 3381 priv->device_info = &mwl8k_info_tbl[id->driver_data];
54bc3a0d 3382 priv->rxd_ops = priv->device_info->rxd_ops;
a43c49a8 3383 priv->sniffer_enabled = false;
0439b1f5 3384 priv->wmm_enabled = false;
a66098da 3385 priv->pending_tx_pkts = 0;
a66098da 3386
a66098da
LB		 3387 SET_IEEE80211_DEV(hw, &pdev->dev);
3388 pci_set_drvdata(pdev, hw);
3389
5b9482dd
LB		 3390 priv->sram = pci_iomap(pdev, 0, 0x10000);
3391 if (priv->sram == NULL) {
3392 printk(KERN_ERR "%s: Cannot map device SRAM\n",
c2c357ce 3393 wiphy_name(hw->wiphy));
a66098da
LB		 3394 goto err_iounmap;
3395 }
3396
5b9482dd
LB		 3397 /*
3398 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
3399 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
3400 */
3401 priv->regs = pci_iomap(pdev, 1, 0x10000);
3402 if (priv->regs == NULL) {
3403 priv->regs = pci_iomap(pdev, 2, 0x10000);
3404 if (priv->regs == NULL) {
3405 printk(KERN_ERR "%s: Cannot map device registers\n",
3406 wiphy_name(hw->wiphy));
3407 goto err_iounmap;
3408 }
3409 }
3410
a66098da
LB		 3411 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
3412 priv->band.band = IEEE80211_BAND_2GHZ;
3413 priv->band.channels = priv->channels;
3414 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
3415 priv->band.bitrates = priv->rates;
3416 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
3417 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
3418
3419 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
3420 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
3421
3422 /*
3423 * Extra headroom is the size of the required DMA header
3424 * minus the size of the smallest 802.11 frame (CTS frame).
3425 */
3426 hw->extra_tx_headroom =
3427 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
3428
3429 hw->channel_change_time = 10;
3430
3431 hw->queues = MWL8K_TX_QUEUES;
3432
547810e3 3433 hw->wiphy->interface_modes = priv->device_info->modes;
a66098da
LB		 3434
3435 /* Set rssi and noise values to dBm */
ce9e2e1b 3436 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
a66098da
LB		 3437 hw->vif_data_size = sizeof(struct mwl8k_vif);
3438 priv->vif = NULL;
3439
3440 /* Set default radio state and preamble */
c46563b7 3441 priv->radio_on = 0;
68ce3884 3442 priv->radio_short_preamble = 0;
a66098da
LB		 3443
3444 /* Finalize join worker */
3445 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
3446
3447 /* TX reclaim tasklet */
3448 tasklet_init(&priv->tx_reclaim_task,
3449 mwl8k_tx_reclaim_handler, (unsigned long)hw);
3450 tasklet_disable(&priv->tx_reclaim_task);
3451
a66098da
LB		 3452 /* Power management cookie */
3453 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
3454 if (priv->cookie == NULL)
3455 goto err_iounmap;
3456
3457 rc = mwl8k_rxq_init(hw, 0);
3458 if (rc)
3459 goto err_iounmap;
3460 rxq_refill(hw, 0, INT_MAX);
3461
618952a7
LB		 3462 mutex_init(&priv->fw_mutex);
3463 priv->fw_mutex_owner = NULL;
3464 priv->fw_mutex_depth = 0;
618952a7
LB		 3465 priv->hostcmd_wait = NULL;
3466
a66098da
LB		 3467 spin_lock_init(&priv->tx_lock);
3468
88de754a
LB		 3469 priv->tx_wait = NULL;
3470
a66098da
LB		 3471 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
3472 rc = mwl8k_txq_init(hw, i);
3473 if (rc)
3474 goto err_free_queues;
3475 }
3476
3477 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
c23b5a69 3478 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3479 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
3480 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3481
a0607fd3 3482 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 3483 IRQF_SHARED, MWL8K_NAME, hw);
3484 if (rc) {
3485 printk(KERN_ERR "%s: failed to register IRQ handler\n",
c2c357ce 3486 wiphy_name(hw->wiphy));
a66098da
LB		 3487 goto err_free_queues;
3488 }
3489
3490 /* Reset firmware and hardware */
3491 mwl8k_hw_reset(priv);
3492
3493 /* Ask userland hotplug daemon for the device firmware */
45a390dd 3494 rc = mwl8k_request_firmware(priv);
a66098da 3495 if (rc) {
c2c357ce
LB		 3496 printk(KERN_ERR "%s: Firmware files not found\n",
3497 wiphy_name(hw->wiphy));
a66098da
LB		 3498 goto err_free_irq;
3499 }
3500
3501 /* Load firmware into hardware */
c2c357ce 3502 rc = mwl8k_load_firmware(hw);
a66098da 3503 if (rc) {
c2c357ce
LB		 3504 printk(KERN_ERR "%s: Cannot start firmware\n",
3505 wiphy_name(hw->wiphy));
a66098da
LB		 3506 goto err_stop_firmware;
3507 }
3508
3509 /* Reclaim memory once firmware is successfully loaded */
3510 mwl8k_release_firmware(priv);
3511
3512 /*
3513 * Temporarily enable interrupts. Initial firmware host
3514 * commands use interrupts and avoids polling. Disable
3515 * interrupts when done.
3516 */
c23b5a69 3517 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3518
3519 /* Get config data, mac addrs etc */
42fba21d
LB		 3520 if (priv->ap_fw) {
3521 rc = mwl8k_cmd_get_hw_spec_ap(hw);
3522 if (!rc)
3523 rc = mwl8k_cmd_set_hw_spec(hw);
3524 } else {
3525 rc = mwl8k_cmd_get_hw_spec_sta(hw);
3526 }
a66098da 3527 if (rc) {
c2c357ce
LB		 3528 printk(KERN_ERR "%s: Cannot initialise firmware\n",
3529 wiphy_name(hw->wiphy));
a66098da
LB		 3530 goto err_stop_firmware;
3531 }
3532
3533 /* Turn radio off */
c46563b7 3534 rc = mwl8k_cmd_802_11_radio_disable(hw);
a66098da 3535 if (rc) {
c2c357ce 3536 printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
a66098da
LB		 3537 goto err_stop_firmware;
3538 }
3539
32060e1b
LB		 3540 /* Clear MAC address */
3541 rc = mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
3542 if (rc) {
3543 printk(KERN_ERR "%s: Cannot clear MAC address\n",
3544 wiphy_name(hw->wiphy));
3545 goto err_stop_firmware;
3546 }
3547
a66098da 3548 /* Disable interrupts */
a66098da 3549 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3550 free_irq(priv->pdev->irq, hw);
3551
3552 rc = ieee80211_register_hw(hw);
3553 if (rc) {
c2c357ce
LB		 3554 printk(KERN_ERR "%s: Cannot register device\n",
3555 wiphy_name(hw->wiphy));
a66098da
LB		 3556 goto err_stop_firmware;
3557 }
3558
eae74e65 3559 printk(KERN_INFO "%s: %s v%d, %pM, %s firmware %u.%u.%u.%u\n",
a74b295e 3560 wiphy_name(hw->wiphy), priv->device_info->part_name,
45a390dd 3561 priv->hw_rev, hw->wiphy->perm_addr,
eae74e65 3562 priv->ap_fw ? "AP" : "STA",
2aa7b01f
LB		 3563 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
3564 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
a66098da
LB		 3565
3566 return 0;
3567
3568err_stop_firmware:
3569 mwl8k_hw_reset(priv);
3570 mwl8k_release_firmware(priv);
3571
3572err_free_irq:
a66098da 3573 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3574 free_irq(priv->pdev->irq, hw);
3575
3576err_free_queues:
3577 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3578 mwl8k_txq_deinit(hw, i);
3579 mwl8k_rxq_deinit(hw, 0);
3580
3581err_iounmap:
3582 if (priv->cookie != NULL)
3583 pci_free_consistent(priv->pdev, 4,
3584 priv->cookie, priv->cookie_dma);
3585
3586 if (priv->regs != NULL)
3587 pci_iounmap(pdev, priv->regs);
3588
5b9482dd
LB		 3589 if (priv->sram != NULL)
3590 pci_iounmap(pdev, priv->sram);
3591
a66098da
LB		 3592 pci_set_drvdata(pdev, NULL);
3593 ieee80211_free_hw(hw);
3594
3595err_free_reg:
3596 pci_release_regions(pdev);
3597 pci_disable_device(pdev);
3598
3599 return rc;
3600}
3601
230f7af0 3602static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
a66098da
LB		 3603{
3604 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
3605}
3606
230f7af0 3607static void __devexit mwl8k_remove(struct pci_dev *pdev)
a66098da
LB		 3608{
3609 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
3610 struct mwl8k_priv *priv;
3611 int i;
3612
3613 if (hw == NULL)
3614 return;
3615 priv = hw->priv;
3616
3617 ieee80211_stop_queues(hw);
3618
60aa569f
LB		 3619 ieee80211_unregister_hw(hw);
3620
a66098da
LB		 3621 /* Remove tx reclaim tasklet */
3622 tasklet_kill(&priv->tx_reclaim_task);
3623
a66098da
LB		 3624 /* Stop hardware */
3625 mwl8k_hw_reset(priv);
3626
3627 /* Return all skbs to mac80211 */
3628 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3629 mwl8k_txq_reclaim(hw, i, 1);
3630
a66098da
LB		 3631 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3632 mwl8k_txq_deinit(hw, i);
3633
3634 mwl8k_rxq_deinit(hw, 0);
3635
c2c357ce 3636 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
a66098da
LB		 3637
3638 pci_iounmap(pdev, priv->regs);
5b9482dd 3639 pci_iounmap(pdev, priv->sram);
a66098da
LB		 3640 pci_set_drvdata(pdev, NULL);
3641 ieee80211_free_hw(hw);
3642 pci_release_regions(pdev);
3643 pci_disable_device(pdev);
3644}
3645
3646static struct pci_driver mwl8k_driver = {
3647 .name = MWL8K_NAME,
45a390dd 3648 .id_table = mwl8k_pci_id_table,
a66098da
LB		 3649 .probe = mwl8k_probe,
3650 .remove = __devexit_p(mwl8k_remove),
3651 .shutdown = __devexit_p(mwl8k_shutdown),
3652};
3653
3654static int __init mwl8k_init(void)
3655{
3656 return pci_register_driver(&mwl8k_driver);
3657}
3658
3659static void __exit mwl8k_exit(void)
3660{
3661 pci_unregister_driver(&mwl8k_driver);
3662}
3663
3664module_init(mwl8k_init);
3665module_exit(mwl8k_exit);
c2c357ce
LB		 3666
3667MODULE_DESCRIPTION(MWL8K_DESC);
3668MODULE_VERSION(MWL8K_VERSION);
3669MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
3670MODULE_LICENSE("GPL");
Motorola kernel-slsi