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mwl8k: allow more time for transmit rings to drain
[GitHub/MotorolaMobilityLLC/kernel-slsi.git] / drivers / net / wireless / mwl8k.c
CommitLineData
a66098da 1/*
ce9e2e1b
LB		 2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
a66098da 4 *
a145d575 5 * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
a66098da
LB		 6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
3d76e82c 15#include <linux/sched.h>
a66098da
LB		 16#include <linux/spinlock.h>
17#include <linux/list.h>
18#include <linux/pci.h>
19#include <linux/delay.h>
20#include <linux/completion.h>
21#include <linux/etherdevice.h>
22#include <net/mac80211.h>
23#include <linux/moduleparam.h>
24#include <linux/firmware.h>
25#include <linux/workqueue.h>
26
27#define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
28#define MWL8K_NAME KBUILD_MODNAME
a145d575 29#define MWL8K_VERSION "0.10"
a66098da 30
a66098da
LB		 31/* Register definitions */
32#define MWL8K_HIU_GEN_PTR 0x00000c10
ce9e2e1b
LB		 33#define MWL8K_MODE_STA 0x0000005a
34#define MWL8K_MODE_AP 0x000000a5
a66098da 35#define MWL8K_HIU_INT_CODE 0x00000c14
ce9e2e1b
LB		 36#define MWL8K_FWSTA_READY 0xf0f1f2f4
37#define MWL8K_FWAP_READY 0xf1f2f4a5
38#define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
a66098da
LB		 39#define MWL8K_HIU_SCRATCH 0x00000c40
40
41/* Host->device communications */
42#define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
43#define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
44#define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
45#define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
46#define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
ce9e2e1b
LB		 47#define MWL8K_H2A_INT_DUMMY (1 << 20)
48#define MWL8K_H2A_INT_RESET (1 << 15)
49#define MWL8K_H2A_INT_DOORBELL (1 << 1)
50#define MWL8K_H2A_INT_PPA_READY (1 << 0)
a66098da
LB		 51
52/* Device->host communications */
53#define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
54#define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
55#define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
56#define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
57#define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
ce9e2e1b
LB		 58#define MWL8K_A2H_INT_DUMMY (1 << 20)
59#define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
60#define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
61#define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
62#define MWL8K_A2H_INT_RADIO_ON (1 << 6)
63#define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
64#define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
65#define MWL8K_A2H_INT_OPC_DONE (1 << 2)
66#define MWL8K_A2H_INT_RX_READY (1 << 1)
67#define MWL8K_A2H_INT_TX_DONE (1 << 0)
a66098da
LB		 68
69#define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
70 MWL8K_A2H_INT_CHNL_SWITCHED | \
71 MWL8K_A2H_INT_QUEUE_EMPTY | \
72 MWL8K_A2H_INT_RADAR_DETECT | \
73 MWL8K_A2H_INT_RADIO_ON | \
74 MWL8K_A2H_INT_RADIO_OFF | \
75 MWL8K_A2H_INT_MAC_EVENT | \
76 MWL8K_A2H_INT_OPC_DONE | \
77 MWL8K_A2H_INT_RX_READY | \
78 MWL8K_A2H_INT_TX_DONE)
79
a66098da
LB		 80#define MWL8K_RX_QUEUES 1
81#define MWL8K_TX_QUEUES 4
82
54bc3a0d
LB		 83struct rxd_ops {
84 int rxd_size;
85 void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
86 void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
20f09c3d
LB		 87 int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status,
88 __le16 *qos);
54bc3a0d
LB		 89};
90
45a390dd 91struct mwl8k_device_info {
a74b295e
LB		 92 char *part_name;
93 char *helper_image;
94 char *fw_image;
54bc3a0d 95 struct rxd_ops *rxd_ops;
547810e3 96 u16 modes;
45a390dd
LB		 97};
98
a66098da 99struct mwl8k_rx_queue {
45eb400d 100 int rxd_count;
a66098da
LB		 101
102 /* hw receives here */
45eb400d 103 int head;
a66098da
LB		 104
105 /* refill descs here */
45eb400d 106 int tail;
a66098da 107
54bc3a0d 108 void *rxd;
45eb400d 109 dma_addr_t rxd_dma;
788838eb
LB		 110 struct {
111 struct sk_buff *skb;
112 DECLARE_PCI_UNMAP_ADDR(dma)
113 } *buf;
a66098da
LB		 114};
115
a66098da
LB		 116struct mwl8k_tx_queue {
117 /* hw transmits here */
45eb400d 118 int head;
a66098da
LB		 119
120 /* sw appends here */
45eb400d 121 int tail;
a66098da 122
45eb400d
LB		 123 struct ieee80211_tx_queue_stats stats;
124 struct mwl8k_tx_desc *txd;
125 dma_addr_t txd_dma;
126 struct sk_buff **skb;
a66098da
LB		 127};
128
129/* Pointers to the firmware data and meta information about it. */
130struct mwl8k_firmware {
a66098da
LB		 131 /* Boot helper code */
132 struct firmware *helper;
a74b295e
LB		 133
134 /* Microcode */
135 struct firmware *ucode;
a66098da
LB		 136};
137
138struct mwl8k_priv {
5b9482dd 139 void __iomem *sram;
a66098da
LB		 140 void __iomem *regs;
141 struct ieee80211_hw *hw;
142
143 struct pci_dev *pdev;
a66098da 144
45a390dd 145 struct mwl8k_device_info *device_info;
eae74e65 146 bool ap_fw;
54bc3a0d 147 struct rxd_ops *rxd_ops;
45a390dd 148
a66098da
LB		 149 /* firmware files and meta data */
150 struct mwl8k_firmware fw;
a66098da 151
618952a7
LB		 152 /* firmware access */
153 struct mutex fw_mutex;
154 struct task_struct *fw_mutex_owner;
155 int fw_mutex_depth;
618952a7
LB		 156 struct completion *hostcmd_wait;
157
a66098da
LB		 158 /* lock held over TX and TX reap */
159 spinlock_t tx_lock;
a66098da 160
88de754a
LB		 161 /* TX quiesce completion, protected by fw_mutex and tx_lock */
162 struct completion *tx_wait;
163
a66098da 164 struct ieee80211_vif *vif;
a66098da
LB		 165
166 struct ieee80211_channel *current_channel;
167
168 /* power management status cookie from firmware */
169 u32 *cookie;
170 dma_addr_t cookie_dma;
171
172 u16 num_mcaddrs;
a66098da 173 u8 hw_rev;
2aa7b01f 174 u32 fw_rev;
a66098da
LB		 175
176 /*
177 * Running count of TX packets in flight, to avoid
178 * iterating over the transmit rings each time.
179 */
180 int pending_tx_pkts;
181
182 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
183 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
184
185 /* PHY parameters */
186 struct ieee80211_supported_band band;
187 struct ieee80211_channel channels[14];
140eb5e2 188 struct ieee80211_rate rates[14];
a66098da 189
c46563b7 190 bool radio_on;
68ce3884 191 bool radio_short_preamble;
a43c49a8 192 bool sniffer_enabled;
0439b1f5 193 bool wmm_enabled;
a66098da 194
a66098da
LB		 195 /* XXX need to convert this to handle multiple interfaces */
196 bool capture_beacon;
d89173f2 197 u8 capture_bssid[ETH_ALEN];
a66098da
LB		 198 struct sk_buff *beacon_skb;
199
200 /*
201 * This FJ worker has to be global as it is scheduled from the
202 * RX handler. At this point we don't know which interface it
203 * belongs to until the list of bssids waiting to complete join
204 * is checked.
205 */
206 struct work_struct finalize_join_worker;
207
208 /* Tasklet to reclaim TX descriptors and buffers after tx */
209 struct tasklet_struct tx_reclaim_task;
a66098da
LB		 210};
211
212/* Per interface specific private data */
213struct mwl8k_vif {
a66098da
LB		 214 /* backpointer to parent config block */
215 struct mwl8k_priv *priv;
216
217 /* BSS config of AP or IBSS from mac80211*/
218 struct ieee80211_bss_conf bss_info;
219
220 /* BSSID of AP or IBSS */
d89173f2
LB		 221 u8 bssid[ETH_ALEN];
222 u8 mac_addr[ETH_ALEN];
a66098da 223
a66098da
LB		 224 /* Index into station database.Returned by update_sta_db call */
225 u8 peer_id;
226
227 /* Non AMPDU sequence number assigned by driver */
228 u16 seqno;
a66098da
LB		 229};
230
a94cc97e 231#define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
a66098da
LB		 232
233static const struct ieee80211_channel mwl8k_channels[] = {
234 { .center_freq = 2412, .hw_value = 1, },
235 { .center_freq = 2417, .hw_value = 2, },
236 { .center_freq = 2422, .hw_value = 3, },
237 { .center_freq = 2427, .hw_value = 4, },
238 { .center_freq = 2432, .hw_value = 5, },
239 { .center_freq = 2437, .hw_value = 6, },
240 { .center_freq = 2442, .hw_value = 7, },
241 { .center_freq = 2447, .hw_value = 8, },
242 { .center_freq = 2452, .hw_value = 9, },
243 { .center_freq = 2457, .hw_value = 10, },
244 { .center_freq = 2462, .hw_value = 11, },
245};
246
247static const struct ieee80211_rate mwl8k_rates[] = {
248 { .bitrate = 10, .hw_value = 2, },
249 { .bitrate = 20, .hw_value = 4, },
250 { .bitrate = 55, .hw_value = 11, },
5dfd3e2c
LB		 251 { .bitrate = 110, .hw_value = 22, },
252 { .bitrate = 220, .hw_value = 44, },
a66098da
LB		 253 { .bitrate = 60, .hw_value = 12, },
254 { .bitrate = 90, .hw_value = 18, },
a66098da
LB		 255 { .bitrate = 120, .hw_value = 24, },
256 { .bitrate = 180, .hw_value = 36, },
257 { .bitrate = 240, .hw_value = 48, },
258 { .bitrate = 360, .hw_value = 72, },
259 { .bitrate = 480, .hw_value = 96, },
260 { .bitrate = 540, .hw_value = 108, },
140eb5e2
LB		 261 { .bitrate = 720, .hw_value = 144, },
262};
263
264static const u8 mwl8k_rateids[12] = {
265 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108,
a66098da
LB		 266};
267
a66098da
LB		 268/* Set or get info from Firmware */
269#define MWL8K_CMD_SET 0x0001
270#define MWL8K_CMD_GET 0x0000
271
272/* Firmware command codes */
273#define MWL8K_CMD_CODE_DNLD 0x0001
274#define MWL8K_CMD_GET_HW_SPEC 0x0003
42fba21d 275#define MWL8K_CMD_SET_HW_SPEC 0x0004
a66098da
LB		 276#define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
277#define MWL8K_CMD_GET_STAT 0x0014
ff45fc60
LB		 278#define MWL8K_CMD_RADIO_CONTROL 0x001c
279#define MWL8K_CMD_RF_TX_POWER 0x001e
08b06347 280#define MWL8K_CMD_RF_ANTENNA 0x0020
a66098da
LB		 281#define MWL8K_CMD_SET_PRE_SCAN 0x0107
282#define MWL8K_CMD_SET_POST_SCAN 0x0108
ff45fc60
LB		 283#define MWL8K_CMD_SET_RF_CHANNEL 0x010a
284#define MWL8K_CMD_SET_AID 0x010d
285#define MWL8K_CMD_SET_RATE 0x0110
286#define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
287#define MWL8K_CMD_RTS_THRESHOLD 0x0113
a66098da 288#define MWL8K_CMD_SET_SLOT 0x0114
ff45fc60
LB		 289#define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
290#define MWL8K_CMD_SET_WMM_MODE 0x0123
a66098da 291#define MWL8K_CMD_MIMO_CONFIG 0x0125
ff45fc60 292#define MWL8K_CMD_USE_FIXED_RATE 0x0126
a66098da 293#define MWL8K_CMD_ENABLE_SNIFFER 0x0150
32060e1b 294#define MWL8K_CMD_SET_MAC_ADDR 0x0202
a66098da 295#define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
ff45fc60 296#define MWL8K_CMD_UPDATE_STADB 0x1123
a66098da
LB		 297
298static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
299{
300#define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
301 snprintf(buf, bufsize, "%s", #x);\
302 return buf;\
303 } while (0)
ce9e2e1b 304 switch (cmd & ~0x8000) {
a66098da
LB		 305 MWL8K_CMDNAME(CODE_DNLD);
306 MWL8K_CMDNAME(GET_HW_SPEC);
42fba21d 307 MWL8K_CMDNAME(SET_HW_SPEC);
a66098da
LB		 308 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
309 MWL8K_CMDNAME(GET_STAT);
310 MWL8K_CMDNAME(RADIO_CONTROL);
311 MWL8K_CMDNAME(RF_TX_POWER);
08b06347 312 MWL8K_CMDNAME(RF_ANTENNA);
a66098da
LB		 313 MWL8K_CMDNAME(SET_PRE_SCAN);
314 MWL8K_CMDNAME(SET_POST_SCAN);
315 MWL8K_CMDNAME(SET_RF_CHANNEL);
ff45fc60
LB		 316 MWL8K_CMDNAME(SET_AID);
317 MWL8K_CMDNAME(SET_RATE);
318 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
319 MWL8K_CMDNAME(RTS_THRESHOLD);
a66098da 320 MWL8K_CMDNAME(SET_SLOT);
ff45fc60
LB		 321 MWL8K_CMDNAME(SET_EDCA_PARAMS);
322 MWL8K_CMDNAME(SET_WMM_MODE);
a66098da 323 MWL8K_CMDNAME(MIMO_CONFIG);
ff45fc60 324 MWL8K_CMDNAME(USE_FIXED_RATE);
a66098da 325 MWL8K_CMDNAME(ENABLE_SNIFFER);
32060e1b 326 MWL8K_CMDNAME(SET_MAC_ADDR);
a66098da 327 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
ff45fc60 328 MWL8K_CMDNAME(UPDATE_STADB);
a66098da
LB		 329 default:
330 snprintf(buf, bufsize, "0x%x", cmd);
331 }
332#undef MWL8K_CMDNAME
333
334 return buf;
335}
336
337/* Hardware and firmware reset */
338static void mwl8k_hw_reset(struct mwl8k_priv *priv)
339{
340 iowrite32(MWL8K_H2A_INT_RESET,
341 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
342 iowrite32(MWL8K_H2A_INT_RESET,
343 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
344 msleep(20);
345}
346
347/* Release fw image */
348static void mwl8k_release_fw(struct firmware **fw)
349{
350 if (*fw == NULL)
351 return;
352 release_firmware(*fw);
353 *fw = NULL;
354}
355
356static void mwl8k_release_firmware(struct mwl8k_priv *priv)
357{
358 mwl8k_release_fw(&priv->fw.ucode);
359 mwl8k_release_fw(&priv->fw.helper);
360}
361
362/* Request fw image */
363static int mwl8k_request_fw(struct mwl8k_priv *priv,
c2c357ce 364 const char *fname, struct firmware **fw)
a66098da
LB		 365{
366 /* release current image */
367 if (*fw != NULL)
368 mwl8k_release_fw(fw);
369
370 return request_firmware((const struct firmware **)fw,
c2c357ce 371 fname, &priv->pdev->dev);
a66098da
LB		 372}
373
45a390dd 374static int mwl8k_request_firmware(struct mwl8k_priv *priv)
a66098da 375{
a74b295e 376 struct mwl8k_device_info *di = priv->device_info;
a66098da
LB		 377 int rc;
378
a74b295e
LB		 379 if (di->helper_image != NULL) {
380 rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw.helper);
381 if (rc) {
382 printk(KERN_ERR "%s: Error requesting helper "
383 "firmware file %s\n", pci_name(priv->pdev),
384 di->helper_image);
385 return rc;
386 }
a66098da
LB		 387 }
388
a74b295e 389 rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw.ucode);
a66098da 390 if (rc) {
c2c357ce 391 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
a74b295e 392 pci_name(priv->pdev), di->fw_image);
a66098da
LB		 393 mwl8k_release_fw(&priv->fw.helper);
394 return rc;
395 }
396
397 return 0;
398}
399
7e75b942
BH		 400MODULE_FIRMWARE("mwl8k/helper_8687.fw");
401MODULE_FIRMWARE("mwl8k/fmimage_8687.fw");
402
a66098da
LB		 403struct mwl8k_cmd_pkt {
404 __le16 code;
405 __le16 length;
406 __le16 seq_num;
407 __le16 result;
408 char payload[0];
409} __attribute__((packed));
410
411/*
412 * Firmware loading.
413 */
414static int
415mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
416{
417 void __iomem *regs = priv->regs;
418 dma_addr_t dma_addr;
a66098da
LB		 419 int loops;
420
421 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
422 if (pci_dma_mapping_error(priv->pdev, dma_addr))
423 return -ENOMEM;
424
425 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
426 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
427 iowrite32(MWL8K_H2A_INT_DOORBELL,
428 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
429 iowrite32(MWL8K_H2A_INT_DUMMY,
430 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
431
a66098da
LB		 432 loops = 1000;
433 do {
434 u32 int_code;
435
436 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
437 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
438 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
a66098da
LB		 439 break;
440 }
441
3d76e82c 442 cond_resched();
a66098da
LB		 443 udelay(1);
444 } while (--loops);
445
446 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
447
d4b70570 448 return loops ? 0 : -ETIMEDOUT;
a66098da
LB		 449}
450
451static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
452 const u8 *data, size_t length)
453{
454 struct mwl8k_cmd_pkt *cmd;
455 int done;
456 int rc = 0;
457
458 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
459 if (cmd == NULL)
460 return -ENOMEM;
461
462 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
463 cmd->seq_num = 0;
464 cmd->result = 0;
465
466 done = 0;
467 while (length) {
468 int block_size = length > 256 ? 256 : length;
469
470 memcpy(cmd->payload, data + done, block_size);
471 cmd->length = cpu_to_le16(block_size);
472
473 rc = mwl8k_send_fw_load_cmd(priv, cmd,
474 sizeof(*cmd) + block_size);
475 if (rc)
476 break;
477
478 done += block_size;
479 length -= block_size;
480 }
481
482 if (!rc) {
483 cmd->length = 0;
484 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
485 }
486
487 kfree(cmd);
488
489 return rc;
490}
491
492static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
493 const u8 *data, size_t length)
494{
495 unsigned char *buffer;
496 int may_continue, rc = 0;
497 u32 done, prev_block_size;
498
499 buffer = kmalloc(1024, GFP_KERNEL);
500 if (buffer == NULL)
501 return -ENOMEM;
502
503 done = 0;
504 prev_block_size = 0;
505 may_continue = 1000;
506 while (may_continue > 0) {
507 u32 block_size;
508
509 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
510 if (block_size & 1) {
511 block_size &= ~1;
512 may_continue--;
513 } else {
514 done += prev_block_size;
515 length -= prev_block_size;
516 }
517
518 if (block_size > 1024 || block_size > length) {
519 rc = -EOVERFLOW;
520 break;
521 }
522
523 if (length == 0) {
524 rc = 0;
525 break;
526 }
527
528 if (block_size == 0) {
529 rc = -EPROTO;
530 may_continue--;
531 udelay(1);
532 continue;
533 }
534
535 prev_block_size = block_size;
536 memcpy(buffer, data + done, block_size);
537
538 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
539 if (rc)
540 break;
541 }
542
543 if (!rc && length != 0)
544 rc = -EREMOTEIO;
545
546 kfree(buffer);
547
548 return rc;
549}
550
c2c357ce 551static int mwl8k_load_firmware(struct ieee80211_hw *hw)
a66098da 552{
c2c357ce
LB		 553 struct mwl8k_priv *priv = hw->priv;
554 struct firmware *fw = priv->fw.ucode;
eae74e65 555 struct mwl8k_device_info *di = priv->device_info;
c2c357ce
LB		 556 int rc;
557 int loops;
558
559 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
560 struct firmware *helper = priv->fw.helper;
a66098da 561
c2c357ce
LB		 562 if (helper == NULL) {
563 printk(KERN_ERR "%s: helper image needed but none "
564 "given\n", pci_name(priv->pdev));
565 return -EINVAL;
566 }
a66098da 567
c2c357ce 568 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
a66098da
LB		 569 if (rc) {
570 printk(KERN_ERR "%s: unable to load firmware "
c2c357ce 571 "helper image\n", pci_name(priv->pdev));
a66098da
LB		 572 return rc;
573 }
574 msleep(1);
575
c2c357ce 576 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
a66098da 577 } else {
c2c357ce 578 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
a66098da
LB		 579 }
580
581 if (rc) {
c2c357ce
LB		 582 printk(KERN_ERR "%s: unable to load firmware image\n",
583 pci_name(priv->pdev));
a66098da
LB		 584 return rc;
585 }
586
eae74e65
LB		 587 if (di->modes & BIT(NL80211_IFTYPE_AP))
588 iowrite32(MWL8K_MODE_AP, priv->regs + MWL8K_HIU_GEN_PTR);
589 else
590 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
a66098da
LB		 591 msleep(1);
592
593 loops = 200000;
594 do {
eae74e65
LB		 595 u32 ready_code;
596
597 ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
598 if (ready_code == MWL8K_FWAP_READY) {
599 priv->ap_fw = 1;
600 break;
601 } else if (ready_code == MWL8K_FWSTA_READY) {
602 priv->ap_fw = 0;
a66098da 603 break;
eae74e65
LB		 604 }
605
606 cond_resched();
a66098da
LB		 607 udelay(1);
608 } while (--loops);
609
610 return loops ? 0 : -ETIMEDOUT;
611}
612
613
614/*
615 * Defines shared between transmission and reception.
616 */
617/* HT control fields for firmware */
618struct ewc_ht_info {
619 __le16 control1;
620 __le16 control2;
621 __le16 control3;
622} __attribute__((packed));
623
624/* Firmware Station database operations */
625#define MWL8K_STA_DB_ADD_ENTRY 0
626#define MWL8K_STA_DB_MODIFY_ENTRY 1
627#define MWL8K_STA_DB_DEL_ENTRY 2
628#define MWL8K_STA_DB_FLUSH 3
629
630/* Peer Entry flags - used to define the type of the peer node */
631#define MWL8K_PEER_TYPE_ACCESSPOINT 2
a66098da 632
a66098da
LB		 633struct peer_capability_info {
634 /* Peer type - AP vs. STA. */
635 __u8 peer_type;
636
637 /* Basic 802.11 capabilities from assoc resp. */
638 __le16 basic_caps;
639
640 /* Set if peer supports 802.11n high throughput (HT). */
641 __u8 ht_support;
642
643 /* Valid if HT is supported. */
644 __le16 ht_caps;
645 __u8 extended_ht_caps;
646 struct ewc_ht_info ewc_info;
647
648 /* Legacy rate table. Intersection of our rates and peer rates. */
140eb5e2 649 __u8 legacy_rates[12];
a66098da
LB		 650
651 /* HT rate table. Intersection of our rates and peer rates. */
0b5351a8 652 __u8 ht_rates[16];
c23b5a69 653 __u8 pad[16];
a66098da
LB		 654
655 /* If set, interoperability mode, no proprietary extensions. */
656 __u8 interop;
657 __u8 pad2;
658 __u8 station_id;
659 __le16 amsdu_enabled;
660} __attribute__((packed));
661
662/* Inline functions to manipulate QoS field in data descriptor. */
a66098da
LB		 663static inline u16 mwl8k_qos_setbit_eosp(u16 qos)
664{
665 u16 val_mask = 1 << 4;
666
667 /* End of Service Period Bit 4 */
668 return qos | val_mask;
669}
670
671static inline u16 mwl8k_qos_setbit_ack(u16 qos, u8 ack_policy)
672{
673 u16 val_mask = 0x3;
674 u8 shift = 5;
675 u16 qos_mask = ~(val_mask << shift);
676
677 /* Ack Policy Bit 5-6 */
678 return (qos & qos_mask) | ((ack_policy & val_mask) << shift);
679}
680
681static inline u16 mwl8k_qos_setbit_amsdu(u16 qos)
682{
683 u16 val_mask = 1 << 7;
684
685 /* AMSDU present Bit 7 */
686 return qos | val_mask;
687}
688
689static inline u16 mwl8k_qos_setbit_qlen(u16 qos, u8 len)
690{
691 u16 val_mask = 0xff;
692 u8 shift = 8;
693 u16 qos_mask = ~(val_mask << shift);
694
695 /* Queue Length Bits 8-15 */
696 return (qos & qos_mask) | ((len & val_mask) << shift);
697}
698
699/* DMA header used by firmware and hardware. */
700struct mwl8k_dma_data {
701 __le16 fwlen;
702 struct ieee80211_hdr wh;
20f09c3d 703 char data[0];
a66098da
LB		 704} __attribute__((packed));
705
706/* Routines to add/remove DMA header from skb. */
20f09c3d 707static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos)
a66098da 708{
20f09c3d
LB		 709 struct mwl8k_dma_data *tr;
710 int hdrlen;
711
712 tr = (struct mwl8k_dma_data *)skb->data;
713 hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
714
715 if (hdrlen != sizeof(tr->wh)) {
716 if (ieee80211_is_data_qos(tr->wh.frame_control)) {
717 memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2);
718 *((__le16 *)(tr->data - 2)) = qos;
719 } else {
720 memmove(tr->data - hdrlen, &tr->wh, hdrlen);
721 }
a66098da 722 }
20f09c3d
LB		 723
724 if (hdrlen != sizeof(*tr))
725 skb_pull(skb, sizeof(*tr) - hdrlen);
a66098da
LB		 726}
727
76266b2a 728static inline void mwl8k_add_dma_header(struct sk_buff *skb)
a66098da
LB		 729{
730 struct ieee80211_hdr *wh;
ca009301 731 int hdrlen;
a66098da
LB		 732 struct mwl8k_dma_data *tr;
733
ca009301
LB		 734 /*
735 * Add a firmware DMA header; the firmware requires that we
736 * present a 2-byte payload length followed by a 4-address
737 * header (without QoS field), followed (optionally) by any
738 * WEP/ExtIV header (but only filled in for CCMP).
739 */
a66098da 740 wh = (struct ieee80211_hdr *)skb->data;
ca009301 741
a66098da 742 hdrlen = ieee80211_hdrlen(wh->frame_control);
ca009301
LB		 743 if (hdrlen != sizeof(*tr))
744 skb_push(skb, sizeof(*tr) - hdrlen);
a66098da 745
ca009301
LB		 746 if (ieee80211_is_data_qos(wh->frame_control))
747 hdrlen -= 2;
a66098da
LB		 748
749 tr = (struct mwl8k_dma_data *)skb->data;
750 if (wh != &tr->wh)
751 memmove(&tr->wh, wh, hdrlen);
ca009301
LB		 752 if (hdrlen != sizeof(tr->wh))
753 memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen);
a66098da
LB		 754
755 /*
756 * Firmware length is the length of the fully formed "802.11
757 * payload". That is, everything except for the 802.11 header.
758 * This includes all crypto material including the MIC.
759 */
ca009301 760 tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr));
a66098da
LB		 761}
762
763
764/*
6f6d1e9a
LB		 765 * Packet reception for 88w8366.
766 */
767struct mwl8k_rxd_8366 {
768 __le16 pkt_len;
769 __u8 sq2;
770 __u8 rate;
771 __le32 pkt_phys_addr;
772 __le32 next_rxd_phys_addr;
773 __le16 qos_control;
774 __le16 htsig2;
775 __le32 hw_rssi_info;
776 __le32 hw_noise_floor_info;
777 __u8 noise_floor;
778 __u8 pad0[3];
779 __u8 rssi;
780 __u8 rx_status;
781 __u8 channel;
782 __u8 rx_ctrl;
783} __attribute__((packed));
784
8e9f33f0
LB		 785#define MWL8K_8366_RATE_INFO_MCS_FORMAT 0x80
786#define MWL8K_8366_RATE_INFO_40MHZ 0x40
787#define MWL8K_8366_RATE_INFO_RATEID(x) ((x) & 0x3f)
788
6f6d1e9a
LB		 789#define MWL8K_8366_RX_CTRL_OWNED_BY_HOST 0x80
790
791static void mwl8k_rxd_8366_init(void *_rxd, dma_addr_t next_dma_addr)
792{
793 struct mwl8k_rxd_8366 *rxd = _rxd;
794
795 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
796 rxd->rx_ctrl = MWL8K_8366_RX_CTRL_OWNED_BY_HOST;
797}
798
799static void mwl8k_rxd_8366_refill(void *_rxd, dma_addr_t addr, int len)
800{
801 struct mwl8k_rxd_8366 *rxd = _rxd;
802
803 rxd->pkt_len = cpu_to_le16(len);
804 rxd->pkt_phys_addr = cpu_to_le32(addr);
805 wmb();
806 rxd->rx_ctrl = 0;
807}
808
809static int
20f09c3d
LB		 810mwl8k_rxd_8366_process(void *_rxd, struct ieee80211_rx_status *status,
811 __le16 *qos)
6f6d1e9a
LB		 812{
813 struct mwl8k_rxd_8366 *rxd = _rxd;
814
815 if (!(rxd->rx_ctrl & MWL8K_8366_RX_CTRL_OWNED_BY_HOST))
816 return -1;
817 rmb();
818
819 memset(status, 0, sizeof(*status));
820
821 status->signal = -rxd->rssi;
822 status->noise = -rxd->noise_floor;
823
8e9f33f0 824 if (rxd->rate & MWL8K_8366_RATE_INFO_MCS_FORMAT) {
6f6d1e9a 825 status->flag |= RX_FLAG_HT;
8e9f33f0
LB		 826 if (rxd->rate & MWL8K_8366_RATE_INFO_40MHZ)
827 status->flag |= RX_FLAG_40MHZ;
828 status->rate_idx = MWL8K_8366_RATE_INFO_RATEID(rxd->rate);
6f6d1e9a
LB		 829 } else {
830 int i;
831
832 for (i = 0; i < ARRAY_SIZE(mwl8k_rates); i++) {
833 if (mwl8k_rates[i].hw_value == rxd->rate) {
834 status->rate_idx = i;
835 break;
836 }
837 }
838 }
839
840 status->band = IEEE80211_BAND_2GHZ;
841 status->freq = ieee80211_channel_to_frequency(rxd->channel);
842
20f09c3d
LB		 843 *qos = rxd->qos_control;
844
6f6d1e9a
LB		 845 return le16_to_cpu(rxd->pkt_len);
846}
847
848static struct rxd_ops rxd_8366_ops = {
849 .rxd_size = sizeof(struct mwl8k_rxd_8366),
850 .rxd_init = mwl8k_rxd_8366_init,
851 .rxd_refill = mwl8k_rxd_8366_refill,
852 .rxd_process = mwl8k_rxd_8366_process,
853};
854
855/*
856 * Packet reception for 88w8687.
a66098da 857 */
54bc3a0d 858struct mwl8k_rxd_8687 {
a66098da
LB		 859 __le16 pkt_len;
860 __u8 link_quality;
861 __u8 noise_level;
862 __le32 pkt_phys_addr;
45eb400d 863 __le32 next_rxd_phys_addr;
a66098da
LB		 864 __le16 qos_control;
865 __le16 rate_info;
866 __le32 pad0[4];
867 __u8 rssi;
868 __u8 channel;
869 __le16 pad1;
870 __u8 rx_ctrl;
871 __u8 rx_status;
872 __u8 pad2[2];
873} __attribute__((packed));
874
54bc3a0d
LB		 875#define MWL8K_8687_RATE_INFO_SHORTPRE 0x8000
876#define MWL8K_8687_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
877#define MWL8K_8687_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
878#define MWL8K_8687_RATE_INFO_40MHZ 0x0004
879#define MWL8K_8687_RATE_INFO_SHORTGI 0x0002
880#define MWL8K_8687_RATE_INFO_MCS_FORMAT 0x0001
881
882#define MWL8K_8687_RX_CTRL_OWNED_BY_HOST 0x02
883
884static void mwl8k_rxd_8687_init(void *_rxd, dma_addr_t next_dma_addr)
885{
886 struct mwl8k_rxd_8687 *rxd = _rxd;
887
888 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
889 rxd->rx_ctrl = MWL8K_8687_RX_CTRL_OWNED_BY_HOST;
890}
891
892static void mwl8k_rxd_8687_refill(void *_rxd, dma_addr_t addr, int len)
893{
894 struct mwl8k_rxd_8687 *rxd = _rxd;
895
896 rxd->pkt_len = cpu_to_le16(len);
897 rxd->pkt_phys_addr = cpu_to_le32(addr);
898 wmb();
899 rxd->rx_ctrl = 0;
900}
901
902static int
20f09c3d
LB		 903mwl8k_rxd_8687_process(void *_rxd, struct ieee80211_rx_status *status,
904 __le16 *qos)
54bc3a0d
LB		 905{
906 struct mwl8k_rxd_8687 *rxd = _rxd;
907 u16 rate_info;
908
909 if (!(rxd->rx_ctrl & MWL8K_8687_RX_CTRL_OWNED_BY_HOST))
910 return -1;
911 rmb();
912
913 rate_info = le16_to_cpu(rxd->rate_info);
914
915 memset(status, 0, sizeof(*status));
916
917 status->signal = -rxd->rssi;
918 status->noise = -rxd->noise_level;
919 status->qual = rxd->link_quality;
920 status->antenna = MWL8K_8687_RATE_INFO_ANTSELECT(rate_info);
921 status->rate_idx = MWL8K_8687_RATE_INFO_RATEID(rate_info);
922
923 if (rate_info & MWL8K_8687_RATE_INFO_SHORTPRE)
924 status->flag |= RX_FLAG_SHORTPRE;
925 if (rate_info & MWL8K_8687_RATE_INFO_40MHZ)
926 status->flag |= RX_FLAG_40MHZ;
927 if (rate_info & MWL8K_8687_RATE_INFO_SHORTGI)
928 status->flag |= RX_FLAG_SHORT_GI;
929 if (rate_info & MWL8K_8687_RATE_INFO_MCS_FORMAT)
930 status->flag |= RX_FLAG_HT;
931
932 status->band = IEEE80211_BAND_2GHZ;
933 status->freq = ieee80211_channel_to_frequency(rxd->channel);
934
20f09c3d
LB		 935 *qos = rxd->qos_control;
936
54bc3a0d
LB		 937 return le16_to_cpu(rxd->pkt_len);
938}
939
940static struct rxd_ops rxd_8687_ops = {
941 .rxd_size = sizeof(struct mwl8k_rxd_8687),
942 .rxd_init = mwl8k_rxd_8687_init,
943 .rxd_refill = mwl8k_rxd_8687_refill,
944 .rxd_process = mwl8k_rxd_8687_process,
945};
946
947
a66098da
LB		 948#define MWL8K_RX_DESCS 256
949#define MWL8K_RX_MAXSZ 3800
950
951static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
952{
953 struct mwl8k_priv *priv = hw->priv;
954 struct mwl8k_rx_queue *rxq = priv->rxq + index;
955 int size;
956 int i;
957
45eb400d
LB		 958 rxq->rxd_count = 0;
959 rxq->head = 0;
960 rxq->tail = 0;
a66098da 961
54bc3a0d 962 size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
a66098da 963
45eb400d
LB		 964 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
965 if (rxq->rxd == NULL) {
a66098da 966 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
c2c357ce 967 wiphy_name(hw->wiphy));
a66098da
LB		 968 return -ENOMEM;
969 }
45eb400d 970 memset(rxq->rxd, 0, size);
a66098da 971
788838eb
LB		 972 rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL);
973 if (rxq->buf == NULL) {
a66098da 974 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
c2c357ce 975 wiphy_name(hw->wiphy));
45eb400d 976 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
a66098da
LB		 977 return -ENOMEM;
978 }
788838eb 979 memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf));
a66098da
LB		 980
981 for (i = 0; i < MWL8K_RX_DESCS; i++) {
54bc3a0d
LB		 982 int desc_size;
983 void *rxd;
a66098da 984 int nexti;
54bc3a0d
LB		 985 dma_addr_t next_dma_addr;
986
987 desc_size = priv->rxd_ops->rxd_size;
988 rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
a66098da 989
54bc3a0d
LB		 990 nexti = i + 1;
991 if (nexti == MWL8K_RX_DESCS)
992 nexti = 0;
993 next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
a66098da 994
54bc3a0d 995 priv->rxd_ops->rxd_init(rxd, next_dma_addr);
a66098da
LB		 996 }
997
998 return 0;
999}
1000
1001static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
1002{
1003 struct mwl8k_priv *priv = hw->priv;
1004 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1005 int refilled;
1006
1007 refilled = 0;
45eb400d 1008 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
a66098da 1009 struct sk_buff *skb;
788838eb 1010 dma_addr_t addr;
a66098da 1011 int rx;
54bc3a0d 1012 void *rxd;
a66098da
LB		 1013
1014 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
1015 if (skb == NULL)
1016 break;
1017
788838eb
LB		 1018 addr = pci_map_single(priv->pdev, skb->data,
1019 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
a66098da 1020
54bc3a0d
LB		 1021 rxq->rxd_count++;
1022 rx = rxq->tail++;
1023 if (rxq->tail == MWL8K_RX_DESCS)
1024 rxq->tail = 0;
788838eb
LB		 1025 rxq->buf[rx].skb = skb;
1026 pci_unmap_addr_set(&rxq->buf[rx], dma, addr);
54bc3a0d
LB		 1027
1028 rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
1029 priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
a66098da
LB		 1030
1031 refilled++;
1032 }
1033
1034 return refilled;
1035}
1036
1037/* Must be called only when the card's reception is completely halted */
1038static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
1039{
1040 struct mwl8k_priv *priv = hw->priv;
1041 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1042 int i;
1043
1044 for (i = 0; i < MWL8K_RX_DESCS; i++) {
788838eb
LB		 1045 if (rxq->buf[i].skb != NULL) {
1046 pci_unmap_single(priv->pdev,
1047 pci_unmap_addr(&rxq->buf[i], dma),
1048 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1049 pci_unmap_addr_set(&rxq->buf[i], dma, 0);
1050
1051 kfree_skb(rxq->buf[i].skb);
1052 rxq->buf[i].skb = NULL;
a66098da
LB		 1053 }
1054 }
1055
788838eb
LB		 1056 kfree(rxq->buf);
1057 rxq->buf = NULL;
a66098da
LB		 1058
1059 pci_free_consistent(priv->pdev,
54bc3a0d 1060 MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
45eb400d
LB		 1061 rxq->rxd, rxq->rxd_dma);
1062 rxq->rxd = NULL;
a66098da
LB		 1063}
1064
1065
1066/*
1067 * Scan a list of BSSIDs to process for finalize join.
1068 * Allows for extension to process multiple BSSIDs.
1069 */
1070static inline int
1071mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
1072{
1073 return priv->capture_beacon &&
1074 ieee80211_is_beacon(wh->frame_control) &&
1075 !compare_ether_addr(wh->addr3, priv->capture_bssid);
1076}
1077
3779752d
LB		 1078static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
1079 struct sk_buff *skb)
a66098da 1080{
3779752d
LB		 1081 struct mwl8k_priv *priv = hw->priv;
1082
a66098da 1083 priv->capture_beacon = false;
d89173f2 1084 memset(priv->capture_bssid, 0, ETH_ALEN);
a66098da
LB		 1085
1086 /*
1087 * Use GFP_ATOMIC as rxq_process is called from
1088 * the primary interrupt handler, memory allocation call
1089 * must not sleep.
1090 */
1091 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
1092 if (priv->beacon_skb != NULL)
3779752d 1093 ieee80211_queue_work(hw, &priv->finalize_join_worker);
a66098da
LB		 1094}
1095
1096static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
1097{
1098 struct mwl8k_priv *priv = hw->priv;
1099 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1100 int processed;
1101
1102 processed = 0;
45eb400d 1103 while (rxq->rxd_count && limit--) {
a66098da 1104 struct sk_buff *skb;
54bc3a0d
LB		 1105 void *rxd;
1106 int pkt_len;
a66098da 1107 struct ieee80211_rx_status status;
20f09c3d 1108 __le16 qos;
a66098da 1109
788838eb 1110 skb = rxq->buf[rxq->head].skb;
d25f9f13
LB		 1111 if (skb == NULL)
1112 break;
54bc3a0d
LB		 1113
1114 rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
1115
20f09c3d 1116 pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos);
54bc3a0d
LB		 1117 if (pkt_len < 0)
1118 break;
1119
788838eb
LB		 1120 rxq->buf[rxq->head].skb = NULL;
1121
1122 pci_unmap_single(priv->pdev,
1123 pci_unmap_addr(&rxq->buf[rxq->head], dma),
1124 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1125 pci_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
a66098da 1126
54bc3a0d
LB		 1127 rxq->head++;
1128 if (rxq->head == MWL8K_RX_DESCS)
1129 rxq->head = 0;
1130
45eb400d 1131 rxq->rxd_count--;
a66098da 1132
54bc3a0d 1133 skb_put(skb, pkt_len);
20f09c3d 1134 mwl8k_remove_dma_header(skb, qos);
a66098da 1135
a66098da 1136 /*
c2c357ce
LB		 1137 * Check for a pending join operation. Save a
1138 * copy of the beacon and schedule a tasklet to
1139 * send a FINALIZE_JOIN command to the firmware.
a66098da 1140 */
54bc3a0d 1141 if (mwl8k_capture_bssid(priv, (void *)skb->data))
3779752d 1142 mwl8k_save_beacon(hw, skb);
a66098da 1143
f1d58c25
JB		 1144 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
1145 ieee80211_rx_irqsafe(hw, skb);
a66098da
LB		 1146
1147 processed++;
1148 }
1149
1150 return processed;
1151}
1152
1153
1154/*
1155 * Packet transmission.
1156 */
1157
a66098da
LB		 1158/* Transmit packet ACK policy */
1159#define MWL8K_TXD_ACK_POLICY_NORMAL 0
a66098da
LB		 1160#define MWL8K_TXD_ACK_POLICY_BLOCKACK 3
1161
a66098da
LB		 1162#define MWL8K_TXD_STATUS_OK 0x00000001
1163#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1164#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1165#define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
a66098da 1166#define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
a66098da
LB		 1167
1168struct mwl8k_tx_desc {
1169 __le32 status;
1170 __u8 data_rate;
1171 __u8 tx_priority;
1172 __le16 qos_control;
1173 __le32 pkt_phys_addr;
1174 __le16 pkt_len;
d89173f2 1175 __u8 dest_MAC_addr[ETH_ALEN];
45eb400d 1176 __le32 next_txd_phys_addr;
a66098da
LB		 1177 __le32 reserved;
1178 __le16 rate_info;
1179 __u8 peer_id;
1180 __u8 tx_frag_cnt;
1181} __attribute__((packed));
1182
1183#define MWL8K_TX_DESCS 128
1184
1185static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1186{
1187 struct mwl8k_priv *priv = hw->priv;
1188 struct mwl8k_tx_queue *txq = priv->txq + index;
1189 int size;
1190 int i;
1191
45eb400d
LB		 1192 memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats));
1193 txq->stats.limit = MWL8K_TX_DESCS;
1194 txq->head = 0;
1195 txq->tail = 0;
a66098da
LB		 1196
1197 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1198
45eb400d
LB		 1199 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
1200 if (txq->txd == NULL) {
a66098da 1201 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
c2c357ce 1202 wiphy_name(hw->wiphy));
a66098da
LB		 1203 return -ENOMEM;
1204 }
45eb400d 1205 memset(txq->txd, 0, size);
a66098da 1206
45eb400d
LB		 1207 txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL);
1208 if (txq->skb == NULL) {
a66098da 1209 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
c2c357ce 1210 wiphy_name(hw->wiphy));
45eb400d 1211 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
a66098da
LB		 1212 return -ENOMEM;
1213 }
45eb400d 1214 memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb));
a66098da
LB		 1215
1216 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1217 struct mwl8k_tx_desc *tx_desc;
1218 int nexti;
1219
45eb400d 1220 tx_desc = txq->txd + i;
a66098da
LB		 1221 nexti = (i + 1) % MWL8K_TX_DESCS;
1222
1223 tx_desc->status = 0;
45eb400d
LB		 1224 tx_desc->next_txd_phys_addr =
1225 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
a66098da
LB		 1226 }
1227
1228 return 0;
1229}
1230
1231static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1232{
1233 iowrite32(MWL8K_H2A_INT_PPA_READY,
1234 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1235 iowrite32(MWL8K_H2A_INT_DUMMY,
1236 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1237 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1238}
1239
7e1112d3 1240static void mwl8k_dump_tx_rings(struct ieee80211_hw *hw)
a66098da 1241{
7e1112d3
LB		 1242 struct mwl8k_priv *priv = hw->priv;
1243 int i;
1244
1245 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
1246 struct mwl8k_tx_queue *txq = priv->txq + i;
1247 int fw_owned = 0;
1248 int drv_owned = 0;
1249 int unused = 0;
1250 int desc;
1251
a66098da 1252 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
7e1112d3
LB		 1253 struct mwl8k_tx_desc *tx_desc = txq->txd + desc;
1254 u32 status;
a66098da 1255
7e1112d3 1256 status = le32_to_cpu(tx_desc->status);
a66098da 1257 if (status & MWL8K_TXD_STATUS_FW_OWNED)
7e1112d3 1258 fw_owned++;
a66098da 1259 else
7e1112d3 1260 drv_owned++;
a66098da
LB		 1261
1262 if (tx_desc->pkt_len == 0)
7e1112d3 1263 unused++;
a66098da 1264 }
a66098da 1265
7e1112d3
LB		 1266 printk(KERN_ERR "%s: txq[%d] len=%d head=%d tail=%d "
1267 "fw_owned=%d drv_owned=%d unused=%d\n",
1268 wiphy_name(hw->wiphy), i,
1269 txq->stats.len, txq->head, txq->tail,
1270 fw_owned, drv_owned, unused);
1271 }
a66098da
LB		 1272}
1273
618952a7 1274/*
88de754a 1275 * Must be called with priv->fw_mutex held and tx queues stopped.
618952a7 1276 */
7e1112d3
LB		 1277#define MWL8K_TX_WAIT_TIMEOUT_MS 1000
1278
950d5b01 1279static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
a66098da 1280{
a66098da 1281 struct mwl8k_priv *priv = hw->priv;
88de754a 1282 DECLARE_COMPLETION_ONSTACK(tx_wait);
7e1112d3
LB		 1283 int retry;
1284 int rc;
a66098da
LB		 1285
1286 might_sleep();
1287
7e1112d3
LB		 1288 /*
1289 * The TX queues are stopped at this point, so this test
1290 * doesn't need to take ->tx_lock.
1291 */
1292 if (!priv->pending_tx_pkts)
1293 return 0;
1294
1295 retry = 0;
1296 rc = 0;
1297
a66098da 1298 spin_lock_bh(&priv->tx_lock);
7e1112d3
LB		 1299 priv->tx_wait = &tx_wait;
1300 while (!rc) {
1301 int oldcount;
1302 unsigned long timeout;
a66098da 1303
7e1112d3 1304 oldcount = priv->pending_tx_pkts;
a66098da 1305
7e1112d3 1306 spin_unlock_bh(&priv->tx_lock);
88de754a 1307 timeout = wait_for_completion_timeout(&tx_wait,
7e1112d3 1308 msecs_to_jiffies(MWL8K_TX_WAIT_TIMEOUT_MS));
a66098da 1309 spin_lock_bh(&priv->tx_lock);
7e1112d3
LB		 1310
1311 if (timeout) {
1312 WARN_ON(priv->pending_tx_pkts);
1313 if (retry) {
1314 printk(KERN_NOTICE "%s: tx rings drained\n",
1315 wiphy_name(hw->wiphy));
1316 }
1317 break;
1318 }
1319
1320 if (priv->pending_tx_pkts < oldcount) {
1321 printk(KERN_NOTICE "%s: timeout waiting for tx "
1322 "rings to drain (%d -> %d pkts), retrying\n",
1323 wiphy_name(hw->wiphy), oldcount,
1324 priv->pending_tx_pkts);
1325 retry = 1;
1326 continue;
1327 }
1328
a66098da 1329 priv->tx_wait = NULL;
a66098da 1330
7e1112d3
LB		 1331 printk(KERN_ERR "%s: tx rings stuck for %d ms\n",
1332 wiphy_name(hw->wiphy), MWL8K_TX_WAIT_TIMEOUT_MS);
1333 mwl8k_dump_tx_rings(hw);
1334
1335 rc = -ETIMEDOUT;
a66098da 1336 }
7e1112d3 1337 spin_unlock_bh(&priv->tx_lock);
a66098da 1338
7e1112d3 1339 return rc;
a66098da
LB		 1340}
1341
c23b5a69
LB		 1342#define MWL8K_TXD_SUCCESS(status) \
1343 ((status) & (MWL8K_TXD_STATUS_OK | \
1344 MWL8K_TXD_STATUS_OK_RETRY | \
1345 MWL8K_TXD_STATUS_OK_MORE_RETRY))
a66098da
LB		 1346
1347static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
1348{
1349 struct mwl8k_priv *priv = hw->priv;
1350 struct mwl8k_tx_queue *txq = priv->txq + index;
1351 int wake = 0;
1352
45eb400d 1353 while (txq->stats.len > 0) {
a66098da 1354 int tx;
a66098da
LB		 1355 struct mwl8k_tx_desc *tx_desc;
1356 unsigned long addr;
ce9e2e1b 1357 int size;
a66098da
LB		 1358 struct sk_buff *skb;
1359 struct ieee80211_tx_info *info;
1360 u32 status;
1361
45eb400d
LB		 1362 tx = txq->head;
1363 tx_desc = txq->txd + tx;
a66098da
LB		 1364
1365 status = le32_to_cpu(tx_desc->status);
1366
1367 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1368 if (!force)
1369 break;
1370 tx_desc->status &=
1371 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1372 }
1373
45eb400d
LB		 1374 txq->head = (tx + 1) % MWL8K_TX_DESCS;
1375 BUG_ON(txq->stats.len == 0);
1376 txq->stats.len--;
a66098da
LB		 1377 priv->pending_tx_pkts--;
1378
1379 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
ce9e2e1b 1380 size = le16_to_cpu(tx_desc->pkt_len);
45eb400d
LB		 1381 skb = txq->skb[tx];
1382 txq->skb[tx] = NULL;
a66098da
LB		 1383
1384 BUG_ON(skb == NULL);
1385 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1386
20f09c3d 1387 mwl8k_remove_dma_header(skb, tx_desc->qos_control);
a66098da
LB		 1388
1389 /* Mark descriptor as unused */
1390 tx_desc->pkt_phys_addr = 0;
1391 tx_desc->pkt_len = 0;
1392
a66098da
LB		 1393 info = IEEE80211_SKB_CB(skb);
1394 ieee80211_tx_info_clear_status(info);
ce9e2e1b 1395 if (MWL8K_TXD_SUCCESS(status))
a66098da 1396 info->flags |= IEEE80211_TX_STAT_ACK;
a66098da
LB		 1397
1398 ieee80211_tx_status_irqsafe(hw, skb);
1399
618952a7 1400 wake = 1;
a66098da
LB		 1401 }
1402
618952a7 1403 if (wake && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
a66098da
LB		 1404 ieee80211_wake_queue(hw, index);
1405}
1406
1407/* must be called only when the card's transmit is completely halted */
1408static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1409{
1410 struct mwl8k_priv *priv = hw->priv;
1411 struct mwl8k_tx_queue *txq = priv->txq + index;
1412
1413 mwl8k_txq_reclaim(hw, index, 1);
1414
45eb400d
LB		 1415 kfree(txq->skb);
1416 txq->skb = NULL;
a66098da
LB		 1417
1418 pci_free_consistent(priv->pdev,
1419 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
45eb400d
LB		 1420 txq->txd, txq->txd_dma);
1421 txq->txd = NULL;
a66098da
LB		 1422}
1423
1424static int
1425mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1426{
1427 struct mwl8k_priv *priv = hw->priv;
1428 struct ieee80211_tx_info *tx_info;
23b33906 1429 struct mwl8k_vif *mwl8k_vif;
a66098da
LB		 1430 struct ieee80211_hdr *wh;
1431 struct mwl8k_tx_queue *txq;
1432 struct mwl8k_tx_desc *tx;
a66098da 1433 dma_addr_t dma;
23b33906
LB		 1434 u32 txstatus;
1435 u8 txdatarate;
1436 u16 qos;
a66098da 1437
23b33906
LB		 1438 wh = (struct ieee80211_hdr *)skb->data;
1439 if (ieee80211_is_data_qos(wh->frame_control))
1440 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1441 else
1442 qos = 0;
a66098da 1443
76266b2a 1444 mwl8k_add_dma_header(skb);
23b33906 1445 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
a66098da
LB		 1446
1447 tx_info = IEEE80211_SKB_CB(skb);
1448 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
a66098da
LB		 1449
1450 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1451 u16 seqno = mwl8k_vif->seqno;
23b33906 1452
a66098da
LB		 1453 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1454 wh->seq_ctrl |= cpu_to_le16(seqno << 4);
1455 mwl8k_vif->seqno = seqno++ % 4096;
1456 }
1457
23b33906
LB		 1458 /* Setup firmware control bit fields for each frame type. */
1459 txstatus = 0;
1460 txdatarate = 0;
1461 if (ieee80211_is_mgmt(wh->frame_control) ||
1462 ieee80211_is_ctl(wh->frame_control)) {
1463 txdatarate = 0;
1464 qos = mwl8k_qos_setbit_eosp(qos);
1465 /* Set Queue size to unspecified */
1466 qos = mwl8k_qos_setbit_qlen(qos, 0xff);
1467 } else if (ieee80211_is_data(wh->frame_control)) {
1468 txdatarate = 1;
1469 if (is_multicast_ether_addr(wh->addr1))
1470 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1471
1472 /* Send pkt in an aggregate if AMPDU frame. */
1473 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1474 qos = mwl8k_qos_setbit_ack(qos,
1475 MWL8K_TXD_ACK_POLICY_BLOCKACK);
1476 else
1477 qos = mwl8k_qos_setbit_ack(qos,
1478 MWL8K_TXD_ACK_POLICY_NORMAL);
1479
1480 if (qos & IEEE80211_QOS_CONTROL_A_MSDU_PRESENT)
1481 qos = mwl8k_qos_setbit_amsdu(qos);
1482 }
a66098da
LB		 1483
1484 dma = pci_map_single(priv->pdev, skb->data,
1485 skb->len, PCI_DMA_TODEVICE);
1486
1487 if (pci_dma_mapping_error(priv->pdev, dma)) {
1488 printk(KERN_DEBUG "%s: failed to dma map skb, "
c2c357ce 1489 "dropping TX frame.\n", wiphy_name(hw->wiphy));
23b33906 1490 dev_kfree_skb(skb);
a66098da
LB		 1491 return NETDEV_TX_OK;
1492 }
1493
23b33906 1494 spin_lock_bh(&priv->tx_lock);
a66098da 1495
23b33906 1496 txq = priv->txq + index;
a66098da 1497
45eb400d
LB		 1498 BUG_ON(txq->skb[txq->tail] != NULL);
1499 txq->skb[txq->tail] = skb;
a66098da 1500
45eb400d 1501 tx = txq->txd + txq->tail;
23b33906
LB		 1502 tx->data_rate = txdatarate;
1503 tx->tx_priority = index;
a66098da 1504 tx->qos_control = cpu_to_le16(qos);
a66098da
LB		 1505 tx->pkt_phys_addr = cpu_to_le32(dma);
1506 tx->pkt_len = cpu_to_le16(skb->len);
23b33906
LB		 1507 tx->rate_info = 0;
1508 tx->peer_id = mwl8k_vif->peer_id;
a66098da 1509 wmb();
23b33906
LB		 1510 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1511
45eb400d
LB		 1512 txq->stats.count++;
1513 txq->stats.len++;
a66098da 1514 priv->pending_tx_pkts++;
a66098da 1515
45eb400d
LB		 1516 txq->tail++;
1517 if (txq->tail == MWL8K_TX_DESCS)
1518 txq->tail = 0;
23b33906 1519
45eb400d 1520 if (txq->head == txq->tail)
a66098da
LB		 1521 ieee80211_stop_queue(hw, index);
1522
23b33906 1523 mwl8k_tx_start(priv);
a66098da
LB		 1524
1525 spin_unlock_bh(&priv->tx_lock);
1526
1527 return NETDEV_TX_OK;
1528}
1529
1530
618952a7
LB		 1531/*
1532 * Firmware access.
1533 *
1534 * We have the following requirements for issuing firmware commands:
1535 * - Some commands require that the packet transmit path is idle when
1536 * the command is issued. (For simplicity, we'll just quiesce the
1537 * transmit path for every command.)
1538 * - There are certain sequences of commands that need to be issued to
1539 * the hardware sequentially, with no other intervening commands.
1540 *
1541 * This leads to an implementation of a "firmware lock" as a mutex that
1542 * can be taken recursively, and which is taken by both the low-level
1543 * command submission function (mwl8k_post_cmd) as well as any users of
1544 * that function that require issuing of an atomic sequence of commands,
1545 * and quiesces the transmit path whenever it's taken.
1546 */
1547static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1548{
1549 struct mwl8k_priv *priv = hw->priv;
1550
1551 if (priv->fw_mutex_owner != current) {
1552 int rc;
1553
1554 mutex_lock(&priv->fw_mutex);
1555 ieee80211_stop_queues(hw);
1556
1557 rc = mwl8k_tx_wait_empty(hw);
1558 if (rc) {
1559 ieee80211_wake_queues(hw);
1560 mutex_unlock(&priv->fw_mutex);
1561
1562 return rc;
1563 }
1564
1565 priv->fw_mutex_owner = current;
1566 }
1567
1568 priv->fw_mutex_depth++;
1569
1570 return 0;
1571}
1572
1573static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1574{
1575 struct mwl8k_priv *priv = hw->priv;
1576
1577 if (!--priv->fw_mutex_depth) {
1578 ieee80211_wake_queues(hw);
1579 priv->fw_mutex_owner = NULL;
1580 mutex_unlock(&priv->fw_mutex);
1581 }
1582}
1583
1584
a66098da
LB		 1585/*
1586 * Command processing.
1587 */
1588
0c9cc640
LB		 1589/* Timeout firmware commands after 10s */
1590#define MWL8K_CMD_TIMEOUT_MS 10000
a66098da
LB		 1591
1592static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1593{
1594 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1595 struct mwl8k_priv *priv = hw->priv;
1596 void __iomem *regs = priv->regs;
1597 dma_addr_t dma_addr;
1598 unsigned int dma_size;
1599 int rc;
a66098da
LB		 1600 unsigned long timeout = 0;
1601 u8 buf[32];
1602
c2c357ce 1603 cmd->result = 0xffff;
a66098da
LB		 1604 dma_size = le16_to_cpu(cmd->length);
1605 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1606 PCI_DMA_BIDIRECTIONAL);
1607 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1608 return -ENOMEM;
1609
618952a7 1610 rc = mwl8k_fw_lock(hw);
39a1e42e
LB		 1611 if (rc) {
1612 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1613 PCI_DMA_BIDIRECTIONAL);
618952a7 1614 return rc;
39a1e42e 1615 }
a66098da 1616
a66098da
LB		 1617 priv->hostcmd_wait = &cmd_wait;
1618 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1619 iowrite32(MWL8K_H2A_INT_DOORBELL,
1620 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1621 iowrite32(MWL8K_H2A_INT_DUMMY,
1622 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
a66098da
LB		 1623
1624 timeout = wait_for_completion_timeout(&cmd_wait,
1625 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1626
618952a7
LB		 1627 priv->hostcmd_wait = NULL;
1628
1629 mwl8k_fw_unlock(hw);
1630
37055bd4
LB		 1631 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1632 PCI_DMA_BIDIRECTIONAL);
1633
a66098da 1634 if (!timeout) {
a66098da 1635 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
c2c357ce 1636 wiphy_name(hw->wiphy),
a66098da
LB		 1637 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1638 MWL8K_CMD_TIMEOUT_MS);
1639 rc = -ETIMEDOUT;
1640 } else {
0c9cc640
LB		 1641 int ms;
1642
1643 ms = MWL8K_CMD_TIMEOUT_MS - jiffies_to_msecs(timeout);
1644
ce9e2e1b 1645 rc = cmd->result ? -EINVAL : 0;
a66098da
LB		 1646 if (rc)
1647 printk(KERN_ERR "%s: Command %s error 0x%x\n",
c2c357ce 1648 wiphy_name(hw->wiphy),
a66098da 1649 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
76c962a2 1650 le16_to_cpu(cmd->result));
0c9cc640
LB		 1651 else if (ms > 2000)
1652 printk(KERN_NOTICE "%s: Command %s took %d ms\n",
1653 wiphy_name(hw->wiphy),
1654 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1655 ms);
a66098da
LB		 1656 }
1657
a66098da
LB		 1658 return rc;
1659}
1660
1661/*
04b147b1 1662 * CMD_GET_HW_SPEC (STA version).
a66098da 1663 */
04b147b1 1664struct mwl8k_cmd_get_hw_spec_sta {
a66098da
LB		 1665 struct mwl8k_cmd_pkt header;
1666 __u8 hw_rev;
1667 __u8 host_interface;
1668 __le16 num_mcaddrs;
d89173f2 1669 __u8 perm_addr[ETH_ALEN];
a66098da
LB		 1670 __le16 region_code;
1671 __le32 fw_rev;
1672 __le32 ps_cookie;
1673 __le32 caps;
1674 __u8 mcs_bitmap[16];
1675 __le32 rx_queue_ptr;
1676 __le32 num_tx_queues;
1677 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1678 __le32 caps2;
1679 __le32 num_tx_desc_per_queue;
45eb400d 1680 __le32 total_rxd;
a66098da
LB		 1681} __attribute__((packed));
1682
04b147b1 1683static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
a66098da
LB		 1684{
1685 struct mwl8k_priv *priv = hw->priv;
04b147b1 1686 struct mwl8k_cmd_get_hw_spec_sta *cmd;
a66098da
LB		 1687 int rc;
1688 int i;
1689
1690 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1691 if (cmd == NULL)
1692 return -ENOMEM;
1693
1694 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1695 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1696
1697 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1698 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
45eb400d 1699 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
4ff6432e 1700 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
a66098da 1701 for (i = 0; i < MWL8K_TX_QUEUES; i++)
45eb400d 1702 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
4ff6432e 1703 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
45eb400d 1704 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
a66098da
LB		 1705
1706 rc = mwl8k_post_cmd(hw, &cmd->header);
1707
1708 if (!rc) {
1709 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1710 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
4ff6432e 1711 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
a66098da 1712 priv->hw_rev = cmd->hw_rev;
a66098da
LB		 1713 }
1714
1715 kfree(cmd);
1716 return rc;
1717}
1718
42fba21d
LB		 1719/*
1720 * CMD_GET_HW_SPEC (AP version).
1721 */
1722struct mwl8k_cmd_get_hw_spec_ap {
1723 struct mwl8k_cmd_pkt header;
1724 __u8 hw_rev;
1725 __u8 host_interface;
1726 __le16 num_wcb;
1727 __le16 num_mcaddrs;
1728 __u8 perm_addr[ETH_ALEN];
1729 __le16 region_code;
1730 __le16 num_antenna;
1731 __le32 fw_rev;
1732 __le32 wcbbase0;
1733 __le32 rxwrptr;
1734 __le32 rxrdptr;
1735 __le32 ps_cookie;
1736 __le32 wcbbase1;
1737 __le32 wcbbase2;
1738 __le32 wcbbase3;
1739} __attribute__((packed));
1740
1741static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
1742{
1743 struct mwl8k_priv *priv = hw->priv;
1744 struct mwl8k_cmd_get_hw_spec_ap *cmd;
1745 int rc;
1746
1747 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1748 if (cmd == NULL)
1749 return -ENOMEM;
1750
1751 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1752 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1753
1754 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1755 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1756
1757 rc = mwl8k_post_cmd(hw, &cmd->header);
1758
1759 if (!rc) {
1760 int off;
1761
1762 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1763 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1764 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1765 priv->hw_rev = cmd->hw_rev;
1766
1767 off = le32_to_cpu(cmd->wcbbase0) & 0xffff;
1768 iowrite32(cpu_to_le32(priv->txq[0].txd_dma), priv->sram + off);
1769
1770 off = le32_to_cpu(cmd->rxwrptr) & 0xffff;
1771 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1772
1773 off = le32_to_cpu(cmd->rxrdptr) & 0xffff;
1774 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1775
1776 off = le32_to_cpu(cmd->wcbbase1) & 0xffff;
1777 iowrite32(cpu_to_le32(priv->txq[1].txd_dma), priv->sram + off);
1778
1779 off = le32_to_cpu(cmd->wcbbase2) & 0xffff;
1780 iowrite32(cpu_to_le32(priv->txq[2].txd_dma), priv->sram + off);
1781
1782 off = le32_to_cpu(cmd->wcbbase3) & 0xffff;
1783 iowrite32(cpu_to_le32(priv->txq[3].txd_dma), priv->sram + off);
1784 }
1785
1786 kfree(cmd);
1787 return rc;
1788}
1789
1790/*
1791 * CMD_SET_HW_SPEC.
1792 */
1793struct mwl8k_cmd_set_hw_spec {
1794 struct mwl8k_cmd_pkt header;
1795 __u8 hw_rev;
1796 __u8 host_interface;
1797 __le16 num_mcaddrs;
1798 __u8 perm_addr[ETH_ALEN];
1799 __le16 region_code;
1800 __le32 fw_rev;
1801 __le32 ps_cookie;
1802 __le32 caps;
1803 __le32 rx_queue_ptr;
1804 __le32 num_tx_queues;
1805 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1806 __le32 flags;
1807 __le32 num_tx_desc_per_queue;
1808 __le32 total_rxd;
1809} __attribute__((packed));
1810
1811#define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
1812
1813static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw)
1814{
1815 struct mwl8k_priv *priv = hw->priv;
1816 struct mwl8k_cmd_set_hw_spec *cmd;
1817 int rc;
1818 int i;
1819
1820 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1821 if (cmd == NULL)
1822 return -ENOMEM;
1823
1824 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC);
1825 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1826
1827 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1828 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
1829 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1830 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1831 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
1832 cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT);
1833 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1834 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
1835
1836 rc = mwl8k_post_cmd(hw, &cmd->header);
1837 kfree(cmd);
1838
1839 return rc;
1840}
1841
a66098da
LB		 1842/*
1843 * CMD_MAC_MULTICAST_ADR.
1844 */
1845struct mwl8k_cmd_mac_multicast_adr {
1846 struct mwl8k_cmd_pkt header;
1847 __le16 action;
1848 __le16 numaddr;
ce9e2e1b 1849 __u8 addr[0][ETH_ALEN];
a66098da
LB		 1850};
1851
d5e30845
LB		 1852#define MWL8K_ENABLE_RX_DIRECTED 0x0001
1853#define MWL8K_ENABLE_RX_MULTICAST 0x0002
1854#define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
1855#define MWL8K_ENABLE_RX_BROADCAST 0x0008
ce9e2e1b 1856
e81cd2d6 1857static struct mwl8k_cmd_pkt *
447ced07 1858__mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
e81cd2d6 1859 int mc_count, struct dev_addr_list *mclist)
a66098da 1860{
e81cd2d6 1861 struct mwl8k_priv *priv = hw->priv;
a66098da 1862 struct mwl8k_cmd_mac_multicast_adr *cmd;
e81cd2d6 1863 int size;
e81cd2d6 1864
447ced07 1865 if (allmulti || mc_count > priv->num_mcaddrs) {
d5e30845
LB		 1866 allmulti = 1;
1867 mc_count = 0;
1868 }
e81cd2d6
LB		 1869
1870 size = sizeof(*cmd) + mc_count * ETH_ALEN;
ce9e2e1b 1871
e81cd2d6 1872 cmd = kzalloc(size, GFP_ATOMIC);
a66098da 1873 if (cmd == NULL)
e81cd2d6 1874 return NULL;
a66098da
LB		 1875
1876 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1877 cmd->header.length = cpu_to_le16(size);
d5e30845
LB		 1878 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
1879 MWL8K_ENABLE_RX_BROADCAST);
1880
1881 if (allmulti) {
1882 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
1883 } else if (mc_count) {
1884 int i;
1885
1886 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1887 cmd->numaddr = cpu_to_le16(mc_count);
1888 for (i = 0; i < mc_count && mclist; i++) {
1889 if (mclist->da_addrlen != ETH_ALEN) {
1890 kfree(cmd);
1891 return NULL;
1892 }
1893 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
1894 mclist = mclist->next;
a66098da 1895 }
a66098da
LB		 1896 }
1897
e81cd2d6 1898 return &cmd->header;
a66098da
LB		 1899}
1900
1901/*
1902 * CMD_802_11_GET_STAT.
1903 */
1904struct mwl8k_cmd_802_11_get_stat {
1905 struct mwl8k_cmd_pkt header;
a66098da
LB		 1906 __le32 stats[64];
1907} __attribute__((packed));
1908
1909#define MWL8K_STAT_ACK_FAILURE 9
1910#define MWL8K_STAT_RTS_FAILURE 12
1911#define MWL8K_STAT_FCS_ERROR 24
1912#define MWL8K_STAT_RTS_SUCCESS 11
1913
1914static int mwl8k_cmd_802_11_get_stat(struct ieee80211_hw *hw,
1915 struct ieee80211_low_level_stats *stats)
1916{
1917 struct mwl8k_cmd_802_11_get_stat *cmd;
1918 int rc;
1919
1920 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1921 if (cmd == NULL)
1922 return -ENOMEM;
1923
1924 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1925 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 1926
1927 rc = mwl8k_post_cmd(hw, &cmd->header);
1928 if (!rc) {
1929 stats->dot11ACKFailureCount =
1930 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1931 stats->dot11RTSFailureCount =
1932 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1933 stats->dot11FCSErrorCount =
1934 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1935 stats->dot11RTSSuccessCount =
1936 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1937 }
1938 kfree(cmd);
1939
1940 return rc;
1941}
1942
1943/*
1944 * CMD_802_11_RADIO_CONTROL.
1945 */
1946struct mwl8k_cmd_802_11_radio_control {
1947 struct mwl8k_cmd_pkt header;
1948 __le16 action;
1949 __le16 control;
1950 __le16 radio_on;
1951} __attribute__((packed));
1952
c46563b7
LB		 1953static int
1954mwl8k_cmd_802_11_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
a66098da
LB		 1955{
1956 struct mwl8k_priv *priv = hw->priv;
1957 struct mwl8k_cmd_802_11_radio_control *cmd;
1958 int rc;
1959
c46563b7 1960 if (enable == priv->radio_on && !force)
a66098da
LB		 1961 return 0;
1962
a66098da
LB		 1963 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1964 if (cmd == NULL)
1965 return -ENOMEM;
1966
1967 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
1968 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1969 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
68ce3884 1970 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
a66098da
LB		 1971 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
1972
1973 rc = mwl8k_post_cmd(hw, &cmd->header);
1974 kfree(cmd);
1975
1976 if (!rc)
c46563b7 1977 priv->radio_on = enable;
a66098da
LB		 1978
1979 return rc;
1980}
1981
c46563b7
LB		 1982static int mwl8k_cmd_802_11_radio_disable(struct ieee80211_hw *hw)
1983{
1984 return mwl8k_cmd_802_11_radio_control(hw, 0, 0);
1985}
1986
1987static int mwl8k_cmd_802_11_radio_enable(struct ieee80211_hw *hw)
1988{
1989 return mwl8k_cmd_802_11_radio_control(hw, 1, 0);
1990}
1991
a66098da
LB		 1992static int
1993mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
1994{
1995 struct mwl8k_priv *priv;
1996
1997 if (hw == NULL || hw->priv == NULL)
1998 return -EINVAL;
1999 priv = hw->priv;
2000
68ce3884 2001 priv->radio_short_preamble = short_preamble;
a66098da 2002
c46563b7 2003 return mwl8k_cmd_802_11_radio_control(hw, 1, 1);
a66098da
LB		 2004}
2005
2006/*
2007 * CMD_802_11_RF_TX_POWER.
2008 */
2009#define MWL8K_TX_POWER_LEVEL_TOTAL 8
2010
2011struct mwl8k_cmd_802_11_rf_tx_power {
2012 struct mwl8k_cmd_pkt header;
2013 __le16 action;
2014 __le16 support_level;
2015 __le16 current_level;
2016 __le16 reserved;
2017 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
2018} __attribute__((packed));
2019
2020static int mwl8k_cmd_802_11_rf_tx_power(struct ieee80211_hw *hw, int dBm)
2021{
2022 struct mwl8k_cmd_802_11_rf_tx_power *cmd;
2023 int rc;
2024
2025 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2026 if (cmd == NULL)
2027 return -ENOMEM;
2028
2029 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
2030 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2031 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2032 cmd->support_level = cpu_to_le16(dBm);
2033
2034 rc = mwl8k_post_cmd(hw, &cmd->header);
2035 kfree(cmd);
2036
2037 return rc;
2038}
2039
08b06347
LB		 2040/*
2041 * CMD_RF_ANTENNA.
2042 */
2043struct mwl8k_cmd_rf_antenna {
2044 struct mwl8k_cmd_pkt header;
2045 __le16 antenna;
2046 __le16 mode;
2047} __attribute__((packed));
2048
2049#define MWL8K_RF_ANTENNA_RX 1
2050#define MWL8K_RF_ANTENNA_TX 2
2051
2052static int
2053mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask)
2054{
2055 struct mwl8k_cmd_rf_antenna *cmd;
2056 int rc;
2057
2058 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2059 if (cmd == NULL)
2060 return -ENOMEM;
2061
2062 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA);
2063 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2064 cmd->antenna = cpu_to_le16(antenna);
2065 cmd->mode = cpu_to_le16(mask);
2066
2067 rc = mwl8k_post_cmd(hw, &cmd->header);
2068 kfree(cmd);
2069
2070 return rc;
2071}
2072
a66098da
LB		 2073/*
2074 * CMD_SET_PRE_SCAN.
2075 */
2076struct mwl8k_cmd_set_pre_scan {
2077 struct mwl8k_cmd_pkt header;
2078} __attribute__((packed));
2079
2080static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
2081{
2082 struct mwl8k_cmd_set_pre_scan *cmd;
2083 int rc;
2084
2085 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2086 if (cmd == NULL)
2087 return -ENOMEM;
2088
2089 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
2090 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2091
2092 rc = mwl8k_post_cmd(hw, &cmd->header);
2093 kfree(cmd);
2094
2095 return rc;
2096}
2097
2098/*
2099 * CMD_SET_POST_SCAN.
2100 */
2101struct mwl8k_cmd_set_post_scan {
2102 struct mwl8k_cmd_pkt header;
2103 __le32 isibss;
d89173f2 2104 __u8 bssid[ETH_ALEN];
a66098da
LB		 2105} __attribute__((packed));
2106
2107static int
ce9e2e1b 2108mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, __u8 *mac)
a66098da
LB		 2109{
2110 struct mwl8k_cmd_set_post_scan *cmd;
2111 int rc;
2112
2113 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2114 if (cmd == NULL)
2115 return -ENOMEM;
2116
2117 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
2118 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2119 cmd->isibss = 0;
d89173f2 2120 memcpy(cmd->bssid, mac, ETH_ALEN);
a66098da
LB		 2121
2122 rc = mwl8k_post_cmd(hw, &cmd->header);
2123 kfree(cmd);
2124
2125 return rc;
2126}
2127
2128/*
2129 * CMD_SET_RF_CHANNEL.
2130 */
2131struct mwl8k_cmd_set_rf_channel {
2132 struct mwl8k_cmd_pkt header;
2133 __le16 action;
2134 __u8 current_channel;
2135 __le32 channel_flags;
2136} __attribute__((packed));
2137
2138static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
2139 struct ieee80211_channel *channel)
2140{
2141 struct mwl8k_cmd_set_rf_channel *cmd;
2142 int rc;
2143
2144 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2145 if (cmd == NULL)
2146 return -ENOMEM;
2147
2148 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
2149 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2150 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2151 cmd->current_channel = channel->hw_value;
2152 if (channel->band == IEEE80211_BAND_2GHZ)
2153 cmd->channel_flags = cpu_to_le32(0x00000081);
2154 else
2155 cmd->channel_flags = cpu_to_le32(0x00000000);
2156
2157 rc = mwl8k_post_cmd(hw, &cmd->header);
2158 kfree(cmd);
2159
2160 return rc;
2161}
2162
2163/*
2164 * CMD_SET_SLOT.
2165 */
2166struct mwl8k_cmd_set_slot {
2167 struct mwl8k_cmd_pkt header;
2168 __le16 action;
2169 __u8 short_slot;
2170} __attribute__((packed));
2171
5539bb51 2172static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
a66098da
LB		 2173{
2174 struct mwl8k_cmd_set_slot *cmd;
2175 int rc;
2176
2177 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2178 if (cmd == NULL)
2179 return -ENOMEM;
2180
2181 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
2182 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2183 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
5539bb51 2184 cmd->short_slot = short_slot_time;
a66098da
LB		 2185
2186 rc = mwl8k_post_cmd(hw, &cmd->header);
2187 kfree(cmd);
2188
2189 return rc;
2190}
2191
2192/*
2193 * CMD_MIMO_CONFIG.
2194 */
2195struct mwl8k_cmd_mimo_config {
2196 struct mwl8k_cmd_pkt header;
2197 __le32 action;
2198 __u8 rx_antenna_map;
2199 __u8 tx_antenna_map;
2200} __attribute__((packed));
2201
2202static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
2203{
2204 struct mwl8k_cmd_mimo_config *cmd;
2205 int rc;
2206
2207 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2208 if (cmd == NULL)
2209 return -ENOMEM;
2210
2211 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
2212 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2213 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
2214 cmd->rx_antenna_map = rx;
2215 cmd->tx_antenna_map = tx;
2216
2217 rc = mwl8k_post_cmd(hw, &cmd->header);
2218 kfree(cmd);
2219
2220 return rc;
2221}
2222
2223/*
2224 * CMD_ENABLE_SNIFFER.
2225 */
2226struct mwl8k_cmd_enable_sniffer {
2227 struct mwl8k_cmd_pkt header;
2228 __le32 action;
2229} __attribute__((packed));
2230
2231static int mwl8k_enable_sniffer(struct ieee80211_hw *hw, bool enable)
2232{
2233 struct mwl8k_cmd_enable_sniffer *cmd;
2234 int rc;
2235
2236 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2237 if (cmd == NULL)
2238 return -ENOMEM;
2239
2240 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
2241 cmd->header.length = cpu_to_le16(sizeof(*cmd));
ce9e2e1b 2242 cmd->action = cpu_to_le32(!!enable);
a66098da
LB		 2243
2244 rc = mwl8k_post_cmd(hw, &cmd->header);
2245 kfree(cmd);
2246
2247 return rc;
2248}
2249
32060e1b
LB		 2250/*
2251 * CMD_SET_MAC_ADDR.
2252 */
2253struct mwl8k_cmd_set_mac_addr {
2254 struct mwl8k_cmd_pkt header;
259a8e7d
LB		 2255 union {
2256 struct {
2257 __le16 mac_type;
2258 __u8 mac_addr[ETH_ALEN];
2259 } mbss;
2260 __u8 mac_addr[ETH_ALEN];
2261 };
32060e1b
LB		 2262} __attribute__((packed));
2263
2264static int mwl8k_set_mac_addr(struct ieee80211_hw *hw, u8 *mac)
2265{
259a8e7d 2266 struct mwl8k_priv *priv = hw->priv;
32060e1b
LB		 2267 struct mwl8k_cmd_set_mac_addr *cmd;
2268 int rc;
2269
2270 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2271 if (cmd == NULL)
2272 return -ENOMEM;
2273
2274 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
2275 cmd->header.length = cpu_to_le16(sizeof(*cmd));
259a8e7d
LB		 2276 if (priv->ap_fw) {
2277 cmd->mbss.mac_type = 0;
2278 memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN);
2279 } else {
2280 memcpy(cmd->mac_addr, mac, ETH_ALEN);
2281 }
32060e1b
LB		 2282
2283 rc = mwl8k_post_cmd(hw, &cmd->header);
2284 kfree(cmd);
2285
2286 return rc;
2287}
2288
2289
a66098da 2290/*
ce9e2e1b 2291 * CMD_SET_RATEADAPT_MODE.
a66098da
LB		 2292 */
2293struct mwl8k_cmd_set_rate_adapt_mode {
2294 struct mwl8k_cmd_pkt header;
2295 __le16 action;
2296 __le16 mode;
2297} __attribute__((packed));
2298
2299static int mwl8k_cmd_setrateadaptmode(struct ieee80211_hw *hw, __u16 mode)
2300{
2301 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
2302 int rc;
2303
2304 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2305 if (cmd == NULL)
2306 return -ENOMEM;
2307
2308 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
2309 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2310 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2311 cmd->mode = cpu_to_le16(mode);
2312
2313 rc = mwl8k_post_cmd(hw, &cmd->header);
2314 kfree(cmd);
2315
2316 return rc;
2317}
2318
2319/*
2320 * CMD_SET_WMM_MODE.
2321 */
2322struct mwl8k_cmd_set_wmm {
2323 struct mwl8k_cmd_pkt header;
2324 __le16 action;
2325} __attribute__((packed));
2326
2327static int mwl8k_set_wmm(struct ieee80211_hw *hw, bool enable)
2328{
2329 struct mwl8k_priv *priv = hw->priv;
2330 struct mwl8k_cmd_set_wmm *cmd;
2331 int rc;
2332
2333 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2334 if (cmd == NULL)
2335 return -ENOMEM;
2336
2337 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
2338 cmd->header.length = cpu_to_le16(sizeof(*cmd));
0439b1f5 2339 cmd->action = cpu_to_le16(!!enable);
a66098da
LB		 2340
2341 rc = mwl8k_post_cmd(hw, &cmd->header);
2342 kfree(cmd);
2343
2344 if (!rc)
0439b1f5 2345 priv->wmm_enabled = enable;
a66098da
LB		 2346
2347 return rc;
2348}
2349
2350/*
2351 * CMD_SET_RTS_THRESHOLD.
2352 */
2353struct mwl8k_cmd_rts_threshold {
2354 struct mwl8k_cmd_pkt header;
2355 __le16 action;
2356 __le16 threshold;
2357} __attribute__((packed));
2358
2359static int mwl8k_rts_threshold(struct ieee80211_hw *hw,
733d3067 2360 u16 action, u16 threshold)
a66098da
LB		 2361{
2362 struct mwl8k_cmd_rts_threshold *cmd;
2363 int rc;
2364
2365 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2366 if (cmd == NULL)
2367 return -ENOMEM;
2368
2369 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
2370 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2371 cmd->action = cpu_to_le16(action);
733d3067 2372 cmd->threshold = cpu_to_le16(threshold);
a66098da
LB		 2373
2374 rc = mwl8k_post_cmd(hw, &cmd->header);
2375 kfree(cmd);
2376
2377 return rc;
2378}
2379
2380/*
2381 * CMD_SET_EDCA_PARAMS.
2382 */
2383struct mwl8k_cmd_set_edca_params {
2384 struct mwl8k_cmd_pkt header;
2385
2386 /* See MWL8K_SET_EDCA_XXX below */
2387 __le16 action;
2388
2389 /* TX opportunity in units of 32 us */
2390 __le16 txop;
2391
2e484c89
LB		 2392 union {
2393 struct {
2394 /* Log exponent of max contention period: 0...15 */
2395 __le32 log_cw_max;
2396
2397 /* Log exponent of min contention period: 0...15 */
2398 __le32 log_cw_min;
2399
2400 /* Adaptive interframe spacing in units of 32us */
2401 __u8 aifs;
2402
2403 /* TX queue to configure */
2404 __u8 txq;
2405 } ap;
2406 struct {
2407 /* Log exponent of max contention period: 0...15 */
2408 __u8 log_cw_max;
a66098da 2409
2e484c89
LB		 2410 /* Log exponent of min contention period: 0...15 */
2411 __u8 log_cw_min;
a66098da 2412
2e484c89
LB		 2413 /* Adaptive interframe spacing in units of 32us */
2414 __u8 aifs;
a66098da 2415
2e484c89
LB		 2416 /* TX queue to configure */
2417 __u8 txq;
2418 } sta;
2419 };
a66098da
LB		 2420} __attribute__((packed));
2421
a66098da
LB		 2422#define MWL8K_SET_EDCA_CW 0x01
2423#define MWL8K_SET_EDCA_TXOP 0x02
2424#define MWL8K_SET_EDCA_AIFS 0x04
2425
2426#define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2427 MWL8K_SET_EDCA_TXOP | \
2428 MWL8K_SET_EDCA_AIFS)
2429
2430static int
2431mwl8k_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2432 __u16 cw_min, __u16 cw_max,
2433 __u8 aifs, __u16 txop)
2434{
2e484c89 2435 struct mwl8k_priv *priv = hw->priv;
a66098da 2436 struct mwl8k_cmd_set_edca_params *cmd;
a66098da
LB		 2437 int rc;
2438
2439 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2440 if (cmd == NULL)
2441 return -ENOMEM;
2442
22995b24
LB		 2443 /*
2444 * Queues 0 (BE) and 1 (BK) are swapped in hardware for
2445 * this call.
2446 */
2447 qnum ^= !(qnum >> 1);
2448
a66098da
LB		 2449 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2450 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 2451 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2452 cmd->txop = cpu_to_le16(txop);
2e484c89
LB		 2453 if (priv->ap_fw) {
2454 cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1));
2455 cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1));
2456 cmd->ap.aifs = aifs;
2457 cmd->ap.txq = qnum;
2458 } else {
2459 cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1);
2460 cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1);
2461 cmd->sta.aifs = aifs;
2462 cmd->sta.txq = qnum;
2463 }
a66098da
LB		 2464
2465 rc = mwl8k_post_cmd(hw, &cmd->header);
2466 kfree(cmd);
2467
2468 return rc;
2469}
2470
2471/*
2472 * CMD_FINALIZE_JOIN.
2473 */
2474
2475/* FJ beacon buffer size is compiled into the firmware. */
2476#define MWL8K_FJ_BEACON_MAXLEN 128
2477
2478struct mwl8k_cmd_finalize_join {
2479 struct mwl8k_cmd_pkt header;
2480 __le32 sleep_interval; /* Number of beacon periods to sleep */
2481 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
2482} __attribute__((packed));
2483
2484static int mwl8k_finalize_join(struct ieee80211_hw *hw, void *frame,
2485 __u16 framelen, __u16 dtim)
2486{
2487 struct mwl8k_cmd_finalize_join *cmd;
2488 struct ieee80211_mgmt *payload = frame;
2489 u16 hdrlen;
2490 u32 payload_len;
2491 int rc;
2492
2493 if (frame == NULL)
2494 return -EINVAL;
2495
2496 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2497 if (cmd == NULL)
2498 return -ENOMEM;
2499
2500 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
2501 cmd->header.length = cpu_to_le16(sizeof(*cmd));
ce9e2e1b 2502 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
a66098da
LB		 2503
2504 hdrlen = ieee80211_hdrlen(payload->frame_control);
2505
2506 payload_len = framelen > hdrlen ? framelen - hdrlen : 0;
2507
2508 /* XXX TBD Might just have to abort and return an error */
2509 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2510 printk(KERN_ERR "%s(): WARNING: Incomplete beacon "
c2c357ce
LB		 2511 "sent to firmware. Sz=%u MAX=%u\n", __func__,
2512 payload_len, MWL8K_FJ_BEACON_MAXLEN);
a66098da 2513
ce9e2e1b
LB		 2514 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2515 payload_len = MWL8K_FJ_BEACON_MAXLEN;
a66098da
LB		 2516
2517 if (payload && payload_len)
2518 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
2519
2520 rc = mwl8k_post_cmd(hw, &cmd->header);
2521 kfree(cmd);
2522 return rc;
2523}
2524
2525/*
2526 * CMD_UPDATE_STADB.
2527 */
2528struct mwl8k_cmd_update_sta_db {
2529 struct mwl8k_cmd_pkt header;
2530
2531 /* See STADB_ACTION_TYPE */
2532 __le32 action;
2533
2534 /* Peer MAC address */
d89173f2 2535 __u8 peer_addr[ETH_ALEN];
a66098da
LB		 2536
2537 __le32 reserved;
2538
2539 /* Peer info - valid during add/update. */
2540 struct peer_capability_info peer_info;
2541} __attribute__((packed));
2542
2543static int mwl8k_cmd_update_sta_db(struct ieee80211_hw *hw,
2544 struct ieee80211_vif *vif, __u32 action)
2545{
2546 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2547 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2548 struct mwl8k_cmd_update_sta_db *cmd;
2549 struct peer_capability_info *peer_info;
a66098da 2550 int rc;
a66098da
LB		 2551
2552 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2553 if (cmd == NULL)
2554 return -ENOMEM;
2555
2556 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2557 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2558
2559 cmd->action = cpu_to_le32(action);
2560 peer_info = &cmd->peer_info;
d89173f2 2561 memcpy(cmd->peer_addr, mv_vif->bssid, ETH_ALEN);
a66098da
LB		 2562
2563 switch (action) {
2564 case MWL8K_STA_DB_ADD_ENTRY:
2565 case MWL8K_STA_DB_MODIFY_ENTRY:
2566 /* Build peer_info block */
2567 peer_info->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2568 peer_info->basic_caps = cpu_to_le16(info->assoc_capability);
140eb5e2
LB		 2569 memcpy(peer_info->legacy_rates, mwl8k_rateids,
2570 sizeof(mwl8k_rateids));
a66098da
LB		 2571 peer_info->interop = 1;
2572 peer_info->amsdu_enabled = 0;
2573
a66098da
LB		 2574 rc = mwl8k_post_cmd(hw, &cmd->header);
2575 if (rc == 0)
2576 mv_vif->peer_id = peer_info->station_id;
2577
2578 break;
2579
2580 case MWL8K_STA_DB_DEL_ENTRY:
2581 case MWL8K_STA_DB_FLUSH:
2582 default:
2583 rc = mwl8k_post_cmd(hw, &cmd->header);
2584 if (rc == 0)
2585 mv_vif->peer_id = 0;
2586 break;
2587 }
2588 kfree(cmd);
2589
2590 return rc;
2591}
2592
2593/*
2594 * CMD_SET_AID.
2595 */
a66098da
LB		 2596#define MWL8K_FRAME_PROT_DISABLED 0x00
2597#define MWL8K_FRAME_PROT_11G 0x07
2598#define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2599#define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
a66098da
LB		 2600
2601struct mwl8k_cmd_update_set_aid {
2602 struct mwl8k_cmd_pkt header;
2603 __le16 aid;
2604
2605 /* AP's MAC address (BSSID) */
d89173f2 2606 __u8 bssid[ETH_ALEN];
a66098da 2607 __le16 protection_mode;
140eb5e2 2608 __u8 supp_rates[14];
a66098da
LB		 2609} __attribute__((packed));
2610
2611static int mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2612 struct ieee80211_vif *vif)
2613{
2614 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2615 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2616 struct mwl8k_cmd_update_set_aid *cmd;
a66098da
LB		 2617 u16 prot_mode;
2618 int rc;
2619
2620 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2621 if (cmd == NULL)
2622 return -ENOMEM;
2623
2624 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
2625 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2626 cmd->aid = cpu_to_le16(info->aid);
2627
d89173f2 2628 memcpy(cmd->bssid, mv_vif->bssid, ETH_ALEN);
a66098da 2629
a66098da
LB		 2630 if (info->use_cts_prot) {
2631 prot_mode = MWL8K_FRAME_PROT_11G;
2632 } else {
9ed6bcce 2633 switch (info->ht_operation_mode &
a66098da
LB		 2634 IEEE80211_HT_OP_MODE_PROTECTION) {
2635 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2636 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2637 break;
2638 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2639 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2640 break;
2641 default:
2642 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2643 break;
2644 }
2645 }
a66098da
LB		 2646 cmd->protection_mode = cpu_to_le16(prot_mode);
2647
140eb5e2 2648 memcpy(cmd->supp_rates, mwl8k_rateids, sizeof(mwl8k_rateids));
a66098da
LB		 2649
2650 rc = mwl8k_post_cmd(hw, &cmd->header);
2651 kfree(cmd);
2652
2653 return rc;
2654}
2655
2656/*
2657 * CMD_SET_RATE.
2658 */
2659struct mwl8k_cmd_update_rateset {
2660 struct mwl8k_cmd_pkt header;
140eb5e2 2661 __u8 legacy_rates[14];
a66098da
LB		 2662
2663 /* Bitmap for supported MCS codes. */
0b5351a8
LB		 2664 __u8 mcs_set[16];
2665 __u8 reserved[16];
a66098da
LB		 2666} __attribute__((packed));
2667
2668static int mwl8k_update_rateset(struct ieee80211_hw *hw,
2669 struct ieee80211_vif *vif)
2670{
a66098da 2671 struct mwl8k_cmd_update_rateset *cmd;
a66098da
LB		 2672 int rc;
2673
2674 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2675 if (cmd == NULL)
2676 return -ENOMEM;
2677
2678 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
2679 cmd->header.length = cpu_to_le16(sizeof(*cmd));
140eb5e2 2680 memcpy(cmd->legacy_rates, mwl8k_rateids, sizeof(mwl8k_rateids));
a66098da
LB		 2681
2682 rc = mwl8k_post_cmd(hw, &cmd->header);
2683 kfree(cmd);
2684
2685 return rc;
2686}
2687
2688/*
2689 * CMD_USE_FIXED_RATE.
2690 */
2691#define MWL8K_RATE_TABLE_SIZE 8
2692#define MWL8K_UCAST_RATE 0
a66098da
LB		 2693#define MWL8K_USE_AUTO_RATE 0x0002
2694
2695struct mwl8k_rate_entry {
2696 /* Set to 1 if HT rate, 0 if legacy. */
2697 __le32 is_ht_rate;
2698
2699 /* Set to 1 to use retry_count field. */
2700 __le32 enable_retry;
2701
2702 /* Specified legacy rate or MCS. */
2703 __le32 rate;
2704
2705 /* Number of allowed retries. */
2706 __le32 retry_count;
2707} __attribute__((packed));
2708
2709struct mwl8k_rate_table {
2710 /* 1 to allow specified rate and below */
2711 __le32 allow_rate_drop;
2712 __le32 num_rates;
2713 struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE];
2714} __attribute__((packed));
2715
2716struct mwl8k_cmd_use_fixed_rate {
2717 struct mwl8k_cmd_pkt header;
2718 __le32 action;
2719 struct mwl8k_rate_table rate_table;
2720
2721 /* Unicast, Broadcast or Multicast */
2722 __le32 rate_type;
2723 __le32 reserved1;
2724 __le32 reserved2;
2725} __attribute__((packed));
2726
2727static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw,
2728 u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table)
2729{
2730 struct mwl8k_cmd_use_fixed_rate *cmd;
2731 int count;
2732 int rc;
2733
2734 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2735 if (cmd == NULL)
2736 return -ENOMEM;
2737
2738 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2739 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2740
2741 cmd->action = cpu_to_le32(action);
2742 cmd->rate_type = cpu_to_le32(rate_type);
2743
2744 if (rate_table != NULL) {
c2c357ce
LB		 2745 /*
2746 * Copy over each field manually so that endian
2747 * conversion can be done.
2748 */
a66098da
LB		 2749 cmd->rate_table.allow_rate_drop =
2750 cpu_to_le32(rate_table->allow_rate_drop);
2751 cmd->rate_table.num_rates =
2752 cpu_to_le32(rate_table->num_rates);
2753
2754 for (count = 0; count < rate_table->num_rates; count++) {
2755 struct mwl8k_rate_entry *dst =
2756 &cmd->rate_table.rate_entry[count];
2757 struct mwl8k_rate_entry *src =
2758 &rate_table->rate_entry[count];
2759
2760 dst->is_ht_rate = cpu_to_le32(src->is_ht_rate);
2761 dst->enable_retry = cpu_to_le32(src->enable_retry);
2762 dst->rate = cpu_to_le32(src->rate);
2763 dst->retry_count = cpu_to_le32(src->retry_count);
2764 }
2765 }
2766
2767 rc = mwl8k_post_cmd(hw, &cmd->header);
2768 kfree(cmd);
2769
2770 return rc;
2771}
2772
2773
2774/*
2775 * Interrupt handling.
2776 */
2777static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2778{
2779 struct ieee80211_hw *hw = dev_id;
2780 struct mwl8k_priv *priv = hw->priv;
2781 u32 status;
2782
2783 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2784 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2785
a66098da
LB		 2786 if (!status)
2787 return IRQ_NONE;
2788
2789 if (status & MWL8K_A2H_INT_TX_DONE)
2790 tasklet_schedule(&priv->tx_reclaim_task);
2791
2792 if (status & MWL8K_A2H_INT_RX_READY) {
2793 while (rxq_process(hw, 0, 1))
2794 rxq_refill(hw, 0, 1);
2795 }
2796
2797 if (status & MWL8K_A2H_INT_OPC_DONE) {
618952a7 2798 if (priv->hostcmd_wait != NULL)
a66098da 2799 complete(priv->hostcmd_wait);
a66098da
LB		 2800 }
2801
2802 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
618952a7 2803 if (!mutex_is_locked(&priv->fw_mutex) &&
88de754a 2804 priv->radio_on && priv->pending_tx_pkts)
618952a7 2805 mwl8k_tx_start(priv);
a66098da
LB		 2806 }
2807
2808 return IRQ_HANDLED;
2809}
2810
2811
2812/*
2813 * Core driver operations.
2814 */
2815static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2816{
2817 struct mwl8k_priv *priv = hw->priv;
2818 int index = skb_get_queue_mapping(skb);
2819 int rc;
2820
2821 if (priv->current_channel == NULL) {
2822 printk(KERN_DEBUG "%s: dropped TX frame since radio "
c2c357ce 2823 "disabled\n", wiphy_name(hw->wiphy));
a66098da
LB		 2824 dev_kfree_skb(skb);
2825 return NETDEV_TX_OK;
2826 }
2827
2828 rc = mwl8k_txq_xmit(hw, index, skb);
2829
2830 return rc;
2831}
2832
a66098da
LB		 2833static int mwl8k_start(struct ieee80211_hw *hw)
2834{
a66098da
LB		 2835 struct mwl8k_priv *priv = hw->priv;
2836 int rc;
2837
a0607fd3 2838 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 2839 IRQF_SHARED, MWL8K_NAME, hw);
2840 if (rc) {
2841 printk(KERN_ERR "%s: failed to register IRQ handler\n",
c2c357ce 2842 wiphy_name(hw->wiphy));
2ec610cb 2843 return -EIO;
a66098da
LB		 2844 }
2845
2ec610cb
LB		 2846 /* Enable tx reclaim tasklet */
2847 tasklet_enable(&priv->tx_reclaim_task);
2848
a66098da 2849 /* Enable interrupts */
c23b5a69 2850 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da 2851
2ec610cb
LB		 2852 rc = mwl8k_fw_lock(hw);
2853 if (!rc) {
2854 rc = mwl8k_cmd_802_11_radio_enable(hw);
a66098da 2855
5e4cf166
LB		 2856 if (!priv->ap_fw) {
2857 if (!rc)
2858 rc = mwl8k_enable_sniffer(hw, 0);
a66098da 2859
5e4cf166
LB		 2860 if (!rc)
2861 rc = mwl8k_cmd_set_pre_scan(hw);
2862
2863 if (!rc)
2864 rc = mwl8k_cmd_set_post_scan(hw,
2865 "\x00\x00\x00\x00\x00\x00");
2866 }
2ec610cb
LB		 2867
2868 if (!rc)
2869 rc = mwl8k_cmd_setrateadaptmode(hw, 0);
a66098da 2870
2ec610cb
LB		 2871 if (!rc)
2872 rc = mwl8k_set_wmm(hw, 0);
a66098da 2873
2ec610cb
LB		 2874 mwl8k_fw_unlock(hw);
2875 }
2876
2877 if (rc) {
2878 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2879 free_irq(priv->pdev->irq, hw);
2880 tasklet_disable(&priv->tx_reclaim_task);
2881 }
a66098da
LB		 2882
2883 return rc;
2884}
2885
a66098da
LB		 2886static void mwl8k_stop(struct ieee80211_hw *hw)
2887{
a66098da
LB		 2888 struct mwl8k_priv *priv = hw->priv;
2889 int i;
2890
d3cea0b8 2891 mwl8k_cmd_802_11_radio_disable(hw);
a66098da
LB		 2892
2893 ieee80211_stop_queues(hw);
2894
a66098da 2895 /* Disable interrupts */
a66098da 2896 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 2897 free_irq(priv->pdev->irq, hw);
2898
2899 /* Stop finalize join worker */
2900 cancel_work_sync(&priv->finalize_join_worker);
2901 if (priv->beacon_skb != NULL)
2902 dev_kfree_skb(priv->beacon_skb);
2903
2904 /* Stop tx reclaim tasklet */
2905 tasklet_disable(&priv->tx_reclaim_task);
2906
a66098da
LB		 2907 /* Return all skbs to mac80211 */
2908 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2909 mwl8k_txq_reclaim(hw, i, 1);
2910}
2911
2912static int mwl8k_add_interface(struct ieee80211_hw *hw,
2913 struct ieee80211_if_init_conf *conf)
2914{
2915 struct mwl8k_priv *priv = hw->priv;
2916 struct mwl8k_vif *mwl8k_vif;
2917
2918 /*
2919 * We only support one active interface at a time.
2920 */
2921 if (priv->vif != NULL)
2922 return -EBUSY;
2923
2924 /*
2925 * We only support managed interfaces for now.
2926 */
240e86ef 2927 if (conf->type != NL80211_IFTYPE_STATION)
a66098da
LB		 2928 return -EINVAL;
2929
a43c49a8
LB		 2930 /*
2931 * Reject interface creation if sniffer mode is active, as
2932 * STA operation is mutually exclusive with hardware sniffer
2933 * mode.
2934 */
2935 if (priv->sniffer_enabled) {
2936 printk(KERN_INFO "%s: unable to create STA "
2937 "interface due to sniffer mode being enabled\n",
2938 wiphy_name(hw->wiphy));
2939 return -EINVAL;
2940 }
2941
a66098da
LB		 2942 /* Clean out driver private area */
2943 mwl8k_vif = MWL8K_VIF(conf->vif);
2944 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
2945
32060e1b
LB		 2946 /* Set and save the mac address */
2947 mwl8k_set_mac_addr(hw, conf->mac_addr);
d89173f2 2948 memcpy(mwl8k_vif->mac_addr, conf->mac_addr, ETH_ALEN);
a66098da
LB		 2949
2950 /* Back pointer to parent config block */
2951 mwl8k_vif->priv = priv;
2952
a66098da
LB		 2953 /* Set Initial sequence number to zero */
2954 mwl8k_vif->seqno = 0;
2955
2956 priv->vif = conf->vif;
2957 priv->current_channel = NULL;
2958
2959 return 0;
2960}
2961
2962static void mwl8k_remove_interface(struct ieee80211_hw *hw,
2963 struct ieee80211_if_init_conf *conf)
2964{
2965 struct mwl8k_priv *priv = hw->priv;
2966
2967 if (priv->vif == NULL)
2968 return;
2969
32060e1b
LB		 2970 mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
2971
a66098da
LB		 2972 priv->vif = NULL;
2973}
2974
ee03a932 2975static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
a66098da 2976{
a66098da
LB		 2977 struct ieee80211_conf *conf = &hw->conf;
2978 struct mwl8k_priv *priv = hw->priv;
ee03a932 2979 int rc;
a66098da 2980
7595d67a
LB		 2981 if (conf->flags & IEEE80211_CONF_IDLE) {
2982 mwl8k_cmd_802_11_radio_disable(hw);
2983 priv->current_channel = NULL;
ee03a932 2984 return 0;
7595d67a
LB		 2985 }
2986
ee03a932
LB		 2987 rc = mwl8k_fw_lock(hw);
2988 if (rc)
2989 return rc;
a66098da 2990
ee03a932
LB		 2991 rc = mwl8k_cmd_802_11_radio_enable(hw);
2992 if (rc)
2993 goto out;
a66098da 2994
ee03a932
LB		 2995 rc = mwl8k_cmd_set_rf_channel(hw, conf->channel);
2996 if (rc)
2997 goto out;
2998
2999 priv->current_channel = conf->channel;
a66098da
LB		 3000
3001 if (conf->power_level > 18)
3002 conf->power_level = 18;
ee03a932
LB		 3003 rc = mwl8k_cmd_802_11_rf_tx_power(hw, conf->power_level);
3004 if (rc)
3005 goto out;
a66098da 3006
08b06347
LB		 3007 if (priv->ap_fw) {
3008 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x7);
3009 if (!rc)
3010 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7);
3011 } else {
3012 rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7);
3013 }
a66098da 3014
ee03a932
LB		 3015out:
3016 mwl8k_fw_unlock(hw);
a66098da 3017
ee03a932 3018 return rc;
a66098da
LB		 3019}
3020
3a980d0a
LB		 3021static void mwl8k_bss_info_changed(struct ieee80211_hw *hw,
3022 struct ieee80211_vif *vif,
3023 struct ieee80211_bss_conf *info,
3024 u32 changed)
a66098da 3025{
a66098da
LB		 3026 struct mwl8k_priv *priv = hw->priv;
3027 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
3a980d0a
LB		 3028 int rc;
3029
3030 if (changed & BSS_CHANGED_BSSID)
3031 memcpy(mwl8k_vif->bssid, info->bssid, ETH_ALEN);
3032
3033 if ((changed & BSS_CHANGED_ASSOC) == 0)
3034 return;
a66098da 3035
a66098da
LB		 3036 priv->capture_beacon = false;
3037
3a980d0a 3038 rc = mwl8k_fw_lock(hw);
942457d6 3039 if (rc)
3a980d0a
LB		 3040 return;
3041
a66098da
LB		 3042 if (info->assoc) {
3043 memcpy(&mwl8k_vif->bss_info, info,
3044 sizeof(struct ieee80211_bss_conf));
3045
3046 /* Install rates */
3a980d0a
LB		 3047 rc = mwl8k_update_rateset(hw, vif);
3048 if (rc)
3049 goto out;
a66098da
LB		 3050
3051 /* Turn on rate adaptation */
3a980d0a
LB		 3052 rc = mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE,
3053 MWL8K_UCAST_RATE, NULL);
3054 if (rc)
3055 goto out;
a66098da
LB		 3056
3057 /* Set radio preamble */
3a980d0a
LB		 3058 rc = mwl8k_set_radio_preamble(hw, info->use_short_preamble);
3059 if (rc)
3060 goto out;
a66098da
LB		 3061
3062 /* Set slot time */
3a980d0a
LB		 3063 rc = mwl8k_cmd_set_slot(hw, info->use_short_slot);
3064 if (rc)
3065 goto out;
a66098da
LB		 3066
3067 /* Update peer rate info */
3a980d0a
LB		 3068 rc = mwl8k_cmd_update_sta_db(hw, vif,
3069 MWL8K_STA_DB_MODIFY_ENTRY);
3070 if (rc)
3071 goto out;
a66098da
LB		 3072
3073 /* Set AID */
3a980d0a
LB		 3074 rc = mwl8k_cmd_set_aid(hw, vif);
3075 if (rc)
3076 goto out;
a66098da
LB		 3077
3078 /*
3079 * Finalize the join. Tell rx handler to process
3080 * next beacon from our BSSID.
3081 */
d89173f2 3082 memcpy(priv->capture_bssid, mwl8k_vif->bssid, ETH_ALEN);
a66098da
LB		 3083 priv->capture_beacon = true;
3084 } else {
3a980d0a 3085 rc = mwl8k_cmd_update_sta_db(hw, vif, MWL8K_STA_DB_DEL_ENTRY);
a66098da
LB		 3086 memset(&mwl8k_vif->bss_info, 0,
3087 sizeof(struct ieee80211_bss_conf));
d89173f2 3088 memset(mwl8k_vif->bssid, 0, ETH_ALEN);
a66098da
LB		 3089 }
3090
3a980d0a
LB		 3091out:
3092 mwl8k_fw_unlock(hw);
a66098da
LB		 3093}
3094
e81cd2d6
LB		 3095static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
3096 int mc_count, struct dev_addr_list *mclist)
3097{
3098 struct mwl8k_cmd_pkt *cmd;
3099
447ced07
LB		 3100 /*
3101 * Synthesize and return a command packet that programs the
3102 * hardware multicast address filter. At this point we don't
3103 * know whether FIF_ALLMULTI is being requested, but if it is,
3104 * we'll end up throwing this packet away and creating a new
3105 * one in mwl8k_configure_filter().
3106 */
3107 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist);
e81cd2d6
LB		 3108
3109 return (unsigned long)cmd;
3110}
3111
a43c49a8
LB		 3112static int
3113mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
3114 unsigned int changed_flags,
3115 unsigned int *total_flags)
3116{
3117 struct mwl8k_priv *priv = hw->priv;
3118
3119 /*
3120 * Hardware sniffer mode is mutually exclusive with STA
3121 * operation, so refuse to enable sniffer mode if a STA
3122 * interface is active.
3123 */
3124 if (priv->vif != NULL) {
3125 if (net_ratelimit())
3126 printk(KERN_INFO "%s: not enabling sniffer "
3127 "mode because STA interface is active\n",
3128 wiphy_name(hw->wiphy));
3129 return 0;
3130 }
3131
3132 if (!priv->sniffer_enabled) {
3133 if (mwl8k_enable_sniffer(hw, 1))
3134 return 0;
3135 priv->sniffer_enabled = true;
3136 }
3137
3138 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
3139 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
3140 FIF_OTHER_BSS;
3141
3142 return 1;
3143}
3144
e6935ea1
LB		 3145static void mwl8k_configure_filter(struct ieee80211_hw *hw,
3146 unsigned int changed_flags,
3147 unsigned int *total_flags,
3148 u64 multicast)
3149{
3150 struct mwl8k_priv *priv = hw->priv;
a43c49a8
LB		 3151 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
3152
c0adae2c
LB		 3153 /*
3154 * AP firmware doesn't allow fine-grained control over
3155 * the receive filter.
3156 */
3157 if (priv->ap_fw) {
3158 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
3159 kfree(cmd);
3160 return;
3161 }
3162
a43c49a8
LB		 3163 /*
3164 * Enable hardware sniffer mode if FIF_CONTROL or
3165 * FIF_OTHER_BSS is requested.
3166 */
3167 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
3168 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
3169 kfree(cmd);
3170 return;
3171 }
a66098da 3172
e6935ea1 3173 /* Clear unsupported feature flags */
447ced07 3174 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
a66098da 3175
e6935ea1
LB		 3176 if (mwl8k_fw_lock(hw))
3177 return;
a66098da 3178
a43c49a8
LB		 3179 if (priv->sniffer_enabled) {
3180 mwl8k_enable_sniffer(hw, 0);
3181 priv->sniffer_enabled = false;
3182 }
3183
e6935ea1 3184 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
77165d88
LB		 3185 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
3186 /*
3187 * Disable the BSS filter.
3188 */
e6935ea1 3189 mwl8k_cmd_set_pre_scan(hw);
77165d88 3190 } else {
a94cc97e
LB		 3191 u8 *bssid;
3192
77165d88
LB		 3193 /*
3194 * Enable the BSS filter.
3195 *
3196 * If there is an active STA interface, use that
3197 * interface's BSSID, otherwise use a dummy one
3198 * (where the OUI part needs to be nonzero for
3199 * the BSSID to be accepted by POST_SCAN).
3200 */
3201 bssid = "\x01\x00\x00\x00\x00\x00";
a94cc97e
LB		 3202 if (priv->vif != NULL)
3203 bssid = MWL8K_VIF(priv->vif)->bssid;
3204
e6935ea1 3205 mwl8k_cmd_set_post_scan(hw, bssid);
a66098da
LB		 3206 }
3207 }
3208
447ced07
LB		 3209 /*
3210 * If FIF_ALLMULTI is being requested, throw away the command
3211 * packet that ->prepare_multicast() built and replace it with
3212 * a command packet that enables reception of all multicast
3213 * packets.
3214 */
3215 if (*total_flags & FIF_ALLMULTI) {
3216 kfree(cmd);
3217 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL);
3218 }
3219
3220 if (cmd != NULL) {
3221 mwl8k_post_cmd(hw, cmd);
3222 kfree(cmd);
e6935ea1 3223 }
a66098da 3224
e6935ea1 3225 mwl8k_fw_unlock(hw);
a66098da
LB		 3226}
3227
a66098da
LB		 3228static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3229{
733d3067 3230 return mwl8k_rts_threshold(hw, MWL8K_CMD_SET, value);
a66098da
LB		 3231}
3232
a66098da
LB		 3233static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
3234 const struct ieee80211_tx_queue_params *params)
3235{
3e4f542c 3236 struct mwl8k_priv *priv = hw->priv;
a66098da 3237 int rc;
a66098da 3238
3e4f542c
LB		 3239 rc = mwl8k_fw_lock(hw);
3240 if (!rc) {
3241 if (!priv->wmm_enabled)
3242 rc = mwl8k_set_wmm(hw, 1);
a66098da 3243
3e4f542c
LB		 3244 if (!rc)
3245 rc = mwl8k_set_edca_params(hw, queue,
3246 params->cw_min,
3247 params->cw_max,
3248 params->aifs,
3249 params->txop);
3250
3251 mwl8k_fw_unlock(hw);
a66098da 3252 }
3e4f542c 3253
a66098da
LB		 3254 return rc;
3255}
3256
3257static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
3258 struct ieee80211_tx_queue_stats *stats)
3259{
3260 struct mwl8k_priv *priv = hw->priv;
3261 struct mwl8k_tx_queue *txq;
3262 int index;
3263
3264 spin_lock_bh(&priv->tx_lock);
3265 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
3266 txq = priv->txq + index;
45eb400d 3267 memcpy(&stats[index], &txq->stats,
a66098da
LB		 3268 sizeof(struct ieee80211_tx_queue_stats));
3269 }
3270 spin_unlock_bh(&priv->tx_lock);
a66098da 3271
954ef509 3272 return 0;
a66098da
LB		 3273}
3274
3275static int mwl8k_get_stats(struct ieee80211_hw *hw,
3276 struct ieee80211_low_level_stats *stats)
3277{
954ef509 3278 return mwl8k_cmd_802_11_get_stat(hw, stats);
a66098da
LB		 3279}
3280
3281static const struct ieee80211_ops mwl8k_ops = {
3282 .tx = mwl8k_tx,
3283 .start = mwl8k_start,
3284 .stop = mwl8k_stop,
3285 .add_interface = mwl8k_add_interface,
3286 .remove_interface = mwl8k_remove_interface,
3287 .config = mwl8k_config,
a66098da 3288 .bss_info_changed = mwl8k_bss_info_changed,
3ac64bee 3289 .prepare_multicast = mwl8k_prepare_multicast,
a66098da
LB		 3290 .configure_filter = mwl8k_configure_filter,
3291 .set_rts_threshold = mwl8k_set_rts_threshold,
3292 .conf_tx = mwl8k_conf_tx,
3293 .get_tx_stats = mwl8k_get_tx_stats,
3294 .get_stats = mwl8k_get_stats,
3295};
3296
3297static void mwl8k_tx_reclaim_handler(unsigned long data)
3298{
3299 int i;
3300 struct ieee80211_hw *hw = (struct ieee80211_hw *) data;
3301 struct mwl8k_priv *priv = hw->priv;
3302
3303 spin_lock_bh(&priv->tx_lock);
3304 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3305 mwl8k_txq_reclaim(hw, i, 0);
3306
88de754a 3307 if (priv->tx_wait != NULL && !priv->pending_tx_pkts) {
ce9e2e1b
LB		 3308 complete(priv->tx_wait);
3309 priv->tx_wait = NULL;
a66098da
LB		 3310 }
3311 spin_unlock_bh(&priv->tx_lock);
3312}
3313
3314static void mwl8k_finalize_join_worker(struct work_struct *work)
3315{
3316 struct mwl8k_priv *priv =
3317 container_of(work, struct mwl8k_priv, finalize_join_worker);
3318 struct sk_buff *skb = priv->beacon_skb;
ce9e2e1b 3319 u8 dtim = MWL8K_VIF(priv->vif)->bss_info.dtim_period;
a66098da
LB		 3320
3321 mwl8k_finalize_join(priv->hw, skb->data, skb->len, dtim);
3322 dev_kfree_skb(skb);
3323
3324 priv->beacon_skb = NULL;
3325}
3326
bcb628d5
JL		 3327enum {
3328 MWL8687 = 0,
3329 MWL8366,
6f6d1e9a
LB		 3330};
3331
bcb628d5
JL		 3332static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = {
3333 {
3334 .part_name = "88w8687",
3335 .helper_image = "mwl8k/helper_8687.fw",
3336 .fw_image = "mwl8k/fmimage_8687.fw",
3337 .rxd_ops = &rxd_8687_ops,
3338 .modes = BIT(NL80211_IFTYPE_STATION),
3339 },
3340 {
3341 .part_name = "88w8366",
3342 .helper_image = "mwl8k/helper_8366.fw",
3343 .fw_image = "mwl8k/fmimage_8366.fw",
3344 .rxd_ops = &rxd_8366_ops,
3345 .modes = 0,
3346 },
45a390dd
LB		 3347};
3348
3349static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
bcb628d5
JL		 3350 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, },
3351 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, },
3352 { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, },
3353 { },
45a390dd
LB		 3354};
3355MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
3356
a66098da
LB		 3357static int __devinit mwl8k_probe(struct pci_dev *pdev,
3358 const struct pci_device_id *id)
3359{
2aa7b01f 3360 static int printed_version = 0;
a66098da
LB		 3361 struct ieee80211_hw *hw;
3362 struct mwl8k_priv *priv;
a66098da
LB		 3363 int rc;
3364 int i;
2aa7b01f
LB		 3365
3366 if (!printed_version) {
3367 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
3368 printed_version = 1;
3369 }
a66098da
LB		 3370
3371 rc = pci_enable_device(pdev);
3372 if (rc) {
3373 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
3374 MWL8K_NAME);
3375 return rc;
3376 }
3377
3378 rc = pci_request_regions(pdev, MWL8K_NAME);
3379 if (rc) {
3380 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
3381 MWL8K_NAME);
3382 return rc;
3383 }
3384
3385 pci_set_master(pdev);
3386
3387 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
3388 if (hw == NULL) {
3389 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
3390 rc = -ENOMEM;
3391 goto err_free_reg;
3392 }
3393
3394 priv = hw->priv;
3395 priv->hw = hw;
3396 priv->pdev = pdev;
bcb628d5 3397 priv->device_info = &mwl8k_info_tbl[id->driver_data];
54bc3a0d 3398 priv->rxd_ops = priv->device_info->rxd_ops;
a43c49a8 3399 priv->sniffer_enabled = false;
0439b1f5 3400 priv->wmm_enabled = false;
a66098da 3401 priv->pending_tx_pkts = 0;
a66098da 3402
a66098da
LB		 3403 SET_IEEE80211_DEV(hw, &pdev->dev);
3404 pci_set_drvdata(pdev, hw);
3405
5b9482dd
LB		 3406 priv->sram = pci_iomap(pdev, 0, 0x10000);
3407 if (priv->sram == NULL) {
3408 printk(KERN_ERR "%s: Cannot map device SRAM\n",
c2c357ce 3409 wiphy_name(hw->wiphy));
a66098da
LB		 3410 goto err_iounmap;
3411 }
3412
5b9482dd
LB		 3413 /*
3414 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
3415 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
3416 */
3417 priv->regs = pci_iomap(pdev, 1, 0x10000);
3418 if (priv->regs == NULL) {
3419 priv->regs = pci_iomap(pdev, 2, 0x10000);
3420 if (priv->regs == NULL) {
3421 printk(KERN_ERR "%s: Cannot map device registers\n",
3422 wiphy_name(hw->wiphy));
3423 goto err_iounmap;
3424 }
3425 }
3426
a66098da
LB		 3427 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
3428 priv->band.band = IEEE80211_BAND_2GHZ;
3429 priv->band.channels = priv->channels;
3430 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
3431 priv->band.bitrates = priv->rates;
3432 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
3433 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
3434
3435 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
3436 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
3437
3438 /*
3439 * Extra headroom is the size of the required DMA header
3440 * minus the size of the smallest 802.11 frame (CTS frame).
3441 */
3442 hw->extra_tx_headroom =
3443 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
3444
3445 hw->channel_change_time = 10;
3446
3447 hw->queues = MWL8K_TX_QUEUES;
3448
547810e3 3449 hw->wiphy->interface_modes = priv->device_info->modes;
a66098da
LB		 3450
3451 /* Set rssi and noise values to dBm */
ce9e2e1b 3452 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
a66098da
LB		 3453 hw->vif_data_size = sizeof(struct mwl8k_vif);
3454 priv->vif = NULL;
3455
3456 /* Set default radio state and preamble */
c46563b7 3457 priv->radio_on = 0;
68ce3884 3458 priv->radio_short_preamble = 0;
a66098da
LB		 3459
3460 /* Finalize join worker */
3461 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
3462
3463 /* TX reclaim tasklet */
3464 tasklet_init(&priv->tx_reclaim_task,
3465 mwl8k_tx_reclaim_handler, (unsigned long)hw);
3466 tasklet_disable(&priv->tx_reclaim_task);
3467
a66098da
LB		 3468 /* Power management cookie */
3469 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
3470 if (priv->cookie == NULL)
3471 goto err_iounmap;
3472
3473 rc = mwl8k_rxq_init(hw, 0);
3474 if (rc)
3475 goto err_iounmap;
3476 rxq_refill(hw, 0, INT_MAX);
3477
618952a7
LB		 3478 mutex_init(&priv->fw_mutex);
3479 priv->fw_mutex_owner = NULL;
3480 priv->fw_mutex_depth = 0;
618952a7
LB		 3481 priv->hostcmd_wait = NULL;
3482
a66098da
LB		 3483 spin_lock_init(&priv->tx_lock);
3484
88de754a
LB		 3485 priv->tx_wait = NULL;
3486
a66098da
LB		 3487 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
3488 rc = mwl8k_txq_init(hw, i);
3489 if (rc)
3490 goto err_free_queues;
3491 }
3492
3493 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
c23b5a69 3494 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3495 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
3496 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3497
a0607fd3 3498 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 3499 IRQF_SHARED, MWL8K_NAME, hw);
3500 if (rc) {
3501 printk(KERN_ERR "%s: failed to register IRQ handler\n",
c2c357ce 3502 wiphy_name(hw->wiphy));
a66098da
LB		 3503 goto err_free_queues;
3504 }
3505
3506 /* Reset firmware and hardware */
3507 mwl8k_hw_reset(priv);
3508
3509 /* Ask userland hotplug daemon for the device firmware */
45a390dd 3510 rc = mwl8k_request_firmware(priv);
a66098da 3511 if (rc) {
c2c357ce
LB		 3512 printk(KERN_ERR "%s: Firmware files not found\n",
3513 wiphy_name(hw->wiphy));
a66098da
LB		 3514 goto err_free_irq;
3515 }
3516
3517 /* Load firmware into hardware */
c2c357ce 3518 rc = mwl8k_load_firmware(hw);
a66098da 3519 if (rc) {
c2c357ce
LB		 3520 printk(KERN_ERR "%s: Cannot start firmware\n",
3521 wiphy_name(hw->wiphy));
a66098da
LB		 3522 goto err_stop_firmware;
3523 }
3524
3525 /* Reclaim memory once firmware is successfully loaded */
3526 mwl8k_release_firmware(priv);
3527
3528 /*
3529 * Temporarily enable interrupts. Initial firmware host
3530 * commands use interrupts and avoids polling. Disable
3531 * interrupts when done.
3532 */
c23b5a69 3533 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3534
3535 /* Get config data, mac addrs etc */
42fba21d
LB		 3536 if (priv->ap_fw) {
3537 rc = mwl8k_cmd_get_hw_spec_ap(hw);
3538 if (!rc)
3539 rc = mwl8k_cmd_set_hw_spec(hw);
3540 } else {
3541 rc = mwl8k_cmd_get_hw_spec_sta(hw);
3542 }
a66098da 3543 if (rc) {
c2c357ce
LB		 3544 printk(KERN_ERR "%s: Cannot initialise firmware\n",
3545 wiphy_name(hw->wiphy));
a66098da
LB		 3546 goto err_stop_firmware;
3547 }
3548
3549 /* Turn radio off */
c46563b7 3550 rc = mwl8k_cmd_802_11_radio_disable(hw);
a66098da 3551 if (rc) {
c2c357ce 3552 printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
a66098da
LB		 3553 goto err_stop_firmware;
3554 }
3555
32060e1b
LB		 3556 /* Clear MAC address */
3557 rc = mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
3558 if (rc) {
3559 printk(KERN_ERR "%s: Cannot clear MAC address\n",
3560 wiphy_name(hw->wiphy));
3561 goto err_stop_firmware;
3562 }
3563
a66098da 3564 /* Disable interrupts */
a66098da 3565 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3566 free_irq(priv->pdev->irq, hw);
3567
3568 rc = ieee80211_register_hw(hw);
3569 if (rc) {
c2c357ce
LB		 3570 printk(KERN_ERR "%s: Cannot register device\n",
3571 wiphy_name(hw->wiphy));
a66098da
LB		 3572 goto err_stop_firmware;
3573 }
3574
eae74e65 3575 printk(KERN_INFO "%s: %s v%d, %pM, %s firmware %u.%u.%u.%u\n",
a74b295e 3576 wiphy_name(hw->wiphy), priv->device_info->part_name,
45a390dd 3577 priv->hw_rev, hw->wiphy->perm_addr,
eae74e65 3578 priv->ap_fw ? "AP" : "STA",
2aa7b01f
LB		 3579 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
3580 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
a66098da
LB		 3581
3582 return 0;
3583
3584err_stop_firmware:
3585 mwl8k_hw_reset(priv);
3586 mwl8k_release_firmware(priv);
3587
3588err_free_irq:
a66098da 3589 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3590 free_irq(priv->pdev->irq, hw);
3591
3592err_free_queues:
3593 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3594 mwl8k_txq_deinit(hw, i);
3595 mwl8k_rxq_deinit(hw, 0);
3596
3597err_iounmap:
3598 if (priv->cookie != NULL)
3599 pci_free_consistent(priv->pdev, 4,
3600 priv->cookie, priv->cookie_dma);
3601
3602 if (priv->regs != NULL)
3603 pci_iounmap(pdev, priv->regs);
3604
5b9482dd
LB		 3605 if (priv->sram != NULL)
3606 pci_iounmap(pdev, priv->sram);
3607
a66098da
LB		 3608 pci_set_drvdata(pdev, NULL);
3609 ieee80211_free_hw(hw);
3610
3611err_free_reg:
3612 pci_release_regions(pdev);
3613 pci_disable_device(pdev);
3614
3615 return rc;
3616}
3617
230f7af0 3618static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
a66098da
LB		 3619{
3620 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
3621}
3622
230f7af0 3623static void __devexit mwl8k_remove(struct pci_dev *pdev)
a66098da
LB		 3624{
3625 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
3626 struct mwl8k_priv *priv;
3627 int i;
3628
3629 if (hw == NULL)
3630 return;
3631 priv = hw->priv;
3632
3633 ieee80211_stop_queues(hw);
3634
60aa569f
LB		 3635 ieee80211_unregister_hw(hw);
3636
a66098da
LB		 3637 /* Remove tx reclaim tasklet */
3638 tasklet_kill(&priv->tx_reclaim_task);
3639
a66098da
LB		 3640 /* Stop hardware */
3641 mwl8k_hw_reset(priv);
3642
3643 /* Return all skbs to mac80211 */
3644 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3645 mwl8k_txq_reclaim(hw, i, 1);
3646
a66098da
LB		 3647 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3648 mwl8k_txq_deinit(hw, i);
3649
3650 mwl8k_rxq_deinit(hw, 0);
3651
c2c357ce 3652 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
a66098da
LB		 3653
3654 pci_iounmap(pdev, priv->regs);
5b9482dd 3655 pci_iounmap(pdev, priv->sram);
a66098da
LB		 3656 pci_set_drvdata(pdev, NULL);
3657 ieee80211_free_hw(hw);
3658 pci_release_regions(pdev);
3659 pci_disable_device(pdev);
3660}
3661
3662static struct pci_driver mwl8k_driver = {
3663 .name = MWL8K_NAME,
45a390dd 3664 .id_table = mwl8k_pci_id_table,
a66098da
LB		 3665 .probe = mwl8k_probe,
3666 .remove = __devexit_p(mwl8k_remove),
3667 .shutdown = __devexit_p(mwl8k_shutdown),
3668};
3669
3670static int __init mwl8k_init(void)
3671{
3672 return pci_register_driver(&mwl8k_driver);
3673}
3674
3675static void __exit mwl8k_exit(void)
3676{
3677 pci_unregister_driver(&mwl8k_driver);
3678}
3679
3680module_init(mwl8k_init);
3681module_exit(mwl8k_exit);
c2c357ce
LB		 3682
3683MODULE_DESCRIPTION(MWL8K_DESC);
3684MODULE_VERSION(MWL8K_VERSION);
3685MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
3686MODULE_LICENSE("GPL");
Motorola kernel-slsi